Clock recovery circuit and device
The clock recovery circuit optimizes timing recovery in high-speed serial links by adjusting threshold voltages based on error signals from different data patterns, addressing power and complexity challenges while ensuring fast frequency lock and reduced jitter.
Patent Information
- Authority / Receiving Office
- JP · JP
- Patent Type
- Patents
- Current Assignee / Owner
- SAMSUNG DISPLAY CO LTD
- Filing Date
- 2022-03-17
- Publication Date
- 2026-06-26
AI Technical Summary
High-speed serial links face challenges in achieving timing recovery while minimizing power consumption, area, and design complexity.
A clock recovery circuit employing a data slicer, first and second error blocks, a voltage threshold change circuit, and a voltage-controlled oscillator, with a loop filter controlling the oscillator frequency, adjusts threshold voltages based on error signals from different data patterns to optimize sampling phase and reduce power consumption.
The circuit achieves timing recovery efficiently, reducing power consumption, area, and design complexity, and can lock frequency even with repeating data patterns like 1010, achieving frequency lock within 2 μs and reducing inter-symbol interference-induced jitter.
Smart Images
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Abstract
Description
[Technical Field]
[0001] The present invention relates to a clock recovery circuit and apparatus, and more particularly to timing recovery of a high-speed serial link.
[0002] This application claims priority to and incorporates the entirety of U.S. Patent Application No. 63 / 162,883, filed with the U.S. Patent and Trademark Office on 18 March 2021, U.S. Patent Application No. 63 / 227,605, filed on 30 July 2021, and U.S. Patent Application No. 17 / 508,898, filed on 22 October 2021, by reference herein. [Background technology]
[0003] High-speed serial links, also commonly known as serializers / deserializers (SerDes), are widely used in electronic devices such as electronic display devices. As the amount of data transmitted through such high-speed serial links increases (for example, as a result of increased resolution, color depth, and / or refresh rate of the display device), the interface speed also increases. Along with the increased speed, the power consumption and silicon area of the interface's communication receiver also increase. Timing recovery, or clock data recovery (CDR), is a crucial function for ensuring proper data transmission and reception on such serial links. Furthermore, it is preferable to perform timing recovery while reducing the power consumption, area, and design complexity of the serial interface. [Overview of the Initiative] [Problems that the invention aims to solve]
[0004] The problem that this invention aims to solve is to perform timing recovery while reducing the power consumption, area, and design complexity of the serial interface. [Means for solving the problem]
[0005] A clock recovery circuit according to one embodiment of the present invention includes a data slicer that outputs data values based on an input signal, a first error block, a phase adjustment loop including a first error slicer, a second error block, and a voltage threshold change circuit, a voltage-controlled oscillator, and a loop filter that controls the frequency of the voltage-controlled oscillator based on the output of the first error block, wherein the first error slicer generates a first error signal based on a comparison of a threshold voltage with an input voltage, the first error block selectively outputs the first error signal in response to a first pattern of the output data values, the second error block selectively outputs the first error signal in response to a second pattern of the output data values, the voltage threshold change circuit adjusts the threshold voltage based on the output of the second error block, and the data slicer and the first error slicer are clocked based on the output of the voltage-controlled oscillator.
[0006] The first error signal may take a positive value in response to the input voltage being greater than the threshold voltage, or a negative value in response to the input voltage being less than or equal to the threshold voltage.
[0007] The voltage threshold changing circuit may include a state machine that selectively increases the threshold voltage in response to the input voltage of the first error slicer being greater than the threshold voltage.
[0008] The input voltage of the first error slicer may be the output of the voltage-controlled oscillator.
[0009] The threshold voltage may be initialized based on the peak value of the input signal.
[0010] The first pattern and the second pattern may be different from each other.
[0011] Each of the first and second patterns may include the 3-bit output data voltage.
[0012] The aforementioned loop filter may be a low-pass filter that filters out noise from the output signal.
[0013] The phase adjustment loop may further include a second error slicer that generates a second error signal based on a comparison of the threshold voltage and the negative value of the input voltage.
[0014] The first error block selectively outputs an inverted second error signal in response to a third pattern of the output data voltage, and the third pattern may be a complement of the first pattern.
[0015] The second error block selectively outputs the second error signal in response to the fourth pattern of the output data voltage, and the fourth pattern may be a complement of the second pattern.
[0016] A clock recovery method according to one embodiment of the present invention includes the steps of: outputting a data value based on an input signal using a data slicer; generating a first error signal based on a comparison of a threshold voltage and an input voltage using a first error slicer; selectively outputting the first error signal using a first error block in response to a first pattern of the output data value; selectively outputting the first error signal using a second error block in response to a second pattern of the output data value; adjusting the threshold voltage based on the output of the second error block using a voltage threshold changing circuit; clocking the data slicer and the first error slicer using a voltage-controlled oscillator; and controlling the frequency of the voltage-controlled oscillator based on the output of the first error block using a loop filter.
[0017] The first error signal may take a positive value in response to the input voltage being greater than the threshold voltage, or may take a negative value in response to the input voltage being less than or equal to the threshold voltage.
[0018] The step of adjusting the threshold voltage may include selectively increasing the threshold voltage in response to the input voltage of the first error slicer being greater than the threshold voltage.
[0019] The input voltage of the first error slicer may be the output of the voltage-controlled oscillator.
[0020] It may further include the step of initially setting the threshold voltage based on the peak value of the input signal.
[0021] Each of the first pattern and the second pattern may include the 3-bit output data voltage.
[0022] It may further include the step of generating a second error signal by a second error slicer based on a comparison between the threshold voltage and a negative value of the input voltage.
[0023] The first error block may further include selectively outputting an inverted second error signal in response to a third pattern of the output data voltage, and the third pattern may be a complement of the first pattern.
[0024] The second error block may further include selectively outputting the second error signal in response to a fourth pattern of the output data voltage, and the fourth pattern may be a complement of the second pattern.
Advantages of the Invention
[0025] With the above configuration, timing recovery can be performed while reducing the power, area, and design complexity of the serial interface. [Brief explanation of the drawing]
[0026] [Figure 1] This block diagram shows an example of a slicer according to one embodiment of the present invention. [Figure 2] This is a block diagram of an example of a high-speed serial link according to one embodiment of the present invention. [Figure 3] This table shows an example of an error block according to one embodiment of the present invention. [Figure 4] This figure shows an example of a data eye according to an embodiment of the present invention. [Figure 5] This table shows other examples of error blocks according to one embodiment of the present invention. [Figure 6] This flowchart shows a method for performing clock recovery according to an embodiment of the present invention. [Modes for carrying out the invention]
[0027] The features of the embodiments and how they are realized can be better understood by referring to the detailed description of embodiments of the present invention and the accompanying drawings. Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the embodiments described can be realized in a variety of different forms and are not limited to the illustrated embodiments. Rather, these embodiments are presented as examples to complete the invention and to fully demonstrate its features to those skilled in the art. Therefore, processes, elements, techniques, etc., that are not necessary for those skilled in the art to fully understand the features of the present invention may not be specifically described.
[0028] This specification describes timing recovery or clock data recovery techniques for high-speed serial links (SerDes). The SerDes systems and methods described herein utilize two feedback loops that interrupt the operation of a single 1-bit sampler known as a slice. The slicer samples the difference between the input data signal and the offset threshold voltage at the data symbol rate. A first feedback loop, hereafter referred to as the frequency acquisition loop, adjusts the threshold voltage, and a second feedback loop, hereafter referred to as the phase adjustment loop, automatically reacts to adjust the sampling phase. The systems and methods described also include a data signal bit pattern screening function that generates error signals supplied to the two feedback loops, and clock and data recovery (CDR) optimizes the threshold voltage and sampling phase in conjunction so that a specific target standard can be achieved. The pattern screening function avoids the problem of losing frequency lock when the data bits are repeating 1010 clock patterns by configuring it to depend only on the current bit value for the frequency acquisition loop that drives the voltage-controlled oscillator (VCO). On the other hand, the phase adjustment loop can screen other pattern sets to optimize the locking phase and achieve diverse impulse responses.The following describes timing recovery systems and methods that reduce the power consumption, area, and design complexity of serial interfaces.
[0029] Clock data recovery algorithms are generally divided into two categories: oversampled or baud rate (hereinafter also called symbol-spaced). In high-speed serial links (SerDes) that use oversampled timing recovery, two samples are taken per unit interval (UI) at a distance or spacing of half the UI between two samples. One UI can be defined as 1 / (data rate) = 1 symbol time = T. Therefore, for example, the well-known early-late algorithm can be used to obtain the time information of the signal. The early-late algorithm is a robust algorithm, but it has the disadvantage that the receiver must generate the clock at twice the data rate. In systems using baud rate timing recovery, such as the bang-bang or Mueller-Muller scheme, a common clock recovery technique used in many digital receivers (e.g., analog-to-digital converter (ADC) based receivers), only one sample is taken per UI. However, this technique requires sampling at two or more UIs to obtain time error information, and is generally implemented within the digital domain. Therefore, such conventional techniques require additional clock phases and additional slicers, which leads to increased power consumption.
[0030] This specification describes embodiments of a technique that performs timing recovery or clock data recovery (CDR) independently of the ADC by taking only one sample per UI, without using the magnitude of the error and only the sign of the error. Furthermore, while some techniques lose frequency lock when a specific pattern is transmitted to the receiver (e.g., a clock pattern such as 1010), embodiments of the present invention provide a technique that can obtain frequency lock for all types of data patterns, including repeating clock patterns such as 1010. Thus, frequency lock can be achieved even faster than other conventional techniques. For example, with a Nyquist channel loss between 10 dB and 35 dB at a data rate of 10 Gbps, a locking range of 500,000 ppm can be obtained when the transmitter transmits a single clock pattern, and a locking range of 30,000 ppm can be obtained when the transmitter transmits a random non-return-to-zero (NRZ) data bit sequence. Furthermore, frequency locking can be achieved within 2 μs, and inter-symbol interference (ISI) induced jitter can be reduced by channel loss, allowing frequency locking to be obtained between 1 and 5 picoseconds RMS.
[0031] Various timing recovery techniques can be distinguished by the method used to generate and process time errors produced by a phase detector in order to adjust the receiver clock. According to embodiments of the present invention, a basic form of the time error function is used for frequency acquisition, and multiple time errors are used for phase optimization. Therefore, the aforementioned techniques use a data slicer and an error slicer that ceases operation with the same clock signal, but do not use a crossing slicer.
[0032] Figure 1 shows an example block diagram of slicer 102. In embodiments of the present invention, slicer 102 operates on the principle of comparing an input signal 104 (e.g., an analog voltage) with a threshold 106 and generating an error output 108. As shown in the figure, slicer 102 receives an input signal 104 and generates an error output 108 based on the result of comparing the input signal 104 with the threshold 106. Specifically, if the voltage of the input signal 104 is greater than the threshold 106, slicer 102 outputs +1 (e.g., a positive error), and if the voltage of the input signal 104 is less than the threshold 106, it outputs -1 (e.g., a negative error). According to embodiments of the present invention, the threshold for the data slicer is 0, and the threshold for the error slicer starts initially with a predetermined threshold voltage Vth of approximately 100 to 400 mV and is subsequently adjusted to optimize the sampling phase.
[0033] Figure 2 is a block diagram of an example of a high-speed serial link according to one embodiment of the present invention. The link includes a transmitter 202, a receiver 210, and a channel 204 connecting the transmitter 202 to the receiver 210. In embodiments of the present invention, the transmitter 202 may be a linear finite-impulse-response filter (FIR), and the receiver 210 may be a continuous-time linear equalizer (CTLE). Here, the transmitter 202 uses a transmitter clock signal 214 to send a serial data signal 212 through channel 204 to a clock data recovery (CDR) input V in (t) is transmitted to the receiver 210. In embodiments of the present invention, noise 206 may be introduced as the CDR input.
[0034] In an embodiment of the present invention, CDR input V in (t) can be calculated as follows:
[0035] V in (t) = Σ k d k p(t-kT)+n(t)
[0036] Here, dk ∫ represents the transmit alphabet (+1 / -1 in NRZ transmission), n(t) is noise generally modeled as additive white Gaussian noise (AWGN), p(t) represents the pulse response of the entire channel including the analog front end (AFE), kT represents time in units of T seconds, where T is the symbol period. For example, serial data signal 212 is sampled every T seconds (1UI=T seconds) so that the time sequence in which serial data signal 212 is sampled is T, 2T, 3T. Transmission sequence d k These can be assumed to be independent and identically distributed (IID).
[0037] In embodiments of the present invention, the receiver 210 includes an analog front-end (AFE) 205, a frequency acquisition loop 216, and a phase adjustment loop 208. The AFE 205 may be any of the various front-end circuits known to those skilled in the art, which are not described in detail here. According to one embodiment of the present invention, the phase adjustment of the phase adjustment loop 208 is performed automatically based on specific parameters, such as the bit pattern of the input data bits. Thus, the frequency acquisition loop 216 and the phase adjustment loop 208 interrupt each other's operation to achieve different objectives, and the receiver 210 stabilizes when both objectives are met. For example, the objective of the frequency acquisition loop 216 may be to obtain a specific frequency, and the objective of the phase adjustment loop 208 may be to obtain a specific phase. The frequency acquisition loop 216 and the phase adjustment loop 208 continue to operate to achieve their respective objectives until both objectives are met. In embodiments of the present invention, the frequency acquisition loop 216 operates at a speed approximately 100 times faster than the phase adjustment loop 208.
[0038] In embodiments of the present invention, the frequency acquisition loop 216 includes a data slicer 218 that samples the data signal 212 received from the transmitter 202. In embodiments of the present invention, the threshold voltage is set to 0. Thus, the data slicer 218 outputs the received data signal. As will be described in detail later, the output of the data slicer 218 may be connected to a first error block 220. The output of the first error block 220 may be connected to a loop filter 230 (for example, a proportional-integral loop filter). In embodiments of the present invention, the loop filter 230 may be a standard loop filter that filters out noise detected as the data signal is transmitted through channel 204, for example. The filtered data signal is then output from the loop filter 230 to control the voltage-controlled oscillator (VCO) 232. The loop filter 230 may be a standard loop filter such as a low-pass filter, which is well known to those skilled in the art, so a detailed description is omitted.
[0039] In embodiments of the present invention, the phase adjustment loop 208 includes an error slicer 222 and a second error block 224. The error slicer 222 may be similar to the example shown in Figure 1 and operates similarly to the data slicer 218, except that the threshold is an initial threshold voltage that is then adjusted for optimization.
[0040] Returning to Figure 2, the error slicer 222 receives the input signal from the VCO 232 and receives the threshold voltage Vth as the comparison voltage. In embodiments of the present invention, the threshold voltage Vth may be any predetermined value greater than 0, for example, a value of 100 to 400 mV. In embodiments of the present invention, the predetermined threshold voltage Vth may be set to a value of about half the peak input signal. However, the threshold voltage may be set to any value as long as the error value is not set to be low, mainly around +1, or high, mainly around -1.
[0041] In embodiments of the present invention, the error output from the error slicer 222 is supplied to a first error block 220 in the frequency acquisition loop 216. When a specific bit pattern (e.g., a predetermined pattern) is detected in the input data signal 212, the first error block 220 can perform a first function f1. Similarly, the same error output from the error slicer 222 is also supplied to a second error block 224 in the phase adjustment loop 208. When a specific bit pattern (e.g., a predetermined pattern) is detected in the input data signal 212, the second error block 224 can perform a second function f2. In some details, as will be described later, in embodiments of the present invention, the first error block 220 and the second error block 224 search for different bit patterns from each other.
[0042] In embodiments of the present invention, when the pattern category for the first error block 220 is satisfied, the output of the second error block 224 is supplied to a voltage threshold modification circuitry 226 that adjusts the threshold voltage Vth, which is ultimately fed back to the error slicer 222. Thus, the phase adjustment loop 208 controls the threshold voltage Vth, and the threshold voltage Vth controls the error slicer 222. The error slicer 222 generates error outputs that are supplied to both the first error block 220 and the second error block 224. Each of the first error block 220 and the second error block 224 performs a different function from each other when their respective pattern categories are satisfied, and when the functions f1 and f2 of the first error block 220 and the second error block 224 are combined, the phase adjustment loop 208 and the frequency acquisition loop 216 converge, the threshold voltage Vth is no longer updated, and frequency lock is achieved.
[0043] Figure 3 is a table showing an example of an error block. In this table, the primary loop represents the frequency acquisition loop 216, and the secondary loop represents the phase adjustment loop 208. In this specification, the notation (1) below means that the average value of the error is Previous Data (d n-1 )=0, Current Data (dn ) = 1, Next Data (d n+1 ) = 0 means that it is conditional.
[0044]
Number
[0045] In other words, the function is exerted only when the data pattern 010 is detected. The notation "X" means that the bit may be either 0 or 1. Therefore, for example, the notation X1X for the first loop means considering the case where the current data bit is 1 instead of considering whether the previous data bit and the next data bit are 1 or 0.
[0046] For example, in case #1, when the data signal 212 shows a 3-bit pattern of 011, the error from the second error block 224 is applied to the second loop. Different from case #1, in case #2, the error from the second error block 224 is applied to the second loop only when the bit pattern is 110. In other words, if the bit pattern is not 110, the second loop ignores the error. In the case of case #3, when the bit pattern corresponds to x10, the error from the second error block 224 is applied to the second loop. In other words, ignoring the previous bit, only the current bit and the next bit are monitored so that the current bit is 1 and the next bit is 0. Similarly, in case #4, if the bit pattern is 01x, the error from the second error block 224 is applied to the second loop. In other words, ignoring the next bit, only the previous bit and the current bit are monitored so that the previous bit is 0 and the current bit is 1. In such a manner, the first error block 220 and the second error block 224 receive the same error output from the error slicer 222, but the error can be applied to the corresponding first loop or second loop only when the bit pattern screening category is satisfied. Four cases are shown as examples in Figure 3, but other variations of the bit pattern can also be applied.
[0047] Therefore, the threshold voltage Vth of the phase adjustment loop 208 (i.e., the second loop) is adjusted by applying the error from the second error block 224 to the phase adjustment loop 208 until the frequency lock condition is achieved. Thus, for example, in case #1 and case #2, the impulse response value h1 = h -1 Frequency lock is achieved when h1=0 in case #3, and in case #4, h -1 Frequency lock is achieved when = 0.
[0048] Returning to Figure 2, the error output from the error slicer 222 is also supplied to the first error block 220 of the frequency acquisition loop 216. Similar to the second error block 224, the first error block 220 can perform screening for a given bit pattern. For example, as shown in Figure 3, the first error block 220 may look for the X1X pattern, which means that when the current data bit is 1, an error is applied to the frequency acquisition loop 216 (i.e., the first circuit).
[0049] In embodiments of the present invention, when an error from the first error block 220 is applied to the frequency acquisition loop 216, the error is filtered by a loop filter 230 (e.g., a proportional-integral loop filter), and the output of the loop filter 230 controls the VCO frequency as shown in Figure 2. In embodiments of the present invention, an error value of +1 acts to increase the VCO frequency, and an error value of -1 acts to decrease the VCO frequency. Thus, the error (i.e., time error) information can be used to drive the timing recovery loop. When the timing recovery achieves lock, the expected value of the signal voltage in the sampling instance shown in (2) below becomes the same as the threshold shown in Figure 4. Here, Figure 4 is a diagram showing an example of a data eye according to embodiments of the present invention. Here, (2) below is defined as the average of the signal voltage in the sampling instance.
[0050]
number
[0051] In embodiments of the present invention, as shown in Figure 3, the error signal input to the VCO (or other clock generation block) is adjusted based on a different bit pattern than that of the phase optimization loop. Therefore, although the errors for both loops are the same output from the error slicer 222, the two loops are adjusted based on different patterns. The error information entering the VCO loop directly affects the frequency, while the error entering the phase optimization loop affects only the threshold voltage Vth, and the loop converges when the time error is driven to zero such that the VCO loop input error equals the phase optimization loop input error. In embodiments of the present invention, the VCO loop is substantially (about 10 to 100 times) faster than the phase optimization loop in adjusting the phase for the new threshold voltage Vth.
[0052] In embodiments of the present invention, the frequency acquisition loop 216 can acquire a frequency lock even when the transmitter is transmitting data bits having a clock pattern (e.g., a repetition of 1010). Since the initial part of the data signal often includes a clock pattern, achieving a frequency lock during such a clock pattern has the advantage of greatly improving (e.g., reducing) the amount of time required to achieve the frequency lock. As mentioned above, a frequency lock can also be achieved with a random data sequence, but if the transmitter sends a few clock patterns with inter-symbol interference (ISI), the achievement of the frequency lock will be much faster. In the Mueller-Müller phase detector, the time error information is X k *A k-1 -X k-1 *A k Given. In SerDes, only sign information is available, so this equation is Sign(X k )*d k-1 -Sign(X k-1 )*d kThis results in a value that is always 0 for 1010 patterns, preventing time information from being transmitted to the CDR. In various embodiments of the present invention, E(V in )=V threshold =h0, which allows the CDR to be locked under a clock pattern (e.g., 1010). For example, using a 1010 clock pattern, if the starting ppm offset is 500,000, frequency lock can be achieved in less than 2μs.
[0053] In embodiments of the present invention, an additional bit pattern, such as the complement of the screening bit pattern shown in Figure 3, is implemented, and an additional slicer may be included to obtain similar results. An example of a complemented screening bit pattern is shown in Figure 5. Thus, the first error block 220 can apply the error to the first loop if the bit pattern is X0X, indicating that the current data bit is 0. As described above, the bit pattern X0X is the complement of X1X. Similarly, if the bit pattern is 100, 001, X01, 10X in cases #1-4, i.e., the complement of 011, 110, x10, 01x in cases #1-4 of Figure 3, then the second error block 224 can apply the error to the second loop. In embodiments of the present invention, such complementary screening can be performed by including an additional error slicer configured to look for a threshold voltage Vth and the opposite polarity. In other words, the error slicer used with the screening pattern shown in Figure 3 looks for a positive threshold voltage +Vth and applies the error to the second loop. In embodiments of the present invention, another error slicer is implemented to search for a negative threshold voltage -Vth, and similar results can be obtained using a complemented screening bit pattern. Thus, the bandwidth of the feedback loop can be doubled.
[0054] Figure 6 is a flowchart illustrating a method for performing clock recovery according to an embodiment of the present invention. According to one embodiment of the present invention, in step 602, a data slicer 218 generates a data value based on an input signal. Next, in step 604, a first error slicer 222 generates a first error signal based on a comparison of a threshold voltage with an input voltage. In step 606, in response to a first pattern in the output data value, the first error signal is selectively output by the first error block 220. Next, in step 608, in response to a second pattern in the output data value, the first error signal is selectively output by the second error block 224. Next, in step 610, based on the output of the second error block 224, the voltage threshold change circuit 226 can adjust the threshold voltage. In step 612, the data slicer 218 and the first error slicer 222 are clocked by a voltage-controlled oscillator 232. In embodiments of the present invention, the frequency of the voltage-controlled oscillator 232 can be controlled by the loop filter 230 based on the output of the first error block 220. In this way, clock data recovery can be performed on a high-speed serial link to achieve the target category by optimizing the threshold voltage and sampling phase in coordination.
[0055] Unless otherwise specified, the same reference numerals in the drawings and throughout the specification indicate the same components, and their descriptions will not be repeated. Furthermore, descriptions of parts unrelated to the descriptions of embodiments may be omitted for clarity.
[0056] In drawings, the relative sizes of parts, layers, and regions may be exaggerated for clarity. Furthermore, in attached drawings, cross hatching and / or shading may be used to clearly define boundaries between adjacent elements. Thus, the presence or absence of cross hatching and shading does not, unless otherwise specified, indicate a preference for or requirement of specific materials, properties, dimensions, parts, commonalities between illustrated parts, and / or other characteristics, attributes, or properties of the elements.
[0057] In the detailed description of the invention, various specific examples are presented for illustrative purposes to ensure a full understanding of the various embodiments. However, the various embodiments can be realized without such specific examples, or by using one or more equivalent examples. Furthermore, well-known structures and devices are shown in the form of block diagrams to avoid unnecessarily obscuring the various embodiments.
[0058] For the sake of clarity, spatial terms such as "below," "down," and "above" may be used to indicate the relationship between one part or feature and another part or feature shown in the drawing. Such spatial terms are intended to indicate the different positions and / or orientations of the device in use or operation shown in the drawing. For example, a part shown in the drawing as being "below" or "down" a part would be "above" the device if it were inverted. Thus, for example, "below" and "down" can refer to both up and down. The device may rotate, for example, 90 degrees or face another direction, in which case the spatial terms must be interpreted accordingly. Similarly, if it is stated that the first part is positioned "above" the second part, this does not mean that it is limited to an upper surface based on the direction of gravity, but rather that the first part is positioned on the upper or lower surface of the second part.
[0059] When we say that a part, layer, region, or component is "formed on" or "connected" to another part, layer, region, or component, this includes not only cases where it is "immediately" above or "directly" connected, but also cases where it is formed separately from or indirectly connected to another part, layer, region, or component with other parts, layers, regions, or components in between. Furthermore, this collectively includes direct or indirect connections and integrated or non-integrated connections. For example, when we say that a layer, region, or component is "electrically connected" or "electrically coupled" to another part, layer, region, or component, this could mean that it is directly electrically connected or coupled to the other part, layer, region, or component, or that other parts, layers, regions, or components are in between. However, when we say that it is "immediately above" or "directly connected," it means that there are no other parts in between. On the other hand, other expressions indicating relationships between components, such as "between," "directly between," "adjacent," and "directly adjacent," can be interpreted similarly. Also, when we say that one part or layer is "between" two other parts or layers, it is possible that only that layer exists between the two layers, but it is also possible that one or more other layers exist.
[0060] Terms such as "first," "second," and "third" are used for various elements, components, regions, layers, and parts, but these are not limited by such modifiers. Such terms are used to distinguish one element, component, region, layer, or part from other elements, components, regions, layers, and parts. Therefore, a first element, component, region, layer, or part can also be called a second element, component, region, layer, or part without departing from the spirit and scope of the present invention. Describing an element as a "first" element does not require the existence of a second element or other elements, nor does it imply their existence. Terms such as "first," "second," and "third" can also be used to distinguish different categories or sets of elements from each other. For concise expression, "first," "second," etc., can also refer to "first category (or first set)," "second category (or second set)," etc., respectively.
[0061] In the embodiments, the x-axis, y-axis, and / or z-axis are not limited to representing the three axes of a Cartesian coordinate system, but can be interpreted in a broader sense. For example, the x-axis, y-axis, and z-axis may be perpendicular to each other, or they may represent different directions that are not perpendicular to each other. The same can be applied to the first, second, and / or third directions.
[0062] The terms used herein are for the purpose of describing specific embodiments and are not intended to limit the invention. Unless otherwise specified, numbers here include both singular and plural cases. When a feature, stage, operation, part, component, etc., is "included," it means that other features, stages, operations, parts, components, etc., may also be included in addition to the part in question. The expression "and / or" includes all combinations of one or more of the listed items.
[0063] Here, "substantially," "about," "approximately," and similar expressions are merely approximations and do not indicate "degree," but are used to describe the inherent error of a measured or calculated value that is known to those skilled in the art. The expressions "about" and "approximately" include the value mentioned and the average within an acceptable range of error for that value, which can be determined by those skilled in the art considering the measured value in question and the error associated with the measurement of a particular quantity (e.g., the limits of the measuring system). For example, "about" can mean within one or more standard deviations or within ±30%, 20%, 10%, or 5% of the value in question. The expression "may" used when describing embodiments of the present invention means that it is applicable to "one or more embodiments of the present invention." "Use," "utilize," etc., can be used with similar meanings together with other similar expressions.
[0064] When one or more specific embodiments are implemented in different ways, the specific process order may differ from the order described. For example, two processes described as being executed consecutively may be executed simultaneously or in the reverse order of the description.
[0065] Here, various embodiments will be described with reference to cross-sectional views showing schematic and / or intermediate structures of the embodiments. The illustrated forms may be varied or changed in various ways, for example, by manufacturing techniques and / or tolerances. Furthermore, the descriptions of specific structures or functions described herein are merely illustrative examples for illustrating embodiments based on the concept of the present invention. Therefore, the embodiments described herein should be interpreted not as being limited to specific forms of the illustrated regions, but as including variations in form due to, for example, manufacturing methods. For example, even if the injection region is illustrated as a rectangle, it may generally be round or curved, and the injection concentration may change gradually with a concentration gradient rather than changing abruptly and binaryly at the boundary between the injection region and the non-injection region. Similarly, when an embedded region is formed by injection, particles or ions may also be injected into the region between the surface where injection occurs and the embedded region. Therefore, the forms of the regions shown in the drawings are essentially schematic and are not intended to show or limit the actual form of the region in the apparatus.
[0066] Furthermore, the numerical ranges described or cited herein include all sub-ranges of the same precision that fall within that range. For example, the range "1.0 to 10.0" includes the minimum value of 1.0 and the maximum value of 10.0 and all sub-ranges between them, i.e., sub-ranges having a minimum value of 1.0 or greater and a maximum value of 10.0 or less, for example, 2.4 to 7.6. The maximum value mentioned herein includes all numerical limits that are contained within it and smaller than it, and the minimum value described herein includes all numerical limits that are contained within it and larger than it. Accordingly, the applicant has the right to amend the specification, including the claims, to explicitly refer to any sub-range that falls within the range explicitly mentioned herein. All such ranges described herein contain the necessary elements to ensure that amendments explicitly referring to sub-ranges satisfy the amendment requirements stipulated in the Patent Act.
[0067] The electronic, electrical devices and / or other related devices or parts described in embodiments of the present invention can be realized using appropriate hardware, firmware (e.g., application-specific integrated circuits), software, or a combination thereof for processing data or digital signals. For example, the diverse components of these devices may be formed on a single integrated circuit chip, or they may be realized on different integrated circuit chips. Alternatively, the diverse components of these devices may be realized on flexible printed circuit films, tape carrier packages (TCPs), printed circuit boards, etc., or formed on a single substrate. The circuit hardware may include non-transitory storage media, digital signal processors (DSPs), application-specific integrated circuits (ASICs) that execute instructions stored in programmable logic devices such as graphics processing units (GPUs) and FPGAs, general-purpose or dedicated central processing units (CPUs), etc.
[0068] Furthermore, the diverse components of these devices may be processes or threads running on one or more processors within one or more computer devices that execute computer program instructions and interact with other system elements to perform the diverse functions described herein. The computer program instructions may be stored in memory implemented in the computer device using a standard memory device such as RAM (random access memory). In addition, those skilled in the art may combine or integrate the functions of diverse computer devices into a single computer device, or distribute the functions of a particular computer device to one or more other computer devices, without departing from the concept and scope of the embodiments of the present invention.
[0069] Unless otherwise specified, all terms used herein (including technical and scientific terms) have the same meaning as those commonly known to those skilled in the art in the field to which this invention pertains. Terms such as those defined in commonly used dictionaries should be construed as having the meaning consistent with their meaning in the relevant art and / or herein, and should not be construed in an ideal or overly strict sense unless expressly stated herein.
[0070] The embodiments described above are, and are not limited thereto. Although several embodiments have been described, those skilled in the art can modify the embodiments without substantially departing from the new content and effects presented in the embodiments. Therefore, all such modifications or variations are included within the scope of the embodiments as defined in the claims. The functional expression of the claims is intended to include structures that perform the functions mentioned herein, as well as their structural equivalents and equivalent structures. Therefore, the above description relates to embodiments and is not limited to any particular embodiment, and variations of this embodiment and other embodiments are also within the scope of the claims. The core of the invention is defined by the following claims, and the equivalents of the claims are included therein. [Explanation of Symbols]
[0071] 102: Slicer 104: Input signal 106: Threshold 108: Error Output 202: Transmitter 204: Channel 205: Analog Front End (AFE) 206: Noise 208: Phase adjustment loop 210: Receiver 212: Data signal 214: Transmitter clock signal 216: Frequency acquisition loop 218: Data slicer 220, 224: Error Blocks 222: Error Slicer 226: Voltage threshold changing circuit 230: Loop Filter 232: Voltage-controlled oscillator / VCO
Claims
1. A data slicer that outputs output data values by sampling an input signal from a transmitter, The first error block and, A phase adjustment loop including a first error slicer, a second error block, and a voltage threshold changing circuit, Voltage-controlled oscillator, and A loop filter that controls the frequency of the voltage-controlled oscillator based on the output of the first error block, Includes, The first error slicer is connected to the voltage threshold changing circuit and the voltage control oscillator, and generates a first error signal based on a comparison between the threshold voltage adjusted by the voltage threshold changing circuit and the input voltage from the voltage control oscillator. The first error block is connected to the data slicer and the first error slicer, and receives the first error signal from the first error slicer. When it detects a first pattern in the input signal from the transmitter, it performs a first function to selectively output a first error signal corresponding to the first pattern in the output data value from the data slicer. The second error block is connected to the first error slicer and receives the first error signal from the first error slicer. When it detects a second pattern in the input signal from the transmitter, it performs a second function to selectively output the first error signal corresponding to the second pattern in the output data value from the data slicer. The voltage threshold changing circuit is connected to the second error block and adjusts the threshold voltage based on the first error signal that responds to the second pattern output from the second error block. The loop filter is connected to the first error block and adjusts the frequency of the voltage-controlled oscillator based on the first error signal that responds to the first pattern output from the first error block. The first pattern is a condition that determines whether the loop filter continues frequency adjustment to control the frequency of the voltage-controlled oscillator or whether it becomes frequency-locked. The second pattern is a condition that determines whether the voltage threshold changing circuit continues phase adjustment to adjust the threshold voltage or frequency locks. The data slicer and the first error slicer are clocked based on the output of the voltage-controlled oscillator. Clock recovery circuit.
2. The clock recovery circuit according to claim 1, wherein the first error signal takes a positive value in response to the input voltage being greater than the threshold voltage, or takes a negative value in response to the input voltage being less than or equal to the threshold voltage.
3. The clock recovery circuit according to claim 2, wherein the voltage threshold changing circuit includes a state machine that selectively increases the threshold voltage in response to the input voltage of the first error slicer being greater than the threshold voltage.
4. The clock recovery circuit according to claim 3, wherein the input voltage of the first error slicer is the output of the voltage-controlled oscillator.
5. The clock recovery circuit according to claim 4, wherein the threshold voltage is initialized based on the peak value of the input signal.
6. The clock recovery circuit according to claim 1, wherein the first pattern and the second pattern are different patterns from each other.
7. The clock recovery circuit according to claim 6, wherein each of the first pattern and the second pattern includes the 3-bit output data value.
8. The clock recovery circuit according to claim 1, wherein the loop filter is a low-pass filter that filters out noise from the output signal.
9. The clock recovery circuit according to claim 1, further comprising a second error slicer that generates a second error signal based on a comparison of negative values between the threshold voltage and the input voltage, wherein the phase adjustment loop further comprises a second error slicer.
10. The first error block selectively outputs an inverted second error signal in response to the third pattern of the output data value. The clock recovery circuit according to claim 9, wherein the third pattern is the complement of the first pattern.
11. The second error block selectively outputs the second error signal in response to the fourth pattern of the output data value. The clock recovery circuit according to claim 10, wherein the fourth pattern is the complement of the second pattern.
12. A clock recovery method in a clock recovery circuit comprising a data slicer, a first error block, a phase adjustment loop including the first error slicer, a second error block, and a voltage threshold changing circuit, a voltage-controlled oscillator, and a loop filter, The first error slicer is connected to the voltage threshold changing circuit and the voltage control oscillator, The first error block is connected to the data slicer and the first error slicer, The second error block is connected to the first error slicer, The voltage threshold changing circuit is connected to the second error block, The loop filter is connected to the first error block, The data slicer outputs output data values by sampling the input signal from the transmitter. The first error slicer generates a first error signal based on a comparison between a threshold voltage adjusted by the voltage threshold changing circuit and the input voltage from the voltage control oscillator. The first error block receives the first error signal from the first error slicer, and when it detects a first pattern in the input signal from the transmitter, it performs a first function to selectively output the first error signal corresponding to the first pattern in the output data value from the data slicer. The second error block receives the first error signal from the first error slicer and, upon detecting a second pattern in the input signal from the transmitter, performs a second function to selectively output the first error signal corresponding to the second pattern in the output data value from the data slicer. The step of adjusting the threshold voltage based on the first error signal that responds to the second pattern output from the second error block using the voltage threshold changing circuit, The steps include: controlling the frequency of the voltage-controlled oscillator based on a first error signal that responds to the first pattern output from the first error block using the loop filter; and In the step of clocking the data slicer and the first error slicer using the voltage-controlled oscillator, Includes, The first pattern is a condition that determines whether the loop filter continues frequency adjustment to control the frequency of the voltage-controlled oscillator or whether it becomes frequency-locked. The second pattern is a condition that determines whether the voltage threshold changing circuit continues phase adjustment to adjust the threshold voltage or frequency locks. Hmm, clock recovery method.
13. The clock recovery method according to claim 12, wherein the first error signal takes a positive value in response to the input voltage being greater than the threshold voltage, or takes a negative value in response to the input voltage being less than or equal to the threshold voltage.
14. The clock recovery method according to claim 13, wherein the step of adjusting the threshold voltage includes a step of selectively increasing the threshold voltage in response to the input voltage of the first error slicer being greater than the threshold voltage.
15. The clock recovery method according to claim 14, wherein the input voltage of the first error slicer is the output of the voltage-controlled oscillator.
16. The clock recovery method according to claim 15, further comprising the step of initializing the threshold voltage based on the peak value of the input signal.
17. The clock recovery method according to claim 12, wherein each of the first pattern and the second pattern includes the three-bit output data value.
18. The clock recovery method according to claim 12, further comprising the step of generating a second error signal based on a comparison of the threshold voltage and the negative value of the input voltage using a second error slicer.
19. The first error block further includes a step of selectively outputting an inverted second error signal in response to a third pattern of the output data value, The clock recovery method according to claim 18, wherein the third pattern is the complement of the first pattern.
20. The second error block further includes the step of selectively outputting the second error signal in response to a fourth pattern of the output data value, The clock recovery method according to claim 19, wherein the fourth pattern is the complement of the second pattern.