Photoelectric converter

Abstract

To provide a technique advantageous for ensuring uniformity of characteristics of pixels.SOLUTION: A photoelectric conversion device has a plurality of pixels arranged therein. The plurality of pixels each include: an avalanche photodiode that is arranged between a first potential supply line and a second potential supply line; a first transistor that is arranged to form a current path between the first potential supply line and the avalanche photodiode; and a holding circuit that, when the avalanche photodiode goes into avalanche breakdown, holds a second potential according to a first potential of an electrode of the avalanche photodiode connected with the first transistor. The second potential is supplied to a gate of the first transistor from the holding circuit.SELECTED DRAWING: Figure 4

Description

Technical Field

[0004] , , ,

[0005] , ,

[0001] The present invention relates to a photoelectric conversion device.

Background Art

[0002] A photoelectric conversion device having a single photon avalanche photodiode (SPAD) element capable of detecting weak light at the single photon level in each pixel is known. Patent Document 1 shows a light receiving device in which SPAD elements are arranged in each of a plurality of pixels. In the SPAD element, a voltage obtained by adding an excess voltage to the breakdown voltage of an avalanche photodiode (APD) is applied to the APD. When the breakdown voltage of the APD varies between pixels, if the same voltage is applied to the APDs of each pixel, the value of the excess voltage supplied to the APDs will vary between the respective pixels. If the excess voltage varies between pixels, it becomes impossible to maintain the uniformity of the characteristics in each pixel. In Patent Document 1, it is shown that the signal output from the APD is detected by a signal processing unit, and the voltage value of the excess voltage is adjusted by feeding back the detection result to a bias adjustment unit.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] The configuration shown in Patent Document 1 has a large circuit scale, such as detecting the dead time during which the SPAD element cannot react to photons in the signal processing unit.

[0005] An object of the present invention is to provide a technique advantageous for ensuring the uniformity of characteristics between pixels.

Means for Solving the Problems

[0006] In view of the above problems, a photoelectric conversion device according to an embodiment of the present invention is a photoelectric conversion device having a plurality of pixels, each of the plurality of pixels including an avalanche photodiode disposed between a first potential supply line and a second potential supply line, a first transistor disposed to form a current path between the first potential supply line and the avalanche photodiode, and a holding circuit that holds a second potential corresponding to a first potential of an electrode connected to the first transistor of the avalanche photodiode when the avalanche photodiode undergoes avalanche breakdown, wherein the second potential is supplied to the gate of the first transistor from the holding circuit. The holding circuit includes a holding node that holds the second potential and is connected to the gate of the first transistor, a second transistor for resetting the holding node, and a third transistor arranged to form a current path between the holding node and a third potential supply line, with its gate connected to the electrode, wherein an excess voltage corresponding to the difference between the threshold voltage of the first transistor and the absolute value of the threshold voltage of the third transistor is supplied to the avalanche photodiode. It is characterized by the following. [Effects of the Invention]

[0007] According to the present invention, it is possible to provide a technology that is advantageous in ensuring uniformity of characteristics between pixels. [Brief explanation of the drawing]

[0008] [Figure 1] A diagram showing an example configuration of the photoelectric conversion device according to this embodiment. [Figure 2] This figure illustrates an example of the pixel configuration in the photoelectric converter shown in Figure 1. [Figure 3] Figure 2 shows the signal waveforms at node A and node B of the pixel. [Figure 4] Figure 2 shows an equivalent circuit diagram illustrating an example of pixel configuration. [Figure 5] A timing diagram showing an example of pixel operation in Figure 4. [Figure 6] Equivalent circuit diagram showing a modified version of the pixel in Figure 4. [Figure 7] A timing diagram showing an example of pixel operation in Figure 6. [Figure 8] Equivalent circuit diagram showing a modified version of the pixel in Figure 4. [Figure 9] Equivalent circuit diagram showing a modified version of the pixel in Figure 4. [Modes for carrying out the invention]

[0009] The embodiments will be described in detail below with reference to the attached drawings. Note that the following embodiments do not limit the invention as defined in the claims. While the embodiments describe multiple features, not all of these features are essential to the invention, and the features may be combined in any way. Furthermore, in the attached drawings, identical or similar configurations are given the same reference numerals, and redundant descriptions are omitted.

[0010] A photoelectric conversion device according to an embodiment of the present disclosure will be described with reference to Figures 1 to 9. In the following embodiment, a single-photon avalanche photodiode (hereinafter sometimes referred to as SPAD) element will be described in which electrons are the signal carrier and the change in the cathode potential of the avalanche photodiode (hereinafter sometimes referred to as APD) due to the avalanche current when the avalanche photodiode undergoes avalanche breakdown. However, holes may be the signal carrier, or a configuration may be adopted in which the change in the anode potential of the APD is detected.

[0011] In this embodiment, after detecting the avalanche current flowing when the APD undergoes avalanche breakdown, a potential corresponding to the potential of the cathode of the APD is held, and a potential obtained by applying a predetermined voltage to the held potential is supplied to the APD. The cathode potential after detecting the avalanche current corresponds to the breakdown voltage Vbd of the APD with respect to the anode potential reference, and the predetermined voltage to be added corresponds to the excess voltage Vex. The circuit for holding the potential corresponding to the potential of the cathode of the APD in this case and the circuit for supplying the potential to the APD are basically transistor circuits including MOS (MIS) transistors. Here, it is assumed that the variation in the threshold voltage Vth of the transistors constituting this transistor circuit is sufficiently smaller than the variation in the breakdown voltage Vbd of the APD (Vbd > Vth). This is because, in the case of Vbd < Vth, the problem of the variation in the excess voltage Vex due to the variation in the breakdown voltage Vbd of the APD is only replaced by the problem of the variation in the threshold voltage Vth of the transistors. However, depending on the conditions for forming the transistors, the variation in the threshold voltage Vth of the transistors can be made about 1 / 3 to 1 / 4 of the variation in the breakdown voltage Vbd of the APD. That is, the premise for the establishment of the following disclosure of the present invention is sufficiently realistic.

[0012] First Embodiment FIG. 1 is a block diagram showing a configuration example of a photoelectric conversion device 100 according to the first embodiment of the present disclosure. The photoelectric conversion device 100 includes a pixel section 101, a control pulse generation circuit 115, a horizontal scanning circuit 111, a readout circuit 112, signal lines 113, and a vertical scanning circuit 110. In the pixel section 101, a plurality of pixels 104 are arranged in a matrix. Each pixel 104 includes a photoelectric conversion section 102 including an APD and a signal processing circuit 103. The photoelectric conversion section 102 converts the light incident on the pixel 104 into an electrical signal. The signal processing circuit 103 outputs the electrical signal generated by the photoelectric conversion section 102 in response to the incident light to the readout circuit 112.

[0013] The vertical scanning circuit 110 supplies control pulses to each pixel 104 in accordance with the pulse signal supplied from the control pulse generation circuit 115. Logic circuits such as a shift register and an address decoder can be used for the vertical scanning circuit 110.

[0014] The signal output from the photoelectric conversion unit 102 of the pixel 104 is processed by the signal processing circuit 103. The signal processing circuit 103 may include a counter, a memory, etc. The memory may hold the digital value counted by the counter.

[0015] The horizontal scanning circuit 111 inputs a control pulse for sequentially selecting the pixels 104 column by column to the signal processing circuit 103 in order to read out signals from the memories of the pixels 104 holding digital signals. Signals are output from the signal processing circuits 103 of the pixels 104 selected by the vertical scanning circuit 110 to the signal line 113. The signals output to the signal line 113 are output via the output circuit 114 to a signal processing device arranged outside the photoelectric conversion device 100 and can be displayed, for example, as a captured image on a display device.

[0016] As shown in FIG. 1, the pixels 104 may be arranged in an array, but are not limited thereto. For example, the pixels 104 may be arranged in a one-dimensional (linear) manner. Also, the functions of the signal processing circuit 103 do not necessarily have to be provided one by one for all the pixels 104. For example, one signal processing circuit 103 may be shared by a plurality of pixels 104 and signal processing may be performed sequentially.

[0017] FIG. 2 is a block diagram for explaining a configuration example of a pixel 104 arranged in the photoelectric conversion device 100. An avalanche photodiode (APD) 201 is arranged between a potential supply line 251 and a potential supply line 252 in the pixel 104. The APD 201 generates charge pairs corresponding to incident light by photoelectric conversion. A voltage VL is supplied from the potential supply line 252 to the anode of the APD 201. A voltage VH higher than the voltage VL supplied to the anode is supplied from the potential supply line 251 to the cathode of the APD 201. A reverse bias voltage is supplied between the anode and the cathode so that the APD 201 performs an avalanche breakdown operation. By supplying such a voltage, the charges generated by the incident light cause avalanche multiplication, and an avalanche current is generated.

[0018] In the operation of the APD 201, there are a Geiger mode in which the potential difference (voltage) between the anode and the cathode is operated at a voltage higher than the breakdown voltage Vbd, and a linear mode in which the voltage between the anode and the cathode is operated at a voltage near or below the breakdown voltage. An APD operated in the Geiger mode is called a SPAD element. When the breakdown voltage Vbd of the APD 201 is 30V, for example, the voltage VL is set to -30V and the voltage VH is set to 3V.

[0019] The signal processing circuit 103 may include a waveform shaping circuit 210, a count circuit 211, and a selection circuit 212. The signal processing circuit 103 may also include a quench element 202. The quench element 202 is arranged between the potential supply line 251 that supplies the voltage VH and the APD 201. The quench element 202 has a function of replacing a change in the avalanche current generated in the APD 201 with a voltage signal. The quench element 202 functions as a load circuit (quench circuit) during signal multiplication by avalanche breakdown, and has a function of suppressing the voltage supplied to the APD 201 to suppress avalanche breakdown (quench operation). The quench element 202 may be, for example, a resistance element, or a transistor or the like may function as a load.

[0020] The waveform shaping circuit 210 is connected to a node connected to the cathode or anode of the APD201 and outputs a signal based on the potential of the electrodes (cathode or anode) of the APD201. In this embodiment, the waveform shaping circuit 210 will be described later using Figures 3(a) to 3(c) to shape the potential change of the cathode of the APD201 obtained when a photon is incident on the APD201 and outputs a pulse signal. For example, an inverter circuit can be used as the waveform shaping circuit 210. In the configuration shown in Figure 2, an example is shown in which one inverter is used as the waveform shaping circuit 210, but for example, a circuit in which multiple inverters are connected in series may be used. Any circuit can be used as the waveform shaping circuit 210 as long as it can shape the potential change of the APD201 into a desired waveform.

[0021] The count circuit 211 may include a counter that counts the number of times the waveform shaping circuit 210 outputs a pulse signal, and a memory that holds the count value (number of times). When a control pulse is supplied from the vertical scanning circuit 110 via the drive line 213, the count value held in the count circuit 211 is reset.

[0022] The selection circuit 212 receives control pulses from the vertical scanning circuit 110 via the drive line 214, which switch the electrical connection between the count circuit 211 and the signal line 113. When the count circuit 211 and the signal line 113 are electrically connected, the count circuit 211 outputs a count value to the signal line 113. The selection circuit 212 may include, for example, a buffer circuit for outputting signals.

[0023] A switching element such as a transistor may be placed between the quench element 202 and the APD201, or between the photoelectric conversion unit 102 and the signal processing circuit 103, to switch the electrical connection. Similarly, the supply of voltage VH or voltage VL to the photoelectric conversion unit 102 may be electrically switched using a switching circuit such as a transistor.

[0024] In this embodiment, a configuration is shown in which a count circuit 211 is provided in the signal processing circuit 103. However, the embodiment is not limited to this. Instead of the count circuit 211, a time-to-digital converter (TDC) and memory may be used to create a photoelectric converter 100 that acquires pulse detection timing. In this case, the generation timing of the pulse signal output from the waveform shaping circuit 210 is converted into a digital signal by the TDC. The TDC may be supplied with a control pulse (reference signal) via a drive line from the vertical scanning circuit 110 to measure the timing of the pulse signal. The TDC acquires a digital signal when the input timing of the signal output from the APD201 via the waveform shaping circuit 210 is relative to the control pulse.

[0025] Figures 3(a) to 3(c) schematically illustrate the relationship between the operation of the APD201 and the output signal of the waveform shaping circuit 210. As shown in Figure 3(a), node A represents the potential of the cathode among the electrodes of the APD201. Node B represents the potential of the output of the waveform shaping circuit 210. Figures 3(b) and 3(c) show the waveform changes at nodes A and B, respectively.

[0026] Between time t0 and time t1, a voltage (VH-VL) is applied to APD201. As shown in Figure 3(b), when a photon is incident on APD201 at time t1, an avalanche current flows through the quench element 202, and the potential of node A drops. As the amount of potential drop at node A increases further and the voltage applied to APD201 decreases, the avalanche breakdown of APD201 stops, and the potential level of node A no longer drops below a predetermined value (time t2). Subsequently, a current flows from the potential supply line 251 to compensate for the potential drop at node A, and at time t3, node A settles to its original potential level. As shown in Figure 3(c), when APD201 undergoes avalanche breakdown, if the output waveform at node A exceeds a predetermined threshold, the waveform shaping circuit 210 shapes the output waveform of node A and outputs a signal (pulse signal) to node B.

[0027] In the configuration shown in Figure 1, the signal processing circuit 103 and the scanning circuit around the pixel section 101 are depicted as being formed on the same semiconductor substrate as the APD201. However, this is not the only option, and the signal processing circuit 103 and the scanning circuit around the pixel section 101 may be formed on a different semiconductor substrate from the pixel section 101 on which the APD201 is located. In that case, the substrate containing the pixel section 101 with the APD201 and pixels 104 located on it, and the substrate on which the signal processing circuit 103 and the like are located, may be stacked.

[0028] Figure 4 is an equivalent circuit diagram of the pixel 104 according to this embodiment. In Figure 4, the signal processing circuit 103 is shown up to the output of the waveform shaping circuit 210 (node ​​B). As shown in Figure 4, the pixel 104 includes a transistor 311 arranged to form a current path between the potential supply line 251 and the APD 201, and a holding circuit 300 that maintains a potential corresponding to the potential of the cathode (node ​​A), which is the electrode connected to the transistor 311 of the APD 201, when the APD 201 undergoes avalanche breakdown. Here, when it is said that the transistor is arranged to form a current path between "A" and "B", it means that "A" is connected to one main electrode that functions as the source or drain of the transistor, and "B" is connected to the other main electrode. Also, "A" and "B" are not connected to the gate of the transistor.

[0029] As shown in Figure 4, the holding circuit 300 includes node C, which is a holding node that holds a potential corresponding to the potential of node A and is connected to the gate of transistor 311; transistor 304 for resetting the potential of node C; and transistor 301, which is arranged to form a current path between node C and the potential supply line 351 and whose gate is connected to node A. The gate of transistor 311 is supplied with a potential corresponding to the potential of node A from the holding circuit 300.

[0030] In the configuration shown in Figure 4, transistor 301 is a P-type MOS transistor, and its gate is connected to node A, i.e., the cathode of APD201. Ground potential is supplied to the potential supply line 351. The threshold voltage Vtp of transistor 301 is negative. Transistor 311 is an N-type MOS transistor. The threshold voltage Vtn of transistor 311 is positive. Transistor 304 is a P-type MOS transistor. Transistor 304 is positioned to form a current path between the potential supply line 251 and node C, which is a holding node. Transistor 304 operates according to a control pulse 305 input to its gate. The control pulse 305 may be supplied from the vertical scanning circuit 110, or a control circuit supplying the control pulse 305 may be located in the photoelectric converter 100. A hold capacitor 306 is connected to node C. The hold capacitor 306 holds a potential corresponding to the potential of node A. The hold capacitance 306 may be intentionally placed as a capacitive element, but it may also be a parasitic capacitance of the wiring pattern or transistors 301 and 304. In addition, in the configuration shown in Figure 4, a quench element 202 is placed between transistor 311 and APD201.

[0031] Figure 5 is a timing diagram illustrating the operation of pixel 104 shown in Figure 4. Figure 5 shows the waveform changes of the control pulse 305 input to the gate of transistor 304, node A, and node C. In Figure 5, the timing of photon incidence on APD201 is indicated by "↓".

[0032] To explain the operation of pixel 104, we first describe the relationship between the voltages (potentials) of each component of pixel 104. The breakdown voltage Vbd of APD201 is 30V and is assumed to vary within a range of ±0.5V. The excess voltage Vex is set to 2.0V. In this case, for example, the voltage VL supplied to potential supply lines 252 and 251 is set to -30V, and the voltage VH is set to 3V. Also, the threshold voltage Vtn of transistor 311 is set to 0.2V, and the threshold voltage Vtp of transistor 301 is set to -2.2V. In other words, the threshold voltages Vtn and Vtp are set so that the difference between the absolute value of the threshold voltage Vtp of transistor 301 and the threshold voltage Vtn of transistor 311 is the excess voltage Vex (Vex = |Vtp| - Vtn).

[0033] Transistor 304 receives, for example, one control pulse 305 for each field (in Figure 5, control pulse 305 becomes L), and node C is reset to voltage VH. In other words, the interval at which control pulse 305 is supplied determines the duration of one field. While control pulse 305 is input, a reset operation is performed by transistor 304, resetting node C, which is the holding node, to voltage VH. When node C is reset, the gate potential of transistor 311 becomes voltage VH, so if a small drain current flows through transistor 311, the source potential of transistor 311, i.e., node A, becomes potential (VH-Vtn). In the example of the voltage (potential) relationship described above, the potential of node A becomes 2.8V. Even when light is not shining on APD201, a small reverse bias current flows within APD201 through a path that does not cause avalanche breakdown. Therefore, the potential of node A is considered to be 2.8V. In this case, the source-gate voltage of transistor 301 is 0.2V. This source-gate voltage of transistor 301 is a positive voltage that further turns off transistor 301, so transistor 301 is completely off.

[0034] After the reset operation of node C, when the first photon is incident on APD201, APD201 undergoes avalanche breakdown, and the reverse bias voltage applied to APD201 by the avalanche current drops to the breakdown voltage Vbd. The potential of node A at this time is denoted as potential Vb, as shown in Figure 4. If the breakdown voltage Vbd of APD201 is 30V, then potential Vb = 0V. At this time, transistor 301 turns on, and the potential of node C drops, but since the source-gate voltage of transistor 301 turns off when the threshold voltage Vtp of transistor 301 occurs, node C becomes (Vb + Vtp). In the example of the voltage (potential) relationship described above, the potential of node C becomes 2.2V. When the avalanche current has almost stopped, node A becomes (Vb + |Vtp| -Vtn) due to transistor 302. In the example of the voltage (potential) relationship described above, the potential at node A is 2.0V.

[0035] In this case, the voltage (Vbd + |Vtp| - Vtn) is applied to APD201 as a reverse bias voltage. Here, as mentioned above, (|Vtp| - Vtn) = Vex, so the voltage (Vbd + Vex) is applied to APD201 as a reverse bias voltage. In other words, even if the breakdown voltage Vbd varies for each APD201, the excess voltage Vex remains constant, and in the case of the voltage (potential) relationship described above, the desired 2.0V can be applied as the excess voltage Vex. That is, by having each pixel 104 equipped with a holding circuit 300, it becomes possible to apply the same excess voltage Vex to the APD201 of each pixel 104.

[0036] Thus, when the APD201 first undergoes avalanche breakdown after a reset operation in which node C, which is a holding node, is reset by transistor 304, the holding circuit 300 holds a potential (Vb + Vtp) corresponding to the potential of node A. Furthermore, when a second or subsequent photon is incident during the duration of one field, the potential of node A drops to potential Vb, but because transistor 301 is in the off state, node C maintains the potential (Vb + Vtp) that was held at the time of the first photon incident after the reset operation. In other words, because the potential (Vb + Vtp) held at the time of the first photon incident after node C's reset is maintained, a constant excess voltage Vex is applied to the APD201 until the next reset of node C. In this way, an excess voltage Vex corresponding to the difference between the absolute value of the threshold voltage of transistor 301 and the threshold voltage of transistor 311 is supplied to the APD201.

[0037] However, to be precise, when a second or subsequent photon is incident, a small subthreshold current flows through transistor 301, so the potential held at node C becomes slightly lower than the potential when the first photon was incident. However, as the potential at node C decreases, transistor 301 becomes less likely to turn on, so when many photons are incident, node C effectively converges to a certain constant value. If this converged value is the potential (Vb + |Vtp| - ΔV), then the threshold voltages Vtp and Vtn of transistors 301 and 311 may be set so that the potential (|Vtp| - ΔV - Vtn) becomes the desired excess voltage Vex. For example, if ΔV = 0.1V, Vtp = 2.3V and Vtn = 0.2V can be set.

[0038] In this case, APD201 with Vbd=30V is subjected to a reverse bias of 32.8V upon the first photon incidence after node C is reset, resulting in an excess voltage Vex of 2.8V. Upon the second photon incidence, a reverse bias of 32.1V is applied, and the excess voltage Vex becomes 2.1V. Thereafter, with each subsequent photon incidence, the excess voltage Vex gradually decreases from 2.1V towards 2.0V. In any case, an excess voltage Vex corresponding to the difference between the absolute value of the threshold voltage of transistor 301 and the absolute value of the threshold voltage of transistor 311 is supplied to APD201. In the following explanation, for simplicity, ΔV will be considered negligible.

[0039] If the breakdown voltage Vbd of the APD201 varies across each pixel 104, the excess voltage Vex at the time of the first photon incidence after node C reset depends on the value of the breakdown voltage Vbd. For example, an APD201 with Vbd = 29.5V will have an excess voltage Vex of 3.3V applied at the time of the first photon incidence. Similarly, an APD201 with Vbd = 30.5V will have an excess voltage Vex of 2.3V applied at the time of the first photon incidence. However, within a single field period, the value of the excess voltage Vex at the time of the second and subsequent photon incidences will be the same at 2.0V for all APD201s of each pixel 104, given the voltage (potential) relationship described above.

[0040] The fluctuating potential of node A at each pixel 104 when a photon is incident depends on the breakdown voltage Vbd of the APD201 located at each pixel 104. When the breakdown voltage Vbd is 29.5V, the lowest potential of node A when light is incident is -0.5V, and the lowest potential when light is not incident is 1.5V. When the breakdown voltage Vbd is 30.5V, the lowest potential of node A when light is incident is 0.5V, and the lowest potential when light is not incident is 2.5V. Therefore, in order for the waveform shaping circuit 210 to detect the avalanche current caused by photon incidence, the threshold voltage of the waveform shaping circuit 210 should be set between 0.5V and 1.5V. In the case of the above voltage relationship, the threshold voltage of the waveform shaping circuit 210 for detecting that a photon has been incident on pixel 104 may be, for example, 1.0V.

[0041] As described above, transistor 304 receives a control pulse 305 once per field, resetting node C. If leakage current occurs between the source or drain and well of transistors 301 and 304 connected to node C, the potential held at node C will change. Therefore, node C needs to be reset again before the effects of this leakage current become apparent. In typical semiconductor devices, this reset period can be around several tens of milliseconds, but the period for supplying the control pulse 305 can be appropriately determined according to the characteristics of transistors 301 and 304.

[0042] When operating the photoelectric converter 100, it is necessary to set the excess voltage Vex so that the APD201s, which are placed in all pixels 104, undergo avalanche breakdown in response to the incidence of photons. In this case, due to variations in the breakdown voltage Vbd of the APD201s, an excessive excess voltage Vex may be applied to APD201s with a low breakdown voltage Vbd. When an excessive excess voltage Vex is applied, the energy required for signal detection increases, resulting in increased power consumption of the photoelectric converter 100 as a whole. In addition, when an excessive excess voltage Vex is applied, the amount of light emitted during avalanche breakdown increases, leading to increased crosstalk. Furthermore, when an excessive excess voltage Vex is applied, the characteristics of the APD201 deteriorate more rapidly, reducing reliability, and the dark current of the APD201 increases, potentially leading to increased noise. Furthermore, if the excess voltage Vex applied to the APD201 of each pixel 104 varies, the probability of avalanche breakdown occurring due to photon incidence will vary, resulting in variations in sensitivity for each pixel 104.

[0043] On the other hand, as described above, the pixels 104 of the photoelectric converter 100 of this embodiment are equipped with a holding circuit 300 having a simple circuit configuration. When a parasitic capacitance is used for the hold capacitance 306 as described above, the holding circuit 300 consists of only two transistors 301 and 304. This is a much smaller circuit in scale compared to the signal processing unit and bias adjustment unit shown in Patent Document 1. With this holding circuit 300, the excess voltage Vex varies only during the first photon incidence after the reset of node C, but when detecting the second and subsequent photons, the desired excess voltage Vex is applied to the APD201 of each pixel 104. In other words, the holding circuit 300 of this embodiment makes it possible to realize a photoelectric converter 100 equipped with a SPAD element that has excellent characteristics, such as suppressed power consumption, low crosstalk, high reliability, low dark current, and low sensitivity variation.

[0044] Second Embodiment Figure 6 is an equivalent circuit diagram showing an example configuration of a pixel 104 of a photoelectric converter 100 in a second embodiment of the present disclosure. Compared to the configuration of the pixel 104 shown in Figure 4, transistor 321 is arranged to form a current path between transistor 311 and APD201. Transistor 321 is an N-type MOS transistor. Transistor 321 operates according to a control pulse 322 input to its gate. The control pulse 322 may be supplied from the vertical scanning circuit 110, or a control circuit supplying the control pulse 322 may be provided in the photoelectric converter 100. Although not shown in Figure 6, a quench element 202 may be provided between transistor 321 and APD201, similar to the first embodiment described above.

[0045] Figure 7 is a timing diagram illustrating the operation of pixel 104 shown in Figure 6. Figure 7 shows the waveform changes of the control pulse 305 input to the gate of transistor 304, the control pulse 322 input to the gate of transistor 321, and node A. In Figure 7, the timing of photon incidence on APD201 is indicated by a "↓" as in Figure 5.

[0046] In the operation shown in Figure 7, the photon count is controlled by a control pulse 322. When the control pulse 322 is input (in Figure 7, the control pulse 322 becomes H), transistor 321 turns ON. Therefore, when the control pulse 322 is H, node A is set to its initial state, and when the control pulse 322 becomes L, transistor 321 turns OFF, and node A becomes floating. When a photon is incident on APD201 while node A is floating, APD201 undergoes avalanche breakdown, and the potential of node A drops to potential Vb. In this state, when the control pulse 322 is input, the potential of node A is set again to its initial state. During the period of one field in which the control pulse 305 is input to transistor 304, multiple control pulses 322 are applied to the gate of transistor 321. In other words, as shown in Figure 7, transistor 321 repeatedly turns on intermittently, and the intervals between transistor 321 turning on are shorter than the intervals between transistor 304 turning on and resetting node C, which is the holding node.

[0047] When the control pulse 305 is input to the gate of transistor 304, and node C of the holding circuit 300 is reset, the potential of node C is voltage VH as described above. If there is no photon incidence, after node C of the holding circuit 300 is reset, the potential of node A is set to potential (VH + Vtn) by the first control pulse 322. Then, when the first photon is incident after node A is set to potential (VH + Vtn), node A drops to potential Vb, and at this time, node C is held at potential (Vb + Vtp). Thereafter, as described above, the potential of node C is potential (Vb + Vtp) until the next control pulse 305 is input. Therefore, for the second and subsequent photon incidences, the excess voltage Vex across APD201 becomes the desired voltage, such as 2.0V as described above.

[0048] In the operation shown in Figure 7, whether one photon or multiple photons are incident on the APD201 between two control pulses 322, the number of times a photon is incident will be counted as 1. Therefore, the number of incident photons detected will be less than or equal to the number of control pulses 322. However, consider the case of very strong light, in other words, when many photons are incident in a short time. In this case, in the operation of the first embodiment shown in Figure 5, the potential of node A may stick to potential Vb, preventing counting from progressing, i.e., a pile-up may occur, making it impossible to count the number of photons incident on the APD201. On the other hand, in the operation of this embodiment shown in Figure 7, even when many photons are incident in a short time, the number of photons can be counted at least as many times as the number of times the control pulse 322 is input. Also, in the operation of the first embodiment, the potential of node A instantaneously becomes potential Vb, as shown in Figure 5, except in the case of a pile-up. Therefore, it may be difficult in time to lower the potential of node C to a potential that reflects potential Vb (Vb + Vtp). On the other hand, in the operation of this embodiment, the potential of node A is potential Vb until the control pulse 322 is input after the photon is incident, and since the time during which node A is at potential Vb is extended, the potential of node C can be sufficiently lowered to potential (Vb + Vtp).

[0049] In this embodiment, as in the first embodiment, the excess voltage Vex varies only during the first photon incidence after node C is reset, but when detecting subsequent photons, the desired excess voltage Vex is applied to the APD201 of each pixel 104. Therefore, the photoelectric converter 100 equipped with the pixels 104 of this embodiment can obtain the same effects as the first embodiment described above. Furthermore, compared to the first embodiment described above, it is possible to realize a photoelectric converter 100 equipped with SPAD elements that have excellent characteristics that make pile-up less likely to occur.

[0050] Third Embodiment Figure 8 is an equivalent circuit diagram showing an example configuration of a pixel 104 of a photoelectric converter 100 in a third embodiment of this disclosure. In the first and second embodiments described above, the configuration of each holding circuit 300 was shown to be arranged in each of the multiple pixels 104. On the other hand, in the pixel shown in Figure 8, transistors 311 and 304 are shared by two pixels 104a and 104b. Node C and hold capacitance 306 are similarly shared by pixels 104a and 104b. Meanwhile, transistor 301 of the holding circuit 300 is arranged in each of the pixels 104a and 104b (transistors 301a and 301b). In addition, APD 201, quench element 202, and waveform shaping circuit 210 are arranged in each of the pixels 104. Here, we explain how two pixels 104a and 104b share transistors 311 and 304, but three or more pixels 104 may also share transistors 311 and 304. For example, four pixels 104 may share transistors 311 and 304. Because two or more pixels 104 share transistors 304 and 311, the number of components required for each pixel 104 (pixel section 101) is reduced, and the effect of the holding circuit 300 described above can be achieved even when the pixel size is relatively small. Also, although not shown in Figure 8, as described above, the count circuit 211 and other components of the signal processing circuit 103 may be shared by two or more pixels 104.

[0051] In the configuration shown in Figure 8, the potential held at node C reflects the potential (Vb+Vtp) of the pixel with the smaller breakdown voltage Vbd among the two pixels 104a and 104b. The pixel with the larger breakdown voltage Vbd among the two pixels 104a and 104b will have an excess voltage Vex smaller than the desired excess voltage Vex applied to it. However, the variation in the breakdown voltage Vbd of APD201 may be small between APD201s that are physically close to each other, and large between APD201s that are far apart. Therefore, if two or more pixels 104 that share node C are adjacent pixels 104 (for example, adjacent to each other), the desired excess voltage Vex will be applied to the APD201 of each pixel 104.

[0052] Furthermore, in the operation described in the first and second embodiments above, it was explained that at the time of the first photon incidence after the reset operation of node C, an excess voltage Vex different from the desired voltage is applied to all pixels 104. On the other hand, in this embodiment, after the reset operation of node C, an excess voltage Vex different from the desired voltage is applied to the pixel that is first incident on among the multiple pixels 104 (hereinafter sometimes referred to as shared pixels) that share transistors 304, 311, etc. However, at this time, node C, which is shared by the shared pixels, becomes at potential (Vb + Vtp). Therefore, for pixels other than the pixel that was first incident on the shared pixels, the desired excess voltage Vex is applied and the pixels operate from the time of the first photon incidence.

[0053] In this embodiment, transistors 304, 311, etc., are shared by multiple pixels 104 (shared pixels). Of the shared pixels, only the pixel 104 to which the first photon is incident after node C reset does not have an excess voltage Vex that is not the desired value. However, when detecting photons incident thereafter, the desired excess voltage Vex is supplied to the APD201 of all shared pixels. Therefore, the photoelectric converter 100 of this embodiment can obtain the same effects as the first and second embodiments described above. Furthermore, since the shared pixels share transistors 304, 311, etc., it is possible to incorporate the holding circuit 300 into the pixel 104 even when the size of the pixel 104 is small. Thus, in this embodiment as well, a photoelectric converter 100 equipped with SPAD elements with excellent characteristics can be realized.

[0054] Fourth Embodiment Figure 9 is an equivalent circuit diagram showing an example configuration of a pixel 104 of a photoelectric converter 100 in a fourth embodiment of this disclosure. In the first to third embodiments described above, an inverter was used as the waveform shaping circuit 210, but here, the details of the waveform shaping circuit 210 will be described below.

[0055] As shown in Figure 9, the waveform shaping circuit 210 of this embodiment includes transistor 401, which is an N-type MOS transistor; transistor 402, which is a P-type MOS transistor; and transistor 403, which is an N-type MOS transistor. Transistors 401 and 402 constitute an inverter 411 that receives the potential of node A, which is connected to the cathode of APD201, and outputs a signal to node B based on the potential of node A. Transistor 403 is arranged to form a current path between the inverter 411 and the potential supply line 251. More specifically, the source of transistor 402, which constitutes the inverter 411, and the potential supply line 251, which supplies voltage VH, are connected via transistor 403. The gate of transistor 403 is connected to node C, and the aforementioned potential corresponding to the potential of node A is supplied from the holding circuit 300. The source of transistor 401 is connected to the potential supply line 351.

[0056] In the first to third embodiments described above, the potential fluctuation range of node A depends on the breakdown voltage Vbd of each APD201. In the voltage (potential) relationship described above, when Vbd = 30V, the potential fluctuation range of node A is 2.8V to 0.0V for the first photon incidence and 2.0V to 0.0V for subsequent photon incidences. When Vbd = 30.5V, the potential fluctuation range of node A is 2.8V to 0.5V for the first photon incidence and 2.5V to 0.5V for subsequent photon incidences. When Vbd = 29.5V, the potential fluctuation range of node A is 2.8V to -0.5V for the first photon incidence and 1.5V to -0.5V for subsequent photon incidences. Therefore, it was explained that the waveform shaping circuit 210 is an inverter, and the threshold voltage at which the waveform shaping circuit 210 outputs a signal to node B for detecting that a photon has been incident on the APD201 is set to 1.0V.

[0057] However, two problems may arise in the waveform shaping circuit 210 used as a signal detection circuit. One is that, for the second and subsequent photons incident after the reset operation of node C, the margin of the potential fluctuation range relative to the inverter threshold voltage is narrow at 0.5V. Since 1.0V is included in all of the aforementioned potential fluctuation ranges, the avalanche current can be detected by the waveform shaping circuit 210. However, it is possible that the breakdown voltage Vbd of APD201 may vary more than ±0.5V, or that the inverter threshold voltage itself may vary, or that the inverter threshold voltage may fluctuate due to temperature. Considering these factors, a margin of 0.5V in the potential fluctuation range relative to the inverter threshold voltage may be insufficient.

[0058] The next issue to consider is through-current. A typical inverter is constructed using transistors 401 and 402 (inverter 411) for the waveform shaping circuit 210 shown in Figure 9, and transistor 403 is not included. The threshold voltages of transistors 401 and 402 that make up inverter 411 can be set to about 0.6V when the power supply voltage is about 3V. The threshold voltage values ​​of P-type MOS transistors are generally negative, but here they are written as absolute values. In reality, the threshold voltage of transistor 402 is -0.6V. The potential fluctuation range of node A is 2.0V to 0.0V for pixel 104 equipped with an APD201 with Vbd=30V (average pixel 104) when the second and subsequent photons are incident, and 1.5V to -0.5V for pixel 104 equipped with an APD201 with Vbd=29.5V. In that case, the potential of node A while waiting for the incidence of the second and subsequent photons is an average of 2.0V and a minimum of 1.5V, so a shoot-through current flows through inverter 411. Transistor 401, which is an N-type MOS transistor that makes up a typical inverter 411, turns ON when the gate potential is 0.6V or higher. Also, as mentioned above, if VH = 3.0V, transistor 402, which is a P-type MOS transistor, turns ON when the gate potential is 2.4V or lower. Therefore, both transistors 401 and 402, which are N-type and P-type, turn ON. To prevent such shoot-through current, the threshold voltage of transistor 402, which is a P-type MOS transistor, needs to be 1.5V or higher. However, if the threshold voltage of transistor 402 is increased, the driving force and response speed of inverter 411 will be impaired.

[0059] To address the potential for such problems, a waveform shaping circuit 210 including transistor 403 is provided, as shown in Figure 9. The operation of the waveform shaping circuit 210 including transistor 403 will be described below.

[0060] Here, the threshold voltage of transistor 401 is set to a typical value of 0.6V. Similarly, the threshold voltage of transistor 402 is also set to 0.6V. The threshold voltage of transistor 403 is set to 0.2V, the same as the threshold voltage of transistor 311, which is also an N-type MOS transistor. As with each of the embodiments described above, the voltage VH supplied to the potential supply line 251 is set to 3.0V. The source potential of transistor 403 is the power supply potential of the inverter 411, which is composed of transistors 401 and 402, but it is 0.2V lower than the potential of node C.

[0061] The threshold voltage of the inverter 411, which is composed of transistors 401 and 402, is set to half the power supply potential. Therefore, the threshold voltage of the waveform shaping circuit 210 changes as follows for the pixel 104 on which the APD201 with Vbd=30V is located. (1) After the reset operation of node C, until the first photon is incident Threshold voltage = 2.8V / 2 = 1.4V (2) After the first photon is incident Threshold voltage = 2.0V / 2 = 1.0V Since the potential fluctuation range of node A during the first photon injection is 2.8 to 0V, the waveform shaping circuit 210 (inverter 411) has a sufficient margin of 1.4V relative to the threshold voltage. Furthermore, since the potential fluctuation range of node A during the second and subsequent photon injections is 2.0 to 0V, the waveform shaping circuit 210 has a margin of 1.0V relative to the threshold voltage.

[0062] Next, the threshold voltage of the waveform shaping circuit 210 of pixel 104, where an APD201 with Vbd=30.5V is located, changes as follows. (1) From the time node C is reset until the first photon is incident Threshold voltage = 2.8V / 2 = 1.4V (2) After the first photon is incident Threshold voltage = 2.5V / 2 = 1.25V Since the potential fluctuation range of node A during the second and subsequent photon incidence is 2.5 to 0.5V, the margin of the waveform shaping circuit 210 with respect to the threshold voltage is 0.75V. Similarly, the margin of the waveform shaping circuit 210 with respect to the threshold voltage of pixel 104, which is equipped with an APD201 with Vbd=29.5V, is also 0.75V.

[0063] As described above, the minimum margin of the waveform shaping circuit 210 with respect to the threshold voltage in the potential fluctuation range of node A is 0.75V, which is 1.5 times larger than the 0.5V margin when the threshold voltage of the waveform shaping circuit 210 is fixed at 1.0V as described above. Furthermore, it can be seen from the above example that there is no concern about through-current.

[0064] In this way, the characteristics (circuit parameters) of the waveform shaping circuit 210 (e.g., inverter 411) change depending on the potential that reflects the breakdown voltage Vbd of the APD201 of each pixel 104 held at node C. The characteristics of this waveform shaping circuit 210 are the threshold voltage at which the waveform shaping circuit 210 outputs a signal relative to the potential of node A connected to the cathode of the APD201. This ensures an operating margin for the waveform shaping circuit 210.

[0065] In the configuration shown in Figure 9, the waveform shaping circuit 210 of this embodiment is added to the pixel 104 having the configuration shown in Figure 4 of the first embodiment described above. However, it is not limited to this, and the waveform shaping circuit 210 of this embodiment can also be applied to the pixel 104 having the configurations shown in Figures 6 and 8 described in the second and third embodiments described above.

[0066] According to this embodiment, not only are the effects of the first to third embodiments described above obtained, but the operating margin of the waveform shaping circuit 210, which functions as a signal detection circuit that detects when a photon is incident on the APD201, is widened, and concerns about through-current are also suppressed. In other words, a SPAD element with a signal detection circuit that can be used stably can be realized. As a result, the reliability of the photoelectric converter 100 is improved.

[0067] The disclosures herein include the following photoelectric conversion devices.

[0068] (Item 1) A photoelectric converter having multiple pixels, Each of the aforementioned plurality of pixels is An avalanche photodiode is placed between the first potential supply line and the second potential supply line, A first transistor is arranged to form a current path between the first potential supply line and the avalanche photodiode, The avalanche photodiode includes a holding circuit that maintains a second potential corresponding to a first potential of the electrode connected to the first transistor of the avalanche photodiode when the avalanche photodiode undergoes avalanche breakdown, A photoelectric conversion device characterized in that the second potential is supplied to the gate of the first transistor from the holding circuit.

[0069] (Item 2) The photoelectric conversion device according to item 1, characterized in that the holding circuit includes a holding node that holds the second potential and is connected to the gate of the first transistor, a second transistor for resetting the holding node, and a third transistor arranged to form a current path between the holding node and the third potential supply line, with its gate connected to the electrode.

[0070] (Item 3) The photoelectric conversion device according to item 2, characterized in that the holding circuit holds the second potential when the avalanche photodiode first undergoes avalanche breakdown after a reset operation in which the holding node is reset by the second transistor.

[0071] (Item 4) The photoelectric conversion device according to item 2 or 3, characterized in that the second transistor is arranged to form a current path between the first potential supply line and the holding node.

[0072] (Item 5) A photoelectric conversion device according to any one of items 2 to 4, characterized in that an excess voltage corresponding to the difference between the threshold voltage of the first transistor and the absolute value of the threshold voltage of the third transistor is supplied to the avalanche photodiode.

[0073] (Item 6) The photoelectric converter according to item 5, characterized in that the first transistor is an N-type MOS transistor and the third transistor is a P-type MOS transistor.

[0074] (Item 7) The first transistor and the second transistor are shared by two or more pixels among the plurality of pixels, The photoelectric conversion device according to any one of items 2 to 6, characterized in that the third transistor is arranged in each of the plurality of pixels.

[0075] (Item 8) A photoelectric conversion device according to any one of items 1 to 7, characterized in that a fourth transistor is arranged to form a current path between the first transistor and the avalanche photodiode.

[0076] (Item 19) A fourth transistor is arranged to form a current path between the first transistor and the avalanche photodiode. The fourth transistor repeatedly turns on intermittently. A photoelectric converter according to any one of items 2 to 7, characterized in that the interval at which the fourth transistor repeatedly turns on is shorter than the interval at which the second transistor turns on and resets the holding node.

[0077] (Item 10) A photoelectric conversion device according to any one of items 1 to 9, characterized in that a quench element is disposed between the first transistor and the avalanche photodiode.

[0078] (Item 11) The photoelectric converter according to any one of items 1 to 10, characterized in that each of the plurality of pixels is connected to the electrode and further includes a waveform shaping circuit that outputs a signal based on the potential of the electrode.

[0079] (Item 12) The photoelectric conversion device according to item 11, characterized in that the characteristics of the waveform shaping circuit change according to the second potential.

[0080] (Item 13) The photoelectric conversion device according to item 12, characterized in that the aforementioned characteristic is a threshold voltage at which the waveform shaping circuit outputs a signal with respect to the potential of the electrode.

[0081] (Item 14) The waveform shaping circuit includes an inverter that receives the potential of the electrodes and outputs a signal based on the potential of the electrodes, and a fifth transistor arranged to form a current path between the inverter and the first potential supply line. A photoelectric conversion device according to any one of items 11 to 13, characterized in that the second potential is supplied to the gate of the fifth transistor.

[0082] (Item 15) The photoelectric converter according to any one of items 11 to 14, characterized in that each of the plurality of pixels further includes a counting circuit that counts the number of times the waveform shaping circuit has output a signal.

[0083] The invention is not limited to the embodiments described above, and various modifications and variations are possible without departing from the spirit and scope of the invention. Accordingly, claims are attached to disclose the scope of the invention. [Explanation of symbols]

[0084] 100: Photoelectric converter, 104: Pixel, 201: Avalanche photodiode, 251, 252: Potential supply line, 300: Holding circuit, 311: Transistor

Claims

1. A photoelectric converter having multiple pixels, Each of the aforementioned plurality of pixels is An avalanche photodiode is placed between the first potential supply line and the second potential supply line, A first transistor is arranged to form a current path between the first potential supply line and the avalanche photodiode, The avalanche photodiode includes a holding circuit that maintains a second potential corresponding to a first potential of the electrode connected to the first transistor of the avalanche photodiode when the avalanche photodiode undergoes avalanche breakdown, The second potential is supplied to the gate of the first transistor from the holding circuit. The holding circuit includes a holding node that holds the second potential and is connected to the gate of the first transistor, a second transistor for resetting the holding node, and a third transistor arranged to form a current path between the holding node and the third potential supply line, with its gate connected to the electrode. A photoelectric conversion device characterized in that an excess voltage corresponding to the difference between the threshold voltage of the first transistor and the absolute value of the threshold voltage of the third transistor is supplied to the avalanche photodiode.

2. The photoelectric conversion device according to claim 1, characterized in that the holding circuit holds the second potential when the avalanche photodiode first undergoes avalanche breakdown after a reset operation in which the holding node is reset by the second transistor.

3. The photoelectric conversion device according to claim 1, characterized in that the second transistor is arranged to form a current path between the first potential supply line and the holding node.

4. The photoelectric conversion device according to claim 1, characterized in that the first transistor is an N-type MOS transistor and the third transistor is a P-type MOS transistor.

5. The first transistor and the second transistor are shared by two or more pixels among the plurality of pixels, The photoelectric conversion device according to claim 1, characterized in that the third transistor is arranged in each of the plurality of pixels.

6. The photoelectric conversion device according to claim 1, characterized in that a fourth transistor is arranged to form a current path between the first transistor and the avalanche photodiode.

7. A fourth transistor is arranged so as to form a current path between the first transistor and the avalanche photodiode. The fourth transistor repeatedly turns on intermittently. The photoelectric conversion device according to claim 1, characterized in that the interval at which the fourth transistor repeatedly turns on is shorter than the interval at which the second transistor turns on and resets the holding node.

8. The photoelectric conversion device according to claim 1, characterized in that a quench element is disposed between the first transistor and the avalanche photodiode.

9. The photoelectric converter according to claim 1, further comprising a waveform shaping circuit connected to the electrode and outputting a signal based on the potential of the electrode, each of the plurality of pixels.

10. The photoelectric conversion device according to claim 9, characterized in that the characteristics of the waveform shaping circuit change according to the second potential.

11. The photoelectric conversion device according to claim 10, characterized in that the aforementioned characteristic is a threshold voltage at which the waveform shaping circuit outputs a signal with respect to the potential of the electrode.

12. The waveform shaping circuit includes an inverter that receives the potential of the electrodes and outputs a signal based on the potential of the electrodes, and a fifth transistor arranged to form a current path between the inverter and the first potential supply line. The photoelectric conversion device according to claim 9, characterized in that the second potential is supplied to the gate of the fifth transistor.

13. The photoelectric converter according to claim 9, wherein each of the plurality of pixels further includes a counting circuit that counts the number of times the waveform shaping circuit has output a signal.

Images