Stacked complementary field-effect transistors

Abstract

A complementary field effect transistor (CFET) structure includes a first transistor disposed above a second transistor and a first source / drain region of the first transistor disposed above a second source / drain region of the second transistor, the second source / drain region including a recessed notch beneath the first source / drain region.

Description

[Technical Field]

[0001] This disclosure generally relates to stacked complementary field-effect transistors (CFETs). In particular, this disclosure relates to stacked CFETs having recessed notches formed in the epitaxially grown source-drain regions of the lower FET of the stack, wherein the notches are located directly beneath the insulating layer and the source-drain regions of the upper FET of the stack. [Background technology]

[0002] Integrated circuit (IC) chips are being formed on semiconductor wafers at increasingly smaller scales. At current technology nodes, transistor devices are constructed as three-dimensional (3D) field-effect transistor (FET) structures. However, chip manufacturers face countless challenges at 5nm, 3nm, and beyond scales. Currently, chip scaling continues to slow down as process complexity and cost increase at each node.

[0003] A complex gate-all-around technology is complementary FETs (CFETs), in which nFET and pFET nanowires / nanosheets are stacked vertically on top of each other. [Overview of the Initiative]

[0004] A summary is provided below to provide a basic understanding of one or more embodiments of this disclosure. This summary is not intended to identify any major or important elements, or to describe any specific embodiment or claim within any scope. Its sole purpose is to present the concepts in a simplified form as a prelude to the more detailed description to be presented later.

[0005] The complementary field-effect transistor (CFET) structure includes a first transistor positioned above a second transistor, and a first source / drain region of the first transistor positioned above a second source / drain region of the second transistor, the second source / drain region including a recessed notch directly below the first source / drain region.

[0006] A complementary field-effect transistor (CFET) device is formed by creating a stacked set of channel elements for a field-effect transistor, forming a lower source / drain region for a first transistor, forming a recessed notch on the upper surface of the lower source / drain region, forming an insulating layer within the notch and above the lower source / drain region, and forming a second source / drain region above the notch.

[0007] More detailed descriptions of some embodiments of this disclosure in the accompanying drawings will make the above and other purposes, features, and advantages of this disclosure more apparent, and the same references generally refer to the same components of embodiments of this disclosure. [Brief explanation of the drawing]

[0008] [Figure 1A] A schematic plan view of a device according to one embodiment of the present invention is shown. The figure shows the position of the cross-sectional lines corresponding to each of the figures 1B to 17. [Figure 1B] This diagram shows a cross-sectional view of the process for manufacturing a semiconductor device according to one embodiment of the present invention. The diagram shows a laminate in which epitaxially grown nanosheet layers have been formed and patterned. [Figure 2] This diagram shows a cross-sectional view of the manufacturing process for a semiconductor device according to one embodiment of the present invention. The diagram shows a dummy gate structure formed above a stack of nanosheet layers. [Figure 3] This diagram shows a cross-sectional view of the manufacturing process for a semiconductor device according to one embodiment of the present invention. The diagram shows the device after the sacrificial layer between the upper and lower nanosheet elements has been removed. [Figure 4]This figure shows a cross-sectional view of the manufacturing process for a semiconductor device according to one embodiment of the present invention. The figure shows the device after dielectric spacers have been added between nanosheet devices and protective dielectric sidewalls have been added to the dummy gate structure. [Figure 5] This diagram shows a cross-sectional view of the manufacturing process for a semiconductor device according to one embodiment of the present invention. The diagram shows the device after the excess dielectric material has been selectively removed from the vertical plane. [Figure 6] This diagram shows a cross-sectional view of the manufacturing process for a semiconductor device according to one embodiment of the present invention. The diagram shows the device after the individual CFET stacks have been recessed and spacers have been formed for the internal CFET stacks. [Figure 7] This figure shows a cross-sectional view of the process for manufacturing a semiconductor device according to one embodiment of the present invention. The figure shows the device after epitaxial formation of the source / drain regions for the lower nanosheet device. [Figure 8] This diagram shows a cross-sectional view of the manufacturing process for a semiconductor device according to one embodiment of the present invention. The diagram shows the device after a protective sacrificial dielectric has been deposited around the source / drain region of the lower nanosheet device. [Figure 9] This diagram shows a cross-sectional view of the manufacturing process for a semiconductor device according to one embodiment of the present invention. The diagram shows the device after a notch has been recessed into the upper surface of the source / drain region of the lower nanosheet device. [Figure 10] This diagram shows a cross-sectional view of the manufacturing process for a semiconductor device according to one embodiment of the present invention. The diagram shows the device after the sacrificial dielectric has been removed along one side of the S / D region of the lower device. [Figure 11] This figure shows a cross-sectional view of the manufacturing process for a semiconductor device according to one embodiment of the present invention. The figure shows the device after a protective dielectric has been deposited around and above the S / D region of the lower nanosheet device. [Figure 12]A cross-sectional view of a process for manufacturing a semiconductor device according to an embodiment of the present invention is shown. The figure shows the device after the source / drain regions of the upper device have been epitaxially grown. [Figure 13] A cross-sectional view of a process for manufacturing a semiconductor device according to an embodiment of the present invention is shown. The figure shows the device after the source / drain regions of the upper device have been encapsulated. [Figure 14] A cross-sectional view of a process for manufacturing a semiconductor device according to an embodiment of the present invention is shown. The figure shows the device after a high-k metal gate structure has been formed on the upper and lower devices. [Figure 15] A cross-sectional view of a process for manufacturing a semiconductor device according to an embodiment of the present invention is shown. The figure shows the device after contact vias have been formed in the source / drain regions of the upper and lower devices. [Figure 16] A cross-sectional view of a process for manufacturing a semiconductor device according to an embodiment of the present invention is shown. The figure shows the device after a sacrificial layer material adjacent to the source / drain region of the lower device has been removed. [Figure 17] A cross-sectional view of a process for manufacturing a semiconductor device according to an embodiment of the present invention is shown. The figure shows the device after contacts have been formed in the individual S / D regions. [Figure 18] A flowchart representing an operating process for forming a semiconductor device according to an embodiment of the present invention is shown.

Embodiments for Carrying Out the Invention

[0009] Some preferred embodiments will be described in more detail with reference to the accompanying drawings in which embodiments of the present disclosure are illustrated. However, the present disclosure can be implemented in various ways and should not be construed as being limited to the embodiments disclosed herein.

[0010] Aspects of the present invention will be described from the perspective of a given exemplary configuration. However, it should be understood that other architectures, structures, substrate materials, process features, and steps can be varied within the scope of the aspects of the present invention.

[0011] Also, when an element such as a layer, region, or substrate is referred to as being "on" or "above" another element, it should be understood that the element may be directly on the other element or there may also be intervening elements. In contrast, when an element is referred to as being "directly on" or "directly above" another element, there are no intervening elements. Also, when an element is referred to as being "connected" or "coupled" to another element, it should be understood that the element may be directly connected or coupled to the other element or there may be intervening elements. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements.

[0012] This embodiment may include the design of an integrated circuit chip that is created in a graphical computer programming language and can be stored on a computer storage medium (such as a disk, tape, physical hard drive, or virtual hard drive such as in a storage access network). If the designer does not manufacture the chip or the photolithography mask used in the manufacture of the chip, the designer can transmit the resulting design directly or indirectly to such an entity either physically (e.g., by providing a copy of the storage medium storing the design) or electronically (e.g., via the Internet). This stored design is then converted into a format suitable for manufacturing a photolithography mask (such as GDSII), which typically includes multiple copies of the chip design to be formed on the wafer. The photolithography mask is used to define regions of the wafer (or layers thereon or both) to be processed by etching or other methods.'

[0013] Methods such as those described herein can be used to manufacture integrated circuit chips. The resulting integrated circuit chips may be distributed by the manufacturer in the form of raw wafers (i.e., as a single wafer with multiple unpackaged chips), as bare dies, or in packaged form. In the latter case, the chips are mounted in single-chip packages (such as a plastic carrier with leads that attach to a motherboard or other higher carrier) or multi-chip packages (such as a ceramic carrier with either surface interconnects or embedded interconnects, or both). In either case, the chips are then integrated together with other chips, discrete circuit elements, and / or other signal processing devices as part of either (a) an intermediate product such as a motherboard, or (b) a final product. The final product may be any product containing integrated circuit chips, ranging from toys and other low-end applications to displays, keyboards or other input devices, and state-of-the-art computer products with central processing units.

[0014] It should be understood that material compounds can also be described in terms of the enumerated elements, such as SiGe. These compounds contain elements in different proportions; for example, SiGe can be SixGe1-x (where x is less than or equal to 1). In addition, compounds can still function according to this principle even if they contain other elements. Compounds containing additional elements are referred to as alloys in this specification.

[0015] References herein to “one embodiment,” “one embodiment,” and other variations thereof mean that the specific features, structures, characteristics, etc. described in relation to that embodiment are included in at least one embodiment. Accordingly, the phrases “in one embodiment” or “in one embodiment,” which appear in various places throughout this specification, as well as any other variations, do not necessarily all refer to the same embodiment.

[0016] Please understand that the use of any of the following " / ", "or ~ or both", and "at least one of", for example, "A / B", "A or B or both", and "at least one of A and B", is intended to include the selection of only the first-listed option (A), or only the second-listed option (B), or the selection of both options (A and B). As further examples, in the case of "A, B, and / or C", and "at least one of A, B, and C", such phrases are intended to include the selection of only the first-listed option (A), or only the second-listed option (B), or only the third-listed option (C), or only the first and second-listed options (A and B), or only the first and third-listed options (A and C), or only the second and third-listed options (B and C), or the selection of all three options (A, B, and C). This can be broadly applied in proportion to the number of items listed, as will be easily understood by those skilled in the art in this and related technologies.

[0017] The terms used herein are for the purpose of describing specific embodiments and are not intended to limit the exemplary embodiments. Where used herein, the singular forms “a,” “an,” and “the” are intended to include the plural form unless the context explicitly indicates otherwise. Where used herein, the terms “comprises,” “comprising,” “includes,” and / or “including” indicate the existence of a specified feature, integer, process, operation, element, and / or component, but do not preclude the existence or addition of one or more other features, integers, processes, operations, elements, components, and / or groups thereof.

[0018] To describe the relationship between one element or feature and another, as shown in the diagram, spatially relative terms such as “directly below,” “downward,” “below,” “upward,” and “top” may be used herein to facilitate explanation. It should be understood that spatially relative terms are intended to encompass different orientations of the device during use or operation, in addition to the orientation shown in the diagram. For example, if the device in the diagram is turned upside down, an element described as being “below” or “directly below” another element or feature will be oriented “upward” of the other element or feature. Thus, the term “downward” may include both upward and downward orientations. The device can be oriented in other ways (by rotating it 90 degrees or in other orientations), and the spatially relative descriptive terms used herein may be interpreted accordingly. In addition, it should be understood that when a layer is referred to as being “between” two layers, that layer may be the only layer between the two layers, or there may be one or more intervening layers.

[0019] While terms such as "first," "second," etc., may be used herein to describe various elements, it will be understood that these elements should not be limited by these terms. These terms are merely used to distinguish one element from another. Therefore, the first element described below can be referred to as the second element without exceeding the scope of this concept.

[0020] Examples of deposition processes for metal liners and sacrificial materials include chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or gas cluster ion beam (GCIB) deposition. CVD is a deposition process in which deposition species are formed as a result of chemical reactions between gaseous reactants at temperatures higher than room temperature (e.g., approximately 25°C to approximately 900°C). Solid products of the reactants are deposited on the surface, where a film, coating, or layer of solid products is formed. Variations of the CVD process include, but are not limited to, atmospheric pressure CVD (APCVD), reduced pressure CVD (LPCVD), plasma CVD (PECVD), and metal-organic CVD (MOCVD), and combinations thereof may also be used. In alternative embodiments using PVD, sputtering equipment may include DC diode systems, high-frequency sputtering, magnetron sputtering, or ionized metal plasma sputtering. In alternative embodiments using ALD, chemical precursors react with the material surface one at a time to deposit thin films on the surface. In an alternative embodiment using GCIB deposition, a high-pressure gas is expanded in a vacuum and then condensed into clusters. By ionizing these clusters and orienting them toward the surface, a high degree of anisotropic deposition can be achieved.

[0021] One of the complex processes for CFETs that needs to be addressed at nodes beyond 5 nm is the independent growth of source / drain epitaxy for nFETs and pFETs while maintaining vertical integration and electrical isolation. Conventional nanowire / nanosheet source / drain epitaxy processes for CFETs result in the formation of overlapping n-doped and p-doped epitaxy, making it difficult to form independent upper and lower device source / drain regions with sufficient electrical isolation to prevent short circuits or other device reliability issues caused by the proximity of the upper and lower device source / drain (S / D) regions. The disclosed embodiments provide a CFET structure having stacked S / D regions that maintains vertical integration and electrical isolation of source / drain epitaxy for nFETs and pFETs, and a method for forming a CFET.

[0022] The disclosed embodiments provide a CFET structure including source / drain regions for stacked and electrically isolated CFETs, where the physical separation of the upper and lower S / D regions is increased by recessing a portion of the lower S / D region directly beneath the upper S / D region. This provides further spacing for depositing insulating dielectric material between the S / D regions of the upper and lower devices. The disclosed embodiments are illustrated by an example embodying a nanosheet field-effect transistor. The present invention should not be considered to be limited in any way to the nanosheet structure of this example.

[0023] The following diagrams are shown. The diagrams show schematic cross-sectional views of semiconductor devices in an intermediate stage of manufacturing according to one or more embodiments of the present invention. The diagrams show a front cross-sectional view (X) and a side cross-sectional view (Y) along the cross-sectional lines X and Y of the plan view in Figure 1A. The diagrams are provided as schematic diagrams of the devices of the present invention and should not be considered accurate or limiting in terms of the scale of the device elements.

[0024] Figure 1A shows a schematic plan view of device 100 according to one embodiment of the present invention. As shown in the figure, the gate structure 12 is positioned perpendicular to the nanosheet laminate 14. Section lines X and Y indicate the viewpoints in the respective figures 1B to 17.

[0025] Figure 1B shows a schematic plan view of device 100 according to one embodiment of the present invention after material has been deposited, patterned, and selectively removed, leaving a laminate of layers, to form a nanosheet CFET device. In one embodiment, the laminate comprises alternating layers of epitaxially grown silicon germanium (SiGe) 140, 150, and silicon 130. Other materials with similar properties may be used instead of SiGe and Si.

[0026] The terms "epitaxially grow and / or deposit" and "epitaxially grown and / or deposited" refer to growing a semiconductor material on a deposition surface of a semiconductor material, where the grown semiconductor material has the same crystalline properties as the semiconductor material on the deposition surface. In the epitaxial deposition process, the chemical reactants supplied from the source gas are controlled and the system parameters are set so that the deposited atoms move around on the surface and reach the deposition surface of the semiconductor substrate with sufficient energy to orient themselves into the crystalline arrangement of atoms on the deposition surface. Thus, the epitaxial semiconductor material has the same crystalline properties as the formed deposition surface.

[0027] The nanosheet laminate includes a first semiconductor material such as SiGe in the lowermost layer and a second semiconductor material such as Si in the uppermost layer. The nanosheet laminate is shown with 10 layers (3 SiGe layers and 2 Si layers for forming the lower device, 2 SiGe layers and 2 Si layers for forming the upper device, and a high-Ge-concentration SiGe layer 150 that separates the upper device and the lower device, for example, with Ge being 50% to 70%), however, as long as the layers alternate between SiGe and Si to form the lower device and the upper device and include a high-Ge-concentration SiGe layer that separates the lower device and the upper device, any number and combination of layers can be used. The nanosheet laminate is shown as layers in the form of nanosheets, however, the width of any given nanosheet layer can be changed to be in the form of nanowires, nanoellipsoids, nanorods, etc. The SiGe layers 140, 150 can be composed of, for example, SiGe B2 , A2 , B1 , A1 and examples thereof include, but are not limited to, SiGe 20 , SiGe 25 , SiGe 30 ~SiGe 65 .

[0028] The substrate 110 can be composed of any semiconductor material known currently or developed in the future, and includes, but is not limited to, silicon, germanium, silicon carbide, and one or more III-V compound semiconductors essentially composed of a composition defined by the formula Al X1 Ga X2 In X3 As Y1 P Y2 N Y3 Sb Y4 , where X1, X2, X3, Y1, Y2, Y3, and Y4 represent relative ratios, each being zero or more, and X1 + X2 + X3 + Y1 + Y2 + Y3 + Y4 = 1 (1 is the total relative molar amount). Other suitable substrates include Zn A1 Cd A2 Se B1 Te B2Examples include II-VI compound semiconductors having the following composition, where A1, A2, B1, and B2 are relative ratios greater than or equal to zero, and A1 + A2 + B1 + B2 = 1 (where 1 is the total molar amount). An insulating layer 120 may be present on the substrate 110, and if present, it is located between the substrate 110 and the nanosheet laminate. The insulating layer 120 may be, for example, an embedded oxide layer (typically SiO2) or a lower dielectric insulating layer formed early in the process (typically SiN, SiBCN, SiOCN, SiOC, or any combination of low-k materials).

[0029] In one embodiment, each sacrificial semiconductor material layer 140 and 150 is composed of a first semiconductor material whose composition differs from that of at least the upper portion of the semiconductor substrate 110. In one embodiment, the upper portion of the semiconductor substrate 110 is composed of silicon, while each sacrificial semiconductor material layer 140 and 150 is composed of a silicon-germanium alloy. In such an embodiment, the SiGe alloy providing each sacrificial semiconductor material layer 150 has a germanium content of more than 50 atomic percent germanium. In one example, the SiGe alloy providing each sacrificial semiconductor material layer 150 has a germanium content of 50 atomic percent to 70 atomic percent germanium. In such an embodiment, the SiGe alloy providing each sacrificial semiconductor material layer 140 has a germanium content of less than 50 atomic percent germanium. In one example, the SiGe alloy providing each sacrificial semiconductor material layer 140 has a germanium content of 20 atomic percent to 40 atomic percent germanium. The first semiconductor material providing the sacrificial semiconductor material layers 140 and 150 can be formed using epitaxial growth (or a deposition process).

[0030] Each semiconductor channel material layer 130 is composed of a second semiconductor material that has a different etching rate from the first semiconductor material of the sacrificial semiconductor material layers 140 and 150, and also has resistance to Ge enrichment. The second semiconductor material of each semiconductor channel material layer 130 may be the same as, or different from, the semiconductor material of at least the upper part of the semiconductor substrate 110. The second semiconductor material may be a SiGe alloy, provided that the SiGe alloy has a germanium content of less than 50 atomic percent germanium, and the first semiconductor material is different from the second semiconductor material.

[0031] In one example, at least the upper portion of the semiconductor substrate 110 and each semiconductor channel material layer 130 are composed of Si or a III-V compound semiconductor, while each sacrificial semiconductor material layer 140, 150 are composed of a silicon-germanium alloy. The second semiconductor material of each semiconductor channel material layer 130 can be formed using epitaxial growth (or a deposition process).

[0032] After depositing a laminate of layers 130, 140, and 150 across the surface of the device die, the layers are patterned and selectively etched using processes such as lithography masking to produce a fin pattern for the device, which includes a laminate of nanosheets of the upper and lower devices separated by a sacrificial layer of semiconductor material. Such a laminate defines the active region of the device.

[0033] Figure 2 shows device 100 after forming at least one dummy gate structure on a nanosheet laminate. Three dummy gates are illustrated, however, any number of gates can be formed. The dummy gate structure can be formed by depositing a dummy gate material 210 on the nanosheet laminate. The dummy gate material may be, for example, a thin layer of oxide followed by polycrystalline silicon, amorphous silicon, or microcrystalline silicon. Subsequently, a hard mask layer 220 is deposited on the dummy gate, followed by lithography patterning, masking, and etching processes.

[0034] In one embodiment, the hard mask 220 comprises a nitride, an oxide, an oxide-nitride bilayer, or another preferred material. In some embodiments, the hard mask 220 may include oxides such as silicon oxide (SiO), nitrides such as silicon nitride (SiN), oxynitrides such as silicon oxynitride (SiON), combinations thereof, and the like. In some embodiments, the hard mask 220 is silicon nitride such as Si3N4.

[0035] Figure 3 shows the device 100 after selective removal of the sacrificial layer 150 that separates the upper and lower FET devices of the CFET. In one embodiment, because the Ge concentration of the sacrificial layer 150 is higher than that of the sacrificial layer 140 or the channel layer 130, the high Ge concentration SiGe in layer 150 can be selectively etched off without removing the sacrificial layer 140 or the channel layer 130.

[0036] Figure 4 shows device 100 after conformally depositing and selectively etching a spacer material to fill the void left by removing layer 150. The spacer material 410 further forms sidewall spacers along the sidewalls of the dummy gate structure 210, the hard mask 220, and the sidewalls of the nanosheet laminate in the S / D epitaxial region. In one embodiment, the spacer material 410 may be the same material as the hard mask 220 or a different material, and may consist of one or more of various different insulating materials such as Si3N4, SiBCN, SiNC, SiN, SiCO, SiO2, SiNOC, etc. In this embodiment, after conformal deposition, the spacer material 410 is removed from the horizontal surface of the intermediate layer of device 100 by selective etching, such as anisotropic reactive ion etching.

[0037] Figure 5 shows device 100 after selective removal of spacer sidewalls 410 from a stack of nanosheets 130-140. In one embodiment, anisotropic etching is used to selectively remove vertical sidewall spacers from the nanosheet stack. In one embodiment, after partially removing the spacer material 410 from the hard mask 220, a protective cap 510 is formed by depositing a material such as SiC or SiO2 on the exposed vertical surface of the hard mask 220 to protect against excessive removal of the spacer material 410 from the dummy gate 210 and the hard mask 220.

[0038] In one embodiment, forming the protective cap 510 involves depositing a sacrificial material such as OPL onto the wafer, then etching back the OPL to expose the upper portion of the gate spacers 410 on the sidewalls of the hard mask 220, while leaving the OPL completely covering the spacers on the sidewalls of the nanosheet laminate in the S / D region. Subsequently, after selectively removing the exposed spacers 410, the protective cap 510 is deposited and anisotropic etch-back is performed. The removal of the sacrificial material (OPL) is performed, for example, by an N2 / H2 ashing process. Finally, an anisotropic spacer etch process can be performed to etch down the sidewall spacers of the nanosheet laminate in the S / D region without pulling down the gate sidewall spacers 410 beneath the protective cap 510.

[0039] Figure 6 shows device 100 after the nanosheet laminate layers 130, 140 and spacer layer 410 have been recessed to form an S / D cavity for the CFET device. Figure 6 further shows device 100 after internal spacers have been formed between the nanosheets of each FET device. The portions of nanosheet laminates 130, 140, and 410 that are not directly beneath the gate spacer 410 and not directly beneath the dummy gate 210 are removed. Etching generally refers to the removal of material from a substrate (or a structure formed on a substrate), and is often performed with a mask in place so that material can be selectively removed from specific areas of the substrate while leaving unaffected material in other areas of the substrate.

[0040] Generally, there are two categories of etching: (i) wet etching and (ii) dry etching. Wet etching is performed using a solvent (such as an acid) which can be chosen for its ability to selectively dissolve a given material (such as an oxide) while leaving another material (such as polysilicon) relatively intact. This ability to selectively etch a given material is fundamental to many semiconductor manufacturing processes. While wet etching generally etches homogeneous materials (e.g., oxides) isotropically, it can also etch single-crystal materials (e.g., silicon wafers) anisotropically. Dry etching can be performed using plasma. Plasma systems can be operated in multiple modes by adjusting the plasma parameters. In typical plasma etching, strong free radicals with a neutral charge are generated, and these free radicals react on the surface of the wafer. Because the neutral particles attack the wafer from all angles, this process is isotropic. Ion milling, or sputter etching, involves bombarding a wafer with energetic ions from a rare gas. Because these ions approach the wafer from almost one direction, the process exhibits a high degree of anisotropy. Reactive ion etching (RIE) operates under conditions intermediate between sputter etching and plasma etching.

[0041] Generally, after etching the nanosheet laminate, the portion directly beneath the gate spacer 410 is removed by selectively etching the SiGe layer 140 of the nanosheet laminate. An internal spacer 610 is then formed in the etched portion, thereby positioning the internal spacer 610 below the gate spacer 410. The internal spacer 610 can be made of any suitable dielectric material, such as Si3N4, SiBCN, SiNC, SiN, SiCO, SiO2, SiNOC, etc. Since the internal spacer is formed by isotropic etch-back after depositing a conformal dielectric liner, the dielectric liner is removed everywhere except in areas that are pinched off within the spacer cavity.

[0042] Figure 7 shows the device 100 after epitaxial growth of the source / drain region 710 for the lower FET device of the CFET. In one embodiment, a pair of epitaxial source / drain regions are formed on opposing sides of the nanosheet stack and the dummy gate structure. In one embodiment, boron-doped SiGe (SiGe:B) is epitaxially grown from an exposed semiconductor surface (layer 130). In one embodiment, a sacrificial material such as OPL is deposited to cover the sidewalls of the lower nanosheet channel 130. Then, a thin sacrificial spacer such as SiO2 or SiN covers the sidewalls of the upper nanosheet channel 130. The sacrificial material such as OPL can be removed by ashing with N2 / H2, after which the lower S / D 710 is epitaxially grown. Subsequently, the sacrificial spacer can be removed from the sidewalls of the upper nanosheet channel 130.

[0043] In this embodiment, the source / drain region 710 can be doped in situ by adding one or more dopant species to the epitaxial material. The dopants used depend on the type of FET being formed, whether p-type or n-type. As used herein, “p-type” refers to the addition of impurities to an intrinsic semiconductor that cause valence electron depletion. In silicon-containing semiconductors, examples of p-type dopants, i.e., impurities, include, but are not limited to, boron, aluminum, gallium, and indium. As used herein, “n-type” refers to the addition of impurities to an intrinsic semiconductor that confer free electrons. In silicon-containing substrates, examples of n-type dopants, i.e., impurities, include, but are not limited to, antimony, arsenic, and phosphorous acid. In one embodiment, the upper S / D region of the device contains n-type material, and the lower region contains p-type material.

[0044] Figure 8 shows TiO around the lower source / drain 710. xThe device 100 is shown after a sacrificial spacer layer 810, such as (TiO2), has been deposited and recessed. Layer 810 protects the lower S / D region 710 while etching the isolation notch within the source / drain region 710. This can be achieved by conformally depositing the sacrificial spacer 810 to pinch off the space between the gates, or by simply overfilling the sacrificial spacer material and then CMPing. A recess process is then applied to the sacrificial spacer layer 810 to expose the upper portion of the S / D epi 710.

[0045] Figure 9 shows device 100 after selective etching of the exposed portion of the lower source / drain region 710 to form a notch-like separation between the lower S / D region and the corresponding upper S / D region 710.

[0046] Figure 10 shows device 100 after selectively masking the sacrificial layer 810 with OPL1010, and then removing the sacrificial material 810 located to the left of the lower S / D region 710 in cross-sectional view Y. The OPL1010 is then removed.

[0047] Figure 11 shows the device 100 after the insulating layer 1110 has been deposited above and around the lower S / D region 710, and above the sacrificial layer 810, then CMP'd and recessed. In one embodiment, the insulating layer 1110 is composed of a material such as SiO2, SiN, SiOC, and combinations thereof.

[0048] Figure 12 shows device 100 after epitaxial growth of the S / D region 1210 of the paired upper device. In one embodiment, the S / D region for the nFET device of the CFET is provided by epitaxial growth of phosphorous acid-doped Si(Si:P). The S / D region 1210 is in contact with the nanosheet layer 130 of the upper FET device.

[0049] The disclosed example provides for the manufacture of a CFET device having an upper nFET and a lower pFET. In one embodiment, the CFET includes an upper pFET and a lower nFET. In this embodiment, the desired patterns of the nFET and pFET for the CFET device are obtained by appropriately doping the upper and lower S / D regions.

[0050] Figure 13 shows the device 100 after CMP (Chemical Manufacturing) of interlayer dielectric (ILD) material 1310 deposited around and above the upper S / D epitaxy, dummy gate, and gate spacer 410. The figure shows the device after CMP has removed the protective cap 510 and hard mask 220 from the dummy gate structure 210, exposing the top surface of the material of the dummy gate 210. In one embodiment, the ILD 1310 is composed of materials such as SiO2, SiN, SiOC, and combinations thereof.

[0051] Figure 14 shows device 100 after the dummy gate 210 and sacrificial SiGe 140 have been removed and a high-k metal gate (HKMG) laminate 1410 and a protective gate dielectric cap 1420 have been formed. As shown in the figure, the replacement metal gate structure is formed in the void created by removing the dummy gate 210 and the sacrificial SiGe layer 140. The gate structure 1410 includes a gate dielectric layer and a gate metal layer (not shown). The gate dielectric is generally a thin film and can be silicon oxide, silicon nitride, silicon oxynitride, boron nitride, SiOCN, SiBCN, SiOC, SiCN, high-k material, or any combination of these materials. Examples of high-k materials include, but are not limited to, metal oxides such as hafnium oxide, silicon hafnium oxide, silicon hafnium oxynitride, lanthanum oxide, aluminum lanthanum oxide, zirconium oxide, silicon zirconium oxide, silicon zirconium oxynitride, tantalum oxide, titanium oxide, titanium barium strontium oxide, titanium barium oxide, titanium strontium oxide, yttrium oxide, aluminum oxide, scandium tantalum lead oxide, and zinc lead niobate. High-k materials may further include dopants such as lanthanum, aluminum, and magnesium. The gate dielectric can be deposited by CVD, ALD, or any other suitable technique. The metal gate may include any known metal gate material known to those skilled in the art, such as TiN, TiAl, TiC, TiAlC, tantalum (Ta) and tantalum nitride (TaN), W, Ru, Co, and Al. The metal gate can be formed by known deposition techniques such as atomic layer deposition, chemical vapor deposition, or physical vapor deposition. It should be understood that a chemical mechanical planarization (CMP) process can be applied to the top surface.

[0052] In one embodiment, the substitutional metal gate comprises a work function metal (WFM) layer (e.g., titanium nitride, titanium aluminum nitride, titanium aluminum carbide, titanium aluminum carbonitride, and tantalum nitride), as well as other suitable metal and conductive metal layers (e.g., tungsten, cobalt, tantalum, aluminum, ruthenium, copper, metal carbides, and metal nitrides). After forming and CMPing the HKMG1410, the HKMG1410 can optionally be recessed, and then the manufacturing step of the substitutional metal gate of the device is completed by depositing and CMPing the gate dielectric material 1420.

[0053] Figure 15 shows device 100 after contact vias 1510 have been formed from the upper ILD surface to the upper surface of the S / D region 910 and the upper surface of the sacrificial material layer 810 of the upper device. The figure further shows that a common contact via has been formed between the upper S / D region and the lower S / D region on the left side of the cross-sectional view X of the figure.

[0054] Figure 16 shows device 100 after the sacrificial material 810 has been removed from the portion adjacent to the S / D region 710 of the lower device. As shown in the cross-sectional view Y of the figure, the sacrificial semiconductor material 810 has been removed, exposing the S / D region 710 of the lower device.

[0055] Figure 17 shows device 100 after depositing a metal S / D contact 1710 within the contact vias of the S / D region. In one embodiment, the contact is formed by depositing a silicide liner such as Ti, Ni, Co, or NiPt, followed by an adhesive metal liner such as a thin layer of TiN, followed by a conductive metal such as Cu, Ag, Au, W, Co, or Ru, or a combination thereof. The shape of the contact reduces contact resistance by increasing the surface area of ​​the silicide between the contact and the S / D epitaxial region including the S / D region.

[0056] Figure 18 shows a flowchart 1800 of a manufacturing process according to one embodiment of the present invention. As shown in flowchart 1800, a set of nanosheets for a CFET device is formed in block 1810. A laminate of alternating nanosheet layers of different semiconductor materials is epitaxially grown on a lower substrate or on an insulating layer placed on the substrate. The laminate includes a sacrificial layer and a channel layer. The channel layer forms the nanosheets for the upper and lower FETs of the CFET. This layer is patterned and etched to form fins on the lower substrate. A dummy gate structure, including sidewall spacers, is added to the tops and along the fins. The nanosheet layers are recessed to align with the dummy gate spacers and internal spacers are formed between the nanosheet channel layers to isolate the gate from the S / D region of the device.

[0057] In block 1820, the S / D region for the lower device is epitaxially grown on the device in contact with the nanosheet channel layer. The S / D region is patterned and etched back to form the final lower S / D region in contact with the nanosheet channel layer of the lower FET. Before growing the lower S / D region, the semiconductor channel of the upper device is protected by a thin layer of sacrificial protective material.

[0058] In block 1830, recesses are formed on the upper surface of the S / D region of the lower device. These notches provide further physical separation between the S / D regions of the upper and lower devices, reducing the possibility of short circuits between the respective S / D regions. Sacrificial layer material is deposited around the lower S / D region, leaving a portion of the S / D region exposed. The exposed portion is then selectively etched away and further recessed to create separation notches.

[0059] In block 1840, an insulating layer is formed above the lower S / D region. The insulating layer is formed around and above the S / D region and the remaining sacrificial material layer of the lower device. The insulating layer fills the recessed notch of the S / D region of the lower device and covers the remaining sacrificial layer material.

[0060] In block 1850, the S / D region of the upper device is formed on the upper surface of the insulating layer from the semiconductor nanosheet channel of the upper device.

[0061] In block 1860, an HKMG structure is formed as a replacement for the dummy gate structure. This is completed by removing the dummy gate, depositing a high-k layer, depositing a work function metal, and then depositing a sacrificial protective cap on top of the HKMG structure.

[0062] In block 1870, independent source / drain contacts for the CFET device are formed. Vias are etched through the protective dielectric material layer to expose the upper S / D region and the sacrificial material positioned around the lower S / D region on the first side of the device. The first via exposes the upper S / D region on one side of the device. The second via exposes the material adjacent to the lower S / D region on the same side of the device. The sacrificial material is then removed to expose the lower S / D region. A third common via exposes the upper and lower S / D regions on the other side of the device. Contact metal is then placed within the vias to provide electrically independent contacts to the upper and lower S / D regions of the device, respectively.

[0063] The flowcharts and block diagrams in the figures illustrate the architecture, function, and operation of executable implementations of systems, methods, and device manufacturing processes according to various embodiments of the present invention. In this regard, each block in the flowchart or block diagram may represent a module, segment, or part of an instruction that includes one or more manufacturing processes for manufacturing the specified device. In some alternative implementations, the functions mentioned within a block may occur regardless of the order in which they are mentioned in the figure. For example, two blocks shown consecutively may actually be executed substantially simultaneously, or blocks may be executed in reverse order depending on the functionality involved.

[0064] References in this specification to “one embodiment,” “one example,” or “exemplary embodiment” indicate that the described embodiments may include certain features, structures, or characteristics, but not all embodiments may necessarily include such features, structures, or characteristics. Furthermore, such phrases do not necessarily refer to the same embodiment. Moreover, where certain features, structures, or characteristics are described in relation to an embodiment, it is presented that any influence on such features, structures, or characteristics in relation to other embodiments, whether explicitly stated or not, is within the knowledge of those skilled in the art.

[0065] For illustrative purposes, various embodiments of the present invention have been described, but are not intended to be comprehensive or limitless to the disclosed embodiments. Numerous modifications and variations will be apparent to those skilled in the art without departing from the scope of the invention. The terms used herein have been selected to best describe the principles of the embodiments, their practical applications or technical improvements to the art found in the market, or to enable other those skilled in the art to understand the embodiments disclosed herein.

Claims

1. A CFET (complementary field-effect transistor) structure, The first transistor is positioned above the second transistor, The first source / drain region of the first transistor is positioned above the second source / drain region of the second transistor and Includes, The second source / drain region includes a notch recessed directly below the first source / drain region, the notch having a wall surface and a bottom surface located below the upper surface of the second source / drain region. The first dielectric material is further disposed within the notch and in contact with the bottom surface of the first source / drain region. CFET structure.

2. The CFET structure according to claim 1, further comprising a metal contact positioned in contact with the first source / drain region.

3. The CFET structure according to claim 1, further comprising a second metal contact positioned in contact with the second source / drain region.

4. The CFET structure according to claim 1, further comprising a metal gate structure disposed adjacent to the first source / drain region and the second source / drain region.

5. The CFET structure according to claim 1, wherein the first transistor includes an nFET.

6. The CFET structure according to claim 1, wherein the first transistor includes a pFET.

7. A CFET (complementary field-effect transistor) structure, The first transistor is positioned above the second transistor, The first source / drain region of the pair of first transistors is positioned above the second source / drain region of the pair of second transistors and Includes, Each of the pair of second source / drain regions includes a notch recessed directly below the corresponding first source / drain region, the notch having a wall and a bottom surface located below the upper surface of the second source / drain region, The present invention further includes a first dielectric material disposed between the first transistor and the second transistor, wherein the first dielectric material is disposed in the notch. CFET structure.

8. The CFET structure according to claim 7, further comprising a first metal contact positioned in contact with one of the first source / drain regions.

9. The CFET structure according to claim 7, further comprising a second metal contact positioned in contact with one of the second source / drain regions.

10. The CFET structure according to claim 7, further comprising a metal gate structure disposed between the pair of first source / drain regions and the pair of second source / drain regions.

11. The CFET structure according to claim 7, wherein the first transistor includes an nFET.

12. The CFET structure according to claim 7, wherein the first transistor includes a pFET.

13. A method for manufacturing semiconductor devices, Forming a stacked set of channel elements for a field-effect transistor, To form a first source / drain region for the first transistor, A notch recessed in the upper surface of the first source / drain region, the notch having a wall surface and a bottom surface located below the upper surface of the first source / drain region, An insulating layer is formed within the notch and above and around the first source / drain region, To form a second source / drain region for a second transistor on the insulating layer above the notch. A method that includes this.

14. A method for manufacturing a semiconductor device according to claim 13, further comprising forming a complementary field-effect transistor stack including the first transistor and the second transistor.

15. A method for manufacturing a semiconductor device according to claim 13, further comprising forming a first source / drain contact connected to the first source / drain region.

16. A method for manufacturing a semiconductor device according to claim 13, further comprising forming a second source / drain contact connected to the source / drain region of the second transistor.

17. The method for manufacturing a semiconductor device according to claim 13, wherein the first transistor includes an nFET.

18. The method for manufacturing a semiconductor device according to claim 13, wherein the first transistor includes a pFET.

Images