Power converter

Abstract

A power conversion device (1) comprises: a power converter (10) configured to have a plurality of leg circuits (100u, 100v, 100w) which are connected in parallel and in which positive-side arms and negative-side arms (110) are connected in series; and a control device (20) for controlling the power converter (10). The control device (20): generates an arm output voltage command value (Varm) that is a command value for a voltage to be outputted by the plurality of arms (100); controls the circulating current for each of the leg circuits (100u, 100v, 100w); makes a correction, with a voltage command correction value (ΔVarm), when a voltage total value (Vcu, Vcv, Vcw) of a direct current capacitor (111C) included in at least one leg circuit (100u, 100v, 100w) is at or above a first threshold value (δ1), so that in said leg circuit (100u, 100v, 100w), the arm output voltage command value (Varm) of one of the arms will come to an upper threshold value (Vcp, Vcn) or below if exceeding the upper threshold value, and will come to a lower threshold value (0 V) or above if being under the lower threshold value; and also corrects the arm output voltage command value (Varm) of the other of the arms on the basis of the correction voltage (ΔVarm).

Description

Technical Field

[0001] This application relates to a power conversion device.

Background Art

[0002] In recent years, in power conversion devices used for high-voltage applications such as power systems, practical application of a multilevel converter configured by connecting a plurality of converter cells each having an energy storage element in series multiple connection has been attempted. These converters are called a modular multilevel converter (MMC) method, a cascaded multilevel converter (CMC) method, etc., and are used for conversion from three-phase alternating current to direct current or vice versa.

[0003] In a power conversion device having a capacitor as an energy storage element, it is possible to suppress voltage fluctuations. However, if the capacitance of the capacitor is small, the voltage applied to the switching element constituting the converter cell may exceed the withstand voltage of the switching element. Therefore, increasing the capacitance of the capacitor or increasing the withstand voltage of the switching element increases the cost of the power conversion device or increases its size.

[0004] In response to such problems, Patent Document 1 discloses adjusting the circulating current flowing through the arm unit constituting the power conversion device so that the average value of the capacitor voltage in each arm unit is constant and suppressing the fluctuation range.

[0005] Also, the applicant has disclosed in Patent Document 2 correcting the arm voltage command value using a zero-phase voltage command value so as not to exceed the arm output voltage range.

Prior Art Documents

Patent Documents

[0006]

Patent Document 1

[0007] On the other hand, if there is significant overmodulation during or immediately after an accident, fluctuations in the system voltage to which the power converter is connected or an imbalance in the capacitor voltage may prevent each arm from outputting the voltage it is supposed to output, resulting in an unexpected current flow. In that case, the imbalance in the capacitor voltage may not be resolved, and there is a risk that the power converter may not be able to continue operating.

[0008] This application discloses technology to solve the above-mentioned problems and aims to provide a power conversion device that can quickly balance the imbalance in the capacitor voltage between arms. [Means for solving the problem]

[0009] The power conversion device disclosed in this application is A power converter comprising a power converter that performs power conversion between multiple phases of AC and DC, wherein multiple leg circuits, each having a positive arm and a negative arm connected in series, are connected in parallel, and the connection points between the positive and negative arms of the multiple leg circuits are connected to the AC lines of each phase; and a control device that controls the power converter, Each of the positive and negative arms has one or more converter cells connected in series, each having a series unit in which a plurality of semiconductor switching elements are connected in series and a DC capacitor connected in parallel to this series unit. The control device has an arm output voltage command value generation unit that generates an arm output voltage command value, which is a command value of the voltage output by the plurality of arms. Circulation current control is performed for each of the aforementioned leg circuits. When the sum of the voltages of all DC capacitors included in at least one of the leg circuits is equal to or greater than a preset first threshold, the leg circuit generates and corrects a voltage command correction value to correct the arm output voltage command value of one of the positive arm and the negative arm such that if the arm output voltage command value exceeds a preset upper threshold, it becomes equal to or less than the upper threshold, and if the arm output voltage command value falls below a preset lower threshold, it becomes equal to or greater than the lower threshold. The configuration is such that the arm output voltage command value of the other arm of the leg circuit, which is being controlled for circulating current, is corrected based on the voltage command correction value. [Effects of the Invention]

[0010] The power conversion device according to this disclosure makes it possible to quickly balance the imbalance in the capacitor voltage between arms. [Brief explanation of the drawing]

[0011] [Figure 1] This is a schematic diagram showing the configuration of the power conversion device according to Embodiment 1. [Figure 2A] This is a configuration diagram showing an example of a converter cell that constitutes a power conversion device according to Embodiment 1. [Figure 2B] This is a configuration diagram showing another example of a converter cell that constitutes the power conversion device according to Embodiment 1. [Figure 2C] This is a configuration diagram showing another example of a converter cell that constitutes the power conversion device according to Embodiment 1. [Figure 3] This is a functional block diagram showing the configuration of the control device according to Embodiment 1. [Figure 4] This diagram shows the state in which the generated modulated signal is input to the gate signal generation unit. [Figure 5] This is a functional block diagram showing the configuration of the command generation unit of the control device according to Embodiment 1. [Figure 6] This diagram shows the configuration of the voltage command value correction unit according to Embodiment 1. [Figure 7]This is a diagram showing the configuration of the correction voltage calculation unit according to Embodiment 1. [Figure 8A] This is a diagram for explaining the effect of the power conversion device according to Embodiment 1. [Figure 8B] In FIG. 8A, it is an enlarged view of the regions of the broken lines A and B. [Figure 9] This is a functional block diagram showing the configuration of the command generation unit of the control device according to Embodiment 2. [Figure 10] This is a diagram showing the configuration of the voltage command value correction unit according to Embodiment 2. [Figure 11] This is a diagram showing the configuration of the correction voltage calculation unit according to Embodiment 2. [Figure 12] This is a diagram for explaining the correction margin of the correctable voltage calculated by the correction voltage calculation unit. [Figure 13] This is a diagram showing the configuration of the correction zero-phase voltage calculation unit according to Embodiment 2. [Figure 14] This is a hardware configuration diagram which is an example of the control device according to Embodiments 1 and 2.

Embodiments for Carrying out the Invention

[0012] Hereinafter, the present embodiment will be described with reference to the drawings. In each figure, the same reference numerals denote the same or corresponding parts.

[0013] <统一码注释: Embodiment 1. Hereinafter, the power conversion device according to Embodiment 1 will be described with reference to the drawings. <Configuration of the Power Conversion Device> Figure 1 is a diagram illustrating the schematic configuration of an example of a power system to which the power converter 1 according to Embodiment 1 is applied. As shown in Figure 1, the power converter 1 comprises a power converter 10 which is the main circuit, and a control device 20 which is the control unit for controlling the power converter 10. The power converter 10 converts power between alternating current (AC) and direct current (DC). Its AC side is connected to an AC power source 2 which is a three-phase AC system as a multi-phase AC system via a transformer 3, and its DC side is connected to a DC system (not shown) via a positive DC terminal 6P and a negative DC terminal 6N. The DC system is, for example, a DC power source such as a large-scale solar power generation system or an industrial UPS (Uninterruptible Power Supply), or another power converter.

[0014] The power converter 10 is equipped with three leg circuits 100u, 100v, and 100w, each corresponding to the U, V, and W phases of the three-phase AC, connected in parallel between the positive DC terminal 6P and the negative DC terminal 6N. The leg circuit 100u has a pair of arms, a positive arm 100uP and a negative arm 100uN, which are connected in series with each other. One end of the positive arm 100uP is connected to the positive DC terminal 6P, and one end of the negative arm 100uN is connected to the negative DC terminal 6N. The connection point 4u between the positive arm 100uP and the negative arm 100uN is connected to the U-phase terminal of the transformer 3.

[0015] The REG circuit 100V has a pair of arms, a positive arm 100vP and a negative arm 100vN, which are connected in series with each other. One end of the positive arm 100vP is connected to the positive DC terminal 6P, and one end of the negative arm 100vN is connected to the negative DC terminal 6N. The connection point 4v between the positive arm 100vP and the negative arm 100vN is connected to the V-phase terminal of the transformer 3.

[0016] The REG circuit 100w has a pair of arms, a positive arm 100wP and a negative arm 100wN, which are connected in series with each other. One end of the positive arm 100wP is connected to the positive DC terminal 6P, and one end of the negative arm 100wN is connected to the negative DC terminal 6N. The connection point 4w between the positive arm 100wP and the negative arm 100wN is connected to the W phase terminal of the transformer 3.

[0017] The configurations of each leg circuit 100u, 100v, and 100w will be described below. Since the V-phase and W-phase leg circuits 100v and 100w have the same configuration as the U-phase leg circuit 100u, the U-phase leg circuit 100u will be used as a representative example for explanation. The positive arm 100uP of the leg circuit 100u has multiple series-connected converter cells 111 and a reactor 112uP, and these multiple converter cells 111 and reactor 112uP are connected in series with each other. Similarly, the negative arm 100uN of the leg circuit 100u has multiple series-connected converter cells 111 and a reactor 112uN, and these converter cells 111 and reactor 112uN are connected in series with each other. Note that there may be only one converter cell 111 in each arm.

[0018] Furthermore, the reactor 112uP may be located at any position within the positive arm 100uP, and similarly, the reactor 112uN may be located at any position within the negative arm 100uN. The inductance values ​​of reactors 112uP and 112uN may be different from each other, and they may be coupled with reactors of other phases. Moreover, the reactor 112uP may be provided only within the positive arm 100uP, or the reactor 112uN may be provided only within the negative arm 100uN. In the following explanation, unless it is necessary to distinguish between the positive arms 100uP, 100vP, and 100wP, and the negative arms 100uN, 100vN, and 100wN, they will be referred to as arm 100, or positive arm 100P, and negative arm 100N.

[0019] The following describes the configuration of the converter cell 111 that makes up each leg circuit 100u, 100v, and 100w. Figure 2A is a circuit diagram showing an example of the configuration of the converter cell 111 according to Embodiment 1. Figure 2B is a circuit diagram showing a different configuration example of the converter cell 111 according to Embodiment 1 from Figure 2A. Figure 2C is a circuit diagram showing a different configuration example of the converter cell 111 according to Embodiment 1 from Figures 2A and 2B. The converter cell 111 may use any of the circuit configurations shown in Figures 2A to 2C, and the various circuit configurations may be combined within the positive arm 100uP and the negative arm 100uN.

[0020] The converter cell 111 shown in Figure 2A comprises a series configuration of semiconductor switching elements 111U and 111L connected in series, a DC capacitor 111C as an energy storage element connected in parallel to this series configuration, and a voltage sensor 111S for detecting the voltage Vcap of the DC capacitor 111C. The connection point between semiconductor switching elements 111U and 111L is connected to the positive input / output terminal 111a, and the connection point between semiconductor switching element 111L and DC capacitor 111C is connected to the negative input / output terminal 111b.

[0021] In the converter cell 111 with the configuration shown in Figure 2A, the semiconductor switching elements 111U and 111L are controlled by gate signals GU and GL such that one is ON and the other is OFF. When semiconductor switching element 111U is ON and semiconductor switching element 111L is OFF, the voltage across the DC capacitor 111C is applied between the input / output terminals 111a and 111b. A positive voltage is applied to input / output terminal 111a and a negative voltage is applied to input / output terminal 111b.

[0022] Furthermore, the converter cell 111 shown in Figure 2B comprises a series configuration of semiconductor switching elements 111U and 111L connected in series, a DC capacitor 111C as an energy storage element connected in parallel to this series configuration, and a voltage sensor 111S for detecting the voltage value Vcap of the DC capacitor 111C. The connection point between semiconductor switching elements 111U and 111L is connected to the negative input / output terminal 111b, and the connection point between semiconductor switching element 111U and DC capacitor 111C is connected to the positive input / output terminal 111a.

[0023] In the converter cell 111 with the configuration shown in Figure 2B, the semiconductor switching elements 111U and 111L are controlled by gate signals GU and GL such that one is ON and the other is OFF. When semiconductor switching element 111U is OFF and semiconductor switching element 111L is ON, the voltage across the DC capacitor 111C is applied between the input / output terminals 111a and 111b. A positive voltage is applied to input / output terminal 111a and a negative voltage is applied to input / output terminal 111b.

[0024] Furthermore, the converter cell 111 with the configuration shown in Figure 2C includes a series of semiconductor switching elements 111U1 and 111L1 connected in series with each other, a series of semiconductor switching elements 111U2 and 111L2 also connected in series with each other, a DC capacitor 111C as an energy storage element, and a voltage sensor 111S for detecting the voltage Vcap of the DC capacitor 111C. These series of semiconductor switching elements 111U1 and 111L1, the series of semiconductor switching elements 111U2 and 111L2, and the DC capacitor 111C are connected in parallel.

[0025] In the converter cell 111 with the configuration shown in Figure 2C, semiconductor switching elements 111U1 and 111L1 are controlled by gate signals GU1 and GL1 so that one is ON and the other is OFF. Similarly, semiconductor switching elements 111U2 and 111L2 are controlled by gate signals GU2 and GL2 so that one is ON and the other is OFF. When semiconductor switching element 111U1 is ON and semiconductor switching element 111L1 is OFF, and semiconductor switching element 111U2 is OFF and semiconductor switching element 111L2 is ON, the voltage across the DC capacitor 111C is applied between the input / output terminals 111a and 111b. A positive voltage is applied to the input / output terminal 111a and a negative voltage is applied to the input / output terminal 111b.

[0026] Furthermore, in addition to the voltage sensor 111S that detects the DC capacitor voltage Vcap, the power converter 1 is equipped with multiple detectors that detect the voltage and current of the power converter 10. As shown in Figure 1, the control device 20 receives the values ​​detected by these detectors. Specifically, the control device 20 receives the phase voltages Vacu, Vacu, Vacuw at the AC terminals of the power converter 10, the currents Iacu, Iacv, Iacw at the AC terminals, the DC voltage Vdc between the positive DC terminal 6P and the negative DC terminal 6N, the DC current Idc flowing through the positive DC terminal 6P or the negative DC terminal 6N, the currents IuP, IvP, IwP flowing through the positive arms 100uP, 100vP, 100wP, the currents IuN, IvN, IwN flowing through the negative arms 100uN, 100vN, 100wN, and the voltage Vcap of the DC capacitor 111C.

[0027] Next, the configuration of the control device 20 will be described. The control device 20 generates gate signals GU and GL to drive the respective semiconductor switching elements 111U and 111L in each converter cell 111 of the power converter 10, based on the detected values ​​detected by each detector.

[0028] Figure 3 is a functional block diagram showing the configuration of the main parts of the control device 20 according to Embodiment 1. As shown in Figure 3, the control device 20 includes a DC control unit 21, an AC current control unit 22, a circulating current control unit 23, a command value generation unit 24, and an arm capacitor voltage average value calculation unit 25.

[0029] The DC control unit 21 receives the DC voltage Vdc between the positive DC terminal 6P and the negative DC terminal 6N of the power converter 10, and the DC current Idc flowing through either the positive DC terminal 6P or the negative DC terminal 6N as input. It also receives a DC voltage command value Vdcref and a DC current command value Idcref. The DC control unit 21 outputs an arm DC component voltage command value VarmDC such that the DC voltage Vdc follows the DC voltage command value Vdcref, or the DC current Idc follows the DC current command value Idcref.

[0030] The AC current control unit 22 receives the AC current Iac at the AC terminal of the power converter 10 (when the AC terminal currents Iacu, Iacv, and Iacw are collectively referred to as AC current Iac) and the AC voltage command value Iacref for controlling the AC voltage of each phase (the AC voltage command value Iacref is used as a general term for the AC voltage command values ​​of the U, V, and W phases). The AC current control unit 22 outputs an arm AC component voltage command value VarmAC such that the AC current Iac follows the AC current command value Iacref.

[0031] The circulating current control unit 23 outputs an arm circulating voltage command value Varmcc for controlling the circulating current Icc to follow a circulating current command value Iccref, which is used to balance the voltage of the DC capacitor 111C contained in each arm 100 between the arms 100. Here, the circulating current Icc does not flow at the AC and DC ends of the power converter 10, but represents the current that flows between each phase leg circuit 100u, 100v, and 100w.

[0032] The arm capacitor voltage average value calculation unit 25 calculates the average voltage of the DC capacitors in each arm. The total voltages Vcap of the DC capacitors 111C in the converter cells 111 of each arm, Vcpu, Vcnu, Vcpv, Vcnv, Vcpw, Vcnw, are input to the arm capacitor voltage average value calculation unit 25, and the average voltages Vcarmpu, Vcarmnu, Vcarmpv, Vcarmnv, Vcarmpw, Vcarmnw, which are obtained by dividing the total voltages Vc of the DC capacitors in each arm by the number of converter cells N (N is an integer of 1 or more) in each arm, are output. When referring to the total voltages Vc of the capacitors in each arm collectively, the total voltage Vc of the capacitors in each arm is used, and when referring to the average voltages Vcarm of the capacitors in each arm collectively, the average voltage Vcarm of the capacitors in each arm is used.

[0033] The command value generation unit 24 receives the arm DC component voltage command value VarmDC from the DC control unit 21, the arm AC component voltage command value VarmAC from the AC current control unit 22, the arm circulating voltage command value Varmcc from the circulating current control unit 23, and the average value Vcarm of the capacitor voltage of each arm from the arm capacitor voltage average value calculation unit 25. The details of the command value generation unit 24 will be described later, but the command value generation unit 24 outputs the modulation command kref for each arm (the arm modulation command kref is used as a general term for the modulation commands krefpu, krenu, krefpv, krefnv, krefpw, and krenw for each arm).

[0034] Figure 4 shows the state in which the modulation command kref for each arm, generated and output by the command value generation unit 24, is input to the gate signal generation unit 26. The gate signal generation unit 26 receives the modulation command kref for each arm and generates gate signals G (G1U, G1L, G2U, G2L, G3U, G3L...) that drive the semiconductor switching elements 111U, 111L contained in all the converter cells 111 of the corresponding arm 100. The gate signal generation unit 26 obtains the gate signals G by, for example, a pulse width modulation (PWM) method that compares the magnitude of the input arm modulation command kref with that of the carrier wave.

[0035] The multiple gate signal generation units 26 may be provided in the control device 20 as a downstream of the command value generation unit 24, but each gate signal generation unit 26 may also be included in the converter cell 111.

[0036] Next, the configuration of the command value generation unit 24 will be described. Figure 5 is a functional block diagram showing the configuration of the command generation unit 24. As shown in Figure 5, the command value generation unit 24 includes an arm output voltage command value generation unit 244, a voltage command value correction unit 240, and a normalization unit 246.

[0037] The arm output voltage command value generation unit 244 receives the arm DC component voltage command value VarmDC, the arm AC component voltage command value VarmAC, and the arm circulating voltage command value Varmcc as inputs, calculates the voltage output by each arm, and outputs the arm output voltage command values ​​Varmpu, Varmnu, Varmpv, Varmnv, Varmpw, and Varmnw.

[0038] The voltage command value correction unit 240 includes voltage command value correction units 240U, 240V, and 240W corresponding to each phase, and corrects the voltage output of the arms by referring to the average value Vcarm of the capacitor voltages inside each arm (or, if the total value Vc of the capacitor voltages inside the arms is used, calculated as Vc = Vcarm × N), thereby correcting the arm output voltage command value. Figure 6 shows the configuration of the voltage command value correction unit 240 provided in the command generation unit 24. As shown in Figure 6, the voltage command value correction unit 240 includes a corrected voltage calculation unit 241. Figure 7 shows the configuration of the corrected voltage calculation unit 241. Figures 6 and 7 will be explained using the U-phase voltage command value correction unit 240U as an example of the voltage command value correction unit.

[0039] The correction voltage calculation unit 241U of the U-phase voltage command value correction unit 240U receives the positive arm output voltage command value Varmpu, the negative arm output voltage command value Varmnu, the total capacitor voltage value Vcpu within the positive arm, the total capacitor voltage value Vcnu within the negative arm, and a determination signal CCprModeU indicating whether the power converter 10 is in circulating current priority mode. In the corrected voltage calculation unit 241, adders 2411p, 2413p, 2415p, 2416p, 2417, 2411n, 2413n, 2415n, and 2416n add the input signals and output the result, while filters 2412p, 2414p, 2412n, and 2414n output 0 if the input signal is 0 or less, and output the value of the input signal if it is greater than 0. For the multiplier 2418, CCprModeU is input to 1 if the power converter 10 is in circulating current priority mode, and CCprModeU is input to 0 if it is not in circulating current priority mode.

[0040] Here, the circulating current priority mode is a mode in which, when the sum of all capacitor voltages included in a single leg circuit exceeds a preset threshold (δ1) and the arm included in that leg circuit becomes overmodulated, the output voltage of the arm is corrected to prioritize the output of the circulating current control. As shown in Figure 6, the U-phase voltage command value correction unit 240U receives the average values ​​of each arm's capacitor voltages, Vcarmpu and Vcarmnu, as input. That is, the sum of the capacitor voltages in the positive arm, Vcpu, and the sum of the capacitor voltages in the negative arm, Vcnu, are input. Therefore, the filter 242U compares the sum of the two, the U-phase capacitor voltages Vcu (=Vcpu+Vcnu), with the threshold (δ1), and if it is greater than or equal to the threshold (δ1), the output of the circulating current priority mode determination signal CCprModeU is set to 1. If the U-phase capacitor voltages Vcu are less than the threshold (δ1), the filter 242U sets the output of the circulating current priority mode determination signal CCprModeU to 0. In this way, the system determines whether it is in circulating current priority mode and outputs the circulating current priority mode determination signal CCprModeU.

[0041] When the circulating current priority mode determination signal CCprModeU is 0, in Figure 5, the arm output voltage command value generation unit 244 generates the arm output voltage command value Varm without considering the arm circulating voltage command value Varmcc.

[0042] Furthermore, the threshold value (δ1) should be set to a value greater than or equal to half of the DC voltage Vdc between the positive DC terminal 6P and the negative DC terminal 6N of the power converter 10. This is because if the sum of the capacitor voltages of all capacitors included in one leg circuit is less than half of the DC terminal voltage Vdc, it is necessary to charge the entire capacitor voltage, but if a correction is made to prioritize the circulating current output, it will affect the grid side (AC side), which may prevent sufficient charging.

[0043] The operation of the correction voltage calculation unit 241U will be explained for the following five cases. (1) In the positive arm, if the total capacitor voltage value Vcpu is greater than the positive arm output voltage command value Varmpu (Vcpu>Varmpu), and the total capacitor voltage value Vcnu is greater than the negative arm output voltage command value Varmnu (Vcnu>Varmnu), i.e., if no overmodulation occurs, then the positive arm output voltage command correction value ΔVarmpu output from adder 2416p and the negative arm output voltage command correction value ΔVarmnu output from adder 2416n are both 0, and the corrected voltage calculation unit 241 outputs a voltage command correction value ΔVarmu=0.

[0044] (2) In the positive arm, when overmodulation occurs where the positive arm output voltage command value Varmpu is greater than the total capacitor voltage value Vcpu in the positive arm (Vcpu < Varmpu), a positive arm output voltage command correction value ΔVarmpu (≠0) is output from the adder 2416p. At this time, when the total capacitor voltage value (Vcpu + Vcnu) in the leg circuit 100u of phase U is greater than a preset threshold value δ1, 1 is input to the multiplier 2418 as the signal CCprModeU, and the voltage command correction value ΔVarmu is output. On the other hand, when the total capacitor voltage value (Vcpu + Vcnu) in the leg circuit 100u of phase U is less than or equal to the preset threshold value δ1, it is determined that there is a margin in the capacitor voltage, 0 is input to the multiplier 2418 as the signal CCprModeU, and the correction voltage calculation unit 241 outputs a voltage command correction value ΔVarmu = 0.

[0045] (3) Similarly, in the negative arm, when overmodulation occurs where the negative arm output voltage command value Varmnu is greater than the total capacitor voltage value Vcnu in the negative arm (Vcnu < Varmnu), a negative arm output voltage command correction value ΔVarmnu (≠0) is output from the adder 2416n. At this time, when the total capacitor voltage value (Vcpu + Vcnu) in the leg circuit 100u of phase U is greater than a preset threshold value δ1, the signal 1 CCprModeU is input to the multiplier 2418, and the voltage command correction value ΔVarmu is output. On the other hand, when the total capacitor voltage value (Vcpu + Vcnu) in the leg circuit 100u of phase U is less than or equal to the preset threshold value δ1, it is determined that there is a margin in the capacitor voltage, 0 is input to the multiplier 2418 as the signal CCprModeU, and the correction voltage calculation unit 241 outputs a voltage command correction value ΔVarmu = 0.

[0046] (4) In the positive arm, if the positive arm output voltage command value Varmpu is less than 0 (Varmpu < 0), the adder 2416p outputs a positive arm output voltage command correction value ΔVarmpu (≠ 0). At this time, if the total capacitor voltage value (Vcpu + Vcnu) in the U-phase leg circuit 100u is greater than a preset threshold δ1, the multiplier 2418 receives a signal CCprModeU of 1, and the voltage command correction value ΔVarmu is output. On the other hand, if the total capacitor voltage value (Vcpu + Vcnu) in the U-phase leg circuit 100u is less than or equal to a preset threshold δ1, it is determined that there is sufficient capacitor voltage, and the multiplier 2418 receives a signal of 0 as CCprModeU, and the correction voltage calculation unit 241 outputs a voltage command correction value ΔVarmu = 0.

[0047] (5) In the negative arm, if the negative arm output voltage command value Varmnu is less than 0 (Varmnu < 0), the adder 2416n outputs a negative arm output voltage command correction value ΔVarmnu (≠ 0). At this time, if the total capacitor voltage value (Vcpu + Vcnu) in the U-phase leg circuit 100u is greater than a preset threshold δ1, the multiplier 2418 receives a 1 as the CCprModeU signal and outputs a voltage command correction value ΔVarmu. On the other hand, if the total capacitor voltage value (Vcpu + Vcnu) in the U-phase leg circuit 100u is less than or equal to a preset threshold δ1, it is determined that there is sufficient capacitor voltage, and the multiplier 2418 receives a 0 as the CCprModeU signal, and the correction voltage calculation unit 241 outputs a voltage command correction value ΔVarmu = 0.

[0048] In other words, the correction voltage calculation unit 241 outputs a correction voltage if the arm output voltage command value on one side of the corresponding phase exceeds the sum of the arm capacitor voltages on that side, or if the arm output voltage command value is less than 0V, and if it is in circulating current priority mode.

[0049] As shown in Figure 6, the voltage command correction value output from the correction voltage calculation unit 241 ΔVarmuThis is subtracted from the positive arm output voltage command value Varmpu to output the corrected positive arm output voltage command value Varmpu*. Additionally, the voltage command correction value is applied to the negative arm output voltage command value Varmnu. ΔVarmu This is added, and the corrected negative arm output voltage command value Varmnu* is output.

[0050] The corrected arm output voltage command values ​​for each phase, Varmpu*, Varmnu*, Varmpv*, Varmnv*, Varmpw*, Varmnw* (or Varm* when referring to them collectively), output from the voltage command value correction unit 240 are input to the normalization unit 246.

[0051] In Figure 5, the normalization unit 246 normalizes the corrected output voltage command values ​​of each arm output from the voltage command value correction unit 240 based on the sum of the capacitor voltages of each arm, and outputs the modulation command kref for each arm.

[0052] Figures 6 and 7 illustrate how the arm output voltage command value is corrected using the voltage command correction value ΔVarmu calculated by the correction voltage calculation unit 241. Now, Figures 8A and 8B will be used to explain the specific correction details and effects. Figure 8A is a diagram illustrating the effects of the power conversion device according to Embodiment 1, and Figure 8B is an enlarged view of the area enclosed by dotted lines A and B in Figure 8A.

[0053] Figure 8A shows the behavior of the total capacitor voltage in the positive arm (Vcpu), the output voltage command value in the positive arm (Varmpu), the total capacitor voltage in the negative arm (Vcnu), and the output voltage command value in the negative arm (Varmnu) in the U-phase leg circuit 100u. A fault occurred at time t0, and an overmodulation state was entered immediately afterward. At this time, in the negative arm, the output voltage command value in the negative arm (Varmnu) increased and exceeded the total capacitor voltage in the negative arm (Vcnu). This period is shown by the region indicated by dotted line A in the figure. On the other hand, in the positive arm, even if the output voltage command value in the positive arm (Varmpu) oscillates, it does not exceed the total capacitor voltage in the positive arm (Vcpu). The region of the positive arm at the same time corresponding to the region indicated by dotted line A in the negative arm is shown by dotted line B. Note that the U-phase leg circuit 100u is in circulating current priority mode. Furthermore, as explained in Figure 7, in the positive arm, the upper threshold for the positive arm output voltage command value Varmpu is the total capacitor voltage value Vcpu within the positive arm, and in the negative arm, the upper threshold for the negative arm output voltage command value Varmnu is the total capacitor voltage value Vcnu within the negative arm. The lower threshold for both is 0V.

[0054] In Figure 8B, the negative arm output voltage command value Varmnu exceeds the total capacitor voltage value Vcnu within the negative arm in the region indicated by the dotted line A. This portion of the negative arm output voltage command value Varmnu that exceeds the total capacitor voltage value Vcnu is shown by the dashed line. Here, the negative arm output voltage command value Varmnu is corrected by a voltage command correction value ΔVarmu so that it does not exceed the total capacitor voltage value Vcnu within the negative arm. The corrected negative arm output voltage command value Varmnu* is equal to the total capacitor voltage value Vcnu within the negative arm.

[0055] On the other hand, since it is a circulating current priority mode, the corresponding positive arm is corrected by a voltage command correction value ΔVarmu so that the total output voltage value in the leg circuit 100u is equal before and after correction, so that the positive and negative capacitor voltages are balanced. Therefore, the positive arm output voltage command value Varmpu, shown by the dashed line in the region of dotted line B, becomes the corrected positive arm output voltage command value Varmpu*, shown by the solid line.

[0056] In this way, in circulating current priority mode, a correction voltage is used to make the output voltage of the overmodulated arm equal to the output range, which is the sum of the capacitor voltages, and the output voltage of the other arm is also corrected, so that the sum of the output voltages of the two arms within a single leg circuit does not change before and after correction. This makes it possible to control the desired circulating current even when overmodulation occurs.

[0057] As described above, according to this embodiment 1, a power converter is provided which has a power converter that performs power conversion between multiple phases of AC and DC, and a control device that controls the power converter, wherein each arm is configured by connecting multiple leg circuits in series, each of which is connected in parallel, and the connection points between the positive and negative arms of the multiple leg circuits are connected to the AC lines of each phase, and each arm is configured by connecting converter cells in series, each of which has a series unit of multiple semiconductor switching elements connected in series and a DC capacitor connected in parallel to this series unit. The control device has an arm output voltage command value generation unit that generates arm output voltage command values, which are command values ​​for the voltages output by multiple arms. It performs circulating current control for each leg circuit, and when the sum of the voltages of all DC capacitors included in at least one leg circuit is equal to or greater than a preset first threshold (δ1), it generates a correction voltage to correct the arm output voltage command value of one arm in that leg circuit. If the arm output voltage command value exceeds a preset upper threshold, it should be less than or equal to the upper threshold. If the arm output voltage command value falls below a lower threshold, it should be greater than or equal to the lower threshold. The control device also corrects the arm output voltage command value of the other arm based on the correction voltage. With this configuration, the output voltage command values ​​of both arms are corrected with the correction voltage, making it possible to equalize the sum of the output voltages and simplifying circulating current control. Therefore, the capacitor voltages can be quickly balanced in the event of an imbalance in the capacitor voltages between arms during or immediately after a fault.

[0058] Furthermore, when the first threshold is exceeded, a circulating current priority mode is implemented to correct the overmodulated output voltage of the arm, prioritizing the output of the circulating current control. By activating this function only when the capacitor voltage is above a certain level, it can be made effective only for inter-arm capacitor voltage imbalances. By setting the first threshold to more than half of the DC voltage of the power converter, the output voltage of the arm can be corrected to prioritize the circulating current control output only when necessary for inter-arm capacitor voltage imbalances.

[0059] Since the output range of the arm output voltage is from 0V to the sum of the capacitor voltages of the arm, setting the upper threshold for overmodulation to the sum of the capacitor voltages of the arm and setting the upper threshold to 0V makes it possible to maximize the range of the arm output voltage.

[0060] Embodiment 2. The power conversion device according to Embodiment 2 will be described below with reference to the figures. The power conversion device according to Embodiment 2 is equipped with a control device 20 similar to that in Figure 3, but the configuration of the command generation unit 24 differs from that of Embodiment 1. The following description will focus on the differences from Embodiment 1, and explanations of corresponding parts will be omitted.

[0061] Figure 9 is a functional block diagram showing the configuration of the command generation unit 24 included in the control device 20 according to Embodiment 2. As shown in Figure 9, the command generation unit 24 includes an arm output voltage command value generation unit 244, a voltage command value correction unit 1240, and a normalization unit 246. The arm output voltage command value generation unit 244 and the normalization unit 246 are the same as those shown in Figure 5 of Embodiment 1.

[0062] Figure 10 shows the configuration of the voltage command value correction unit 1240. As shown in Figure 10, the voltage command value correction unit 1240 comprises a correction voltage calculation unit 1241 for each phase: a U-phase correction voltage calculation unit 1241U, a V-phase correction voltage calculation unit 1241V, a W-phase correction voltage calculation unit 1241W, a correction zero-sequence voltage calculation unit 1242, and various arithmetic units. Figure 11 shows the configuration of each phase correction voltage calculation unit 1241, and Figure 13 shows the configuration of the correction zero-sequence voltage calculation unit 1242. Note that the correction voltage calculation unit 1241 is used as a general term for the U-phase correction voltage calculation unit 1241U, the V-phase correction voltage calculation unit 1241V, and the W-phase correction voltage calculation unit 1241W.

[0063] First, the configuration of the phase-specific correction voltage calculation unit 1241 will be explained. The correction voltage calculation unit 1241 in Figure 11 is assumed to be the U-phase correction voltage calculation unit 1241U, and the explanation will be based on the U-phase signal. Note that the correction voltage calculation unit 1241 in Figure 11 has a similar configuration to the phase-specific correction voltage calculation unit 241 shown in Figure 7 of Embodiment 1, and the input signals are the same, but the output signals are slightly different.

[0064] In Figure 11, the U-phase corrected voltage calculation unit 1241U The following are inputs: the positive arm output voltage command value Varmpu, the negative arm output voltage command value Varmnu, the total capacitor voltage value Vcpu within the positive arm, the total capacitor voltage value Vcnu within the negative arm, and a determination signal CCprModeU indicating whether the power converter 10 is in circulating current priority mode. Although Figures 10 and 11 show the determination signal CCprModeU being input, as explained in Figure 6 of Embodiment 1, the determination signal CCprModeU is generated by comparing the sum of the total capacitor voltage value Vcpu within the positive arm and the total capacitor voltage value Vcnu within the negative arm (Vcu) with a threshold value (δ1). The generation of the determination signal CCprModeU is omitted in Figures 10 and 11.

[0065] In the U-phase correction voltage calculation unit 1241U, adders 2411p, 2413p, 2416p, 2417, 2411n, 2413n, 2415n, and 2416n output the difference of the input signals, while filters 2412p, 2414p, 2412n, and 2414n output 0 if the input signal is 0 or less, and output the value if the input signal is greater than 0. The multiplier 2418 receives 1 if the power converter 10 is in circulating current priority mode, and 0 if it is not in circulating current priority mode. Here, circulating current priority mode is a mode in which the circulating current is controlled to follow the circulating current command value when the sum of the capacitor voltages of all components in a single leg circuit exceeds a preset threshold, thereby balancing the output voltages of the positive and negative arms in the leg circuit.

[0066] Cases (1) through (5) below are the same as those in Figure 7 of Embodiment 1, and therefore the explanation will be simplified. (1) In the positive arm, when the total voltage of the capacitors in the positive arm Vcpu is greater than the output voltage command value of the positive arm Varmpu (Vcpu > Varmpu) and the total voltage of the capacitors in the negative arm Vcnu is greater than the output voltage command value of the negative arm Varmnu (Vcnu > Varmnu), that is, when overmodulation does not occur, the voltage command correction value ΔVarmu = 0 is output.

[0067] (2) In the positive arm, in the case of overmodulation where the output voltage command value of the positive arm Varmpu is greater than the total voltage of the capacitors in the positive arm Vcpu (Vcpu < Varmpu), when the signal of CCprModeU is 1, the voltage command correction value ΔVarmu (≠0) is output. On the other hand, when the signal of CCprModeU is 0, the voltage command correction value ΔVarmu = 0 is output.

[0068] (3) Similarly, in the negative arm, in the case of overmodulation where the output voltage command value of the negative arm Varmnu is greater than the total voltage of the capacitors in the negative arm Vcnu (Vcnu < Varmnu), when the signal of CCprModeU is 1, the voltage command correction value ΔVarmu (≠0) is output. On the other hand, when the signal of CCprModeU is 0, the voltage command correction value ΔVarmu = 0 is output.

[0069] (4) In the positive arm, when the output voltage command value of the positive arm Varmpu is less than 0 (Varmpu < 0), when CCprModeU is 1, the voltage command correction value ΔVarmu (≠0) is output. On the other hand, when the signal of CCprModeU is 0, the voltage command correction value ΔVarmu = 0 is output.

[0070] ((5) In the negative arm, when the output voltage command value of the negative arm Varmnu is less than 0 (Varmnu < 0), when the signal of CCprModeU is 1, the voltage command correction value ΔVarmu (≠0) is output. On the other hand, when the signal of CCprModeU is 0, the voltage command correction value ΔVarmu = 0 is output.

[0071] In other words, the correction voltage calculation unit 1241 outputs a voltage command correction value ΔVarm if the arm output voltage command value on one side of the corresponding phase exceeds the sum of the arm capacitor voltages on that side, or if the arm output voltage command value is less than 0V, in the circulating current priority mode.

[0072] Furthermore, in the correction voltage calculation unit 1241 of this embodiment 2, the correctable voltage range in the correction of each arm is calculated as the correction margin. Figure 12 is a diagram for explaining the voltage correction margin and shows the behavior of the U-phase positive side arm output voltage command value Varmpu. In Figure 12, σUpu is the U-phase positive side arm upper correction margin, and the positive side arm output voltage command value Varmpu is calculated from the total capacitor voltage value Vcpu within the positive side arm. reduced This is the value. Also, σLpu is the lower correction margin of the positive arm of the U phase, and is the value of the positive arm output voltage command value Varmpu. However, in Figure 11, these are the outputs of filters 2412p and 2414p respectively, so σUpu and σLpu are 0 if they are less than or equal to 0. That is, in the case of overmodulation in case (2) above, when the positive arm output voltage command value Varmpu is greater than the total capacitor voltage value Vcpu inside the positive arm, the upper correction margin σUpu of the positive arm of the U phase is 0. In the case (4) above, when the positive arm output voltage command value Varmpu is < 0, the lower correction margin σLpu of the positive arm of the U phase is 0.

[0073] Similarly, Figure 11 also calculates the correction margin σUnu on the upper side of the negative arm of the U phase and the correction margin σLnu on the lower side of the negative arm of the U phase. Furthermore, the other V-phase corrected voltage calculation unit 1241V and W-phase corrected voltage calculation unit 1241W also output voltage command correction value ΔVarmv and correction margins σUpv, σLpv, σUnv, σLnv, and voltage command correction value ΔVarmw and correction margins σUpw, σLpw, σUnw, σLnw, respectively.

[0074] Next, the corrected zero-sequence voltage calculation unit 1242 will be explained using Figure 13. As shown in Figure 13, the corrected zero-sequence voltage calculation unit 1242 receives the corrected voltage and correction margin for each phase, which are the outputs of the corrected voltage calculation unit 1241 for each phase, and outputs the corrected zero-sequence voltage ΔVz. When it is necessary to correct the output voltage command value of any arm, the corrected zero-sequence voltage ΔVz is used for correction. As a result, if the AC system voltage is isolated by a transformer or the like, no change occurs in the inter-phase voltage, and overmodulation can be prevented without affecting the system. However, since the zero-sequence voltage is a common component of the AC voltage output by each phase, the corrected zero-sequence voltage ΔVz is used for correction in any arm, and if the corrected zero-sequence voltage ΔVz is large, it may cause overmodulation in other arms that are not experiencing overmodulation. To prevent this, the corrected zero-sequence voltage calculation unit 1242 of this embodiment 2 sets a limit value for the corrected zero-sequence voltage ΔVz from the correction margin of the corrected voltage of each arm and calculates the corrected zero-sequence voltage ΔVz.

[0075] Filter 2421 detects the maximum value from the voltage command correction values ​​ΔVarmu, ΔVarmv, and ΔVarmw for each phase input to the corrected zero-sequence voltage calculation unit 1242, and filter 2422 detects the minimum value. The detected maximum and minimum values ​​are added together and input to the limiter 2423. The limiter 2423 limits the input value to a maximum value ΔVzLIMH and a minimum value ΔVzLIML. The maximum value ΔVzLIMH and minimum value ΔVzLIML of the limiter 2423 are calculated as follows.

[0076] When the corrected zero-sequence voltage ΔVz is positive, the correction margins σUnu, σUnv, σUnw on the negative arm of each phase and the correction margins σLpu, σLpv, σLpw on the positive arm of each phase decrease. That is, as a result of correction by the corrected zero-sequence voltage ΔVz, one of σUnu, σUnv, σUnw, σLpu, σLpv, or σLpw may become 0 or less, potentially causing overmodulation in an arm other than the corrected arm. Therefore, with respect to the corrected zero-sequence voltage ΔVz, the positive value must be limited to the minimum value of σUnu, σUnv, σUnw, σLpu, σLpv, or σLpw.

[0077] Therefore, the filter 2424 detects the minimum value from the correction margins of the correction voltages of each arm input to the corrected zero-sequence voltage calculation unit 1242, specifically the negative arm upper correction margins σUnu, σUnv, σUnw and the positive arm lower correction margins σLpu, σLpv, σLpw for each phase, and sets this value as the maximum value ΔVzLIMH of the limiter 2423.

[0078] When the corrected zero-sequence voltage ΔVz is negative, the upper correction margins σUpu, σUpv, σUpw on the positive arm of each phase and the lower correction margins σLnu, σLnv, σLnw on the negative arm of each phase decrease. That is, as a result of correction by the corrected zero-sequence voltage ΔVz, one of σUpu, σUpv, σUpw, σLnu, σLnv, or σLnw may become 0 or less, and an arm other than the corrected arm may become overmodulated. Therefore, with respect to the corrected zero-sequence voltage ΔVz, the negative values ​​must be limited to the minimum value of σUpu, σUpv, σUpw, σLnu, σLnv, or σLnw multiplied by -1.

[0079] Therefore, the filter 2425 detects the minimum value from the correction margins of the correction voltage of each arm input to the corrected zero-sequence voltage calculation unit 1242, specifically the upper correction margins σUpu, σUpv, σUpw of the positive arm for each phase and the lower correction margins σLnu, σLnv, σLnw of the negative arm for each phase. The inversion circuit 2426 then inverts the sign of this detected value, and this value is set as the minimum value ΔVzLIML of the limiter 2423.

[0080] Returning to the voltage command value correction unit 1240 in Figure 10, we will explain how to calculate the corrected positive arm output voltage command value Varmpu* and the corrected negative arm output voltage command value Varmnu*, using the U phase as an example. Note that the U phase is the phase that includes the arm to be corrected for overmodulation.

[0081] First, the U phase is defined as the phase containing the arm to be corrected for overmodulation, while the other phases are defined as the phases that do not contain the arm to be corrected for overmodulation. The corrected zero-sequence voltage ΔVz output from the corrected zero-sequence voltage calculation unit 1242 is input to the adder 1243u and subtracted from the positive arm output voltage command value Varmpu. The negative arm output voltage command value Varmnu is then added to the corrected zero-sequence voltage ΔVz in the adder 1244u.

[0082] The U-phase voltage command correction value ΔVarmu calculated by the U-phase correction voltage calculation unit 1241U is input to the filter 1246u. Filter 1246u outputs 0 to the multiplier 1247u when the input value is 0, and 1 if the input value is not 0. Adder 1245u subtracts the corrected zero-sequence voltage ΔVz from the U-phase voltage command correction value ΔVarmu, and this value is input to the multiplier 1247u. Here, since the U-phase is the phase that includes the arm to be corrected for overmodulation, the U-phase voltage command correction value ΔVarmu is not 0, so the output of multiplier 1247u is 1. Therefore, the input from 1247u to adders 1248u and 1249u is ΔVarmu - ΔVz. Therefore, the corrected positive arm output voltage command value Varmpu* will be Varmpu - ΔVarmu, and the corrected negative arm output voltage command value Varmnu* will be Varmnu + ΔVarmu, both of which will be output from the voltage command value correction unit 1240.

[0083] Since the other phases do not include the arms to be corrected, the outputs of 1246V and 1246W are 0. Therefore, the corrected positive arm output voltage command value Varmpv* for the V phase is Varmpv - ΔVz, and the corrected negative arm output voltage command value Varmnv* is Varmnv + ΔVz. Similarly, the corrected positive arm output voltage command value Varmpw* for the W phase is Varmpw - ΔVz, and the corrected negative arm output voltage command value Varmnw* is Varmpw + ΔVz.

[0084] In this way, if the voltage command correction value ΔVarmu for the U phase is within the range of the maximum value ΔVzLIMH and minimum value ΔVzLIML of the corrected zero-sequence voltage calculation unit 1242, then ΔVz = ΔVarmu, and the correction is performed only by the zero-sequence voltage component. As a result, there is no change in the inter-phase voltage, and the effect does not propagate to the grid side. If the voltage command correction value ΔVarmu for the U phase exceeds the maximum value ΔVzLIMH (ΔVarmu > ΔVzLIMH), then ΔVz = ΔVzLIMH, and the correction cannot be performed only by the zero-sequence voltage component. However, since the maximum value ΔVzLIMH portion of the voltage command correction value ΔVarmu for the U phase is corrected by the zero-sequence voltage component, the change in inter-phase voltage can be minimized compared to the case where zero-sequence voltage is not used (when the V phase and W phase are not corrected). In addition, by correcting only the U phase with the voltage command correction value ΔVarmu, the voltage of the circulating current control portion of the U phase becomes equal before and after the correction, so the impact on circulating current control is reduced, contributing to the capacitor voltage balance. The same effect is achieved when the voltage command correction value ΔVarmu for the U phase is below the minimum value ΔVzLIML (ΔVarmu < ΔVzLIML), or when another phase includes the arm to be corrected.

[0085] In the voltage command value correction unit 1240, although the U phase was used as an example in the explanation, other phases can similarly output corrected positive arm output voltage command values ​​and corrected negative arm output voltage command values.

[0086] In the command generation unit 24 of Figure 9, the corrected arm output voltage command values ​​Varmpu*, Varmnu*, Varmpv*, Varmnv*, Varmpw*, Varmnw* for each phase output from the voltage command value correction unit 1240 are input to the normalization unit 246. The normalization unit 246 normalizes the corrected output voltage command values ​​for each arm output from the voltage command value correction unit 1240 based on the total capacitor voltage of each arm, as described in Embodiment 1, and outputs the modulation command kref for each arm.

[0087] As described above, Embodiment 2 provides the same effects as Embodiment 1. Furthermore, when circulating current control is performed in all of the multiple leg circuits, the voltage command correction value ΔVarm corresponding to overmodulation is corrected by the zero-sequence voltage, i.e., the corrected zero-sequence voltage that corrects the zero-sequence voltage, thereby suppressing the influence on the AC side.

[0088] Furthermore, since the correction zero-sequence voltage used for correction is limited by a margin between the output voltage command value of all arms and the upper and lower thresholds, it is possible to suppress the impact on arms that are not experiencing overmodulation.

[0089] Figure 14 shows an example of the hardware configuration of the control device 20 in the embodiments 1 and 2 described above. As shown in Figure 14, the control device 20 includes, for example, a processor 1000 and a storage device 1100 as processing circuits. The processor 1000 may include a CPU (Central Processing Unit), an ASIC (Application Specific Integrated Circuit), an IC (Integrated Circuit), an FPGA (Field Programmable Gate Array), various logic circuits, and various signal processing circuits. Furthermore, the processor 1000 may consist of multiple processors of the same or different types, each performing a portion of the processing. The storage device 1100 may include a RAM (Random Access Memory) configured to read and write data from the processor 1000, and a ROM (Read Only Memory) configured to read data from the processor 1000. The processor 1000 executes programs input from the storage device 1100, such as the ROM.

[0090] Furthermore, if the gate signal generation unit 26 shown in Figure 4 is not provided in the control device 20 but is included in the converter cell 111, 14 A hardware configuration like the one shown is also acceptable.

[0091] <Other embodiments> (1) In Figures 2A to 2C, the semiconductor switching elements 111U and 111L constituting the converter cell 111 were explained using IGBTs (Insulated Gate Bipolar Transistors) with diodes connected in antiparallel as an example, but MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) may also be used.

[0092] (2) The semiconductor switching element is not limited to one composed of a Si (silicon) semiconductor, but may also be a wide-bandgap semiconductor such as SiC (silicon carbide) or GaN (gallium nitride). Wide-bandgap semiconductors are suitable for application to MMCs due to their characteristics such as enabling faster switching, high-temperature operation, and high dielectric breakdown field strength.

[0093] While this disclosure describes various exemplary embodiments and examples, the various features, aspects, and functions described in one or more embodiments are not limited to the application of a particular embodiment, but are applicable individually or in various combinations to the embodiments. Accordingly, countless variations not illustrated are conceivable within the scope of the technology disclosed herein. These include, for example, modifications, additions, or omissions of at least one component, as well as the extraction of at least one component and its combination with components of other embodiments. [Explanation of symbols]

[0094] 1: Power converter, 2: AC power supply, 3: Transformer, 4u, 4v, 4w: Connection point, 6P: Positive DC terminal, 6N: Negative DC terminal, 10: Power converter, 100u, 100v, 100w: Reg circuit, 100, 100P, 100N, 100uP, 100uN, 100vP, 100vN, 100wP, 100wN: Arm, 111: Converter cell, 111U, 111L, 111U1, 111L1, 111U2, 111L2: Semiconductor switching element, 111C: DC capacitor, 111S: Voltage sensor, 111a, 111b: Input / output terminals 112uP, 112uN, 112vP, 112vN, 112wP, 112wN: Reactor, 20: Control device, 21: DC control unit, 22: AC current control unit, 23: Circulating current control unit, 24: Command generation unit, 25: Arm capacitor voltage average value calculation unit, 26: Gate signal generation unit, 240, 240U, 240V, 240W, 1240: Voltage command value correction unit, 241, 241U, 1241, 1241U, 1241V, 1241W: Corrected voltage calculation unit, 242, 242U: Filter, 1243u, 1244u, 1245u, 1248u, 1249u: Adder, 1246u: Filter, 1247u: Multiplier, 244: Arm output voltage command value generation unit, 246: Normalization unit, 1242: Corrected zero-sequence voltage calculation unit, 2411p, 2413p, 2415p, 2416p, 2417, 2411n, 2413n, 2415n, 2416n: Adders, 2412p, 2414p, 2412n, 2414n: Filters, 2418: Multiplier, 2421, 2422, 2424, 2425: Filters, 2423: Limiter, 2426: Inverting circuit, 1000: Processor, 1100: Memory device, Idc: DC current, Vdc: DC voltage, Iac: AC current, Icc: circulating current, Vcap: capacitor voltage, Vc: total capacitor voltage within the arm, Vcarm: average capacitor voltage within the arm, Varm: arm output voltage command value, kref: arm modulation command, G: gate signal

Claims

1. A power converter comprising a power converter that performs power conversion between multiple phases of AC and DC, wherein multiple leg circuits, each having a positive arm and a negative arm connected in series, are connected in parallel, and the connection points between the positive and negative arms of the multiple leg circuits are connected to the AC lines of each phase; and a control device that controls the power converter, Each of the positive and negative arms has one or more converter cells connected in series, each having a series unit in which a plurality of semiconductor switching elements are connected in series and a DC capacitor connected in parallel to this series unit. The control device has an arm output voltage command value generation unit that generates an arm output voltage command value, which is a command value of the voltage output by the plurality of arms. Circulation current control is performed for each of the aforementioned leg circuits. When the sum of the voltages of all DC capacitors included in at least one of the leg circuits is equal to or greater than a preset first threshold, the leg circuit generates and corrects a voltage command correction value to correct the arm output voltage command value of one of the positive arm and the negative arm such that if the arm output voltage command value exceeds a preset upper threshold, it becomes equal to or less than the upper threshold, and if the arm output voltage command value falls below a preset lower threshold, it becomes equal to or greater than the lower threshold. A power converter that corrects the arm output voltage command value of the other arm of the leg circuit, which is subject to circulating current control, based on the voltage command correction value.

2. The power conversion device according to claim 1, wherein the first threshold is 1 / 2 or more of the DC terminal voltage of the power converter.

3. The power conversion device according to claim 1 or 2, wherein in each of the plurality of arms, the upper threshold is the sum of the voltages of the DC capacitors in the arm, and the lower threshold is 0V.

4. The control device is The power conversion device according to claim 1 or 2, in the leg circuit where the sum of the voltages of all the DC capacitors is equal to or greater than a preset first threshold, the device controls the sum of the capacitor voltages of the positive arm and the negative arm to be equal before and after correction based on the voltage command correction value.

5. When, in all of the multiple leg circuits, the sum of the voltages of all the DC capacitors included in each of the leg circuits is equal to or greater than a preset first threshold, The power conversion device according to claim 1 or 2, wherein the voltage command correction value is corrected using a corrected zero-sequence voltage that corrects the zero-sequence voltage.

6. The power conversion device according to claim 5, wherein the corrected zero-sequence voltage is limited by a margin between all the arm output voltage command values ​​and the upper threshold and the lower threshold.

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