Topological structure used in IP core and IP core

Abstract

An embodiment of the present disclosure discloses a topology structure used in an IP core, which includes a first topology structure and a second topology structure. The first topology structure includes a driver chip, multiple stages of first signal lines, and at least two first loads. A signal output terminal of one first signal line in a front stage is connected to signal input terminals of two first signal lines in a rear stage connected in parallel. The signal input terminal of the first signal line in the first stage is connected to a signal output terminal of the driving signal. An output terminal of each first signal line in the last stage is connected to one first load. The second topology structure includes multiple branch structures, each branch structure including at least one second load. The signal input terminal of each branch structure is connected to a signal output terminal of one first signal line in the last stage of the first topology structure. This provides a new topology structure for the IP core and realizes diversified IP core topology structures to meet different needs.

Description

Technical Field

[0001] (Cross-reference to Related Applications) This application claims the priority of a Chinese patent application with the application number 202210904304.5 and the invention title "Topology Structure and IP Core Used in IP Core", which was filed on July 29, 2022, and the full text of this application is incorporated into this application by reference.

[0002] The present disclosure relates to the field of integrated circuit technology, and particularly to a topology structure and an IP core used in an IP core.

Background Art

[0003] With the increasing scale of integrated circuits, the design is becoming increasingly complex. In order to design and manufacture integrated circuits with various functions more quickly, an integrated circuit module with appropriate functions may be designed as a reusable IP core. In integrated circuit (IC) design, an IP core refers to an integrated circuit design module with some verified and reusable appropriate functions.

[0004] A memory integrated circuit module having a high-speed data read / write function can be made reusable in different integrated circuits by using a driver chip and a double data rate synchronous dynamic random access memory (abbreviated as DDR) as an IP core.

Summary of the Invention

[0005] The summary of this invention is provided to introduce the concepts in a simple form, and these concepts will be described in detail in the form for implementing the subsequent invention. The summary of this invention is not intended to identify the key features or essential features of the claimed technical solution, nor is it intended to limit the scope of the claimed technical solution.

[0006] The embodiments of this disclosure provide a topology structure used in an IP core and an IP core.

[0007] According to a first aspect, embodiments of the present disclosure provide a topology structure for use in an IP core, the topology structure comprising a first topology structure and a second topology structure, the first topology structure comprising a driver chip, a plurality of stages of first signal lines, and at least two first loads, wherein the signal output terminal of one preceding first signal line is connected to the signal input terminals of two subsequent first signal lines connected in parallel, the signal input terminal of the first stage of first signal lines is connected to the signal output terminal of the drive signal, and the output terminal of each last stage of first signal lines is connected to one first load, the second topology structure comprising a plurality of branch structures, each branch structure comprising at least one second load, and the signal input terminal of each branch structure is connected to the signal output terminal of one last stage of first signal line of the first topology structure.

[0008] According to a second aspect, embodiments of the present disclosure provide an IP core comprising a substrate, a driver chip provided on the substrate, a plurality of loads, and a connection structure between the plurality of loads and the driver chip, wherein the topology structure connected between the plurality of loads and the driver chip comprises a first topology structure and a second topology structure, the first topology structure comprising a driver chip, a plurality of stages of first signal lines, and at least two first loads, the signal output terminal of one preceding first signal line being connected to the signal input terminals of two subsequent first signal lines connected in parallel, the signal input terminal of the first stage first signal line being connected to the signal output terminal of the drive signal, and the output terminal of each last stage first signal line being connected to one first load, the second topology structure comprising a plurality of branch structures, each branch structure comprising at least one second load, and the signal input terminal of each branch structure being connected to the signal output terminal of one last stage first signal line of the first topology structure.

[0009] The topology structure used in the IP core according to the embodiments of this disclosure includes a first topology structure and a second topology structure, the first topology structure includes a driver chip, multiple stages of first signal lines, and at least two first loads, the signal output terminal of one preceding first signal line is connected to the signal input terminals of two subsequent first signal lines connected in parallel, the signal input terminal of the first stage first signal line is connected to the signal output terminal of the drive signal, and the output terminals of each last stage first signal line are connected to one first load, the second topology structure includes multiple branch structures, each branch structure includes at least one second load, and the signal input terminal of each branch structure is connected to the signal output terminal of one last stage first signal line of the first topology structure, thereby enabling the combination of the first topology structure and the second topology structure to form a topology structure used in the IP core, providing a new topology structure for the IP core, realizing a diversified IP core topology structure that can be applied to different needs. [Brief explanation of the drawing]

[0010] The above and other features, advantages, and aspects of each embodiment of this disclosure will become more apparent by referring to the embodiments for carrying out the invention described below, in conjunction with the accompanying drawings. In all accompanying drawings, identical or similar reference numerals represent identical or similar elements. It should be understood that the accompanying drawings are schematic and the originals and elements are not necessarily drawn to scale. [Figure 1] This is a schematic diagram of the topology structure used in the IP core according to this disclosure. [Figure 2] This is another schematic diagram of the topology structure used in the IP core according to this disclosure. [Figure 3] This is a schematic diagram of the IP core eye diagram as disclosed in this document. [Modes for carrying out the invention]

[0011] The following describes embodiments of this disclosure in more detail with reference to the accompanying drawings. While the accompanying drawings illustrate several embodiments of this disclosure, it should be understood that this disclosure can be implemented in various forms and should not be construed as being limited to the embodiments described herein. Conversely, these embodiments are provided to provide a more thorough and complete understanding of this disclosure. It should be understood that the accompanying drawings and embodiments of this disclosure are illustrative only and do not limit the scope of protection of this disclosure.

[0012] It should be understood that each step described in the embodiments of the method of this disclosure may be performed in a different order and / or in parallel. Furthermore, embodiments of the method may include additional steps and / or omit the performance of the indicated steps. The scope of this disclosure is not limited in this respect.

[0013] As used herein, the term “including” and its variations are open inclusions, meaning “including, but not limited to.” The term “based on” means “based at least partially.” The term “one embodiment” means “at least one embodiment,” the term “another embodiment” means “at least one other embodiment,” and the term “several embodiments” means “at least several embodiments.” Relevant definitions of other terms are given in the following description.

[0014] Furthermore, the terms “first,” “second,” etc., as used in this disclosure are merely for distinguishing different devices, modules, or units, and are not intended to limit the order or interdependence of the functions performed by these devices, modules, or units.

[0015] It should be understood by those skilled in the art that the modifications “one” and “multiple” as described in this disclosure are illustrative and not restrictive, and should be understood as “one or more” unless otherwise specified.

[0016] The names of messages or information exchanged between multiple devices in the embodiments of this disclosure are descriptive only and do not limit the scope of such messages or information.

[0017] To the extent that they do not contradict each other, the embodiments and features of the embodiments of this disclosure can be combined with each other.

[0018] Referring to Figure 1, Figure 1 shows a schematic diagram of the topology structure used in the IP core according to this disclosure. As shown in Figure 1, the topology structure used in the IP core includes a first topology structure 11 and a second topology structure 12. The first topology structure 11 includes a driver chip D, multiple stages of first signal lines S11, S2, ..., S1M, and at least two first loads B1. The driver chip D here may include various chips for generating operating signals, including but not limited to field-programmable gate arrays (FPGAs) and system-on-chip (SoCs). The driver chip D can emit a clock signal. The clock signal here may be a control signal for controlling the loads. The control signal here may be, for example, a controller and address (CA) signal.

[0019] In the first topology structure, the number of stages of the multiple stages of first signal lines S11, S2, ..., S1M may be set according to the specific application scene. Here, the output terminal of one preceding stage first signal line is connected to the signal input terminals of two subsequent stages of first signal lines connected in parallel. The input terminal of the first stage first signal line is connected to the output terminal of the driver chip. The output terminals of each of the last stage's first signal lines are connected to one first load B1.

[0020] In other words, the signal input terminals of the two subsequent first signal lines are connected in parallel, and then connected to the signal output terminal of the single first signal line preceding them.

[0021] The first signal line in the first stage includes one first signal line. The signal input end of the first signal line in the first stage is connected to the signal output end of the driver chip D.

[0022] The output end of the first signal line S1M in the last stage is connected to the first load.

[0023] When there are two stages of the first signal lines, the second-stage first signal lines include two first signal lines, and the first-stage first signal lines include one first signal line. When there are three stages of the first signal lines, among the three stages of the first signal lines, the first-stage first signal lines include one first signal line, the second-stage first signal lines include two first signal lines, and the third-stage first signal lines include four first signal lines. When there are four stages of the first signal lines, among the four stages of the first signal lines, the first-stage first signal lines include one first signal line, the second-stage first signal lines include two first signal lines, the third-stage first signal lines include four first signal lines, and the fourth-stage first signal lines include eight first signal lines, and so on by analogy.

[0024] The output end of the first signal line in the last stage is connected to the first load B1.

[0025] In the first topology structure, the number B1 of the first loads may be less than or equal to the number of the first signal lines in the last stage. The control signal emitted by the driver chip D is transmitted to the output end of the first signal line in the last stage through the first signal lines of each stage, and further transmitted to the first load, so as to control the operation of the first load B1.

[0026] The above first topology structure may be a T-shaped topology structure.

[0027] The second topology structure 12 includes a plurality of branch structures 121, and each branch structure 121 includes at least one second load B2. The signal input end of each branch structure 121 is connected to the output end of one first signal line in the last stage of the first topology structure 11.

[0028] For each branch structure 121, at least one second load B2 in the branch structure 121 may be connected in series. The connections between each second load B2 in a single branch structure 121 may be via a second signal line S22.

[0029] Since the signal input terminal of each branch structure 121 is connected to the output terminal of the first signal line S1M at the last stage of the first topology structure 11, the control signals emitted by the driver chip D can be transmitted to the second load B2 via the first signal line and second signal line S22 of each stage.

[0030] The number of branch structures 121 in the second topology structure 12 may be less than or equal to the number of first signal lines in the last stage of the first topology structure.

[0031] The output terminal of the last stage first signal line of the first topology structure 11 is connected to the input terminal of one second signal line in the branch structure 121. The output terminal of this second signal line is connected to one second load B2. In some application scenarios, one branch structure includes two second loads. The branch structure may include multiple second signal lines. The input terminal of the first second signal line in the branch structure is connected to the output terminal of one of the first signal lines in the last stage first topology structure. The output terminal of the first second signal line is connected to one second load. Furthermore, the output terminal of the first second signal line S22 is connected to the input terminal of a second second signal line S22. The output terminal of the second second signal line S22 is connected to one second load.

[0032] The second topological structure 12 may also be a fly_by structure.

[0033] The number of second loads in the branch structure in the second topology structure 12 may be determined according to the driving capability of the driver chip.

[0034] The first load B1 and the second load B2 may be electronic components that complete the same function, for example, electronic components that complete a data storage function. Specifically, the first load and the second load may be Double Data Rate Synchronous Dynamic Random Access Memory (DDR), Low Power Double Data Rate Synchronous Dynamic Random Access Memory (Low Power Double Data Rate Synchronous Dynamic Random Access Memory (LPDDR) or similar may also be used.

[0035] The topology structure used in the IP core according to this embodiment is formed by combining the first topology structure and the second topology structure, thereby providing a new topology structure for the IP core, realizing a diversified IP core topology structure, and being applicable to different needs.

[0036] In some application scenarios, in the first topology structure 11, the equivalent impedance formed by the two parallel-connected first signal lines in the subsequent stage is equal to the impedance of the single first signal line in the preceding stage that is connected to them.

[0037] The impedances of the two parallel-connected first signal lines in the subsequent stage may be equal.

[0038] For example, the magnitude of the equivalent impedance formed by two parallel-connected first signal lines of the second stage is equal to the impedance of the first signal line of the first stage connected to the two parallel-connected first signal lines of the second stage.

[0039] For example, if the impedance of the first signal line of the first stage is 10 ohms, the impedance of each first signal line of the second stage connected to the first signal line of the first stage may be 20 ohms. The equivalent impedance after the first signal lines of the second stage are connected in parallel may be 10 ohms, which is equal to the impedance of the first signal line of the first stage.

[0040] In these application scenarios, the equivalent impedance formed by the two parallel-connected first signal lines in the subsequent stage is equal to the impedance of the single first signal line in the preceding stage connected to it. Thus, the impedances of the two parallel-connected first signal lines in the subsequent stage are set to be equal, ensuring good continuity in the impedance of the first signal lines in each stage.

[0041] In some selective implementations, the branch structure of the second topology structure 12 includes at least one second signal line connected to the second load. The second signal line here may include a second signal line S22 connected to the last stage first signal line in the first topology structure and a second signal line S22 between each second load B2.

[0042] In these selective implementations, the impedance of the second signal line at each stage in the branch structure 121 of the second topology structure 12 is set to be equal to the impedance of the first signal line connected to the branch structure, thereby improving the continuity of signal line impedance throughout the topology structure.

[0043] In some selective implementations, the first topology structure 11 described above includes two stages of first signal lines and two first loads.

[0044] In other words, the first topology structure 11 includes one first-stage signal line and two second-stage first signal lines. The two second-stage first signal lines are connected in parallel and then connected to the output terminals of the first-stage first signal line. The output terminals of the two second-stage first signal lines are each connected to a first load.

[0045] In some selective implementations, the second topology structure 12 may include two branch structures. Each branch structure 121 includes one second load.

[0046] Thus, the second topology structure 12 may include a total of two second loads B2.

[0047] In some application scenarios, referring to Figure 2, which shows a schematic diagram of the topology structure used in the IP core according to this disclosure, the first topology structure 11' may include two stages of first signal lines S11 and S12.

[0048] The second topology structure 12' includes two branch structures 121', where the input terminal of the second signal line S22' of each branch structure may be connected to the output terminal of the second stage first signal line S12 of the first topology structure 11'. The output terminal of the second signal line S22' of the branch structure 121' is connected to a second load B2.

[0049] In these selective implementations, the first topology structure 11' is provided with two stages of first signal lines S11 and S12, the first topology structure 11' is provided with two first loads B1, and the second topology structure 12' is provided with two branch structures 121'. Each branch structure 121' is provided with one second load B2. The output terminal of the first topology structure 11' is connected to the input terminal of one branch structure 121' of the second topology structure 12'. Thus, the entire topology structure can accommodate four loads. This topology structure is applicable when the driver chip needs to synchronize four loads, which is difficult to achieve using the first or second topology structure alone.

[0050] Embodiments of the present disclosure further provide an IP core, the IP core comprising a substrate, a driver chip provided on the substrate, a plurality of loads, and a connection structure between the plurality of loads and the driver chip, wherein the topology structure formed by the connection between the plurality of loads and the driver chip comprises a first topology structure and a second topology structure, the first topology structure comprising a driver chip, a plurality of stages of first signal lines, and at least two first loads, wherein the signal output terminal of one preceding first signal line is connected to the signal input terminals of two subsequent first signal lines connected in parallel, the signal input terminal of the first stage first signal line is connected to the signal output terminal of the drive signal, and the output terminal of each last stage first signal line is connected to one first load, the second topology structure comprising a plurality of branch structures, each branch structure comprising at least one second load, and the signal input terminal of each branch structure is connected to the signal output terminal of one last stage first signal line of the first topology structure.

[0051] The driver chip described above may be any chip capable of generating a clock signal, such as a Field Programmable Gate Array (FPGA), a System on Chip (SoC), or a Microcontroller Unit (MCU). The load described above may be an electronic component that performs one or more functions. In some application scenarios, the load described above may be an electronic component that performs a data storage function. For example, the load described above may be DDR, LPDDR, or the like.

[0052] The driver chip, the first load, and the second load may be connected to the circuit board by soldering, adhesive, or other means.

[0053] The first signal line in each of the above stages may be made of substrate material.

[0054] Furthermore, the branching structure may include a second signal line. Each first signal line and the second signal line may be made of a conductive material on the substrate.

[0055] The branching structure of the second topology structure may include a second signal line, which may include a second signal line connected between the output terminal of the last stage of the first topology structure and a second load, or a second signal line connected between different second loads.

[0056] In this example, the above-mentioned substrate may be any substrate used as a driver chip or load carrier, and within it, a signal line in a second topological structure is fabricated for the first signal line.

[0057] As one implementation method, the above-mentioned substrate may be a printed circuit board (PCB), also known as a printed circuit board. A printed circuit board includes a copper coating layer and an insulating layer, and connecting leads and pads can be fabricated on the copper coating layer by processes such as printing and etching.

[0058] The first topology structure described above includes multiple stages of first signal lines, and the second topology structure includes multiple branch structures, each branch structure including at least one second signal line. The first and second signal lines described above are formed on a printed circuit board. Pads may be used to connect the signal output terminal of a driver chip to the input terminal of the first stage of the first signal line. The output terminal of the last stage of the first topology structure may be used to connect the input terminal of the first load. The output terminal of one of the second signal lines of the second topology structure may be used to connect the signal input terminal of the second load.

[0059] If the PCB is a multilayer board, the first signal line and the second signal line may include signal lines provided in the horizontal plane of at least one copper coating layer, and may also include signal lines that span different copper coating layers through holes.

[0060] When creating the first signal lines of each stage using a PCB board, the impedance of the first signal lines of each stage may be controlled so that the equivalent impedance of the two parallel-connected first signal lines of the subsequent stage is equal to the impedance of the first signal line of the preceding stage connected to the two parallel-connected first signal lines, thereby ensuring the continuity of the impedance of the first signal lines of each stage.

[0061] Similarly, when fabricating the second signal lines of each branch structure using a PCB board, it is necessary to control the impedance of the second signal lines of each branch structure. For each branch structure, the impedance of each second signal line on the branch structure may be controlled to be equal. Alternatively, the impedance of the second signal line in the branch structure may be controlled to be equal to the impedance of the first signal line connected to the branch structure.

[0062] What needs to be explained is that if a signal line formed across different copper coating layers by a hole is a first signal line, the impedance of the first signal line needs to be controlled based on the relationship between the impedance of the first signal line and the impedance of the preceding stage connected to it. If a signal line formed across different copper coating layers by a hole is a second signal line, the impedance of the second signal line may be controlled based on the impedance of the first signal line connected to the branch structure in which the second signal line is located. Specifically, the impedance of each node in the IP core may be made to have good continuity by optimizing the value of the antipad to adjust the impedance of the first signal line or the second signal line as described above.

[0063] Various signal lines may be provided on the PCB board to connect the driver chip and the load. The printed circuit board on the PCB board consists of an insulating base plate, connecting lead wires, and pads for soldering electronic components, and can serve as both a conductive line and an insulating base plate. This allows for electrical connections between elements in the circuit to be achieved instead of complex wiring.

[0064] Depending on the impedance requirements of the first signal line, a corresponding PCB substrate may be selected. For example, a PCB substrate capable of achieving the impedance of the final stage first signal line may be selected to fabricate the signal line. When the load supports a high transmission rate, the lower the PCB board material Dk, the better the quality of the high-speed transmitted signal and the faster the speed. Dk is an index that measures the electrical storage capacity of a material; the lower the Dk, the faster the transmission speed in the signal medium and the stronger the capacity.

[0065] Dk is the dielectric constant, the dielectric constant (Dk) of the PCB wiring board material, or the relative permittivity. Dk is not a constant. For example, the Dk of a material changes with frequency. In this disclosure, an IP core is fabricated by selecting a PCB substrate with a Dk value smaller than a predetermined threshold. The predetermined threshold here can be set according to the specific application scene and is not limited here.

[0066] The first topology structure may be a T-type topology structure. When providing the first signal lines of each stage of the first topology structure on the PCB board so that the impedance of the first topology structure has good continuity, the equivalent impedance of each of the two parallel-connected first signal lines of the subsequent stage is equal to twice the impedance of the preceding first signal line connected to those two first signal lines. Thus, the equivalent impedance of the two parallel-connected first signal lines of the subsequent stage after they are connected in parallel is equal to the impedance of the preceding first signal line connected to those two first signal lines.

[0067] In this example, the IP core achieves low manufacturing costs by combining a first topological structure and a second topological structure on a substrate, enabling the driver chip to drive multiple loads.

[0068] In some embodiments, the first and second loads may be memory components having high-speed data read / write capabilities. The first topology structure provided on the substrate includes two stages of first signal lines and two first loads, and the second topology structure includes two branch structures, each branch structure including one second load. Accordingly, the IP core may include one driver chip and four loads. The driver chip may be soldered or glued onto the substrate. Accordingly, the first signal lines formed on the substrate based on the topology structure include two stages. The input terminal of the first stage of the first signal line is connected to the output terminal of the driver chip. The first stage of the first signal line includes one first signal line. The second stage of the second signal line includes two first signal lines connected in parallel. The impedance of one second stage of the first signal line may be twice the impedance of the first stage of the first signal line. The branch structures provided on the substrate may include two branch structures. Each branch structure may include one second load. A branch structure may include one second signal line. The impedance of the second signal line in each branch structure may be equal to the impedance of the second stage first signal line connected to the branch structure.

[0069] In these selective implementations, the first topology structure described above corresponds to a T-shaped topology, and the second topology structure corresponds to a fly-by topology structure. The substrate described above may be a PCB substrate. By fabricating an IP core using a topology structure composed of the first and second topology structures, the driver chip in the IP core can smoothly drive four loads.

[0070] If the load is a high-speed read / write memory component, for example, 64-bit LPDDR5, the driver chip is an SoC. To enable one driver chip to drive four loads using a normal T-topology structure, a double T-topology structure is required. Because there is one more branch structure than in the case of a single T-topology structure, and the number of loads has increased by 1, the driver chip needs stronger driving capability and must strictly satisfy the proportional relationship that a single signal line in a later stage is twice the impedance of the signal line in the preceding stage to which it is connected. However, in actual construction, when creating the first signal line on the PCB, the larger the number of stages of the first signal line in the T-topology structure, the larger the impedance of the first signal line in that stage. On the other hand, there is an upper limit to the impedance of a signal line that can be realized on a PCB board, and it cannot be infinite, so the impedance provided in the T-structure may not be achievable on the PCB board. For this reason, signal lines in a T-topology structure with many stages are difficult to implement. On the other hand, due to variations in the manufacturing process, there is considerable variation in the impedance values ​​actually realized on the PCB board. This variation in impedance values ​​is related to the magnitude of the impedance. The larger the number of stages in the T-structure, the greater the variation due to manufacturing process issues. Consequently, the continuity of the impedance of the first signal line in each stage deteriorates, leading to a worsening of the eye diagram effect.

[0071] These selective implementations employ a method that combines a first topology structure and a second topology structure, where the first topology structure is a T-shaped topology structure and the second topology structure is a fly-by topology structure. Two stages of the first signal lines in the first topology structure are fabricated on the PCB board through processes such as printing and etching, and the second signal lines in the second topology structure are fabricated.

[0072] Of the two stages of first signal lines fabricated on the PCB, the signal input terminal of the first stage signal line may be connected to the signal output terminal of the driver chip. The output terminal of the second stage first signal line is connected to two first loads. Two branch structures are fabricated on the PCB, each branch structure corresponding to one second signal line. The signal input terminal of each second signal line may be connected to the output terminal of one second stage first signal line. The output terminal of the second signal line is connected to one second load.

[0073] Thus, in the implementation of lead wires corresponding to the first topology structure described above, the signal line with the highest impedance is the second-stage first signal line, and its impedance is twice that of the first-stage first signal line. If the center impedance of the first-stage first signal line is 30 ohms, then the center impedance of the second-stage first signal line is 60 ohms. A lead wire impedance of 60 ohms can be achieved with current PCB board materials and manufacturing processes. The magnitude of the impedance of the second signal line in the branch structure corresponding to the second topology structure may be equal to the impedance of the second-stage first signal line. Therefore, the impedance of the second signal line can also be achieved with existing PCB board materials and manufacturing processes. Thus, when driving four loads, each signal line for the topology structure of the embodiment shown in Figure 2 can be implemented on the PCB board, reducing the requirements for the PCB board and lowering the cost of the IP core.

[0074] In these selective implementations, the impedance of the driver chip, the impedances of the first and second loads, and the matching of the first and second signal lines may be set to achieve a better eye diagram effect.

[0075] Taking the example where the impedance of the first signal line of the first stage is 30 ohms, the equivalent impedance of the driver chip may be selected to be close to the impedance of the first signal line of the first stage, which is 30 ohms. For example, 35 ohms may be selected as the equivalent impedance of the driver chip. The equivalent impedance of the first load is close to the impedance of one first signal line of the second stage, which is 60 ohms. For example, 55 ohms may be selected as the impedance of the first load. The equivalent impedance of the second load is close to the impedance of the second signal line connected to it, which is 60 ohms. For example, 55 ohms may be selected as the impedance of the second load. This ensures impedance continuity and good signal integrity.

[0076] To better achieve signal integrity, the length of the second signal line may be determined based on signal integrity.

[0077] In some selective implementations, the length of the second signal line is determined according to the maximum signal transmission rate corresponding to the load and the period of the control signal emitted by the driver chip. Referring to Figure 3, in the eye diagram shown in Figure 3, T UI This represents the period of the control signal. The eye diagram shown in Figure 3 integrates the waveform of the control signal with the data transmission signal corresponding to the load.

[0078] In one implementation, the ratio of the length of the second signal line to the maximum transmission rate of the data transmission signal corresponding to the load is equal to an integer multiple of half the period of the control signal mentioned above. In other words, the transmission delay of the signal corresponding to the load on the second signal line is an integer multiple of half the period of the control signal mentioned above. The above relationship may also be expressed by the following equation (1).

[0079]

number

[0080] Here, L is the length of the second signal line, and V maxK is the maximum data transmission rate of the signal corresponding to the load. K is a positive integer, and T UI This is the period time length of the control signal.

[0081] By providing the length of the second signal line in this way, the reflection position Ed of the second load in the branch structure relative to the first load corresponding to the first topological structure can be pressed precisely to the rising or falling edge position of the eye diagram of the first load. Therefore, it does not affect the eye height in the eye diagram, and furthermore, it does not affect the sampling decision.

[0082] Furthermore, a low-speed section is required in the process of adjusting the synchronization between the control signal and the data transmission signal on the load. In the process of adjusting the synchronization between the control signal and the data transmission signal on the load as described above, 1 / 4 or 3 / 4 of the load's maximum transmission rate is used as the load's transmission rate to ensure that the eye height of the control signal meets appropriate requirements.

[0083] The foregoing describes preferred embodiments and applicable technical principles of the present disclosure. Those skilled in the art will understand that the scope of the disclosure is not limited to technical solutions formed by specific combinations of the above technical features, but also includes other technical solutions formed by arbitrarily combining the above technical features or equivalent features without departing from the concept of the above disclosure. For example, this includes technical solutions formed by substituting the above features with similar functional technical features disclosed in this disclosure (not limited to those disclosed therein).

[0084] Furthermore, although each operation is described in a specific order, this should not be understood as requiring these operations to be performed in a specific order or sequential order as indicated. In a given environment, multitasking and parallel processing may be advantageous. Similarly, some specific implementation details are included in the above description, but these should not be construed as limiting the scope of this disclosure. Certain features described in relation to a single embodiment can be realized in combination in a single embodiment. Conversely, various features described in relation to a single embodiment can also be realized separately or in some appropriate subcombination in multiple embodiments.

[0085] Although this subject matter is described in a language specific to structural features and / or methodological logic, it should be understood that the subject matter limited to the attached claims is not necessarily limited to the specific features or behaviors described above. Conversely, the specific features and behaviors described above are merely exemplary forms of realizing the claims.

Claims

1. A topology structure used in an IP core, comprising a first topology structure and a second topology structure, wherein the first topology structure comprises a driver chip, multiple stages of first signal lines, and at least two first loads, wherein the signal output terminal of one preceding first signal line is connected to the signal input terminals of two subsequent first signal lines connected in parallel, the signal input terminal of the first stage first signal line is connected to the signal output terminal of the driver chip, and the output terminals of each of the last stage first signal lines are connected to one first load. The second topology structure comprises a plurality of branch structures, each branch structure comprising at least one second load, and the signal input terminal of each branch structure is connected to the signal output terminal of a single first signal line at the last stage of the first topology structure.

2. The topology structure according to claim 1, wherein in the first topology structure, the equivalent impedance of the two parallel-connected signal lines in the later stage is equal to the impedance of the one preceding signal line connected thereto.

3. The topology structure according to claim 1, wherein the branching structure includes at least one second signal line connected to a second load, and the impedance of the second signal line is equal to the impedance of a first signal line connected to the branching structure.

4. The topology structure according to claim 1, wherein the first topology structure includes two stages of first signal lines and two first loads.

5. The topology structure according to claim 1 or 4, wherein the second topology structure includes two branch structures, each branch structure includes one second load.

6. An IP core comprising a substrate, a driver chip provided on the substrate, a plurality of loads, and a connection structure between the plurality of loads and the driver chip, wherein the topology structure connected between the plurality of loads and the driver chip includes a first topology structure and a second topology structure. The first topology structure includes the driver chip, a plurality of stages of first signal lines, and at least two first loads, wherein the signal output terminal of one preceding first signal line is connected to the signal input terminals of two subsequent first signal lines connected in parallel, the signal input terminal of the first stage first signal line is connected to the signal output terminal of the driver chip, and the output terminals of each of the last stage first signal lines are connected to one first load. The second topology structure comprises a plurality of branch structures, each branch structure comprising at least one second load, and the signal input terminal of each branch structure is connected to the signal output terminal of a single first signal line at the last stage of the first topology structure, forming an IP core.

7. The IP core according to claim 6, wherein the second topology structure includes a second signal line, and the first signal line and the second signal line are arranged on a PCB board.

8. The IP core according to claim 7, wherein the equivalent impedance of two parallel-connected first signal lines in the subsequent stage is equal to the impedance of one preceding first signal line connected thereto.

9. The IP core according to claim 7, wherein the impedance of at least one second signal line connected to a second load included in the branch structure is equal to the impedance of a first signal line connected to the branch structure.

10. The first signal line provided on the aforementioned substrate has two stages and two first loads. The IP core according to claim 6, having two branch structures, each branch structure including one second load.

11. The IP core according to claim 6, wherein the Dk value of the substrate is smaller than a predetermined threshold.

12. The IP core according to claim 7, wherein the length of the second signal line is determined according to the maximum signal transmission rate corresponding to the load and the period of the control signal emitted by the driver chip.

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