Semiconductor equipment

Abstract

The purpose of the present invention is to provide a semiconductor element in which a surface electrode can be inhibited from generating thermal strain. The semiconductor device comprises a semiconductor layer, a surface electrode provided on a surface of the semiconductor layer, an element-surface-bonding layer selectively provided on the surface of the surface electrode, a lead frame, and an element-surface-bonding material. The lead frame is located on the surface side of the element-surface-bonding layer, and the element-surface-bonding material bonds the lead frame to the element-surface-bonding layer. The element-surface-bonding material has an elastic modulus which is no more than 20% of the elastic modulus of the surface electrode.

Description

Technical Field

[0001] This disclosure relates to a semiconductor device.

Background Art

[0002] A semiconductor device has been proposed in which a lead frame as an external electrode and a surface electrode of a semiconductor element are joined by solder (for example, Patent Document 1).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In the semiconductor device as described above, due to the difference between the linear expansion coefficient of the solder or the lead frame and the linear expansion coefficient of the semiconductor element, thermal stress is generated in the surface electrode of the semiconductor element, and cracks occur in the surface electrode due to repeated thermal stress.

[0005] Therefore, this disclosure has been made in view of the above problems, and an object thereof is to provide a technology capable of suppressing thermal stress generated in the surface electrode of a semiconductor element.

Means for Solving the Problems

[0006] The semiconductor device according to this disclosure includes a semiconductor layer, a surface electrode provided on the surface of the semiconductor layer, an element surface bonding layer selectively provided on the surface of the surface electrode, a lead frame located on the surface side of the element surface bonding layer, and an element surface bonding material that bonds the lead frame and the element surface bonding layer, and an elastic modulus of the element surface bonding material is 20% or less of an elastic modulus of the surface electrode.

Effects of the Invention

[0007] The purposes, features, aspects, and advantages of this disclosure will become more apparent from the following detailed description and accompanying drawings. [Brief explanation of the drawing]

[0008] [Figure 1] This is a cross-sectional view showing the overall configuration of the semiconductor device according to Embodiment 1. [Figure 2] This is a plan view showing the overall configuration of the semiconductor device according to Embodiment 1. [Figure 3] This is an enlarged cross-sectional view showing a part of the configuration of the semiconductor device according to Embodiment 1. [Figure 4] This figure shows the simulation results of the semiconductor device according to Embodiment 1. [Figure 5] This figure shows the material properties used in the simulation. [Modes for carrying out the invention]

[0009] The embodiments will be described below with reference to the attached drawings. The features described in each of the embodiments below are illustrative, and not all features are necessarily required. In addition, in the descriptions below, the same or similar reference numerals are used for similar components in multiple embodiments, and the different components are mainly described. Also, in the descriptions below, specific positions and directions such as "top," "bottom," "left," "right," "front," or "back" do not necessarily have to coincide with the positions and directions in actual implementation.

[0010] <Embodiment 1> Figures 1 and 2 are a cross-sectional view and a plan view, respectively, showing the overall configuration of the semiconductor device 100 according to this embodiment 1, and Figure 3 is an enlarged cross-sectional view of the dotted line portion in Figure 1.

[0011] As shown in Figure 1, the semiconductor device according to this embodiment 1 comprises a semiconductor element 1, an insulating material 2, an element back surface bonding material 5, a lead frame 6, an element front surface bonding material 7, a signal wiring 8, a control terminal 9, and a sealing resin 10.

[0012] The semiconductor device 1 includes, for example, a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), an IGBT (Insulated Gate Bipolar Transistor), an RC-IGBT (Reverse Conducting IGBT) which integrates an IGBT and a diode, an SBD (Schottky Barrier Diode), and a PND (PN junction diode). As shown in Figure 3, the semiconductor device 1 includes a semiconductor layer 1a, a surface electrode 1b, a device surface junction layer 1c, and a protective film 1d.

[0013] The semiconductor layer 1a comprises at least one of a semiconductor wafer and an epitaxial growth layer. In this specification, for example, at least one of A, B, C, ..., and Z means any one of all combinations obtained by selecting one or more from the groups A, B, C, ..., and Z. The material of the semiconductor layer 1a may include Si, or it may include a wide-bandgap semiconductor such as SiC, GaN, or diamond. When the material of the semiconductor layer 1a includes a wide-bandgap semiconductor, stable operation of the semiconductor device 1 at high temperatures and high voltages, and increased switching speed become possible.

[0014] The surface electrode 1b is provided on the surface of the semiconductor layer 1a. The material of the surface electrode 1b mainly contains Al, for example.

[0015] The element surface bonding layer 1c is selectively provided on the surface of the surface electrode 1b. The material of the element surface bonding layer 1c mainly contains, for example, Ni. The outermost surface of the element surface bonding layer 1c may include a layer that has good bonding properties with the element surface bonding material 7. For example, if the element surface bonding material 7 is solder, the outermost surface of the element surface bonding layer 1c may include an Au layer or the like that has good bonding properties with solder. The Young's modulus of the element surface bonding layer 1c is, for example, 150 Gpa or more and 200 Gpa or less.

[0016] The protective film 1d is selectively provided on the surface of the surface electrode 1b and surrounds the element surface bonding layer 1c in a top view. The material of the protective film 1d includes, for example, polyimide.

[0017] The insulating material 2 in FIG. 1 is located on the back side of the semiconductor layer 1a. The material of the insulating material 2 includes, for example, an insulating resin or a ceramic. The insulating resin of the insulating material 2 mainly includes, for example, an epoxy resin, and the ceramic of the insulating material 2 mainly includes at least one of, for example, Al2O3, Si3N4, and AlN.

[0018] Since the insulating material 2 is required to have not only insulation but also heat dissipation, it is generally desirable to reduce the thickness of the insulating material 2 in order to increase the thermal conductivity of the insulating material 2. However, if the insulating material 2 is made too thin, there may be a shortage of insulation withstand voltage or a shortage of structural withstand voltage (such as stress resistance, etc.) during manufacturing. Therefore, it is desirable that the thickness of the insulating material 2 is 100 μm or more.

[0019] The insulating material 2 has a front surface and a back surface provided with a front surface conductive material 3 and a back surface conductive material 4, respectively. The materials of the front surface conductive material 3 and the back surface conductive material 4 include, for example, a metal which is at least one of Al, an Al alloy, Cu, and a Cu alloy. Since the front surface conductive material 3 and the back surface conductive material 4 are located below the semiconductor element 1 and have a function of diffusing the heat of the semiconductor element 1, it is desirable that they have a sufficient thickness so that heat can be sufficiently diffused in the planar direction. Depending on the planar layout, it is desirable that the front surface conductive material 3 and the back surface conductive material 4 have a thickness of, for example, 0.4 mm or more.

[0020] The backside element bonding material 5 electrically connects the back surface of the semiconductor layer 1a and the surface conductive material 3 of the insulating material 2. For example, the backside element bonding material 5 bonds a back electrode (not shown) provided on the back surface of the semiconductor layer 1a and the surface conductive material 3. Thereby, the main current of the semiconductor element 1 flows through the backside element bonding material 5 and the surface conductive material 3 to other semiconductor elements, external electrode terminals, etc. The material of the backside element bonding material 5 may include, for example, a lead-free solder containing Sn as a main component, or a sintered material containing Ag or Cu as a main component. In order to release the heat of the semiconductor element 1 to the backside of the semiconductor device 100, it is desirable that the backside element bonding material 5 has a thickness of, for example, 0.15 mm or less.

[0021] As shown in FIG. 3, the lead frame 6 is located on the surface side of the element surface bonding layer 1c. The material of the lead frame 6 includes, for example, a highly conductive metal that is at least one of Al, an Al alloy, Cu, and a Cu alloy. Since the lead frame 6 constitutes the main current path of the semiconductor device 100, it is desirable that the current cross-sectional area is large. Depending on the planar layout, it is desirable that the lead frame 6 has a thickness of, for example, 0.1 mm or more.

[0022] The element surface bonding material 7 bonds the lead frame 6 and the element surface bonding layer 1c. The material of the element surface bonding material 7 includes a tin alloy and a thermoplastic resin. Details of the element surface bonding material 7 will be described later.

[0023] The signal wiring 8 in FIG. 1 connects a signal electrode such as a gate electrode of the semiconductor element 1 and the control terminal 9. In order to transmit the signal of the control terminal 9 to the signal electrode, a wire made of, for example, Al, Cu, Ag, etc. is used for the signal wiring 8. In order to ensure the mechanical strength of the signal wiring 8, it is desirable that the signal wiring 8 has a diameter of 100 μm or more. The material of the control terminal 9 includes, for example, a highly conductive metal that is at least one of Al, an Al alloy, Cu, and a Cu alloy.

[0024] The sealing resin 10 seals at least the semiconductor layer 1a. In the example shown in Figure 1, the sealing resin 10 seals the semiconductor element 1, the insulating material 2, the surface conductive material 3, part of the back conductive material 4, the element back bonding material 5, part of the lead frame 6, the element surface bonding material 7, the signal wiring 8, and part of the control terminal 9. Depending on the coefficients of thermal expansion of the semiconductor element 1 and the lead frame 6, the material of the sealing resin 10 is preferably a molding resin with a coefficient of thermal expansion of about 10 to 18 ppm / K.

[0025] In the configuration described above, when the ambient temperature around the semiconductor device 100 changes, thermal deformation such as thermal expansion or contraction occurs in the element surface bonding material 7 or lead frame 6 due to the difference between the coefficient of thermal expansion of the element surface bonding material 7 or lead frame 6 and the coefficient of thermal expansion of the semiconductor element 1. This thermal deformation is transmitted to the surface electrode 1b via the element surface bonding layer 1c, causing thermal strain in the surface electrode 1b. Generally, in fatigue phenomena caused by repeated loading, the Munson-Coffin law, which correlates the fracture life with the strain amplitude of thermal strain, applies, and the larger the strain amplitude of the surface electrode 1b, the shorter the fracture life of the surface electrode 1b. Therefore, the inventor investigated a configuration that reduces the strain amplitude of thermal strain generated in the surface electrode 1b.

[0026] Figure 4 shows the results of a strain amplitude simulation using a two-dimensional model with the same configuration as in Figure 3. Figure 4 shows the relationship between the change in the ratio of the elastic modulus of the element surface bonding material 7 to the elastic modulus of the surface electrode 1b (hereinafter sometimes referred to as the "inter-elastic modulus ratio") and the strain amplitude of the thermal strain generated in the surface electrode 1b. The elastic modulus referred to here is the Young's modulus that can be measured by bending tests, etc. In the simulation, the physical properties of each component were as shown in Figure 5, and the Young's modulus of the element surface bonding material was set to a Young's modulus that resulted in an inter-elastic modulus ratio of 5%, 10%, 15%, 20%, 30%, and 50%.

[0027] As can be seen from Figure 4, the smaller the ratio of elastic moduli, the smaller the strain amplitude of the surface electrode 1b. This is thought to be because, when the ratio of elastic moduli is small, that is, when the Young's modulus of the element surface bonding material 7 is small, the element surface bonding material 7 absorbs the thermal stress transmitted from the lead frame 6 to the surface electrode 1b, thereby suppressing the strain generated in the surface electrode 1b. Also, as can be seen from Figure 4, in the range of 20-30% for the ratio of elastic moduli, there is an inflection point in the change in strain amplitude. Therefore, by setting the ratio of elastic moduli to 20% or less, that is, by setting the elastic modulus of the element surface bonding material 7 to 20% or less of the elastic modulus of the surface electrode 1b, the strain amplitude of the thermal strain generated in the surface electrode 1b can be reduced.

[0028] In this embodiment 1, as described above, the material of the element surface bonding material 7 includes, for example, a tin alloy and a thermoplastic resin. Therefore, by increasing the ratio of thermoplastic resin to tin alloy in the element surface bonding material 7, the elastic modulus of the element surface bonding material 7 can be reduced to 20% or less of the elastic modulus of the surface electrode 1b.

[0029] Furthermore, if the material of the surface electrode 1b mainly contains Al, the elastic modulus (Young's modulus) of the surface electrode 1b is approximately 70 GPa. Therefore, the ratio of thermoplastic resin in the element surface bonding material 7 is adjusted so that the elastic modulus (Young's modulus) of the element surface bonding material 7 becomes 14 GPa or less. In addition, in order to stably reduce the strain amplitude generated in the surface electrode 1b due to the thermal deformation of the lead frame 6, it is desirable that the element surface bonding material 7 has a thickness of 0.2 mm or more.

[0030] The effect of reducing the strain amplitude of the surface electrode 1b as described above is particularly effective when the semiconductor layer 1a of the semiconductor device 1 includes a wide-bandgap semiconductor that can operate stably at high temperatures.

[0031] The details of the embodiment can be modified or omitted as appropriate.

[0032] The above explanation is illustrative and not limiting in all respects. It should be understood that countless variations not illustrated are conceivable. [Explanation of Symbols]

[0033] 1a Semiconductor layer, 1b Surface electrode, 1c Element surface bonding layer, 1d Protective film, 2 Insulating material, 3 Surface conductive material, 4 Back surface conductive material, 5 Element back surface bonding material, 6 Lead frame, 7 Element surface bonding material, 8 Signal wiring, 9 Control terminals, 10 Encapsulating resin, 100 Semiconductor device.

Claims

1. Semiconductor layer, A surface electrode provided on the surface of the semiconductor layer, A device surface bonding layer selectively provided on the surface of the surface electrode, A lead frame located on the surface side of the element surface bonding layer, An element surface bonding material that bonds the lead frame and the element surface bonding layer. Equipped with, A semiconductor device in which the elastic modulus of the element surface bonding material is 20% or less of the elastic modulus of the surface electrode.

2. A semiconductor device according to claim 1, A protective film is selectively provided on the surface of the surface electrode and surrounds the element surface bonding layer when viewed from above, An insulating material located on the back side of the semiconductor layer, having a front surface and a back surface, each provided with a surface conductive material and a back surface conductive material, A back surface bonding material for electrically connecting the back surface of the semiconductor layer and the surface conductive material of the insulating material, The sealing resin that seals the semiconductor layer at least A semiconductor device that further enhances these features.

3. A semiconductor device according to claim 1 or claim 2, The elastic modulus of the surface electrode is 70 GPa or more. A semiconductor device wherein the elastic modulus of the element surface bonding material is 14 GPa or less.

4. A semiconductor device according to claim 1 or claim 2, The semiconductor device comprises a tin alloy and a thermoplastic resin as the material for the surface bonding material of the element.

5. A semiconductor device according to claim 1 or claim 2, The semiconductor device comprises a wide-bandgap semiconductor as the material of the semiconductor layer.

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