Composite electronic components
The composite electronic component design addresses the challenge of layer thickness and smoothness by embedding a conductor layer in an insulating layer and using a protruding conductor layer with solder resist, achieving a thinner, more stable, and magnetically enhanced component.
Patent Information
- Authority / Receiving Office
- JP · JP
- Patent Type
- Patents
- Current Assignee / Owner
- TDK CORP
- Filing Date
- 2022-08-05
- Publication Date
- 2026-06-29
AI Technical Summary
Existing composite electronic components with wiring structures on both surfaces of an insulating layer face challenges in further thinning due to the increased number of layers, requiring improved surface smoothness and reduced thickness.
A composite electronic component design with a conductor layer embedded in an insulating layer and a protruding conductor layer on the outer surface, along with a solder resist configuration that enhances adhesion and allows for magnetic enhancements, while maintaining smoothness and reducing thickness.
The design achieves a thinner composite electronic component with improved surface smoothness, reduced solder resist thickness, enhanced adhesion, and increased magnetic properties, facilitating easier mounting and better thermal stability.
Smart Images
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Abstract
Description
Technical Field
[0001] The present disclosure relates to a composite electronic component, and particularly to a composite electronic component including an insulating layer in which an electronic component is embedded and wiring structures provided on the front and back surfaces of the insulating layer.
Background Art
[0002] Patent Document 1 discloses a printed wiring board having a structure in which an electronic component is embedded in an insulating layer.
Prior Art Documents
Patent Documents
[0003]
Patent Document 1
Summary of the Invention
Problems to be Solved by the Invention
[0004] When a composite electronic component is configured by providing wiring structures on the front and back surfaces of an insulating layer in which an electronic component is embedded, the number of layers of the insulating layer increases, and further thinning is required.
[0005] In the present disclosure, a thin-type composite electronic component having a structure in which wiring structures are provided on the front and back surfaces of an insulating layer in which an electronic component is embedded is described.
Means for Solving the Problems
[0006] A composite electronic component relating to one aspect of this disclosure comprises a first insulating layer in which an electronic component is embedded; a first wiring structure located on one surface side of the first insulating layer and including at least one second insulating layer and conductor layers arranged on both sides thereof; and a second wiring structure located on the other surface side of the first insulating layer and including at least one third insulating layer and conductor layers arranged on both sides thereof, wherein the first conductor layer located on the outermost surface of the conductor layers included in the first wiring structure is embedded in the second insulating layer located on the outermost surface, and the second conductor layer located on the outermost surface of the conductor layers included in the second wiring structure protrudes from the surface of the third insulating layer located on the outermost surface.
[0007] According to this disclosure, since the first conductor layer located on one of the outermost layers is embedded in the second insulating layer, the overall thickness can be reduced and the surface smoothness of the first wiring structure can be improved. Furthermore, since the second conductor layer located on the other outermost layer protrudes from the surface of the third insulating layer, a portion of it can be used as an external terminal.
[0008] A composite electronic component relating to one aspect of this disclosure further comprises a first solder resist covering the surface of a first wiring structure and a second solder resist covering the surface of a second wiring structure, wherein the first conductor layer is covered by the first solder resist without being exposed, and a portion of the second conductor layer may be exposed without being covered by the second solder resist. As a result, since the surface of the first wiring structure is highly smooth, it becomes possible to reduce the thickness of the first solder resist.
[0009] In this disclosure, a gap exists between the side surface of the first conductor layer and the second insulating layer, and the gap may be filled with the first solder resist. This improves the adhesion between the first conductor layer and the first solder resist.
[0010] A composite electronic component relating to one aspect of this disclosure may further include a magnetic resin layer covering a first conductor layer via a first solder resist. Furthermore, a second insulating layer located on the outermost surface may contain a magnetic material. Additionally, a gap may exist between the side surface of the first conductor layer and the second insulating layer, and this gap may be filled with a magnetic material. These arrangements make it possible to enhance the magnetic properties of a magnetic circuit, such as a coil pattern, located on the first conductor layer.
[0011] In this disclosure, the first conductor layer includes a first coil pattern, and the first wiring structure may further include a third conductor layer including a second coil pattern that overlaps with the first coil pattern in a plan view. This makes it possible to magnetically couple the first and second coil patterns.
[0012] In this disclosure, the second wiring structure further includes a fourth conductor layer including a third coil pattern and a fifth conductor layer including a fourth coil pattern that overlaps with the third coil pattern in a plan view, wherein the third coil pattern may be connected to the first coil pattern and the fourth coil pattern may be connected to the second coil pattern. This makes it possible to magnetically couple the third and fourth coil patterns and to connect a circuit consisting of the first and second coil patterns and a circuit consisting of the third and fourth coil patterns in series. [Effects of the Invention]
[0013] Thus, the technology described herein makes it possible to provide a thin composite electronic component having a structure in which wiring structures are provided on both the front and back surfaces of an insulating layer in which electronic components are embedded. [Brief explanation of the drawing]
[0014] [Figure 1] Figure 1 is a schematic perspective view showing the appearance of a composite electronic component 1 according to one embodiment of the technology described herein. [Figure 2]FIG. 2(a) is a schematic cross-sectional view of the cross-section along the line A-A shown in FIG. 1 as viewed from one direction side, and FIG. 2(b) is a schematic cross-sectional view of the cross-section along the line A-A shown in FIG. 1 as viewed from the reverse direction side. [Figure 3] FIG. 3 is a schematic exploded perspective view of the composite electronic component 1. [Figure 4] FIG. 4 is a schematic plan view showing the shape of the conductor pattern provided on the conductor layer C4. [Figure 5] FIG. 5 is a schematic plan view showing the shape of the conductor pattern provided on the conductor layer C3. [Figure 6] FIG. 6 is a schematic plan view showing the shape of the conductor pattern provided on the conductor layer C2. [Figure 7] FIG. 7 is a schematic plan view of the layer in which the ESD protection component 2 is embedded. [Figure 8] FIG. 8 is a schematic plan view showing the shape of the conductor pattern provided on the conductor layer C1. [Figure 9] FIG. 9 is a schematic plan view showing the shape of the conductor pattern provided on the conductor layer C0. [Figure 10] FIG. 10 is an equivalent circuit diagram of the composite electronic component 1. [Figure 11] FIG. 11 is a schematic enlarged view of the region B shown in FIG. 2(a). [Figure 12] FIGS. 12(a) and (b) are schematic enlarged views of the region C shown in FIG. 11. [Figure 13] FIG. 13 is a schematic enlarged view according to the first modification example of the region B shown in FIG. 2(a). [Figure 14] FIG. 14 is a schematic enlarged view according to the second modification example of the region B shown in FIG. 2(a). [Figure 15] FIG. 15 is a schematic enlarged view according to the third modification example of the region B shown in FIG. 2(a). [Figure 16] FIG. 16 is a schematic enlarged view according to the fourth modification example of the region B shown in FIG. 2(a). FIG. 18 is a process diagram for explaining a method of manufacturing the composite electronic component 1. [Figure 19] FIG. 19 is a process diagram for explaining a method of manufacturing the composite electronic component 1. [Figure 20] FIG. 20 is a process diagram for explaining a method of manufacturing the composite electronic component 1. [Figure 21] FIG. 21 is a process diagram for explaining a method of manufacturing the composite electronic component 1. [Figure 22] FIG. 22 is a process diagram for explaining a method of manufacturing the composite electronic component 1. [Figure 23] FIG. 23 is a process diagram for explaining a method of manufacturing the composite electronic component 1. [Figure 24] FIG. 24 is a process diagram for explaining a method of manufacturing the composite electronic component 1. [Figure 25] FIG. 25 is a process diagram for explaining a method of manufacturing the composite electronic component 1. [Figure 26] FIG. 26 is a process diagram for explaining a method of manufacturing the composite electronic component 1. [Figure 27] FIG. 27 is a process diagram for explaining a method of manufacturing the composite electronic component 1. [Figure 28] FIG. 28 is a process diagram for explaining a method of manufacturing the composite electronic component 1. [Figure 29] FIG. 29 is a process diagram for explaining a method of manufacturing the composite electronic component 1. [Figure 30] FIG. 30 is a schematic enlarged view showing an example in which a part of the conductor layer C0 is exposed.
Embodiments for Carrying Out the Invention
[0015] Hereinafter, embodiments of the technology according to the present disclosure will be described in detail with reference to the accompanying drawings.
[0016] FIG. 1 is a schematic perspective view showing the appearance of the composite electronic component 1 according to an embodiment of the technology according to the present disclosure.
[0017] The composite electronic component 1 according to this embodiment is a surface-mount type chip component, and as shown in Figure 1, it comprises a base body 10 and a plurality of external terminals arranged in an array on the surface of the base body 10. The plurality of external terminals consist of eight signal terminals 20 to 27 and two ground terminals 28 and 29.
[0018] Figure 2(a) is a schematic cross-sectional view of the cross-section along line AA shown in Figure 1, viewed from one direction, and Figure 2(b) is a schematic cross-sectional view of the cross-section along line AA shown in Figure 1, viewed from the opposite direction.
[0019] As shown in Figures 2(a) and (b), the base body 10 has a structure in which insulating layers 11 to 14 made of resin or the like are stacked in this order. Of these, insulating layer 11 is provided on one surface 12b side of insulating layer 12, and insulating layers 13 and 14 are provided on the other surface 12a side of insulating layer 12. A conductor layer C1 is formed on one surface 12b side of insulating layer 12. Conductor layer C1 is covered by insulating layer 11. A conductor layer C0 is formed on the surface of insulating layer 11. Conductor layer C0 is covered by solder resist 31. The insulating layer 11 and the conductor layers C0 and C1 arranged on both sides thereof constitute a first wiring structure. Conductor layers C0 and C1 are embedded in insulating layers 11 and 12, respectively. As a result, the flatness of the outermost surface of the first wiring structure is improved compared to the case in which the conductor layer C0 is provided so as to protrude from the surface of insulating layer 11, so that sufficient insulating properties can be ensured even if the thickness of solder resist 31 is reduced. In the examples shown in Figures 2(a) and (b), the first wiring structure includes one insulating layer 11, but the number of insulating layers included in the first wiring structure is not particularly limited.
[0020] A conductor layer C2 is formed on the other surface 12a of the insulating layer 12. The conductor layer C2 is covered by the insulating layer 13. A conductor layer C3 is formed on the surface of the insulating layer 13. The conductor layer C3 is covered by the insulating layer 14. A conductor layer C4 is formed on the surface of the insulating layer 14. The conductor layer C4 is covered by solder resist 32. The insulating layers 13, 14 and the conductor layers C2 to C4 arranged on both sides thereof constitute a second wiring structure. Conductor layers C2 and C3 are embedded in the insulating layers 13 and 14, respectively. In contrast, conductor layer C4 protrudes from the surface of the insulating layer 14. In the examples shown in Figures 2(a) and (b), the second wiring structure includes two insulating layers 13 and 14, but the number of insulating layers included in the second wiring structure is not particularly limited.
[0021] Insulating layers 11 to 14 are all interlayer films with conductive layers on both sides, and in that sense, solder resists 31 and 32 do not qualify as insulating layers. Therefore, the insulating layers located on the outermost surface are insulating layers 11 and 14. In the examples shown in Figures 2(a) and (b), solder resist 31 covers the entire outermost surface of insulating layer 11. As a result, in the examples shown in Figures 2(a) and (b), the conductive layer C0 is covered by solder resist 31 without being exposed. In contrast, solder resist 32 has partial openings, and a portion of the conductive layer C4 exposed through these openings is used as an external terminal.
[0022] An ESD protection component 2 is embedded in the insulating layer 12. Since the ESD protection component 2 is made of a semiconductor substrate, its coefficient of thermal expansion is significantly different from that of the insulating layers 11 to 14. However, in this embodiment, the ESD protection component 2 is embedded approximately in the center in the stacking direction, and insulating layers 11, 13, and 14 are provided on both sides of it. This allows for a high degree of freedom in adjusting the symmetry in the stacking direction by adjusting the thickness, and makes it less likely for the entire composite electronic component 1 to warp due to temperature changes.
[0023] Figure 3 is a roughly exploded perspective view of composite electronic component 1.
[0024] As shown in Figure 3, coil patterns 41 to 48 are embedded in the composite electronic component 1. Of these, coil patterns 41 and 42 are located in the conductor layer C3, coil patterns 43 and 44 are located in the conductor layer C2, coil patterns 45 and 46 are located in the conductor layer C1, and coil patterns 47 and 48 are located in the conductor layer C0. Coil patterns 41 and 43 overlap each other in a plan view via the insulating layer 13, and coil patterns 42 and 44 also overlap each other in a plan view via the insulating layer 13. Furthermore, coil patterns 45 and 47 overlap each other in a plan view via the insulating layer 11, and coil patterns 46 and 48 also overlap each other in a plan view via the insulating layer 11.
[0025] Figures 4-6, 8, and 9 are schematic plan views showing the shapes of the conductor patterns provided in conductor layers C4, C3, C2, C1, and C0, respectively. Figure 7 is a schematic plan view of the layer in which the ESD protection component 2 is embedded. Here, the AA line shown in Figures 4-9 corresponds to the cross-section shown in Figures 2(a) and (b).
[0026] As shown in Figure 4, the conductor layer C4 is provided with conductor patterns 50-59 and a ground pattern GP. The portions of conductor patterns 50-57 that are exposed from the solder resist 32 are surface-treated and used as signal terminals 20-27, respectively. The portions of conductor patterns 58 and 59 that are exposed from the solder resist 32 are surface-treated and used as ground terminals 28 and 29, respectively. Conductor patterns 58 and 59 are connected to each other via the ground pattern GP. The ground pattern GP is a linearly extending conductor pattern, and its width is narrower than the width of conductor patterns 58 and 59. Thus, since the ground pattern GP, signal terminals 20-27, and conductor patterns 58 and 59 are all located on the same conductor layer C4, there is no need to add a dedicated conductor layer for the ground pattern GP.
[0027] As shown in Figure 5, the conductor layer C3 is provided with coil patterns 41, 42 and conductor patterns 60, 61, 63-66. The outer edge of coil pattern 41 is connected to conductor pattern 52 via via conductor 102. The outer edge of coil pattern 42 is connected to conductor pattern 57 via via conductor 107. In addition, conductor patterns 60, 61, 63-66 are connected to conductor patterns 50, 51, 53-56, respectively, via via conductors 100, 101, 103-106 provided in the insulating layer 14. Coil patterns 41 and 42 are adjacent to each other with a gap G1 in between. In the conductor layer C3, there is no ground pattern or anything similar in the gap G1, so coil patterns 41 and 42 are directly adjacent to each other with the insulating layer 14 in between.
[0028] As shown in Figure 6, the conductor layer C2 is provided with coil patterns 43, 44 and conductor patterns 70-76. The outer edge of coil pattern 43 is connected to conductor pattern 63 via via conductor 113. The outer edge of coil pattern 44 is connected to conductor pattern 66 via via conductor 116. Conductor patterns 70-74 are connected to conductor patterns 60, 61, 64, 65, and 68, respectively, via via conductors 110, 111, 114, 115, and 118. Conductor patterns 75 and 76 are connected to the inner edges of coil patterns 41 and 42, respectively, via via conductors 112 and 117. Coil patterns 43 and 44 are adjacent to each other with a gap G1 in between. In the conductor layer C2, no ground pattern or the like is provided in the gap G1, and coil patterns 43 and 44 are directly adjacent to each other with an insulating layer 13 in between.
[0029] Coil patterns 41 to 44 all have a configuration in which the conductor pattern is wound approximately 4 times. Coil patterns 41 and 43 overlap in the stacking direction, and their pattern shapes are almost identical except for the positions of the outer and inner edges. Similarly, coil patterns 42 and 44 overlap in the stacking direction, and their pattern shapes are almost identical except for the positions of the outer and inner edges. Furthermore, the pattern shapes of coil patterns 41 and 42 are symmetrical in plan view, and the pattern shapes of coil patterns 43 and 44 are symmetrical in plan view.
[0030] As shown in Figure 7, terminal electrodes 80 to 87 are provided on the surface of the ESD protection component 2. Terminal electrodes 80 to 83 are connected to conductor patterns 70 to 73, respectively, via via conductors 120 to 123 provided in the insulating layer 12. Terminal electrodes 84 to 87 are also connected to the conductor pattern 74 in common via via conductors 124 to 127 provided in the insulating layer 12.
[0031] As shown in Figure 8, the conductor layer C1 is provided with coil patterns 45, 46 and conductor patterns 91, 93, 94, 97. The outer edge of coil pattern 45 is connected to conductor pattern 70 via via conductor 130. The outer edge of coil pattern 46 is connected to conductor pattern 73 via via conductor 135. The inner edge of coil pattern 45 is connected to conductor pattern 75 via via conductor 132. The inner edge of coil pattern 46 is connected to conductor pattern 76 via via conductor 136. In addition, conductor patterns 91 and 94 are connected to conductor patterns 71 and 72, respectively, via via conductors 131 and 134. Furthermore, conductor patterns 93 and 97 are connected to the inner edges of coil patterns 43 and 44, respectively, via via conductors 133 and 137. Coil patterns 45 and 46 are adjacent to each other with a gap G2 in between. In the conductor layer C1, no ground pattern or anything similar is provided in the gap G2, and coil patterns 45 and 46 are directly adjacent to each other via the insulating layer 12.
[0032] As shown in Figure 9, coil patterns 47 and 48 are provided in the conductor layer C0. The outer and inner ends of coil pattern 47 are connected to conductor patterns 91 and 93, respectively, via conductors 141 and 143. The outer and inner ends of coil pattern 48 are connected to conductor patterns 94 and 97, respectively, via conductors 144 and 147. Coil patterns 47 and 48 are adjacent to each other with a gap G2 in between. In the conductor layer C0, no ground pattern or the like is provided in the gap G2, so coil patterns 47 and 48 are directly adjacent to each other with an insulating layer 11 in between.
[0033] Coil patterns 45 to 48 all have a configuration in which the conductor pattern is wound approximately 5 times. Coil patterns 45 and 47 overlap in the stacking direction, and their pattern shapes are almost identical except for the positions of the outer and inner edges. Similarly, coil patterns 46 and 48 overlap in the stacking direction, and their pattern shapes are almost identical except for the positions of the outer and inner edges. Furthermore, the pattern shapes of coil patterns 45 and 46 are symmetrical in plan view, and the pattern shapes of coil patterns 47 and 48 are symmetrical in plan view.
[0034] Figure 10 is an equivalent circuit diagram of the composite electronic component 1 according to this embodiment.
[0035] As shown in Figure 10, in the composite electronic component 1 according to this embodiment, coil patterns 45 and 41 are connected in series between signal terminals 20 and 22, coil patterns 47 and 43 are connected in series between signal terminals 21 and 23, coil patterns 48 and 44 are connected in series between signal terminals 24 and 26, and coil patterns 46 and 42 are connected in series between signal terminals 25 and 27. Then, common mode filter CMF1 is formed by the magnetic coupling of coil patterns 41 and 43, common mode filter CMF2 is formed by the magnetic coupling of coil patterns 42 and 44, common mode filter CMF3 is formed by the magnetic coupling of coil patterns 45 and 47, and common mode filter CMF4 is formed by the magnetic coupling of coil patterns 46 and 48. Furthermore, protective elements integrated into the ESD protection component 2 are inserted between signal terminals 20, 21, 24, and 25 and ground terminals 28 and 29. Thus, the composite electronic component 1 according to this embodiment constitutes an array of common mode filters with ESD protection function. The ground terminal 29 is connected to the ESD protection component 2 via the ground pattern GP.
[0036] The ground pattern GP connects the ground terminals 28 and 29 by connecting the conductor pattern 58 and conductor pattern 59. Here, the conductor pattern 59 does not have a corresponding via conductor, and therefore the ground potential applied to the ground terminal 29 is supplied to the conductor pattern 58 via the conductor pattern 59 and the ground pattern GP. In other words, the ground terminal 29 is used as a so-called dummy terminal. The reason for providing such a ground terminal 29 is to ensure sufficient mounting strength when the composite electronic component 1 according to this embodiment is mounted on a circuit board. Furthermore, since there is no via conductor in the position that overlaps with the conductor pattern 59 in a plan view, the conductor pattern 59 is prone to delamination, but in this embodiment, since the conductor pattern 59 is connected to the conductor pattern 58 via the ground pattern GP, delamination of the conductor pattern 59 is also prevented.
[0037] Figure 11 is a schematic enlarged view of region B shown in Figure 2(a). Figure 12(a) is a schematic enlarged view of region C shown in Figure 11.
[0038] As shown in Figures 11 and 12(a), a gap S exists between the side surface of the conductor layer C0, which includes the coil pattern 47, and the insulating layer 11, and a portion of the solder resist 31 fills this gap S. The side surface of the conductor layer C0 refers to the surface of the conductor layer C0 that is approximately parallel to the lamination direction. As a result, the conductor layer C0 is in contact with the insulating layer 11 on the upper surface shown in Figure 11, and with the solder resist 31 on the lower surface and side surfaces. Therefore, the adhesion between the conductor layer C0 and the solder resist 31 is enhanced. Furthermore, as shown in Figure 12(a), which is a schematic enlargement of region C shown in Figure 11, the lower surface 151, which is the outermost surface of the conductor layer C0, may be set back from the outermost surface 152 of the insulating layer 11. In this case, the thickness of the solder resist 31 increases slightly in the portion covering the conductor layer C0, thereby enhancing the insulating properties of the conductor layer C0 by the solder resist 31.
[0039] Thus, in this embodiment, the composite electronic component 1 has a conductor layer C0 located on one of the outermost layers embedded in the insulating layer 11, which allows for a thinner overall thickness. Furthermore, the smoothness of one of the outermost layers is improved, making it possible to reduce the thickness of the solder resist 31. As a result, this embodiment provides a thinner composite electronic component 1. In addition, since the conductor layer C4 located on the other outermost layer protrudes from the surface of the insulating layer 14, an opening can be provided in the solder resist 32, allowing the portion exposed from the solder resist 32 to be used as an external terminal.
[0040] Furthermore, when the composite electronic component 1 is mounted on the circuit board, the number of turns, wiring length, and coil diameter of the coil patterns 45-48, which are further from the circuit board, are larger than those of the coil patterns 41-44, which are closer to the circuit board. As a result, the coil patterns 45-48, which have greater inductance, become less affected by the circuit board.
[0041] Furthermore, since coil patterns 41-44 are arranged on the other surface 12a side of the insulating layer 12 in which the ESD protection component 2 is embedded, and coil patterns 45-48 are arranged on the other surface 12b side, the inductance of each common mode filter can be sufficiently increased, and the warping of the composite electronic component 1 caused by the difference in thermal expansion coefficients between the insulating layers 11-14 and the ESD protection component 2 can be reduced.
[0042] Furthermore, since coil patterns 41-44 and coil patterns 45-48 are sufficiently separated in the stacking direction, and their pattern shapes, specifically their diameter and number of turns, are different from each other, magnetic coupling between them is suppressed. Therefore, even if the pattern shape of coil patterns 41-44 is changed for characteristic adjustment, the characteristics of coil patterns 45-48 hardly change, making design changes easy. Moreover, since the two coil patterns located in the same conductor layer are symmetrical in plan view, there is almost no difference in characteristics between the two common-mode filters, and pattern design is also simplified.
[0043] Figure 13 is a schematic enlarged view of a first modified example of region B shown in Figure 2(a). In the example shown in Figure 13, the surface of the solder resist 31 is covered with a magnetic resin layer 15. By providing a magnetic resin layer 15 that covers the conductor layer C0 via the solder resist 31 in this way, it is possible to improve the magnetic properties of the coil patterns 45-48. Moreover, since the magnetic resin layer 15 is provided on the solder resist 31, it is also possible to use a conductive material as the material for the magnetic resin layer 15. Furthermore, by using a material for the magnetic resin layer 15 that has a coefficient of thermal expansion similar to that of the ESD protection component 2, it is possible to reduce the warping of the composite electronic component 1.
[0044] Figure 14 is a schematic enlarged view of a second modification of region B shown in Figure 2(a). In the example shown in Figure 14, a magnetic material is included in the insulating layer 11, which significantly increases the magnetic permeability of the insulating layer 11. This makes it possible to further improve the magnetic properties of the coil patterns 45-48.
[0045] Figure 15 is a schematic enlarged view of a third modification of region B shown in Figure 2(a). In the example shown in Figure 15, the solder resist 31 contains a magnetic material, which significantly increases the magnetic permeability of the solder resist 31. This makes it possible to further improve the magnetic properties of the coil patterns 45-48. The magnetic filler added to the solder resist 31 preferably contains a particle size that can penetrate the gap S. This makes it possible to fill the gap S with magnetic material.
[0046] Figure 16 is a schematic enlarged view of a fourth modified example of region B shown in Figure 2(a). In the example shown in Figure 16, the solder resist 31 contains a magnetic material, and recesses 160 are provided on the surface of the insulating layer 11. As a result, the solder resist 31 containing the magnetic material also penetrates into the recesses 160 provided in the insulating layer 11, making it possible to further enhance the magnetic properties of the coil patterns 45-48. The depth of the recesses 160 may be greater than the thickness of the conductor layer C0, or less than the thickness of the conductor layer C0, or it may extend to the conductor layer C1 to the extent that it does not reach the embedded electronic components. Methods for forming the recesses 160 include laser processing and blasting.
[0047] Next, a method for manufacturing the composite electronic component 1 according to this embodiment will be described.
[0048] Figures 17 to 29 are process diagrams illustrating the manufacturing method of the composite electronic component 1 according to this embodiment.
[0049] First, a carrier-attached copper foil 200 is prepared, and a resist pattern 201 is formed on its surface (Figure 17). The carrier-attached copper foil 200 has a structure in which a release layer is provided between two layers of copper foil. The resist pattern 201 is a negative pattern of the conductive layer C0. In this state, electrolytic plating is performed to remove the resist pattern 201 and form the conductive layer C0 (Figure 18). Next, an insulating layer 11 is formed on the surface of the carrier-attached copper foil 200 so that the conductive layer C0 is embedded (Figure 19). As a result, the conductive pattern located in the conductive layer C0 is covered on its sides and top by the insulating layer 11.
[0050] Next, a portion of the conductor layer C0 is exposed by forming vias 202 at the locations where via conductors should be formed, and then a seed layer 203 is formed on the surface of the insulating layer 11 by electroless plating (Figure 20). Next, a resist pattern 204 is formed on the surface of the seed layer 203, and then the conductor layer C1 is formed by electrolytic plating (Figure 21). Next, after removing the resist pattern 204 (Figure 22), an insulating layer 12A is formed on the surface of the insulating layer 11 so that the conductor layer C1 is embedded, and the ESD protection component 2 is mounted on its surface (Figure 23). As a result, the conductor pattern located in the conductor layer C1 is covered on the sides and top by the insulating layer 12A. Next, an insulating layer 12B is formed on the surface of the insulating layer 12A so that the ESD protection component 2 is embedded (Figure 24). As a result, the ESD protection component 2 is embedded in the insulating layer 12 consisting of insulating layers 12A and 12B.
[0051] Next, by repeating the process described using Figures 20 to 22, a conductive layer C2 is formed on the surface of the insulating layer 12, and then an insulating layer 13 is formed on the surface of the insulating layer 12 so that the conductive layer C2 is embedded (Figure 25). By repeating this process, a conductive layer C3 is formed on the surface of the insulating layer 13, and then an insulating layer 14 is formed on the surface of the insulating layer 13 so that the conductive layer C3 is embedded (Figure 26). Next, after forming a conductive layer C4 on the surface of the insulating layer 14, one layer of copper foil is peeled off via a release layer provided on the carrier-attached copper foil 200 (Figure 27), and the remaining copper foil of the carrier-attached copper foil 200 is removed by etching (Figure 28). This etching also removes the seed layer used to form the conductive layer C4. At this time, by adjusting conditions such as the etching time, it is possible to form a gap S between the side surface of the conductive layer C0 and the insulating layer 11. The gap S may be a tapered shape that narrows in the depth direction to improve the filling of the solder resist 31, as shown in Figure 12(b). The gap S does not need to expose the entire side surface of the conductor layer C0; as shown in Figure 12(b), a portion of the side surface of the conductor layer C0 may remain in contact with the insulating layer 11. Furthermore, by setting a longer etching time, it is possible to create a recess in the lower surface 151 of the conductor layer C0 relative to the outermost surface 152 of the insulating layer 11, as shown in Figures 12(a) and (b). After forming solder resists 31 and 32 on the outermost surfaces of the insulating layers 11 and 14, respectively (Figure 29), the composite electronic component 1 according to this embodiment is completed by forming the signal terminals 21-27 and ground terminals 28 and 29 by surface treatment.
[0052] Thus, in the manufacturing process of the composite electronic component 1 according to this embodiment, instead of stacking wiring structures on both sides of the insulating layer 12 in which the ESD protection component 2 is embedded, the conductive layer C0 is stacked in the order of conductive layer C4. As a result, it is possible to obtain a structure in which the conductive layer C0 located on one of the outermost layers is embedded in the insulating layer 11. Moreover, by adjusting the etching conditions, it is also possible to form a gap S between the side surface of the conductive layer C0 and the insulating layer 11.
[0053] While embodiments of the technology described herein have been explained above, it goes without saying that the technology described herein is not limited to the embodiments described above, and various modifications are possible without departing from its spirit, and these modifications are also included within the scope of the technology described herein.
[0054] For example, in the above embodiment, the ESD protection component 2 is embedded in the insulating layer 12, but the electronic components embedded in the insulating layer 12 are not limited to this.
[0055] Furthermore, in the examples shown in Figures 2(a) and (b) described above, the entire surface of the conductor layer C0 is covered with solder resist 31, but the technology of this disclosure is not limited to this. For example, as shown in Figure 30, a part of the conductor layer C0 may be exposed from the solder resist 31 by providing an opening 31a in a part of the solder resist 31. Even when a part of the conductor layer C0 is exposed from the solder resist 31, the overall thickness can be reduced and the smoothness of one of the outermost layers can be improved because the conductor layer C0 is embedded in the insulating layer 11. When a part of the conductor layer C0 is exposed from the opening 31a of the solder resist 31, an external terminal or wiring structure electrically connected to the exposed portion may be provided, or the exposed portion itself may be used as a terminal electrode. In this case, it is also possible to form an external terminal on the side facing the external terminal formed by the conductor layer C4 in the thickness direction (stacking direction) of the composite electronic component 1. [Explanation of symbols]
[0056] 1. Composite electronic components 2 ESD protection parts (electronic parts) 10 Base Body 11-14, 12A, 12B Insulating layer 15 Magnetic resin layer 12a, 12b Surface of the insulating layer 20-27 Signal terminals 28,29 Ground terminal 31,32 Solder Resist 31a opening 41-48 Coil Patterns 50-59 Conductor Pattern Conductor patterns 60, 61, 63~66, 68 70-76 Conductor Pattern 80~87 Terminal electrode 91, 93, 94, 97 Conductor patterns 100~107, 110~118, 120~127, 130~137, 141, 143, 144, 147 via conductors 151,152 Top surface 160 Recessed section 200 Carrier-equipped copper foil 201 Resist Pattern 202 Beer 203 Seed Layer 204 Resist Patterns C0~C4 Conductor Layers CMF1~CMF4 Common Mode Filters G1, G2 gap GP Ground Pattern S Gap
Claims
1. A first insulating layer in which electronic components are embedded, A first wiring structure located on one surface side of the first insulating layer, comprising at least one second insulating layer and conductor layers arranged on both sides thereof, A second wiring structure located on the other surface side of the first insulating layer, comprising at least one third insulating layer and conductor layers arranged on both sides thereof, A first solder resist covering the surface of the first wiring structure, The second wiring structure comprises a second solder resist covering the surface of the second wiring structure, The first conductor layer located on the outermost surface among the conductor layers included in the first wiring structure is embedded in the second insulating layer located on the outermost surface. The second conductor layer located at the outermost surface of the conductor layers included in the second wiring structure protrudes from the surface of the third insulating layer located at the outermost surface. The first conductive layer is covered with the first solder resist without being exposed. A portion of the second conductor layer is exposed without being covered by the second solder resist. A composite electronic component in which a gap exists between the side surface of the first conductive layer and the second insulating layer, and the gap is filled with the first solder resist.
2. A first insulating layer in which electronic components are embedded, A first wiring structure located on one surface side of the first insulating layer, comprising at least one second insulating layer and conductor layers arranged on both sides thereof, A second wiring structure located on the other surface side of the first insulating layer, comprising at least one third insulating layer and conductor layers arranged on both sides thereof, A first solder resist covering the surface of the first wiring structure, The second wiring structure comprises a second solder resist covering the surface of the second wiring structure, The first conductor layer located on the outermost surface among the conductor layers included in the first wiring structure is embedded in the second insulating layer located on the outermost surface. The second conductor layer located at the outermost surface of the conductor layers included in the second wiring structure protrudes from the surface of the third insulating layer located at the outermost surface. A portion of the first conductor layer is exposed without being covered by the first solder resist. A portion of the second conductive layer is exposed without being covered by the second solder resist. A composite electronic component in which a gap exists between the side surface of the first conductive layer and the second insulating layer, and the gap is filled with the first solder resist.
3. A first insulating layer in which electronic components are embedded, A first wiring structure located on one surface side of the first insulating layer, comprising at least one second insulating layer and conductor layers arranged on both sides thereof, A second wiring structure located on the other surface side of the first insulating layer, comprising at least one third insulating layer and conductor layers arranged on both sides thereof, A first solder resist covering the surface of the first wiring structure, The second wiring structure comprises a second solder resist covering the surface of the second wiring structure, The first conductor layer located on the outermost surface among the conductor layers included in the first wiring structure is embedded in the second insulating layer located on the outermost surface. The second conductor layer located at the outermost surface of the conductor layers included in the second wiring structure protrudes from the surface of the third insulating layer located at the outermost surface. The first conductive layer is covered with the first solder resist without being exposed. A portion of the second conductor layer is exposed without being covered by the second solder resist. A composite electronic component further comprising a magnetic resin layer covering the first conductor layer via the first solder resist.
4. A first insulating layer in which electronic components are embedded, A first wiring structure located on one surface side of the first insulating layer, comprising at least one second insulating layer and conductor layers arranged on both sides thereof, A second wiring structure is located on the other surface side of the first insulating layer and includes at least one third insulating layer and conductor layers arranged on both sides thereof, The first conductor layer located on the outermost surface among the conductor layers included in the first wiring structure is embedded in the second insulating layer located on the outermost surface. The second conductor layer located at the outermost surface of the conductor layers included in the second wiring structure protrudes from the surface of the third insulating layer located at the outermost surface. A composite electronic component in which the second insulating layer located on the outermost surface contains a magnetic material.
5. A first insulating layer in which electronic components are embedded, A first wiring structure located on one surface side of the first insulating layer, comprising at least one second insulating layer and conductor layers arranged on both sides thereof, A second wiring structure is located on the other surface side of the first insulating layer and includes at least one third insulating layer and conductor layers arranged on both sides thereof, The first conductor layer located on the outermost surface among the conductor layers included in the first wiring structure is embedded in the second insulating layer located on the outermost surface. The second conductor layer located at the outermost surface of the conductor layers included in the second wiring structure protrudes from the surface of the third insulating layer located at the outermost surface. A composite electronic component in which a gap exists between the side surface of the first conductive layer and the second insulating layer, and a magnetic material is filled in the gap.
6. The first conductor layer includes a first coil pattern, The composite electronic component according to any one of claims 1 to 5, wherein the first wiring structure further includes a third conductor layer having a second coil pattern that overlaps with the first coil pattern in a plan view.
7. The second wiring structure further includes a fourth conductor layer containing a third coil pattern and a fifth conductor layer containing a fourth coil pattern that overlaps with the third coil pattern in a plan view. The third coil pattern is connected to the first coil pattern. The composite electronic component according to claim 6, wherein the fourth coil pattern is connected to the second coil pattern.