Semiconductor equipment
The semiconductor device addresses parasitic resistance in silicon carbide MOSFETs by optimizing contact areas and distances within the silicon carbide layer, resulting in reduced on-resistance and improved performance.
Patent Information
- Authority / Receiving Office
- JP · JP
- Patent Type
- Patents
- Current Assignee / Owner
- KK TOSHIBA
- Filing Date
- 2023-03-24
- Publication Date
- 2026-06-29
AI Technical Summary
Existing silicon carbide MOSFETs face challenges in reducing parasitic resistance, which affects their performance and efficiency.
The semiconductor device incorporates a specific structure with multiple contact surfaces and regions of varying conductivity types and impurity concentrations within the silicon carbide layer, optimizing the contact area and reducing the distance between the source region and the channel region to minimize parasitic resistance.
This design effectively reduces the on-resistance of the MOSFET by minimizing parasitic resistance, enhancing its performance and efficiency.
Smart Images
Figure 0007881505000001 
Figure 0007881505000002 
Figure 0007881505000003
Abstract
Description
[Technical Field]
[0001] Embodiments of the present invention relate to semiconductor devices. [Background technology]
[0002] Silicon carbide is a material used in semiconductor devices. Compared to silicon, silicon carbide has superior physical properties, with a band gap approximately three times larger, a breakdown field strength approximately ten times greater, and a thermal conductivity approximately three times greater. By utilizing these properties, it is possible to realize, for example, MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) that have high voltage resistance, low loss, and can operate at high temperatures.
[0003] To improve the performance of silicon carbide MOSFETs, it is expected that the on-resistance will be reduced. To reduce the on-resistance of a MOSFET, it is thought that the parasitic resistance of the MOSFET will be reduced. Parasitic resistance of a MOSFET is, for example, the electrical resistance of the source region and the contact resistance between the source electrode and the source region. [Prior art documents] [Patent Documents]
[0004] [Patent Document 1] Japanese Patent Publication No. 2017-168668 [Overview of the project] [Problems that the invention aims to solve]
[0005] The problem that this invention aims to solve is to provide a semiconductor device that can reduce parasitic resistance. [Means for solving the problem]
[0006] The semiconductor device of the embodiment includes a silicon carbide layer having a first surface and a second surface facing the first surface, a first gate electrode provided on the side of the first surface of the silicon carbide layer, a second gate electrode provided on the side of the first surface of the silicon carbide layer, a first region provided within the silicon carbide layer and in contact with the first surface, the first region being a first silicon carbide region of a first conductivity type facing the first gate electrode, and a first silicon carbide region provided within the silicon carbide layer and between the first silicon carbide region and the first surface A second region is provided between the first and second surfaces, the second region having a second silicon carbide region of a second conductivity type facing the first gate electrode, a third silicon carbide region of a second conductivity type provided within the silicon carbide layer and between the second silicon carbide region and the first surface, having a second conductivity type impurity concentration higher than that of the second silicon carbide region, and a fourth silicon carbide region of a first conductivity type provided within the silicon carbide layer and between the third silicon carbide region and the first surface. A primary region, a first gate insulating layer provided between the first gate electrode and the second region, and a first electrode provided on the side of the first surface of the silicon carbide layer, including a first portion provided between the first gate electrode and the second gate electrode, the first portion including a first contact surface in contact with the silicon carbide layer and intersecting the first surface, a second contact surface in contact with the silicon carbide layer and intersecting the first contact surface, a third contact surface in contact with the silicon carbide layer and intersecting the second contact surface, and the carbide The first electrode has a fourth contact surface that is in contact with the silicon carbide layer and intersects with the third contact surface, the first contact surface is in contact with the fourth silicon carbide region and faces the second region, the second contact surface is in contact with the fourth silicon carbide region and faces the second surface, the third contact surface is in contact with the fourth silicon carbide region and the third silicon carbide region, and the fourth contact surface is in contact with the third silicon carbide region and faces the second surface, and the second electrode is provided on the side of the second surface of the silicon carbide layer. The distance from the first surface to the second contact surface in the first direction toward the second surface is at least one-third of the depth of the fourth silicon carbide region in the first direction. . [Brief explanation of the drawing]
[0007] [Figure 1] A schematic cross-sectional view of the semiconductor device according to the first embodiment. [Figure 2] Top view of the semiconductor device according to the first embodiment. [Figure 3] Cross-sectional view of the semiconductor device according to the first embodiment. [Figure 4] Enlarged cross-sectional view of the semiconductor device according to the first embodiment. [Figure 5] Enlarged cross-sectional view of the semiconductor device according to the first comparative example. [Figure 6] Enlarged cross-sectional view of the semiconductor device according to the second comparative example. [Figure 7] Cross-sectional view of the semiconductor device according to the second embodiment. [Figure 8] Top view of the semiconductor device according to the second embodiment. [Figure 9] Cross-sectional view of the semiconductor device according to the second embodiment. [Figure 10] Cross-sectional view of the semiconductor device according to the second embodiment.
Embodiments for Carrying Out the Invention
[0008] Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following description, the same or similar members are denoted by the same reference numerals, and the description of the members once described may be omitted as appropriate.
[0009] Also, in the following description, n + , n, n - and, p + , p, p - notation represents the relative level of impurity concentration in each conductivity type. That is, n + has a relatively higher n-type impurity concentration than n, and n - has a relatively lower n-type impurity concentration than n. Also, p + has a relatively higher p-type impurity concentration than p, and p - has a relatively lower p-type impurity concentration than p. Note that n + type, n - type may be simply described as n-type, p + type, p - type may be simply described as p-type.
[0010] The distances of the components of the semiconductor device in the embodiment, such as thickness, width, spacing, and depth, can be determined, for example, from images obtained from an SEM (Scanning Electron Microscope) or a TEM (Transmission Electron Microscope).
[0011] The impurity concentration of the semiconductor device in the embodiment can be measured, for example, by SIMS (Secondary Ion Mass Spectrometry). Furthermore, the relative levels of impurity concentrations can be determined, for example, from the carrier concentrations obtained by SCM (Scanning Capacitance Microscopy). The depth, thickness, and other distances of the impurity regions can be determined, for example, by SIMS. Additionally, the depth, thickness, width, and spacing of the impurity regions can be determined, for example, from a composite image of an SCM image and an AFM (Atomic Force Microscope) image. Furthermore, the depth, thickness, width, and spacing of the impurity regions can be determined, for example, from an image acquired by SEM.
[0012] (First embodiment) The semiconductor device of the first embodiment includes a silicon carbide layer having a first surface and a second surface facing the first surface, a first gate electrode provided on the side of the first surface of the silicon carbide layer, a second gate electrode provided on the side of the first surface of the silicon carbide layer, a first silicon carbide region having a first conductivity type and a first region in contact with the first surface and provided within the silicon carbide layer, and provided between the first silicon carbide region and the first surface and in contact with the first surface, and the second region having a second conductivity type and a first conductivity type The device comprises a second silicon carbide region of a certain shape, a third silicon carbide region of a second conductivity type provided within the silicon carbide layer and between the second silicon carbide region and the first surface, having a higher concentration of second conductivity type impurities than the second conductivity type impurities concentration in the second silicon carbide region, a fourth silicon carbide region of a first conductivity type provided within the silicon carbide layer and between the third silicon carbide region and the first surface, a first gate insulating layer provided between the first gate electrode and the second region, a first electrode provided on the side of the first surface of the silicon carbide layer, and a second electrode provided on the side of the second surface of the silicon carbide layer. The first electrode includes a first portion provided between the first gate electrode and the second gate electrode, the first portion having a first contact surface in contact with the silicon carbide layer and intersecting with the first surface, a second contact surface in contact with the silicon carbide layer and intersecting with the first contact surface, a third contact surface in contact with the silicon carbide layer and intersecting with the second contact surface, and a fourth contact surface in contact with the silicon carbide layer and intersecting with the third contact surface. The first contact surface is in contact with the fourth silicon carbide region and faces the second region, the second contact surface is in contact with the fourth silicon carbide region and faces the second surface, the third contact surface is in contact with the fourth silicon carbide region and the third silicon carbide region, and the fourth contact surface is in contact with the third silicon carbide region and faces the second surface.
[0013] Figure 1 is a schematic cross-sectional view of a semiconductor device according to the first embodiment. Figure 2 is a schematic top view of the first embodiment. Figure 2 shows the gate electrode pattern superimposed with the silicon carbide region on the silicon carbide layer surface and the source electrode pattern. Figure 3 is a schematic cross-sectional view of a semiconductor device according to the first embodiment. Figure 4 is an enlarged schematic cross-sectional view of a semiconductor device according to the first embodiment.
[0014] Figure 1 is a section AA' of Figure 2. Figure 3 is a section BB' of Figure 2. Figure 4 is an enlarged section of a portion of Figure 1.
[0015] The semiconductor device of the first embodiment is a planar gate type vertical MOSFET 100 using silicon carbide. The MOSFET 100 of the first embodiment is a Double Implantation MOSFET (DIMOSFET) in which the body region and source region are formed by ion implantation, for example.
[0016] The following explanation will use the case where the first conductivity type is n-type and the second conductivity type is p-type as an example. MOSFET100 is a vertical n-channel MOSFET that uses electrons as carriers.
[0017] The MOSFET 100 comprises a silicon carbide layer 10, a source electrode 12, a drain electrode 14, a first gate insulating layer 16, a second gate insulating layer 17, a first gate electrode 18, a second gate electrode 19, and an interlayer insulating layer 20. The source electrode 12 is an example of a first electrode. The drain electrode 14 is an example of a second electrode.
[0018] The source electrode includes a silicide region 12a and a metallic region 12b. The source electrode includes a first contact portion 12x. The first contact portion 12x is an example of a first portion. The first contact portion 12x includes a first contact surface CP1, a second contact surface CP2, a third contact surface CP3, and a fourth contact surface CP4.
[0019] Within the silicon carbide layer 10, n + Shape of drain region 22, n - Shape drift region 24, p-shaped body region 26, p + Body contact area 27, n + A shaped source region 28 is provided. The drift region 24 is an example of a first silicon carbide region. The body region 26 is an example of a second silicon carbide region. The body contact region 27 is an example of a third silicon carbide region. The source region 28 is an example of a fourth silicon carbide region.
[0020] The drift region 24 includes the JFET region 24x. The body region 26 includes the channel region 26x. The JFET region 24x is an example of a first region. The channel region 26x is an example of a second region.
[0021] Hereafter, the direction from the first surface P1 to the second surface P2 will be defined as the first direction. The direction parallel to the first surface will be defined as the second direction, and the direction parallel to the first surface P1 and perpendicular to the second direction will be defined as the third direction.
[0022] The silicon carbide layer 10 is provided between the source electrode 12 and the drain electrode 14. The silicon carbide layer 10 is provided between the first gate electrode 18 and the second gate electrode 19 and the drain electrode 14. The silicon carbide layer 10 is single-crystal SiC. The silicon carbide layer 10 is, for example, 4H-SiC.
[0023] The silicon carbide layer 10 comprises a first surface ("P1" in Figure 1) and a second surface ("P2" in Figure 1). Hereinafter, the first surface may be referred to as the front surface and the second surface as the back surface. Hereinafter, "depth" refers to the depth relative to the first surface.
[0024] The first surface P1 is, for example, a surface inclined at an angle of 0 to 8 degrees relative to the (0001) surface. The second surface P2 is, for example, a surface inclined at an angle of 0 to 8 degrees relative to the (000-1) surface. The (0001) surface is referred to as the silicon surface. The (000-1) surface is referred to as the carbon surface.
[0025] n + The drain region 22 is provided on the back side of the silicon carbide layer 10. The drain region 22 contains, for example, nitrogen (N) as an n-type impurity. The concentration of n-type impurities in the drain region 22 is, for example, 1 × 10⁻⁶ 18 cm -3 The above 1 x 10 21 cm -3 The following applies:
[0026] n -The drift region 24 is provided between the drain region 22 and the first surface P1. The drift region 24 is provided between the source electrode 12 and the drain electrode 14.
[0027] The drift region 24 is provided on the drain region 22. The drift region 24 is, for example, a silicon carbide region formed on the drain region 22 using an epitaxial growth method.
[0028] The drift region 24 includes a JFET region 24x in contact with the first surface P1. The JFET region 24x is sandwiched between adjacent body regions 26 in the second direction. The JFET region 24x faces the first gate electrode 18. The JFET region 24x is in contact with the first gate insulating layer 16.
[0029] The drift region 24 contains, for example, nitrogen (N) as an n-type impurity. The concentration of n-type impurities in the drift region 24 is lower than the concentration of n-type impurities in the drain region 22. The concentration of n-type impurities in the drift region 24 is, for example, 4 × 10⁻⁶. 14 cm -3 The above 1 x 10 18 cm -3 The following applies: The thickness of the drift region 24 is, for example, between 5 μm and 150 μm.
[0030] The p-shaped body region 26 is provided between the drift region 24 and the first surface P1. The body region 26 extends in a third direction on the first surface P1. Multiple body regions 26 are arranged spaced apart in a second direction.
[0031] The body region 26 includes a channel region 26x that is in contact with the first surface P1. The channel region 26x is the region where a channel is formed through which carriers flow when the MOSFET 100 is turned on.
[0032] The channel region 26x is sandwiched between the JFET region 24x and the source region 28 in the second direction. The channel region 26x faces the first gate electrode 18. The channel region 26x is in contact with the first gate insulating layer 16.
[0033] Body region 26 contains, for example, aluminum (Al) as a p-type impurity. The concentration of p-type impurities in body region 26 is, for example, 1 × 10⁻⁶ 17 cm -3 The above 1 x 10 18 cm -3 The following applies:
[0034] The depth of the body region 26 is, for example, between 500 nm and 1200 nm.
[0035] The body region 26 is fixed, for example, to the potential of the source electrode 12.
[0036] p + The shaped body contact region 27 is provided between the body region 26 and the first surface P1. The body contact region 27 extends in a third direction.
[0037] The p-type impurity concentration in the body contact region 27 is higher than that in the body region 26.
[0038] The body contact region 27 contains, for example, aluminum (Al) as a p-type impurity. The concentration of the p-type impurity in the body contact region 27 is, for example, 1 × 10⁻⁶. 19 cm -3 The above 1 x 10 21 cm -3 The following applies:
[0039] The depth of the body contact area 27 is, for example, between 300 nm and 600 nm.
[0040] The body contact region 27 is in contact with the source electrode 12. The junction between the body contact region 27 and the source electrode 12 is, for example, an ohmic junction.
[0041] n +The source region 28 of the shape is provided between the body region 26 and the first surface P1. The source region 28 is provided between the body contact region 27 and the first surface P1. The source region 28 extends in a third direction on the first surface P1.
[0042] Source region 28 contains, for example, phosphorus (P) as an n-type impurity. The concentration of n-type impurities in source region 28 is higher than the concentration of n-type impurities in drift region 24.
[0043] The n-type impurity concentration in source region 28 is, for example, 1 × 10⁻⁶ 19 cm -3 The above 1 x 10 21 cm -3 The following conditions apply: The depth of the source region 28 is shallower than the depth of the body region 26 and the depth of the body contact region 27. The depth of the source region 28 is between 150 nm and 300 nm.
[0044] The source region 28 is in contact with the source electrode 12. The junction between the source region 28 and the source electrode 12 is, for example, an ohmic junction.
[0045] The source region 28 is fixed at the potential of the source electrode 12.
[0046] The first gate electrode 18 is provided on the side of the first surface P1 of the silicon carbide layer 10. As shown in Figure 2, the first gate electrode 18 extends in a third direction parallel to the first surface P1.
[0047] The second gate electrode 19 is provided on the side of the first surface P1 of the silicon carbide layer 10. As shown in Figure 2, the second gate electrode 19 extends in a third direction parallel to the first surface P1. The second gate electrode 19 is provided in a second direction relative to the first gate electrode 18.
[0048] The first gate electrode 18 and the second gate electrode 19 are conductive layers. The first gate electrode 18 and the second gate electrode 19 are, for example, polycrystalline silicon containing p-type or n-type impurities.
[0049] The first gate insulating layer 16 is provided between the first gate electrode 18 and the drift region 24 and the body region 26. The first gate insulating layer 16 is provided between the first gate electrode 18 and the JFET region 24x and the channel region 26x.
[0050] The second gate insulating layer 17 is provided between the second gate electrode 19 and the drift region 24 and the body region 26.
[0051] The first gate insulating layer 16 and the second gate insulating layer 17 are, for example, silicon oxide. For the first gate insulating layer 16 and the second gate insulating layer 17, for example, high-k insulating materials (high dielectric constant insulating materials) can be applied.
[0052] The interlayer insulating layer 20 is provided on the first gate electrode 18, the second gate electrode 19, and the silicon carbide layer 10. The interlayer insulating layer 20 is, for example, silicon oxide.
[0053] The source electrode 12 is provided on the side of the first surface P1 of the silicon carbide layer 10. The source electrode 12 is in contact with the source region 28. The source electrode 12 is in contact with the body contact region 27.
[0054] The source electrode 12 includes a silicide region 12a and a metallic region 12b. The silicide region 12a is provided between the metallic region 12b and the silicon carbide layer 10.
[0055] The silicide region 12a is in contact with the silicon carbide layer 10. The silicide region 12a is in contact with the source region 28. The silicide region 12a is in contact with the body contact region 27.
[0056] The source electrode 12 contains a metal. The silicide region 12a is, for example, nickel silicide or titanium silicide. The metal region 12b is, for example, a layered structure of titanium (Ti) and aluminum (Al).
[0057] The source electrode 12 includes a first contact portion 12x. The first contact portion 12x is provided between the first gate electrode 18 and the second gate electrode 19. The first contact portion 12x is provided, for example, in a trench formed in the silicon carbide layer 10. As shown in Figure 3, the first contact portion 12x extends, for example, in a third direction.
[0058] As shown in Figure 4, the first contact portion 12x has a first contact surface CP1 in contact with the silicon carbide layer 10, a second contact surface CP2 in contact with the silicon carbide layer 10, a third contact surface CP3 in contact with the silicon carbide layer 10, and a fourth contact surface CP4 in contact with the silicon carbide layer 10. The first contact surface CP1, the second contact surface CP2, the third contact surface CP3, and the fourth contact surface CP4 are part of the first contact portion 12x. The silicide region 12a of the first contact portion 12x has the first contact surface CP1, the second contact surface CP2, the third contact surface CP3, and the fourth contact surface CP4.
[0059] The first contact surface CP1 intersects with the first surface P1. The angle between the first contact surface CP1 and the first surface P1 is, for example, between 45 degrees and 90 degrees.
[0060] The first contact surface CP1 is in contact with the source region 28. The first contact surface CP1 is opposite the channel region 26x. In the second direction, the channel region 26x is provided between the JFET region 24x and the first contact surface CP1.
[0061] The second contact surface CP2 intersects with the first contact surface CP1. The second contact surface CP2 is continuous with the first contact surface CP1. The angle between the second contact surface CP2 and the first surface P1 is, for example, between 0 degrees and 30 degrees.
[0062] The second contact surface CP2 is in contact with the source region 28. The second contact surface CP2 is opposite the second surface P2. The second contact surface CP2 is opposite the body contact region 27. The source region 28 is provided between the second contact surface CP2 and the body contact region 27.
[0063] The third contact surface CP3 intersects with the second contact surface CP2. The third contact surface CP3 is continuous with the second contact surface CP2. The angle between the third contact surface CP3 and the second contact surface CP2 is, for example, between 45 degrees and 90 degrees. The angle between the third contact surface CP3 and the first surface P1 is, for example, between 45 degrees and 90 degrees.
[0064] The third contact surface CP3 is in contact with the source region 28 and the body contact region 27. The source region 28 is provided between the third contact surface CP3 and the body region 26. The body contact region 27 is provided between the third contact surface CP3 and the body region 26.
[0065] The fourth contact surface CP4 intersects with the third contact surface CP3. The fourth contact surface CP4 is continuous with the third contact surface CP3. The angle between the fourth contact surface CP4 and the first surface P1 is, for example, between 0 degrees and 30 degrees.
[0066] The fourth contact surface CP4 is in contact with the body contact region 27. The fourth contact surface CP4 is opposite the second surface P2. The body contact region 27 is provided between the fourth contact surface CP4 and the body region 26.
[0067] The distance in the first direction from the first surface P1 to the second contact surface CP2 (d1 in Figure 4) is, for example, one-third to three-quarters of the depth in the first direction of the source region 28 relative to the first surface P1 (d2 in Figure 4).
[0068] The distance in the first direction from the first surface P1 to the second contact surface CP2 (d1 in Figure 4) is, for example, 50 nm to 150 nm.
[0069] The length of the portion of the third contact surface CP3 that contacts the source region 28 in the first direction (d3 in Figure 4) is, for example, longer than the length of the portion of the third contact surface CP3 that contacts the body contact region 27 in the first direction (d4 in Figure 4).
[0070] The length of the second contact surface CP2 in the second direction (d5 in Figure 4) is, for example, longer than the distance from the first surface P1 to the second contact surface CP2 in the first direction (d1 in Figure 4).
[0071] The drain electrode 14 is provided on the side of the second surface P2 of the silicon carbide layer 10. The drain electrode 14 is provided on the back surface of the silicon carbide layer 10. The drain electrode 14 is in contact with the drain region 22.
[0072] The drain electrode 14 is, for example, a metal or a metal-semiconductor compound. The drain electrode 14 includes, for example, at least one material selected from the group consisting of nickel silicide, titanium (Ti), nickel (Ni), silver (Ag), and gold (Au).
[0073] Next, the operation and effects of the semiconductor device according to the first embodiment will be described.
[0074] To improve the performance of silicon carbide MOSFETs, it is expected that the on-resistance will be reduced. To reduce the on-resistance of a MOSFET, it is thought that the parasitic resistance of the MOSFET will be reduced. Parasitic resistance of a MOSFET is, for example, the electrical resistance of the source region and the contact resistance between the source electrode and the source region.
[0075] Figure 5 is an enlarged schematic cross-sectional view of the semiconductor device of the first comparative example. Figure 5 corresponds to Figure 4 of the first embodiment.
[0076] The semiconductor device of the first comparative example is a MOSFET 901. The MOSFET 901 differs from the MOSFET 100 of the first embodiment in that the first contact portion 12x does not have a second contact surface CP2.
[0077] The first contact portion 12x is in contact with both the source region 28 and the body contact region 27. Of the contact resistance between the first contact portion 12x and the source region 28 and the contact resistance between the first contact portion 12x and the body contact region 27, the parasitic resistance of the MOSFET 901 is the former, the contact resistance between the first contact portion 12x and the source region 28. Therefore, in order to reduce the parasitic resistance of the MOSFET 901, it is preferable to increase the contact area between the first contact portion 12x and the source region 28.
[0078] In MOSFET901, in the cross-section shown in Figure 5, only the first contact surface C1 and a portion of the third contact surface C3 contribute to the contact area between the first contact portion 12x and the source region 28. In this case, the contact resistance between the first contact portion 12x and the source region 28 is large, and there is a risk that the parasitic resistance of MOSFET901 will not decrease sufficiently.
[0079] Figure 6 is an enlarged schematic cross-sectional view of a semiconductor device of the second comparative example. Figure 6 corresponds to Figure 4 of the first embodiment.
[0080] The semiconductor device of the second comparative example is a MOSFET 902. The MOSFET 902 differs from the MOSFET 100 of the first embodiment in that the first contact portion 12x does not have a first contact surface CP1.
[0081] As the distance between the first contact portion 12x and the source region 28 located between it and the channel region 26x increases, the electrical resistance of the source region 28 increases, which in turn increases the parasitic resistance of the MOSFET 902.
[0082] In MOSFET902, carriers flow through the path indicated by the dotted arrow in Figure 6. If this path becomes long, the effective electrical resistance of the source region 28 increases, and there is a risk that the parasitic resistance of MOSFET902 may not decrease sufficiently.
[0083] The first contact portion 12x of the MOSFET 100 in the first embodiment has a first contact surface CP1 and a second contact surface CP2. By having the second contact surface CP2, the MOSFET 100 in the first embodiment can increase the contact area between the first contact portion 12x and the source region 28 compared to the MOSFET 901 of the first comparative example. Therefore, the parasitic resistance of the MOSFET 100 can be reduced.
[0084] Furthermore, the MOSFET 100 of the first embodiment has a first contact surface CP1, which allows for a smaller distance of the source region 28 between the first contact portion 12x and the channel region 26x compared to the MOSFET 902 of the second comparative example. Therefore, the effective electrical resistance of the source region 28 of the MOSFET 100 can be reduced. Thus, the parasitic resistance of the MOSFET 100 can be reduced.
[0085] As described above, according to the MOSFET 100 of the first embodiment, it is possible to reduce the on-resistance by reducing the parasitic resistance.
[0086] The distance in the first direction from the first surface P1 to the second contact surface CP2 (d1 in Figure 4) is preferably one-third or more of the depth in the first direction of the source region 28 with respect to the first surface P1 (d2 in Figure 4), and more preferably one-half or more. Exceeding the above lower limit increases the portion of the first contact portion 12x where the distance to the channel region 26x is short. Therefore, the effective electrical resistance of the source region 28 of the MOSFET 100 can be further reduced. Thus, the parasitic resistance of the MOSFET 100 can be further reduced.
[0087] The distance in the first direction from the first surface P1 to the second contact surface CP2 (d1 in Figure 4) is preferably 50 nm or more, more preferably 80 nm or more, and even more preferably 100 nm or more. Exceeding the above lower limit increases the portion of the first contact portion 12x where the distance to the channel region 26x is short. Therefore, the effective electrical resistance of the source region 28 of the MOSFET 100 can be further reduced. Thus, the parasitic resistance of the MOSFET 100 can be further reduced.
[0088] Preferably, the length of the portion of the third contact surface CP3 that contacts the source region 28 in the first direction (d3 in Figure 4) is longer than the length of the portion of the third contact surface CP3 that contacts the body contact region 27 in the first direction (d4 in Figure 4). By increasing the length d3 of the portion of the third contact surface CP3 that contacts the source region 28, the contact area between the first contact portion 12x and the source region 28 becomes even larger. Therefore, the contact resistance between the first contact portion 12x and the source region 28 is further reduced. Thus, the parasitic resistance of the MOSFET 100 is further reduced.
[0089] The length of the second contact surface CP2 in the second direction (d5 in Figure 4) is preferably longer than the distance from the first surface P1 to the second contact surface CP2 in the first direction (d1 in Figure 4). An increase in the length d5 of the second contact surface CP2 further increases the contact area between the first contact portion 12x and the source region 28, thereby further reducing the contact resistance between the first contact portion 12x and the source region 28. Consequently, the parasitic resistance of the MOSFET 100 is further reduced.
[0090] As described above, according to the first embodiment, it is possible to provide a semiconductor device that can reduce on-resistance by reducing parasitic resistance.
[0091] (Second embodiment) The semiconductor device of the second embodiment further includes a second portion located in a third direction of the first portion, with the first electrode provided between a first gate electrode and a second gate electrode. A fourth silicon carbide region is provided between the first portion and the second portion. The first portion further has a fifth contact surface that is in contact with the silicon carbide layer and intersects with the fourth contact surface, and the second portion has a sixth contact surface that is in contact with the silicon carbide layer and a seventh contact surface that is in contact with the silicon carbide layer and intersects with the sixth contact surface. The semiconductor device of the second embodiment differs from the semiconductor device of the first embodiment in that the fifth contact surface is in contact with the fourth silicon carbide region and the third silicon carbide region, the sixth contact surface is in contact with the fourth silicon carbide region and the third silicon carbide region and faces the fifth contact surface, and the seventh contact surface is in contact with the third silicon carbide region and faces the second surface. In the following, some descriptions may be omitted if they overlap with those of the first embodiment.
[0092] Figure 7 is a schematic cross-sectional view of a semiconductor device according to the second embodiment. Figure 8 is a schematic top view of the second embodiment. Figure 8 shows the gate electrode pattern superimposed with the silicon carbide region on the silicon carbide layer surface and the source electrode pattern. Figures 9 and 10 are schematic cross-sectional views of a semiconductor device according to the second embodiment.
[0093] Figure 7 is the CC' section of Figure 8. Figure 9 is the DD' section of Figure 8. Figure 10 is the EE' section of Figure 8.
[0094] The semiconductor device of the second embodiment is a planar gate type vertical MOSFET 200 using silicon carbide. The MOSFET 200 of the second embodiment is a DIMOSFET in which the body region and source region are formed by ion implantation, for example.
[0095] The MOSFET 200 comprises a silicon carbide layer 10, a source electrode 12, a drain electrode 14, a first gate insulating layer 16, a second gate insulating layer 17, a first gate electrode 18, a second gate electrode 19, and an interlayer insulating layer 20. The source electrode 12 is an example of a first electrode. The drain electrode 14 is an example of a second electrode.
[0096] The source electrode includes a silicide region 12a and a metallic region 12b.
[0097] The source electrode includes a first contact portion 12x. The first contact portion 12x is an example of a first portion. The first contact portion 12x includes a first contact surface CP1, a second contact surface CP2, a third contact surface CP3, a fourth contact surface CP4, and a fifth contact surface CP5.
[0098] The source electrode includes a second contact portion 12y. The second contact portion 12y is an example of the second portion. The second contact portion 12y includes a sixth contact surface CP6 and a seventh contact surface CP7.
[0099] The source electrode includes a third contact portion 12z. The third contact portion 12z is an example of a third portion. The third contact portion 12z includes an eighth contact surface CP8.
[0100] Within the silicon carbide layer 10, n + Shape of drain region 22, n - Shape drift region 24, p-shaped body region 26, p + Body contact area 27, n + A shaped source region 28 is provided. The drift region 24 is an example of a first silicon carbide region. The body region 26 is an example of a second silicon carbide region. The body contact region 27 is an example of a third silicon carbide region. The source region 28 is an example of a fourth silicon carbide region.
[0101] The drift region 24 includes the JFET region 24x. The body region 26 includes the channel region 26x. The JFET region 24x is an example of a first region. The channel region 26x is an example of a second region.
[0102] The source electrode 12 includes a first contact portion 12x, a second contact portion 12y, and a third contact portion 12z. The first contact portion 12x, the second contact portion 12y, and the third contact portion 12z are provided between the first gate electrode 18 and the second gate electrode 19.
[0103] As shown in Figure 10, the second contact portion 12y is located in a third direction relative to the first contact portion 12x. The first contact portion 12x and the second contact portion 12y are respectively provided in two trenches formed in the silicon carbide layer 10, spaced apart in a third direction. A source region 28 and a body contact region 27 are provided between the first contact portion 12x and the second contact portion 12y.
[0104] As shown in Figure 10, the third contact portion 12z is located between the first contact portion 12x and the second contact portion 12y.
[0105] The first contact portion 12x has a first contact surface CP1 in contact with the silicon carbide layer 10, a second contact surface CP2 in contact with the silicon carbide layer 10, a third contact surface CP3 in contact with the silicon carbide layer 10, a fourth contact surface CP4 in contact with the silicon carbide layer 10, and a fifth contact surface CP5 in contact with the silicon carbide layer 10. The first contact surface CP1, the second contact surface CP2, the third contact surface CP3, the fourth contact surface CP4, and the fifth contact surface CP5 are part of the first contact portion 12x. The silicide region 12a of the first contact portion 12x has the first contact surface CP1, the second contact surface CP2, the third contact surface CP3, the fourth contact surface CP4, and the fifth contact surface CP5.
[0106] The second contact portion 12y has a sixth contact surface CP6 that is in contact with the silicon carbide layer 10, and a seventh contact surface CP7 that is in contact with the silicon carbide layer 10. The silicide region 12a of the second contact portion 12y has the seventh contact surface CP7.
[0107] The third contact portion 12z has an eighth contact surface CP8 that is in contact with the silicon carbide layer 10. The silicide region 12a of the third contact portion 12z has the eighth contact surface CP8.
[0108] The fifth contact surface CP5 intersects with the fourth contact surface CP4. The angle between the fifth contact surface CP5 and the fourth contact surface CP4 is, for example, between 45 degrees and 90 degrees. The fifth contact surface CP5 is in contact with the source region 28 and the body contact region 27.
[0109] The sixth contact surface CP6 is in contact with the source region 28 and the body contact region 27. The sixth contact surface CP6 faces the fifth contact surface CP5 in the third direction. The source region 28 and the body contact region 27 are provided between the fifth contact surface CP5 and the sixth contact surface CP6.
[0110] The seventh contact surface CP7 intersects with the sixth contact surface CP6. The angle between the seventh contact surface CP7 and the sixth contact surface CP6 is, for example, between 45 degrees and 90 degrees. The seventh contact surface CP7 is continuous with the sixth contact surface CP6.
[0111] The seventh contact surface CP7 is in contact with the body contact area 27. The seventh contact surface CP7 is opposite the second surface P2. The body contact area 27 is provided between the seventh contact surface CP7 and the body area 26.
[0112] The eighth contact surface CP8 is in contact with the source region 28. The eighth contact surface CP8 is opposite the second surface P2. The eighth contact surface CP8 intersects with the fifth contact surface CP5 and the sixth contact surface CP6. The source region 28 is provided between the eighth contact surface CP8 and the body contact region 27.
[0113] As shown in Figure 10, the body contact region 27 in contact with the first contact portion 12x and the body contact region 27 in contact with the second contact portion 12y are continuous in the third direction.
[0114] According to the MOSFET 200 of the second embodiment, the source electrode 12 is provided with a first contact portion 12x, a second contact portion 12y, and a third contact portion 12z, which allows the contact area between the source electrode 12 and the source region 28 to be further increased compared to the MOSFET 100 of the first embodiment. Therefore, the parasitic resistance of the MOSFET 200 can be reduced.
[0115] As described above, according to the second embodiment, it is possible to provide a semiconductor device that can reduce on-resistance by reducing parasitic resistance.
[0116] In the first and second embodiments, the case of 4H-SiC as the crystal structure of SiC was described as an example, but the present invention can also be applied to devices using SiC with other crystal structures such as 6H-SiC and 3C-SiC. Furthermore, it is possible to apply a plane other than the (0001) plane to the surface of the silicon carbide layer 10.
[0117] In the first and second embodiments, the case where the first conductivity type is n-type and the second conductivity type is p-type was described as an example, but it is also possible to have the first conductivity type be p-type and the second conductivity type be n-type.
[0118] In the first and second embodiments, aluminum (Al) was exemplified as a p-type impurity, but boron (B) can also be used. Similarly, nitrogen (N) and phosphorus (P) were exemplified as n-type impurities, but arsenic (As), antimony (Sb), etc., can also be applied.
[0119] Furthermore, although the first and second embodiments described a MOSFET in which the gate electrode extends in one direction, the gate electrode may also be a MOSFET having a lattice shape, for example.
[0120] In the first and second embodiments, the semiconductor device was described as a MOSFET, but the semiconductor device may also be an Insulated Gate Bipolar Transistor (IGBT).
[0121] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. For example, components of one embodiment may be replaced or modified with components of another embodiment. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents. [Explanation of symbols]
[0122] 10. Silicon carbide layer 12 Source electrode (first electrode) 12x First contact portion (first portion) 12y Second contact area (second part) 12z Third contact portion (third part) 14. Drain electrode (second electrode) 16. First gate insulating layer 17. Second gate insulating layer 18 First gate electrode 19. Second gate electrode 24. Drift region (first silicon carbide region) 24x JFET area (first area) 26 Body region (second silicon carbide region) 26x channel region (second region) 27 Body contact region (third silicon carbide region) 28. Source region (fourth silicon carbide region) 100 MOSFETs (Semiconductor Devices) 200 MOSFETs (Semiconductor Devices) CP1 First contact surface CP2 Second contact surface CP3 Third contact surface CP4 Fourth contact surface CP5 Fifth contact surface CP6 Sixth contact surface CP7 Seventh contact surface CP8 Eighth contact surface P1 First side P2 Second side
Claims
1. A silicon carbide layer having a first surface and a second surface facing the first surface, A first gate electrode provided on the side of the first surface of the silicon carbide layer, A second gate electrode provided on the side of the first surface of the silicon carbide layer, A first region is provided within the silicon carbide layer and is in contact with the first surface, the first region being a first silicon carbide region of a first conductivity type facing the first gate electrode, Provided within the silicon carbide layer, and located between the first silicon carbide region and the first surface, and having a second region in contact with the first surface, the second region having a second silicon carbide region of a second conductivity type facing the first gate electrode, A third silicon carbide region of a second conductivity type is provided within the silicon carbide layer, between the second silicon carbide region and the first surface, and having a second conductivity type impurity concentration higher than that of the second conductivity type impurity concentration in the second silicon carbide region. A fourth silicon carbide region of first conductivity type is provided within the silicon carbide layer and is located between the third silicon carbide region and the first surface, A first gate insulating layer is provided between the first gate electrode and the second region, A first electrode provided on the side of the first surface of the silicon carbide layer, Including a first portion provided between the first gate electrode and the second gate electrode, The first portion has a first contact surface that is in contact with the silicon carbide layer and intersects with the first surface, a second contact surface that is in contact with the silicon carbide layer and intersects with the first contact surface, a third contact surface that is in contact with the silicon carbide layer and intersects with the second contact surface, and a fourth contact surface that is in contact with the silicon carbide layer and intersects with the third contact surface. The first contact surface is in contact with the fourth silicon carbide region and faces the second region. The second contact surface is in contact with the fourth silicon carbide region and faces the second surface. The third contact surface is in contact with the fourth silicon carbide region and the third silicon carbide region. The fourth contact surface is in contact with the third silicon carbide region and faces the second surface, and is the first electrode. A second electrode provided on the side of the second surface of the silicon carbide layer, Equipped with, A semiconductor device in which the distance from the first surface to the second contact surface in the first direction toward the second surface is one-third or more of the depth of the fourth silicon carbide region in the first direction.
2. A silicon carbide layer having a first surface and a second surface facing the first surface, A first gate electrode provided on the side of the first surface of the silicon carbide layer, A second gate electrode provided on the side of the first surface of the silicon carbide layer, A first region is provided within the silicon carbide layer and is in contact with the first surface, the first region being a first silicon carbide region of a first conductivity type facing the first gate electrode, Provided within the silicon carbide layer, and located between the first silicon carbide region and the first surface, and having a second region in contact with the first surface, the second region having a second silicon carbide region of a second conductivity type facing the first gate electrode, A third silicon carbide region of a second conductivity type is provided within the silicon carbide layer, between the second silicon carbide region and the first surface, and having a second conductivity type impurity concentration higher than that of the second conductivity type impurity concentration in the second silicon carbide region. A fourth silicon carbide region of first conductivity type is provided within the silicon carbide layer and is located between the third silicon carbide region and the first surface, A first gate insulating layer is provided between the first gate electrode and the second region, A first electrode provided on the side of the first surface of the silicon carbide layer, Including a first portion provided between the first gate electrode and the second gate electrode, The first portion has a first contact surface that is in contact with the silicon carbide layer and intersects with the first surface, a second contact surface that is in contact with the silicon carbide layer and intersects with the first contact surface, a third contact surface that is in contact with the silicon carbide layer and intersects with the second contact surface, and a fourth contact surface that is in contact with the silicon carbide layer and intersects with the third contact surface. The first contact surface is in contact with the fourth silicon carbide region and faces the second region. The second contact surface is in contact with the fourth silicon carbide region and faces the second surface. The third contact surface is in contact with the fourth silicon carbide region and the third silicon carbide region. The fourth contact surface is in contact with the third silicon carbide region and faces the second surface, and is the first electrode. A second electrode provided on the side of the second surface of the silicon carbide layer, Equipped with, A semiconductor device in which the distance from the first surface to the second contact surface in the first direction toward the second surface is 50 nm or more.
3. A silicon carbide layer having a first surface and a second surface facing the first surface, A first gate electrode provided on the side of the first surface of the silicon carbide layer, A second gate electrode provided on the side of the first surface of the silicon carbide layer, A first region is provided within the silicon carbide layer and is in contact with the first surface, the first region being a first silicon carbide region of a first conductivity type facing the first gate electrode, Provided within the silicon carbide layer, and located between the first silicon carbide region and the first surface, and having a second region in contact with the first surface, the second region having a second silicon carbide region of a second conductivity type facing the first gate electrode, A third silicon carbide region of a second conductivity type is provided within the silicon carbide layer, between the second silicon carbide region and the first surface, and having a second conductivity type impurity concentration higher than that of the second conductivity type impurity concentration in the second silicon carbide region. A fourth silicon carbide region of first conductivity type is provided within the silicon carbide layer and is located between the third silicon carbide region and the first surface, A first gate insulating layer is provided between the first gate electrode and the second region, A first electrode provided on the side of the first surface of the silicon carbide layer, Including a first portion provided between the first gate electrode and the second gate electrode, The first portion has a first contact surface that is in contact with the silicon carbide layer and intersects with the first surface, a second contact surface that is in contact with the silicon carbide layer and intersects with the first contact surface, a third contact surface that is in contact with the silicon carbide layer and intersects with the second contact surface, and a fourth contact surface that is in contact with the silicon carbide layer and intersects with the third contact surface. The first contact surface is in contact with the fourth silicon carbide region and faces the second region. The second contact surface is in contact with the fourth silicon carbide region and faces the second surface. The third contact surface is in contact with the fourth silicon carbide region and the third silicon carbide region. The fourth contact surface is in contact with the third silicon carbide region and faces the second surface, and is the first electrode. A second electrode provided on the side of the second surface of the silicon carbide layer, Equipped with, The length of the portion where the third contact surface and the fourth silicon carbide region are in contact, in the first direction from the first surface toward the second surface, is A semiconductor device having a portion of the contact between the third contact surface and the third silicon carbide region that is longer than the length in the first direction.
4. The semiconductor device according to claim 1, wherein the first portion includes a silicide region having a first contact surface, a second contact surface, a third contact surface, and a fourth contact surface.
5. The semiconductor device according to claim 4, wherein the silicide region includes nickel silicide.
6. The semiconductor device according to claim 1, wherein the distance in the first direction from the first surface to the fourth contact surface is 150 nm or more.
7. The first gate electrode and the second gate electrode extend in a third direction parallel to the first plane, The first electrode is provided between the first gate electrode and the second gate electrode, and further includes a second portion of the first portion located in the third direction, A fourth silicon carbide region is provided between the first portion and the second portion. The first portion further has a fifth contact surface that is in contact with the silicon carbide layer and intersects with the fourth contact surface, The second portion has a sixth contact surface in contact with the silicon carbide layer and a seventh contact surface in contact with the silicon carbide layer and intersecting with the sixth contact surface. The fifth contact surface is in contact with the fourth silicon carbide region and the third silicon carbide region. The sixth contact surface is in contact with the fourth silicon carbide region and the third silicon carbide region, and faces the fifth contact surface. The semiconductor device according to claim 1, wherein the seventh contact surface is in contact with the third silicon carbide region and faces the second surface.
8. The semiconductor device according to claim 7, wherein the third silicon carbide region in contact with the first portion and the third silicon carbide region in contact with the second portion are continuous in the third direction.
9. The first electrode further includes a third portion provided between the first gate electrode and the second gate electrode, and located between the first portion and the second portion. The third portion has an eighth contact surface that is in contact with the silicon carbide layer, The semiconductor device according to claim 7, wherein the eighth contact surface is in contact with the fourth silicon carbide region and faces the second surface.