Semiconductor equipment

Abstract

To reduce the stress acting on a bonding wire at a joint with a pad.SOLUTION: A semiconductor device 20 with a double-sided heat dissipation structure includes a semiconductor element 40 and substrates 50 and 60. The substrate 50 connected to a drain electrode 40D of the semiconductor element 40 includes a roughened portion 527 on the surface of a surface metal body 52. The substrate 60 connected to the source electrode 40S of the semiconductor element 40 includes a roughened portion 627 and a non-roughened portion 628 on the surface of the surface metal body 62. The non-roughened portion 628 is provided at least in a portion overlapping with a pad 40P in plan view. An encapsulant 30 adheres to the roughened portions 527 and 627 and does not adhere to the non-roughened portion 628.SELECTED DRAWING: Figure 123

Description

Technical Field

[0001] The disclosure in this specification relates to a semiconductor device.

Background Art

[0002] Patent Document 1 discloses a semiconductor device with a double-sided heat dissipation structure. The description of the prior art document is incorporated herein by reference as an explanation of the technical elements in this specification.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In Patent Document 1, a pair of DCB substrates are arranged so as to sandwich a semiconductor chip. DCB is an abbreviation for Direct Copper Bonding. Among the DCB substrates, the surface of the copper layer is roughened. And a sealing body is adhered to the roughened portion. Thereby, peeling of the sealing body can be suppressed.

[0005] However, since the sealing body is adhered to the copper layer, the sealing body is pulled by the deformed copper layer, and there is a problem that the stress acting on the bonding portion between the semiconductor chip pad and the bonding wire increases. The increase in stress causes, for example, cracks or breakage. From the above viewpoints, or from other viewpoints not mentioned, further improvement of the semiconductor device is required.

[0006] One of the disclosed objects is Further improvements have been made. to provide a semiconductor device.

Means for Solving the Problems

[0007] The semiconductor device disclosed herein is It includes an upper arm element (40H) that constitutes the upper arm of the upper and lower arm circuit, and a lower arm element (40L) that constitutes the lower arm of the upper and lower arm circuit. A first main electrode (40D) is provided on one side, and a second main electrode (40S) is provided on the back surface opposite to the one side in the thickness direction of the plate. ,of A semiconductor element (40) having, In a plan view in the thickness direction of the plate, the semiconductor element is enclosed within it, and the first main electrode is positioned on the plate thickness side. It comprises a first insulating substrate (51) and a first surface metal body (52) disposed on the first insulating substrate and electrically connected to the first main electrode. First wiring member (50) and In a plan view, the semiconductor element is enclosed within it, and the second main electrode is positioned on the side of the plate thickness. The device comprises a second insulating substrate (61) and a second surface metal body (62) disposed on the second insulating substrate and electrically connected to the second main electrode. Second wiring member (60) and A conductive spacer (70) electrically connects the second main electrode and the second surface metal body, A joint (81) that electrically connects the second main electrode of the upper arm element and the first main electrode of the lower arm element. and, A semiconductor element, at least a portion of a first wiring member including the surface facing the semiconductor element, and at least one portion of a second wiring member including the surface facing the semiconductor element. department A sealing body (30) for sealing, The first surface metal body has a first power supply wiring (54) connected to the first main electrode of the upper arm element and a first relay wiring (55) connected to the first main electrode of the lower arm element and the joint portion. A gap filled with a sealant is formed between the first power supply wiring and the first relay wiring. The second surface metal body has a second power supply wiring (64) connected to the second main electrode of the lower arm element via a conductive spacer, and a second relay wiring (65) connected to the second main electrode of the upper arm element via a joint and a conductive spacer. A gap filled with a sealant is formed between the second power supply wiring and the second relay wiring. The distance between the joint and the conductive spacer connected to the second main electrode of the lower arm element is narrower than the distance between the joint and the conductive spacer connected to the second main electrode of the upper arm element. .

[0009] The various embodiments disclosed in this specification employ different technical means to achieve their respective objectives. The claims and the reference numerals in parentheses in this section are illustrative in their correspondence with the embodiments described later and are not intended to limit the technical scope. The objectives, features, and effects disclosed in this specification will become clearer by referring to the subsequent detailed description and the accompanying drawings. [Brief explanation of the drawing]

[0010] [Figure 1] This diagram shows the circuit configuration of a power conversion device to which the semiconductor device according to the first embodiment is applied. [Figure 2] This is a perspective view showing a semiconductor device. [Figure 3]It is a perspective view showing a semiconductor device. [Figure 4] It is a plan view showing a semiconductor device. [Figure 5] It is a cross-sectional view taken along the line V-V of FIG. 4. [Figure 6] It is a cross-sectional view taken along the line VI-VI of FIG. 4. [Figure 7] It is a cross-sectional view taken along the line VII-VII of FIG. 4. [Figure 8] It is a cross-sectional view taken along the line VIII-VIII of FIG. 4. [Figure 9] It is an enlarged view of the region IX shown in FIG. 8. [Figure 10] It is an exploded perspective view for explaining a semiconductor device. [Figure 11] It is a plan view showing a state where semiconductor elements are mounted on a substrate on the drain electrode side. [Figure 12] It is a plan view showing a circuit pattern of a substrate on the drain electrode side. [Figure 13] It is a plan view showing a circuit pattern of a substrate on the source electrode side. [[ID=3,2]] [Figure 14] It is a view showing the arrangement of a circuit pattern, semiconductor elements, and terminals on the drain electrode side. [Figure 15] It is a view showing the arrangement of a circuit pattern, semiconductor elements, and terminals on the source electrode side. [Figure 16] It is a plan view showing a current loop of a reference example. [Figure 17] It is a plan view showing a current loop. [Figure 18] It is a side view showing a current loop. [Figure 19] It is a view showing current density for a reference example. [Figure 20] It is a view showing current density for this embodiment. [Figure 21] It is a plan view showing a modified example. [[ID=5,5]] [Figure 22] It is a plan view showing a modified example. [Figure 23] In a modified example, it is a plan view showing a circuit pattern of a substrate on the drain electrode side. <00,00114> [Figure 24] In the modified example, this is a plan view showing the circuit pattern of the substrate on the source electrode side. [Figure 25] This is a cross-sectional view showing a semiconductor device according to the second embodiment. [Figure 26] This is a diagram illustrating the effect of inductance Ls. [Figure 27] This is a diagram illustrating the effect of inductance Ls. [Figure 28] This is a plan view showing the circuit pattern on the source electrode side of the substrate. [Figure 29] This is a diagram showing the current path. [Figure 30] This is a cross-sectional view showing the arm connection point. [Figure 31] This is a plan view showing a modified example of the substrate on the source electrode side. [Figure 32] This is a plan view showing the state in which semiconductor elements are mounted on the substrate on the drain electrode side. [Figure 33] This is a diagram showing the current path. [Figure 34] This is a plan view showing a modified example of the substrate on the drain electrode side. [Figure 35] This is a diagram showing the current path. [Figure 36] This is a cross-sectional view showing a modified example of the arm connection section. [Figure 37] This is a cross-sectional view showing a modified example of the arm connection section. [Figure 38] In the modified example, this is a plan view showing the circuit pattern of the substrate on the source electrode side. [Figure 39] This is a cross-sectional view showing warping at high temperatures. [Figure 40] This is a cross-sectional view showing a semiconductor device according to the third embodiment. [Figure 41] This is a cross-sectional view showing a semiconductor device at room temperature. [Figure 42] This is a cross-sectional view showing a semiconductor device at high temperatures. [Figure 43] This figure shows the relationship between the ratio of thicknesses T1 and T2 and the amount of warping. [Figure 44] This is a cross-sectional view showing a modified example. [Figure 45] This is a cross-sectional view showing a modified example. [Figure 46] This is an enlarged plan view of the area around the signal terminals in the semiconductor device according to the fourth embodiment. [Figure 47] This is a cross-sectional view along the line XLVII-XLVII in Figure 46. [Figure 48] This is a diagram illustrating wire bonding. [Figure 49] This is a cross-sectional view showing a modified example. [Figure 50] This is a cross-sectional view showing a modified example. [Figure 51] This is a cross-sectional view showing a modified example. [Figure 52] This is a cross-sectional view showing a modified example. [Figure 53] This is a plan view illustrating a modified example. [Figure 54] This is a cross-sectional view showing a relay board. [Figure 55] This is a cross-sectional view along the LV-LV line in Figure 53. [Figure 56] This is a cross-sectional view showing a modified example. [Figure 57] This is a cross-sectional view showing a semiconductor device according to the fifth embodiment. [Figure 58] Figure 57 is a plan view taken from the LVIII direction. [Figure 59] Figure 57 shows an enlarged view of the LVIX region. [Figure 60] This figure is a version of Figure 59 with the connecting material omitted. [Figure 61] This is a plan view illustrating a modified example. [Figure 62] Figure 61 is a plan view taken from the LXII direction. [Figure 63] This is a plan view illustrating a modified example. [Figure 64] This is a cross-sectional view showing a modified example. [Figure 65] Figure 64 shows an enlarged view of the region LXV. [Figure 66] This is a cross-sectional view showing a modified example. [Figure 67] Figure 66 shows an enlarged view of region LXVII. [Figure 68] This is a cross-sectional view showing a modified example. [Figure 69] This is a cross-sectional view showing a semiconductor device according to the sixth embodiment. [Figure 70] This figure shows the relationship between the glass transition temperature and the coefficient of thermal expansion for sealing materials and insulating substrates. [Figure 71] This is a diagram illustrating the curvature of an example. [Figure 72] This figure shows warping at high temperatures. [Figure 73] This is a cross-sectional view showing a semiconductor device according to the seventh embodiment. [Figure 74] This is an enlarged view of region LXXIV in Figure 73. [Figure 75] This is a diagram showing the method for forming the roughened area. [Figure 76] This is a cross-sectional view showing a modified example. [Figure 77] This is a cross-sectional view showing a modified example. [Figure 78] This is a cross-sectional view showing a modified example. [Figure 79] This is a cross-sectional view showing a semiconductor device according to the eighth embodiment. [Figure 80] This is an enlarged view of region LXXX in Figure 79. [Figure 81] This diagram shows the relationship between spacing, thickness, and inductance. [Figure 82] This figure shows the simulation results when the spacing is less than the thickness. [Figure 83] This figure shows the simulation results when the spacing > thickness. [Figure 84] This is a cross-sectional view showing a semiconductor device according to the ninth embodiment. [Figure 85] This is a plan view showing the center of the substrate. [Figure 86] This is an enlarged view of region LXXXVI in Figure 84. [Figure 87] This is a diagram showing dimensions and angles. [Figure 88] This is a side view of the laminated structure. [Figure 89]This is a cross-sectional view showing a semiconductor device according to the 10th embodiment. [Figure 90] A planar view showing a semiconductor device. [Figure 91] This is an enlarged view of region XCI in Figure 89. [Figure 92] This is a cross-sectional view showing the arrangement of the sintered members. [Figure 93] This is a cross-sectional view showing the joining method. [Figure 94] This figure shows the relationship between the distance between the inner surface of the protective film and the sintered member and the strain amplitude of the underlying electrode. [Figure 95] This is a cross-sectional view showing the arrangement of solder, which is the bonding material. [Figure 96] This is a cross-sectional view showing a semiconductor device according to the 11th embodiment. [Figure 97] This is an enlarged view of region XCVII in Figure 96. [Figure 98] This is a plan view showing the arrangement of semiconductor elements, sintered components, and uneven oxide films. [Figure 99] This is an enlarged view of region XCIX in Figure 97. [Figure 100] This is a cross-sectional view showing a modified example. [Figure 101] This is a plan view showing the arrangement of semiconductor elements, sintered components, and uneven oxide films. [Figure 102] This is a cross-sectional view showing a modified example. [Figure 103] This is a plan view showing the arrangement of semiconductor elements, sintered components, and uneven oxide films. [Figure 104] This is a cross-sectional view showing a modified example. [Figure 105] This is a cross-sectional view showing a semiconductor device according to the 12th embodiment. [Figure 106] This is an enlarged view of the CVI region in Figure 105. [Figure 107] This figure shows the relationship between the Young's modulus and yield stress of the base electrode, sintered layer, and fragile layer. [Figure 108] This is a cross-sectional view showing a modified example. [Figure 109] This is a cross-sectional view showing a modified example. [Figure 110]This is a cross-sectional view showing a modified example. [Figure 111] This figure shows the circuit configuration of a power conversion device to which the semiconductor device according to the 13th embodiment is applied. [Figure 112] This is a perspective view showing a semiconductor device. [Figure 113] This is a plan view showing a semiconductor device. [Figure 114] This is a plan view showing the state in which semiconductor elements are mounted on the substrate on the drain electrode side. [Figure 115] This is a plan view showing the circuit pattern of the substrate on the drain electrode side. [Figure 116] This is a plan view showing the circuit pattern on the source electrode side of the substrate. [Figure 117] This is a cross-sectional view along the CXVII-CXVII line in Figure 113. [Figure 118] This is a cross-sectional view along the CXVIII-CXVIII line in Figure 113. [Figure 119] This is a cross-sectional view along the CXIX-CXIX line in Figure 113. [Figure 120] This is a cross-sectional view along the CXX-CXX line in Figure 113. [Figure 121] This is an enlarged view of region CXXI ​​in Figure 120. [Figure 122] This is a plan view showing a non-roughened portion provided in the circuit pattern of the source electrode side substrate in a semiconductor device according to the 14th embodiment. [Figure 123] This is a cross-sectional view showing a semiconductor device. [Figure 124] This is an enlarged view of region CXXIV in Figure 123. [Figure 125] This is a reference diagram corresponding to Figure 124. [Figure 126] This figure shows the relationship between the presence or absence of roughening directly above the pad and the strain amplitude at the wire joint. [Figure 127] This is a plan view illustrating a modified example. [Figure 128] This is a cross-sectional view showing a modified example. [Figure 129] This is a cross-sectional view showing a modified example. [Modes for carrying out the invention]

[0011] Several embodiments will be described below with reference to the drawings. In each embodiment, the same reference numerals are used for corresponding components, and redundant explanations may be omitted. If only a part of the configuration is described in each embodiment, the configuration of other embodiments described earlier can be applied to the other parts of that configuration. Furthermore, in addition to the combinations of configurations explicitly stated in the description of each embodiment, configurations from multiple embodiments can be partially combined even if not explicitly stated, as long as there are no particular problems with the combination.

[0012] The semiconductor device of this embodiment is applied, for example, to a power conversion device for a mobile body that uses a rotating electric machine as a drive source. Examples of mobile bodies include electric vehicles such as battery electric vehicles (BEVs), hybrid electric vehicles (HEVs), and plug-in hybrid electric vehicles (PHEVs), as well as aircraft such as electric vertical take-off and landing aircraft and drones, ships, construction machinery, and agricultural machinery. An example of its application to a vehicle will be described below.

[0013] (First Embodiment) First, the general configuration of the vehicle's drive system 1 will be explained based on Figure 1.

[0014] <Vehicle drive system> As shown in Figure 1, the vehicle's drive system 1 includes a DC power supply 2, a motor generator 3, and a power converter 4.

[0015] The DC power supply 2 is a DC voltage source composed of rechargeable secondary batteries. These secondary batteries are, for example, lithium-ion batteries or nickel-metal hydride batteries. The motor generator 3 is a three-phase AC rotating electric machine. The motor generator 3 functions as the vehicle's driving source, i.e., an electric motor. During regeneration, the motor generator 3 functions as a generator. The power converter 4 performs power conversion between the DC power supply 2 and the motor generator 3.

[0016] <Power converter> Next, the circuit configuration of the power converter 4 will be described based on Figure 1. The power converter 4 is equipped with a power conversion circuit. The power converter 4 in this embodiment is equipped with a smoothing capacitor 5 and an inverter 6 which is a power conversion circuit.

[0017] The smoothing capacitor 5 primarily smooths the DC voltage supplied from the DC power supply 2. The smoothing capacitor 5 is connected to the P line 7, which is the high-potential power line, and the N line 8, which is the low-potential power line. The P line 7 is connected to the positive terminal of the DC power supply 2, and the N line 8 is connected to the negative terminal of the DC power supply 2. The positive terminal of the smoothing capacitor 5 is connected to the P line 7 between the DC power supply 2 and the inverter 6. The negative terminal of the smoothing capacitor 5 is connected to the N line 8 between the DC power supply 2 and the inverter 6. The smoothing capacitor 5 is connected in parallel to the DC power supply 2.

[0018] The inverter 6 is a DC-AC conversion circuit. The inverter 6 converts a DC voltage to a three-phase AC voltage according to switching control by a control circuit (not shown) and outputs it to the motor generator 3. This drives the motor generator 3 to generate a predetermined torque. During regenerative braking of the vehicle, the inverter 6 converts the three-phase AC voltage generated by the motor generator 3 in response to the rotational force from the wheels to a DC voltage according to switching control by the control circuit and outputs it to the P line 7. In this way, the inverter 6 performs bidirectional power conversion between the DC power supply 2 and the motor generator 3.

[0019] The inverter 6 is configured with three phase upper and lower arm circuits 9. The upper and lower arm circuits 9 are sometimes referred to as legs. The upper and lower arm circuits 9 each have an upper arm 9H and a lower arm 9L. The upper arm 9H and lower arm 9L are connected in series between the P line 7 and the N line 8, with the upper arm 9H on the P line 7 side. The connection point between the upper arm 9H and the lower arm 9L is connected to the winding 3a of the corresponding phase in the motor generator 3 via the output line 10. The inverter 6 has six arms. Each arm is configured with a switching element. At least a portion of each of the P line 7, N line 8, and output line 10 is made of conductive material such as a busbar.

[0020] In this embodiment, an n-channel type MOSFET 11 is used as the switching element constituting each arm. The number of switching elements constituting each arm is not particularly limited; there may be one or multiple. MOSFET is an abbreviation for Metal Oxide Semiconductor Field Effect Transistor.

[0021] As an example, in this embodiment, each arm has two MOSFETs 11. The two MOSFETs 11 constituting one arm are connected in parallel. In the upper arm 9H, the drains of the two parallel-connected MOSFETs 11 are connected to the P line 7. In the lower arm 9L, the sources of the two parallel-connected MOSFETs 11 are connected to the N line 8. The sources of the two parallel-connected MOSFETs 11 in the upper arm 9H and the drains of the two parallel-connected MOSFETs 11 in the lower arm 9L are interconnected. The two parallel-connected MOSFETs 11 are turned on and off at the same timing by a common gate drive signal (drive voltage).

[0022] Each MOSFET 11 is connected in antiparallel to a freewheeling diode 12. The diode 12 may be a parasitic diode (body diode) of the MOSFET 11, or it may be a separate diode. The anode of the diode 12 is connected to the source of the corresponding MOSFET 11, and the cathode is connected to the drain. The upper and lower arm circuit 9 for one phase is provided by a single semiconductor device 20. Details of the semiconductor device 20 will be described later.

[0023] The power converter 4 may further include a converter as a power conversion circuit. The converter is a DC-DC converter circuit that converts a DC voltage to a DC voltage of a different value. The converter is placed between the DC power supply 2 and the smoothing capacitor 5. The converter is configured, for example, with a reactor and the above-described up-and-down arm circuit 9. With this configuration, step-up and step-down voltage conversion is possible. The power converter 4 may also include a filter capacitor to remove power supply noise from the DC power supply 2. The filter capacitor is placed between the DC power supply 2 and the converter.

[0024] The power converter 4 may include a drive circuit for the switching elements that make up the inverter 6, etc. The drive circuit supplies a drive voltage to the gate of the corresponding arm's MOSFET 11 based on a drive command from the control circuit. The drive circuit drives the corresponding MOSFET 11, i.e., turns it on or off, by applying the drive voltage. The drive circuit is sometimes referred to as a driver.

[0025] The power converter 4 may include a control circuit for the switching element. The control circuit generates a drive command to operate the MOSFET 11 and outputs it to the drive circuit. The control circuit generates the drive command based on, for example, a torque request input from a higher-level ECU (not shown) and signals detected by various sensors. ECU is an abbreviation for Electronic Control Unit.

[0026] Various sensors include, for example, current sensors, rotation angle sensors, and voltage sensors. The current sensor detects the phase current flowing through the windings 3a of each phase. The rotation angle sensor detects the rotation angle of the rotor of the motor generator 3. The voltage sensor detects the voltage across the smoothing capacitor 5. The control circuit outputs, for example, a PWM signal as a drive command. The control circuit is configured, for example, with a processor and memory. PWM is an abbreviation for Pulse Width Modulation.

[0027] <Semiconductor device> Next, the semiconductor device will be described based on Figures 2 to 13. Figure 2 is a perspective view of the semiconductor device 20. Figure 3 is a perspective view of the semiconductor device 20, similar to Figure 2. Figure 3 is a transparent view showing the internal structure. Figure 4 is a plan view of the semiconductor device 20. Figure 4 is a transparent view showing the internal structure. Figure 5 is a cross-sectional view along line VV in Figure 4. Figure 6 is a cross-sectional view along line VI-VI in Figure 4. Figure 7 is a cross-sectional view along line VII-VII in Figure 4. Figure 8 is a cross-sectional view along line VIII-VIII in Figure 4. Figure 9 is an enlarged view of region IX shown by the dashed line in Figure 8.

[0028] Figure 10 is an exploded perspective view illustrating the semiconductor device 20. For convenience, the lead frame 94 is shown in Figure 10. Figure 11 is a plan view showing the semiconductor element 40 mounted on the substrate 50. Figure 12 is a plan view showing the circuit pattern of the surface metal body 52 on the substrate 50. Figure 13 is a plan view showing the circuit pattern of the surface metal body 62 on the substrate 60.

[0029] In the following, the thickness direction of the semiconductor element (semiconductor substrate) is defined as the Z direction. The direction perpendicular to the Z direction, where the semiconductor elements constituting the upper arm 9H and the semiconductor elements constituting the lower arm 9L are aligned, is defined as the Y direction. The direction perpendicular to both the Z and Y directions is defined as the X direction. Unless otherwise specified, the shape viewed from the Z direction, in other words, the shape along the XY plane defined by the X and Y directions, is defined as the planar shape. The view from the Z direction is sometimes simply referred to as the planar view. Furthermore, the term "arrangement" is not limited to the mounting surface, but may also refer to any overlapping positional relationship in a planar view.

[0030] As shown in Figures 2 to 13, the semiconductor device 20 constitutes one of the upper and lower arm circuits 9 described above, that is, one phase of the upper and lower arm circuit 9. The semiconductor device 20 comprises a encapsulant 30, a semiconductor element 40, substrates 50 and 60, a conductive spacer 70, an arm connection part 80, and an external connection terminal 90.

[0031] The encapsulant 30 encapsulates some of the other elements that make up the semiconductor device 20. The remaining parts of the other elements are exposed outside the encapsulant 30. The encapsulant 30 is made of, for example, a resin. An example of a resin is an epoxy resin. The encapsulant 30 is molded from resin, for example, by a transfer molding method. Such an encapsulant 30 may be called a resin encapsulant, molded resin, or resin molded body. The encapsulant 30 may also be formed using, for example, a gel. The gel is filled (placed), for example, in opposing regions of a pair of substrates 50, 60.

[0032] As shown in Figures 2 to 4, the sealing body 30 has a roughly rectangular shape in plan. The sealing body 30 has an outer surface, which is one surface 30a and a back surface 30b that is opposite to the one surface 30a in the Z direction. The one surface 30a and the back surface 30b are, for example, flat surfaces. It also has a side surface that connects the one surface 30a and the back surface 30b. The side surface includes two side surfaces 30c and 30d from which the external connection terminal 90 protrudes. The side surface 30d is opposite to the side surface 30c in the X direction.

[0033] The semiconductor device 40 is formed by forming a switching element on a semiconductor substrate made of materials such as silicon (Si) or a wide-bandgap semiconductor with a wider bandgap than silicon. Examples of wide-bandgap semiconductors include silicon carbide (SiC), gallium nitride (GaN), gallium oxide (Ga2O3), and diamond. The semiconductor device 40 is sometimes referred to as a power device or semiconductor chip.

[0034] The semiconductor element 40 of this embodiment is formed by creating the above-described n-channel type MOSFET 11 on a semiconductor substrate made of SiC. The MOSFET 11 has a vertical structure such that the main current flows in the thickness direction of the semiconductor element 40 (semiconductor substrate), i.e., in the Z direction. The semiconductor element 40 has main electrodes for the switching element on both sides in its thickness direction, i.e., in the Z direction. Specifically, as main electrodes, it has a drain electrode 40D on one side and a source electrode 40S on the back side, which is the side opposite to the other side in the Z direction.

[0035] If diode 12 is a parasitic diode, the source electrode 40S also serves as the anode electrode, and the drain electrode 40D also serves as the cathode electrode. Diode 12 may be configured on a separate chip from MOSFET 11. The drain electrode 40D is the main electrode on the high-potential side (first main electrode), and the source electrode 40S is the main electrode on the low-potential side (second main electrode). Hereafter, the drain electrode 40D and source electrode 40S may be referred to as main electrodes 40D and 40S.

[0036] The semiconductor element 40 has a substantially rectangular shape in plan. As shown in Figure 11, the semiconductor element 40 has a pad 40P formed on its back surface at a different position from the source electrode 40S. The source electrode 40S and the pad 40P are exposed from a protective film (not shown) formed on the back surface of the semiconductor substrate. The drain electrode 40D is formed over almost the entire surface of one side. The source electrode 40S is formed on a portion of the back surface of the semiconductor element 40. In a plan view, the drain electrode 40D has a larger area than the source electrode 40S.

[0037] Pad 40P is a signal electrode. Pad 40P is electrically isolated from the source electrode 40S. Pad 40P is formed in the Y direction at the end opposite to the formation region of the source electrode 40S. Pad 40P includes a pad for the gate electrode.

[0038] The semiconductor device 20 comprises a plurality of semiconductor elements 40 having the above configuration. The configuration of each semiconductor element 40 is common to all others. The plurality of semiconductor elements 40 include semiconductor elements 40H that constitute the upper arm 9H and semiconductor elements 40L that constitute the lower arm 9L. Semiconductor elements 40H are sometimes referred to as upper arm elements, and semiconductor elements 40L are sometimes referred to as lower arm elements. Each of the semiconductor elements 40H and 40L is an arm element that constitutes one arm. The semiconductor device 20 of this embodiment comprises two semiconductor elements 40H and two semiconductor elements 40L. The two semiconductor elements 40H are aligned in the X direction. Similarly, the two semiconductor elements 40L are aligned in the X direction. The semiconductor elements 40H and 40L are aligned in the Y direction. The Y direction is a first direction perpendicular to the Z direction, which is the thickness direction of the semiconductor element 40. The X direction is a second direction perpendicular to the Z direction and the first direction (Y direction). The semiconductor device 20 has two rows of semiconductor elements 40H and 40L arranged along the Y direction.

[0039] Each semiconductor element 40 is positioned at approximately the same location in the Z direction. The drain electrode 40D of each semiconductor element 40 faces the substrate 50. The source electrode 40S of each semiconductor element 40 faces the substrate 60.

[0040] The substrates 50 and 60 are arranged in the Z direction so as to sandwich the multiple semiconductor elements 40. The substrates 50 and 60 are arranged so that at least a portion of them faces each other in the Z direction. In a plan view, the substrates 50 and 60 enclose all of the multiple semiconductor elements 40 (40H, 40L).

[0041] Substrate 50 is positioned on the drain electrode 40D side relative to the semiconductor element 40. Substrate 60 is positioned on the source electrode 40S side relative to the semiconductor element 40. Substrate 50 is electrically connected to the drain electrode 40D as described later and provides a wiring function. Similarly, substrate 60 is electrically connected to the source electrode 40S and provides a wiring function. For this reason, substrates 50 and 60 are sometimes referred to as wiring substrates. Substrate 50 is sometimes referred to as a drain substrate, and substrate 60 is sometimes referred to as a source substrate. Substrates 50 and 60 provide a heat dissipation function to dissipate the heat generated by the semiconductor element 40. For this reason, substrates 50 and 60 are sometimes referred to as heat dissipation members. Of the pair of substrates 50 and 60 that sandwich the semiconductor element 40 in the Z direction, substrate 50 is the first substrate, and substrate 60 is the second substrate.

[0042] Substrate 50 has a facing surface 50a that faces the semiconductor element 40 and a back surface 50b that is the opposite surface to the facing surface 50a. Substrate 50 comprises an insulating substrate 51, a surface metal body 52, and a back surface metal body 53. Substrate 50 is a substrate in which the insulating substrate 51 and the metal bodies 52 and 53 are laminated. Substrate 60 has a facing surface 60a that faces the semiconductor element 40 and a back surface 60b that is the opposite surface to the facing surface 60a. Substrate 60 comprises an insulating substrate 61, a surface metal body 62, and a back surface metal body 63. Substrate 60 is a substrate in which the insulating substrate 61 and the metal bodies 62 and 63 are laminated. In the first substrate, substrate 50, the insulating substrate 51 is the first insulating substrate, the surface metal body 52 is the first surface metal body, and the back surface metal body 53 is the first back surface metal body. In the second substrate, substrate 60, the insulating substrate 61 is the second insulating substrate, the surface metal body 62 is the second surface metal body, and the back metal body 63 is the second back metal body. Hereafter, the surface metal bodies 52, 62 and the back metal bodies 53, 63 may be simply referred to as metal bodies 52, 53, 62, and 63.

[0043] The insulating substrate 51 electrically separates the surface metal body 52 from the back metal body 53. Similarly, the insulating substrate 61 electrically separates the surface metal body 62 from the back metal body 63. The insulating substrates 51 and 61 are sometimes referred to as insulating layers. The material of the insulating substrates 51 and 61 is resin or an inorganic ceramic material. As resins, for example, epoxy resins and polyimide resins can be used. As ceramics, for example, Al2O3 (alumina) and Si3N4 (silicon nitride) can be used. When the insulating substrates 51 and 61 are resin, the substrates 50 and 60 are sometimes referred to as metal-resin substrates. When the insulating substrates 51 and 61 are ceramic, the substrates 50 and 60 are sometimes referred to as metal-ceramic substrates.

[0044] In the case of insulating substrates 51 and 61 made of resin material, inorganic fillers (inorganic fillers) may be included in the resin to improve heat dissipation, insulation, etc. The coefficient of linear expansion may be adjusted by adding fillers. Examples of fillers include Al2O3, SiO2 (silicon dioxide), AlN (aluminum nitride), and BN (boron nitride). The insulating substrates 51 and 61 may contain only one type of filler or multiple types.

[0045] Considering heat dissipation and insulation, in the case of resin-based materials, the thickness of each insulating substrate 51 and 61, i.e., the length in the Z direction, is preferably about 50 μm to 300 μm. In the case of ceramic-based materials, the thickness of the insulating substrates 51 and 61 is preferably about 200 μm to 500 μm. In the Z direction, the surface of the insulating substrates 51 and 61 is the inner surface, i.e., the surface facing the semiconductor element 40, and the back surface, which is the surface opposite to the surface in the Z direction, is the outer surface. The insulating substrates 51 and 61 may have the same material composition or they may be different. In this embodiment, resin-based insulating substrates 51 and 61 are used, and their material composition is the same. The coefficient of linear expansion of the insulating substrates 51 and 61 is adjusted to be approximately the same as that of the encapsulant 30 by adding a filler to the resin. By adding a filler to the resin, the coefficient of linear expansion of the insulating substrates 51 and 61 and the encapsulant 30 is close to that of the metal (Cu) that constitutes the metal bodies 52, 53, 62, and 63.

[0046] The metal bodies 52, 53, 62, and 63 are provided, for example, as metal plates or metal foils. The metal bodies 52, 53, 62, and 63 are formed from metals with good electrical and thermal conductivity, such as Cu or Al. The thickness of each of the metal bodies 52, 53, 62, and 63 is, for example, about 0.1 mm to 3 mm. The surface metal body 52 is located on the surface of the insulating substrate 51 in the Z direction. The back metal body 53 is located on the back surface of the insulating substrate 51. Similarly, the surface metal body 62 is located on the surface of the insulating substrate 61 in the Z direction. The back metal body 63 is located on the back surface of the insulating substrate 61. The insulating substrates 51 and 61 are the surfaces facing the semiconductor element 40 in the Z direction. As shown in Figures 5 to 9, in this embodiment, the surface metal body 52 is thicker than the back metal body 53. The surface metal body 62 is thicker than the back metal body 63. The surface metal body 52 on the drain electrode 40D side is thicker than the surface metal body 62 on the source electrode 40S side. Alternatively, the back metal bodies 53 and 63 may be thicker than the corresponding surface metal bodies 52 and 62. The thickness of the surface metal body 52 and the back metal body 53 may be approximately equal, or the thickness of the surface metal body 62 and the back metal body 63 may be approximately equal.

[0047] The surface metal bodies 52 and 62 are patterned. The surface metal bodies 52 and 62 provide wiring, i.e., circuits. For this reason, the surface metal bodies 52 and 62 are sometimes referred to as circuit patterns, wiring layers, or circuit conductors. The surface metal bodies 52 and 62 may have a plating film of Ni-based or Au on their metal surfaces. Hereinafter, the patterns of the surface metal bodies 52 and 62 may be referred to as circuit patterns. The surface metal body 52 and the non-placed areas of the surface metal body 52 on the surface of the insulating substrate 51 form the opposing surface 50a of the substrate 50. Similarly, the surface metal body 62 and the non-placed areas of the surface metal body 62 on the surface of the insulating substrate 61 form the opposing surface 60a of the substrate 60.

[0048] For example, surface metal bodies 52 and 62, patterned into a predetermined shape by press working or etching, may be prepared and then attached to a two-layer laminate consisting of insulating substrates 51 and 61 and back metal bodies 53 and 63 to form substrates 50 and 60. Alternatively, after forming a three-layer laminate consisting of surface metal bodies 52 and 62, insulating substrates 51 and 61, and back metal bodies 53 and 63, the surface metal bodies 52 and 62 may be patterned by cutting or etching.

[0049] As shown in Figure 11 and other figures, the surface metal body 52 has P wiring 54 and intermediate wiring 55. The P wiring 54 and intermediate wiring 55 are electrically isolated by a predetermined gap. This gap is filled with a sealant 30.

[0050] The P wiring 54 is connected to the P terminal 91P, which will be described later, and the drain electrode 40D of the semiconductor element 40H. The P wiring 54 electrically connects the P terminal 91P and the drain electrode 40D of the semiconductor element 40H. The P wiring 54 is sometimes referred to as positive electrode wiring or high-potential power supply wiring. The relay wiring 55 is connected to the drain electrode 40D of the semiconductor element 40L, the arm connection part 80, and the output terminal 92. The relay wiring 55 electrically connects the arm connection part 80 and the drain electrode 40D of the semiconductor element 40L. The relay wiring 55 electrically connects the source electrode 40S of the semiconductor element 40H and the drain electrode of the semiconductor element 40L and the output terminal 92. In the surface metal body 52 (first surface metal body), the P wiring 54 is the first power supply wiring, and the relay wiring 55 is the first relay wiring.

[0051] The P wiring 54 and the relay wiring 55 are arranged side by side in the Y direction. In the Y direction, the P wiring 54 is located on the side of the power terminal 91, and the relay wiring 55 is located on the side of the output terminal 92. In other words, the P wiring 54 is located close to the side 30c of the encapsulant 30, and the relay wiring 55 is located close to the side 30d.

[0052] The P wiring 54 has a notch 540. The notch 540 opens on one of the four sides of a roughly rectangular plane with the X direction as the longitudinal direction. The notch 540 is located approximately in the center in the X direction on the side facing the side surface 30c. The P wiring 54 has a base 541 and a pair of extensions 542. The base 541 and the pair of extensions 542 define the notch 540. The P wiring 54 has a roughly U-shape (concave shape) in plan.

[0053] The base portion 541 is the part on the relay wiring 55 side of the notch 540 and extension portion 542, and has a roughly rectangular shape in plan view. In plan view, the base portion 541 overlaps the semiconductor element 40H. In other words, the semiconductor element 40H is positioned on the base portion 541. The drain electrode 40D of the semiconductor element 40H is connected to the base portion 541.

[0054] The two extensions 542 extend from the base 541 in the same direction, specifically in the Y direction, towards the side 30c of the sealant 30. One extension 542 is connected to the base 541 near one end in the X direction, and the other is connected to the base 541 near the other end. The U-shaped ends of the P wiring 54, that is, the ends of the two extensions 542 opposite to the base 541, are approximately the same in the Y direction. The pair of extensions 542 straddle the notch 540 in the X direction. In the Y direction, the base 541 is longer than the depth of the notch 540 and the extensions 542.

[0055] The relay wiring 55 also has a notch 550. The notch 550 opens on one of the four sides of the substantially rectangular planar shape. The notch 550 is located approximately in the center in the X direction on the side opposite the side surface 30d. In other words, the surface metal body 52 has a notch 540 at one end in the Y direction and a notch 550 at the other end.

[0056] The relay wiring 55 has a base portion 551 and a pair of extension portions 552. The base portion 551 and the pair of extension portions 552 define the notch 550. The relay wiring 55 has a roughly U-shape (concave shape) in plan view. The base portion 551 is the part on the P wiring 54 side of the notch 550 and the extension portions 552, and has a roughly rectangular shape in plan view. In plan view, the base portion 551 overlaps the semiconductor element 40L. In other words, the semiconductor element 40L is positioned on the base portion 551. The drain electrode 40D of the semiconductor element 40L is connected to the base portion 551.

[0057] The two extensions 552 extend from the base 551 in the same direction, specifically in the Y direction, towards the side 30d of the sealing body 30. One extension 552 is connected to the base 551 near one end in the X direction, and the other is connected to the base 551 near the other end. The U-shaped ends of the relay wiring 55, that is, the ends of the two extensions 552 opposite to the base 551, are approximately the same in the Y direction. The pair of extensions 552 straddle the notch 550 in the X direction. In the Y direction, the base 551 is longer than the depth of the notch 550 and the extensions 552.

[0058] On the other hand, the surface metal body 62 has N wiring 64 and relay wiring 65, as shown in Figures 10 and 13. The N wiring 64 and relay wiring 65 are electrically isolated by a predetermined gap. This gap is filled with a sealant 30.

[0059] N wiring 64 is connected to the N terminal 91N, which will be described later, and the source electrode 40S of the semiconductor element 40L. N wiring 64 electrically connects the N terminal 91N and the source electrode 40S of the semiconductor element 40L. N wiring 64 is sometimes referred to as N wiring. Relay wiring 65 is connected to the source electrode 40S of the semiconductor element 40H and the arm connection part 80. Relay wiring 65 electrically connects the source electrode 40S of the semiconductor element 40H and the arm connection part 80. In the surface metal body 62 (second surface metal body), N wiring 64 is the second power supply wiring, and relay wiring 65 is the second relay wiring.

[0060] The N wiring 64 has a base portion 640 and a pair of extension portions 641. The N wiring 64 has a roughly U-shape in plan view. The base portion 640 is arranged alongside the relay wiring 65 in the Y direction. The base portion 640 is located on the side 30d in the Y direction. The base portion 640 has a roughly rectangular shape in plan view with the X direction as its longitudinal direction. As shown in Figure 15, the base portion 640 overlaps the semiconductor element 40L in plan view. In other words, the semiconductor element 40L is located on the base portion 640. The source electrode 40S of the semiconductor element 40L is connected to the base portion 640.

[0061] The two extensions 641 extend from the base 640 in the same direction, specifically in the Y direction, towards the side surface 30c of the sealant 30. One extension 641 is connected to the base 640 near one end in the X direction, and the other is connected to the base 640 near the other end. The two ends of the U-shape of the N wiring 64, that is, the ends of the two extensions 641 opposite to the base 640, are in approximately the same position in the Y direction.

[0062] The pair of extensions 641 form both ends of the surface metal body 62 in the X direction. The pair of extensions 641 are positioned near the edges of the substrate 60. In plan view, a portion of each of the pair of extensions 641 overlaps the P wiring 54. In the Y direction, the length of the extensions 641 is longer than that of the base 640. The N wiring 64 also has a notch 642. The notch 642 opens on one of the four sides of a roughly rectangular plane with the Y direction as its longitudinal direction. The notch 642 is located approximately in the center in the X direction on the side opposite the side surface 30c. The base 640 and the pair of extensions 641 define the notch 642.

[0063] As described above, the relay wiring 65 is arranged in the Y direction alongside the N wiring 64, specifically the base portion 640. In the Y direction, the relay wiring 65 is positioned close to the side surface 30c of the sealing body 30, and the base portion 640 is positioned close to the side surface 30d. In the X direction, the relay wiring 65 is positioned between a pair of extension portions 641. The relay wiring 65 is sandwiched between the pair of extension portions 641. The relay wiring 65 is positioned within the notch 642. The relay wiring 65 is positioned with a predetermined gap between it and the N wiring 64. In a plan view, a portion of the relay wiring 65 overlaps with the P wiring 54, and another portion overlaps with the relay wiring 55.

[0064] As shown in Figure 15, the relay wiring 65 overlaps the semiconductor element 40H in a plan view. In other words, the semiconductor element 40H is positioned on the relay wiring 65. The source electrode 40S of the semiconductor element 40H is connected to the relay wiring 65. A more detailed example of the circuit pattern of the surface metal body 62 will be described later.

[0065] The back metal bodies 53 and 63 are electrically isolated from the circuit including the semiconductor element 40 by the insulating substrates 51 and 61. The back metal bodies 53 and 63 are sometimes referred to as metal base substrates. The heat generated by the semiconductor element 40 is transferred to the back metal bodies 53 and 63 via the front metal bodies 52 and 62 and the insulating substrates 51 and 61. The back metal bodies 53 and 63 provide a heat dissipation function. In this embodiment, the back metal bodies 53 and 63 have a substantially rectangular shape in plan, and their outer contours substantially coincide with the outer contours of the front metal bodies 52 and 62. The back metal bodies 53 and 63 are so-called solid conductors arranged over almost the entire back surface of the insulating substrates 51 and 61. As described above, the coefficient of linear expansion of the insulating substrates 51 and 61 is adjusted by adding fillers, so warping can be suppressed even if the pattern is changed on the front and back surfaces. Of course, the back metal bodies 53 and 63 may be patterned so that they coincide with the front metal bodies 52 and 62 in a plan view.

[0066] In this embodiment, the back metal bodies 53 and 63 are arranged over almost the entire back surface of the corresponding insulating substrates 51 and 61. To further enhance the heat dissipation effect, at least one of the back metal bodies 53 and 63 may be exposed from the sealant 30. In this embodiment, the back metal body 53 is exposed from one surface 30a of the sealant 30, and the back metal body 63 is exposed from the back surface 30b. The exposed surface of the back metal body 53 is substantially flush with the surface 30a. The exposed surface of the back metal body 63 is substantially flush with the back surface 30b. The back metal bodies 53 and 63 constitute the back surfaces 50b and 60b of the substrates 50 and 60.

[0067] The conductive spacer 70 provides a spacer function to ensure a predetermined gap between the semiconductor element 40 and the substrate 60. For example, the conductive spacer 70 ensures height for electrically connecting the corresponding signal terminal 93 to the pad 40P of the semiconductor element 40. The conductive spacer 70 is located in the middle of the electrical and thermal conduction path between the source electrode 40S of the semiconductor element 40 and the substrate 60, and provides wiring and heat dissipation functions. The conductive spacer 70 contains a metallic material with good electrical and thermal conductivity, such as Cu. The conductive spacer 70 may have a plating film on its surface. The conductive spacer 70 is a columnar body with a planar shape that is approximately the same size as the source electrode 40S in a plan view.

[0068] The conductive spacer 70 is sometimes referred to as a terminal, terminal block, or metal block. The semiconductor device 20 has the same number of conductive spacers 70 as the semiconductor elements 40. Specifically, it has four conductive spacers 70. The conductive spacers 70 are individually connected to the semiconductor elements 40.

[0069] The arm connection portion 80 electrically connects the relay wirings 55 and 65. In other words, the arm connection portion 80 electrically connects the upper arm 9H and the lower arm 9L. The arm connection portion 80 is provided between the semiconductor element 40H and the semiconductor element 40L in the Y direction. In a plan view, the arm connection portion 80 is provided in the overlapping region of the relay wiring 55 and the relay wiring 65. The arm connection portion 80 of this embodiment is composed of a joint portion 81 and a joining material 103, which will be described later.

[0070] The joint portion 81 is a metal columnar body provided separately from the surface metal bodies 52 and 62. Such a joint portion 81 is sometimes referred to as a joint terminal. In the Z direction, a connecting material 103 is interposed between one end of the joint portion 81 and the relay wiring 55, and another connecting material 103 is interposed between the other end and the relay wiring 65.

[0071] Alternatively, the joint portion 81 may be integrally connected to at least one of the surface metal bodies 52 and 62. In other words, the joint portion 81 may be integrally provided with the surface metal bodies 52 and 62 as part of the substrates 50 and 60. The arm connection portion 80 may be configured without the joint portion 81. In other words, the arm connection portion 80 may be configured to consist only of the joining material 103.

[0072] The external connection terminal 90 is a terminal for electrically connecting the semiconductor device 20 to an external device. The external connection terminal 90 is formed using a metal material with good conductivity, such as copper. The external connection terminal 90 is, for example, a plate. The external connection terminal 90 is sometimes referred to as a lead. The external connection terminal 90 includes a power terminal 91, an output terminal 92, and a signal terminal 93. The power terminal 91 includes a P terminal 91P and an N terminal 91N. The P terminal 91P, the N terminal 91N, and the output terminal 92 are main terminals that are electrically connected to the main electrodes of the semiconductor element 40. The signal terminal 93 includes a signal terminal 93H on the upper arm 9H side and a signal terminal 93L on the lower arm 9L side.

[0073] The power terminal 91 is an external connection terminal 90 that is electrically connected to the power lines 7 and 8 described above. The P terminal 91P is electrically connected to the positive terminal of the smoothing capacitor 5. The P terminal 91P is sometimes referred to as the positive terminal or high-potential power terminal. The P terminal 91P is connected to the P wiring 54 of the surface metal body 52. ​​In other words, the P terminal 91P is connected to the drain electrode 40D of the semiconductor element 40H that constitutes the upper arm 9H.

[0074] The P terminal 91P is connected to the vicinity of one end of the P wiring 54 in the Y direction. The P terminal 91P extends in the Y direction from the connection (joint) with the P wiring 54 and protrudes out of the encapsulant 30 from near the center in the Z direction on the side surface 30c. The semiconductor device 20 of this embodiment has two P terminals 91P. As shown in Figure 11, one P terminal 91P is connected to one of the pair of extensions 542, and the other is connected to the other of the pair of extensions 542. The P terminals 91P are positioned close to the notch 540, i.e., towards the inside, in each extension 542, so as to be adjacent to the N terminal 91N in a plan view. The two P terminals 91P are arranged side by side in the X direction. The two P terminals 91P are positioned in approximately the same position in the Z direction.

[0075] The N terminal 91N is electrically connected to the negative terminal of the smoothing capacitor 5. The N terminal 91N is sometimes referred to as the negative terminal or low-potential power supply terminal. The N terminal 91N is connected to the N wiring 64 of the surface metal body 62. In other words, the N terminal 91N is connected to the source electrode 40S of the semiconductor element 40L that constitutes the lower arm 9L.

[0076] The N terminal 91N is connected to the vicinity of one end of the N wiring 64 in the Y direction. The N terminal 91N extends in the Y direction from the junction with the N wiring 64 and protrudes out of the encapsulant 30 from near the center in the Z direction on the side surface 30c. The semiconductor device 20 has two N terminals 91N. As shown in Figure 15 and other figures, one N terminal 91N is connected to one of the pair of extensions 641, and the other is connected to the other of the pair of extensions 641. The two N terminals 91N are arranged side by side in the Y direction. The two N terminals 91N are arranged in approximately the same position in the Z direction.

[0077] The two N terminals 91N are located outside the two P terminals 91P in the X direction. In a plan view, one N terminal 91N is located near one P terminal 91P, and the other N terminal 91N is located near the other P terminal 91P. In the X direction, adjacent N terminals 91N and P terminals 91P have their sides facing each other in a portion including the portion that protrudes from the sealant 30.

[0078] The output terminal 92 is electrically connected to the corresponding phase winding 3a (stator coil) of the motor generator 3. The output terminal 92 is sometimes referred to as the O terminal or AC terminal. As shown in Figures 3 and 7, the output terminal 92 is connected to the relay wiring 55 of the surface metal body 52 on the substrate 50. In other words, the output terminal 92 is connected to the connection point between the upper arm 9H and the lower arm 9L.

[0079] The output terminal 92 is connected to the vicinity of one end of the relay wiring 55 in the Y direction. The output terminal 92 extends in the Y direction from the junction with the relay wiring 55 and protrudes out of the encapsulant 30 from near the center in the Z direction on the side surface 30d. The semiconductor device 20 has two output terminals 92. One output terminal 92 is connected to one of the pair of extensions 552, and the other is connected to the other of the pair of extensions 552. The two output terminals 92 are arranged side by side in the X direction. The two output terminals 92 are located in approximately the same position in the Z direction.

[0080] Signal terminal 93 is electrically connected to a drive circuit (driver) not shown. Signal terminal 93H is electrically connected to the pad 40P of the semiconductor element 40H via a connecting member such as a bonding wire 110. The number of signal terminals 93H is not particularly limited. Signal terminals 93H only need to include at least one terminal for applying a drive voltage to the gate electrode of the semiconductor element 40H. The semiconductor device 20 of this embodiment has two signal terminals 93H. One of the signal terminals 93H is a terminal for the gate electrode. The gate electrode signal terminal 93H is electrically connected to the gate electrode pads 40P of the two semiconductor elements 40H. The signal terminal 93H is positioned to overlap the notch 540 of the P wiring 54 in a plan view. At signal terminal 93H, the joint with the bonding wire 110 faces the insulating substrate 51, not the surface metal body 52. ​​The two signal terminals 93H are arranged side by side in the X direction.

[0081] The signal terminal 93H extends in the Y direction from the joint with the bonding wire 110 and protrudes out of the encapsulant 30 from near the center in the Z direction on the side surface 30c. At least a portion of the protruding part of the signal terminal 93H extends in the same direction as the power terminal 91. The signal terminal 93H is located between the two P terminals 91P in the X direction. In other words, the external connection terminals 90 protruding from the side surface 30c are arranged in the X direction in the order of N terminal 91N, P terminal 91P, two signal terminals 93H, P terminal 91P, and N terminal 91N.

[0082] The signal terminals 93L are electrically connected to the pads 40P of the semiconductor element 40L via connecting members such as bonding wires 110. The number of signal terminals 93L is not particularly limited. The signal terminals 93L only need to include at least one terminal for applying a drive voltage to the gate electrode of the semiconductor element 40L. The semiconductor device 20 of this embodiment has four signal terminals 93L. One of the signal terminals 93L is a terminal for the gate electrode. The gate electrode signal terminal 93L is electrically connected to the gate electrode pads 40P of the two semiconductor elements 40L. The signal terminals 93L are positioned to overlap the notches 550 of the relay wiring 55 in a plan view. At the signal terminals 93L, the joint with the bonding wire 110 faces the insulating substrate 51, not the surface metal body 52. ​​The four signal terminals 93L are arranged side by side in the X direction.

[0083] The signal terminal 93L extends in the Y direction from the joint with the bonding wire 110 and protrudes out of the sealant 30 from near the center in the Z direction on the side surface 30d. At least a portion of the protruding part of the signal terminal 93L extends in the same direction as the output terminal 92. The signal terminal 93L is positioned between the two output terminals 92 in the X direction. In other words, the external connection terminal 90 protruding from the side surface 30d is arranged in the X direction in the order of output terminal 92, four signal terminals 93L, and output terminal 92.

[0084] The drain electrode 40D of the semiconductor element 40 is joined to the surface metal body 52 via a bonding material 100. The source electrode 40S of the semiconductor element 40 is joined to the conductive spacer 70 via a bonding material 101. The conductive spacer 70 is joined to the surface metal body 62 via a bonding material 102. The joint portion 81 is joined to the metal bodies 52 and 62 via a bonding material 103. Of the external connection terminals 90, the main terminals P terminal 91P, N terminal 91N, and output terminal 92 are joined to the corresponding surface metal bodies 52 and 62 via a bonding material 104.

[0085] The bonding materials 100-104 are conductive bonding materials. For example, solder can be used as the bonding materials 100-104. An example of solder is a multi-component lead-free solder containing Cu, Ni, etc., in addition to Sn. Instead of solder, a sintered bonding material such as sintered silver may be used. The P terminal 91P, N terminal 91N, and output terminal 92 may be directly bonded to the corresponding surface metal bodies 52, 62 without using the bonding material 104. The P terminal 91P, N terminal 91N, and output terminal 92 may also be directly bonded to the surface metal bodies 52, 62 by methods such as ultrasonic bonding, friction stir bonding, or laser welding. If the joint portion 81 is provided separately from the substrates 50, 60, the joint portion 81 may be directly bonded to the surface metal bodies 52, 62.

[0086] As described above, in the semiconductor device 20, multiple semiconductor elements 40 constituting one phase of the upper and lower arm circuit 9 are sealed by a encapsulant 30. The encapsulant 30 integrally seals multiple semiconductor elements 40, a part of the substrate 50, a part of the substrate 60, multiple conductive spacers 70, arm connection parts 80, and a part of the external connection terminals 90. The encapsulant 30 seals the insulating substrates 51, 61 and surface metal bodies 52, 62 on the substrates 50 and 60.

[0087] The semiconductor element 40 is positioned between substrates 50 and 60 in the Z direction. The semiconductor element 40 is sandwiched between the opposing substrates 50 and 60. This allows heat from the semiconductor element 40 to be dissipated on both sides in the Z direction. The semiconductor device 20 has a double-sided heat dissipation structure. The back surface 50b of substrate 50 is substantially flush with one surface 30a of the encapsulant 30. The back surface 60b of substrate 60 is substantially flush with the back surface 30b of the encapsulant 30. Since the back surfaces 50b and 60b are exposed surfaces, heat dissipation can be enhanced.

[0088] <Manufacturing method> Next, an example of a method for manufacturing the semiconductor device 20 will be described based on Figure 10. In Figure 10, the substrate 50 and the substrate 60 are shown facing each other to make the subsequent assembly easier to understand.

[0089] First, the semiconductor element 40, substrates 50 and 60, conductive spacer 70, joint portion 81, and lead frame 94 are prepared. As shown in Figure 10, the lead frame 94 is equipped with external connection terminals 90. The lead frame 94 is formed by processing a metal plate, such as by pressing. The external connection terminals 90 are supported on the outer peripheral frame 94b via tie bars 94a.

[0090] Next, the semiconductor element 40, the joint portion 81, and the external connection terminal 90 are joined (connected) to the substrate 50. A conductive spacer 70 is also joined to the semiconductor element 40.

[0091] At this time, the lead frame 94 and semiconductor element 40 are placed on the substrate 50. A conductive spacer 70 is also placed on the source electrode 40S of the semiconductor element 40. The lead frame 94 is positioned such that a portion of each of the external connection terminals 90 overlaps the substrate 50 in a plan view. Specifically, the P terminal 91P and N terminal 91N are positioned to overlap the P wiring 54 of the surface metal body 52, and the output terminal 92 is positioned to overlap the relay wiring 55. In addition, the signal terminal 93H is positioned to overlap the insulating substrate 51 exposed from the notch 540, and the signal terminal 93L is positioned to overlap the insulating substrate 51 exposed from the notch 550.

[0092] Then, the bonding material 100 is used to bond the drain electrode 40D of the semiconductor element 40 to the surface metal body 52. ​​The bonding material 101 is used to bond the source electrode 40S to the conductive spacer 70. The bonding material 103 is used to bond the joint portion 81 to the surface metal body 52. ​​The bonding material 104 is used to bond the P terminal 91P and the output terminal 92 to the surface metal body 52. ​​For example, in the case of solder, the bonding can be performed all at once by reflow soldering. Figure 10 shows this bonding state.

[0093] Next, the pad 40P of semiconductor element 40H and the signal terminal 93H are electrically connected using the bonding wire 110. Similarly, the pad 40P of semiconductor element 40L and the signal terminal 93L are electrically connected using the bonding wire 110.

[0094] Next, the substrate 60 is joined (connected). The source electrode 40S of the semiconductor element 40 and the surface metal body 62 are joined via the bonding material 102. The joint portion 81 and the surface metal body 62 are joined via the bonding material 103. The N terminal 91N and the surface metal body 62 are joined via the bonding material 104. For example, in the case of solder, the joining can be performed all at once by reflow soldering.

[0095] Next, the sealant 30 is molded using the transfer molding method. Although not shown in the figures, in this embodiment, the sealant 30 is molded so that the substrates 50 and 60 are completely covered, and then cutting is performed after molding. The sealant 30 is cut along with a portion of the back metal bodies 53 and 63 of the substrates 50 and 60. This exposes the back surfaces 50b and 60b. Back surface 50b is substantially flush with one surface 30a of the sealant 30, and back surface 60b is substantially flush with back surface 30b. Alternatively, the sealant 30 may be molded with the back surfaces 50b and 60b pressed against the cavity wall of the molding die and in close contact. In this case, the back surfaces 50b and 60b are exposed from the sealant 30 at the time of molding. Therefore, cutting after molding becomes unnecessary.

[0096] Next, unnecessary parts such as the tie bar 94a and the outer frame 94b are removed from the lead frame 94. This completes the process to obtain the semiconductor device 20.

[0097] <Positional relationship> Next, the positional relationships between the semiconductor element 40, the circuit patterns of the surface metal bodies 52 and 62, the arm connection portion 80, and the external connection terminals 90 connected to the circuit patterns will be explained based on Figures 14 and 15. Figure 14 is a diagram showing the arrangement of the circuit pattern of the surface metal body 52, the semiconductor element 40, and the terminals. Figure 15 is a diagram showing the arrangement of the circuit pattern of the surface metal body 62, the semiconductor element 40, and the terminals. For convenience, only the external connection terminals 90 connected to the circuit patterns are shown in Figures 14 and 15. In Figure 14, the main electrode (drain electrode 40D) connected to the surface metal body 52 is indicated by "D" in the arrangement area of ​​the semiconductor element 40 for clarity. Similarly, in Figure 15, the main electrode (source electrode 40S) connected to the surface metal body 62 is indicated by "S" in the arrangement area of ​​the semiconductor element 40 for clarity.

[0098] The imaginary line CL1 shown in Figure 14 is a hypothetical line passing through the midpoint of two semiconductor elements 40 that constitute one arm. The imaginary line CL1 passes through the midpoint (center) of the two semiconductor elements 40 in the direction of alignment and extends in the Y direction. The imaginary line CL1 is, for example, a line passing through the midpoint of two semiconductor elements 40H. Instead of semiconductor element 40H, it may be a line passing through the midpoint of semiconductor element 40L.

[0099] As shown in Figure 14, the arrangement of the two semiconductor elements 40H is approximately symmetric with respect to the virtual line CL1. Similarly, the arrangement of the two semiconductor elements 40L is also approximately symmetric with respect to the virtual line CL1. Here, approximately symmetric means that an error of the magnitude of manufacturing variation is tolerable. The circuit pattern of the surface metal body 52 is also approximately symmetric with respect to the virtual line CL1. In other words, both the P wiring 54 and the relay wiring 55 are approximately symmetric with respect to the virtual line CL1.

[0100] The arrangement of the arm connection section 80 connected to the relay wiring 55 is also approximately symmetrical with respect to the virtual line CL1. The arrangement of the external connection terminal 90 connected to the surface metal body 52 is also approximately symmetrical with respect to the virtual line CL1. In other words, the arrangement of the two P terminals 91P is also approximately symmetrical with respect to the virtual line CL1. The arrangement of the two output terminals 92 is also approximately symmetrical with respect to the virtual line CL1.

[0101] Similar to Figure 14, Figure 15 also shows a virtual line CL1. The arrangement of semiconductor elements 40H and 40L is the same as in Figure 14. As shown in Figure 15, the circuit pattern of the surface metal body 62 is also approximately symmetric with respect to the virtual line CL1. That is, both the N wiring 64 and the relay wiring 65 are approximately symmetric with respect to the virtual line CL1. The arrangement of the arm connection part 80 connected to the relay wiring 65 is also approximately symmetric with respect to the virtual line CL1, similar to Figure 14. The arrangement of the two N terminals 91N, which are external connection terminals 90 connected to the surface metal body 62, is also approximately symmetric with respect to the virtual line CL1.

[0102] <Circuit Pattern> Next, the circuit pattern of the surface metal body 62 will be described in more detail based on Figure 15. The dashed lines shown in Figure 15 indicate the boundaries of each region.

[0103] As described above, the surface metal body 62 of the substrate 60 has N wiring 64 and relay wiring 65. The N wiring 64 has a base portion 640 and a pair of extension portions 641. The pair of extension portions 641 extend from the base portion 640 in the Y direction toward the side surface 30c of the sealant 30. The N wiring 64 defines the outer contour of the surface metal body 62. The relay wiring 65 is sandwiched between the pair of extension portions 641. The relay wiring 65 is located within a notch 642 of the N wiring 64.

[0104] As shown in Figure 15, the relay wiring 65 has an end portion 650 as one end in the Y direction. The end portion 650 is the end on the base portion 640 side in the Y direction. On the other hand, the base portion 640 of the N wiring 64 has an opposite side 640a to the end portion 650. The opposite side 640a is the portion of the base portion 640 between a pair of extension portions 641. The base portion 640 also has a placement region 640b for the semiconductor element 40L. The placement region 640b is defined by the outer contour of the semiconductor element 40L, as shown by the dashed line in Figure 15. The placement region 640b includes the region that overlaps with the semiconductor element 40L in a plan view, and also includes the region between elements if there are multiple semiconductor elements 40L. The region between elements is the region opposite to the semiconductor elements 40L in the direction in which the semiconductor elements 40L are arranged.

[0105] Here, the lengths L1, L2, and L3 in the X direction are defined as follows. The length L1 is the length of the end portion 650 of the relay wiring 65 as shown in FIG. 15. The length L2 is the length of the opposing side 640a of the base portion 640. The length L3 is the length of the arrangement region 640b in the base portion 640. In the present embodiment, the relationship L1 < L2 < L3 is satisfied.

[0106] The relay wiring 65 of the present embodiment has a width-reducing portion 651a. The width-reducing portion 651a includes the end portion 650. The width-reducing portion 651a is a portion within a predetermined range in the Y direction from the end portion 650. The length in the X direction of the width-reducing portion 651a, that is, the width, is minimum at the end portion 650. In the width-reducing portion 651a, the width W1 at an arbitrary first position is less than or equal to the width W2 at a second position farther from the end portion 650 than the first position.

[0107] The width of the width-reducing portion 651a may be reduced stepwise, for example, for each predetermined length in the Y direction. That is, the end portion in the X direction of the width-reducing portion 651a may change in a stepped manner. In the present embodiment, the length in the X direction of the width-reducing portion 651a becomes shorter as it approaches the base portion 640. That is, the width of the width-reducing portion 651a continuously decreases toward the base portion 640. The arm connection portion 80 is arranged in the width-reducing portion 651a.

[0108] The relay wiring 65 may have only the width-reducing portion 651a including the end portion 650. In this case, the semiconductor element 40H is also arranged in the width-reducing portion 651a. The relay wiring 65 of the present embodiment has a constant-width portion 651b. The constant-width portion 651b is continuous with the width-reducing portion 651a and is a portion having a constant width over a predetermined range in the Y direction. And the semiconductor element 40H is arranged in the constant-width portion 651b.

[0109] The relay wiring 65 of this embodiment further has a narrowed width section 651c. The narrowed width section 651c includes an end 652 opposite to the end 650. The narrowed width section 651c is connected to the constant width section 651b, opposite to the narrowed width section 651a. The width of the narrowed width section 651c is minimum at the end 652. In the narrowed width section 651c, the width of any first position is less than or equal to the width of a second position that is further from the end 652 than the first position. In this embodiment, the width of the narrowed width section 651c is continuously reduced toward the end 652. In the relay wiring 65, the width of the narrowed width sections 651a and 651c becomes narrower the further they are from the constant width section 651b.

[0110] In this embodiment, the distance between the N wiring 64 and the relay wiring 65 is substantially constant throughout the entire opposing region. The extended portion 641 of the N wiring 64 is patterned so that the distance from the relay wiring 65 is substantially constant. Each of the extended portions 641 has a widened portion 641a, a constant width portion 641b, and a widened portion 641c.

[0111] The widened portion 641a is connected to the base portion 640 and is a portion within a predetermined range in the Y direction from the boundary with the base portion 640. The length in the X direction of the widened portion 641a, i.e., the width, is maximum at the boundary with the base portion 640. In the widened portion 641a, the width at any first position is greater than or equal to the width at a second position that is further from the base portion 640 than the first position. In this embodiment, the width of the widened portion 641a expands continuously toward the base portion 640. The constant width portion 641b is connected to the widened portion 641a and is a portion with a constant width over a predetermined range in the Y direction. The constant width portion 641b faces the constant width portion 651b of the relay wiring 65.

[0112] The widened section 641c, unlike the widened section 641a, is connected to the fixed-width section 641b. The widened section 641a extends to a position closer to the side surface 30c than the narrowed section 651c. The widened section 641c includes the tip 641d of the extended section 641. The width of the widened section 641c is greatest at the tip 641d. In the widened section 641c, the width of any first position is greater than or equal to the width of a second position further from the tip 641d than the first position. In this embodiment, the width of the widened section 641c continuously expands toward the tip 641d in the portion facing the narrowed section 651c. In the widened section 641c, the portion closer to the tip 641d than the opposing portion has a fixed width. In the N wiring 64, a part of the widened section 641c and the widened section 641a become wider the further they are from the fixed-width section 641b.

[0113] <Current Path> Next, the current path will be explained based on Figures 16 to 20. Figure 16 is a diagram showing the PN current loop of a reference example. In the reference example, the sign of each element is the same as that of the related element of the semiconductor device 20 with 'r' added to the end. The configuration of the reference example is almost the same as that of the semiconductor device 20, except that the number of signal terminals 93Lr and the patterns of the N wiring 64r and relay wiring 65r are different. Figure 17 is a diagram showing the PN current loop in the semiconductor device 20 of this embodiment. Figure 18 is a diagram showing the PN current loop in a side view of the semiconductor device 20 viewed from the X direction. The PN current loop refers to the loop shape of the current path from the P terminal 91P to the N terminal 91N.

[0114] When considering inductance, we consider the PN current loop from P terminal 91P → P wiring 54 → semiconductor element 40H → relay wiring 65 → arm connection 80 → relay wiring 55 → semiconductor element 40L → N wiring 64 → N terminal 91N. For this reason, to make the PN current loop easier to understand, the line from P terminal 91P to N terminal 91N is shown as a continuous solid line. In reality, semiconductor elements 40H and 40L are controlled so that they do not turn on simultaneously. For convenience, only the current path for one semiconductor element 40H and one semiconductor element 40L is shown, but the same applies to the other semiconductor element 40H and the other semiconductor element 40L.

[0115] Figures 19 and 20 show the results of electromagnetic field simulations. Figure 19 shows the current density of the reference example shown in Figure 18. Figure 20 shows the current density of the configuration of this embodiment shown in Figure 16. The conditions for the electromagnetic field simulations were common to both, except for the difference in the circuit pattern of the surface metal body 62. In Figures 19 and 20, a lower current density indicates a coarser (lighter color), and a higher current density indicates a denser (darker color).

[0116] As shown in Figure 16, in the reference example semiconductor device 20r, the relay wiring 65r has a roughly rectangular shape in plan. The length of the end 650r of the relay wiring 65r is approximately equal to the length of the placement area 640br of the semiconductor element 40Lr at the base 640r. The length of the opposite side 640ar at the base 640r is longer than the placement area 640br. Therefore, as shown by the solid arrows in Figure 16, current enters the roughly rectangular semiconductor element 40Lr from one side 400r and exits from another side 401r. Side 400r is the side opposite to the relay wiring 65r. Side 401r is the side opposite to the side on which the two semiconductor elements 40Lr face each other. Thus, the current flows outward in the X direction from the semiconductor element 40Lr, resulting in a large PN current loop. The simulation results shown in Figure 19 also clearly show that the current flows outward in the X direction from the semiconductor element 40Lr through the base 640r.

[0117] On the other hand, in the semiconductor device 20 of this embodiment, as described above, the N wiring 64 and the relay wiring 65 are patterned and satisfy a predetermined positional relationship with the semiconductor element 40L. Due to this positional relationship, as shown in Figure 17, the N wiring 64 (extension portion 641) is also located above one side 400 of the semiconductor element 40L in a plan view. Side 400 is the side opposite to the relay wiring 65. Therefore, current enters from side 400 of the semiconductor element 40L and exits from the same side 400. Of the current flowing from the semiconductor element 40L to the N terminal 91N, the Y-direction component increases particularly in the vicinity of the semiconductor element 40L. The simulation results shown in Figure 20 also clearly show that the current flows from the semiconductor element 40L with a Y-direction component.

[0118] In this way, the current flowing through the N wiring 64 approaches the relay wiring 65, and the current path through the N wiring 64, that is, the current path between the semiconductor element 40L and the N terminal 91N, becomes shorter. Therefore, the PN current loop is smaller compared to the reference example. As shown in Figure 18, the PN current loop is also small in the Z direction. The P wiring 54 and the N wiring 64 face each other in the Z direction. Also, the relay wiring 55 and the N wiring 64 face each other in the Z direction.

[0119] <Summary of the First Embodiment> If the inductance of the main circuit wiring is large, the surge voltage will be large. Increasing the thickness of the semiconductor element to ensure voltage resistance increases steady-state losses. To reduce steady-state losses, the element area needs to be increased. Also, the surge voltage can be reduced by lowering the switching speed. In this case, the output to the motor generator will be smaller. Thus, if the inductance is large, the size of the semiconductor element will be larger or the output will be smaller.

[0120] When components through which currents flow in opposite directions are placed opposite each other, the inductance can be reduced due to the canceling effect of the magnetic fluxes generated by the currents. If the PN current loop of the main circuit wiring is smaller, the components through which currents flow in opposite directions will be closer to each other, increasing the canceling effect of the magnetic fluxes and thus reducing the inductance.

[0121] In this embodiment, semiconductor elements 40H and 40L are arranged side by side in the Y direction, and the arm connection portion 80 is positioned between the semiconductor elements 40H and 40L. Of the main terminals, the power terminals 91 (91P and 91N) are brought out in the same direction. In the Y direction, the P wiring 54 is positioned on the side of the power terminal 91, and the relay wiring 55 is positioned on the opposite side. In the Y direction, the relay wiring 65 is positioned on the side of the power terminal 91, and the base portion 640 of the N wiring 64 is positioned on the opposite side. The extension portion 641 of the N wiring 64 is extended towards the power terminal 91, sandwiching the relay wiring 65.

[0122] With such a configuration, the PN current loop becomes smaller. As a result, the inductance of the main circuit wiring can be reduced. For example, by arranging the P terminal 91P and the N terminal 91N in parallel, the inductance can be reduced. The relay wiring 65 and the N wiring 64 are also arranged (in parallel) with a predetermined interval therebetween. As a result, the inductance can be reduced. Further, the extended portion 641 of the N wiring 64 faces the P wiring 54. As a result, the inductance can be reduced.

[0123] In the present embodiment, the surface metal body 52 of the substrate 50 and the surface metal body 62 of the substrate 60 provide a wiring function for the semiconductor element 40. The surface metal bodies 52 and 62 are sealed by the sealing body 30. Since it is not necessary to secure a creepage distance as in the prior art, the N wiring 64 and the relay wiring 65 can be arranged closer to each other. As a result, the effect of magnetic flux cancellation is enhanced, and the inductance can be further reduced.

[0124] Also, as shown in FIG. 15, the length L1 of the end portion 650 of the relay wiring 65, the length L of the opposing side 640a of the base portion 640, and the length L3 of the arrangement region 640b of the semiconductor element 40L in the base portion 640 satisfy the relationship L1 < L2 < L3. By satisfying this dimensional relationship, as described above, current enters from one side 400 of the semiconductor element 40L and exits from the same side 400. Among the currents flowing from the semiconductor element 40L toward the N terminal 91N, particularly in the vicinity of the semiconductor element 40L, the Y-direction component increases. As a result, the current path through the N wiring 64, that is, the current path between the semiconductor element 40L and the N terminal 91N becomes shorter, and the PN current loop becomes smaller. Therefore, the inductance of the main circuit wiring can be further reduced.

[0125] Also, the higher the frequency of the current, the more the current concentrates on the opposing side between the extended portion 641 of the N wiring 64 and the relay wiring 65 due to the skin effect. As a result, the PN current loop can be further reduced, and thus the inductance can be further reduced.

[0126] In this embodiment, as shown in Figure 15, the relay wiring 65 has a narrowed portion 651a. This allows the width of the portion of the extended portion 641 that faces the narrowed portion 651a to be increased. Therefore, heat generation due to current flow can be suppressed without changing the size of the surface metal body 62, and consequently the substrate 60. In other words, heat generation can be suppressed while reducing inductance.

[0127] In this embodiment in particular, the length of the narrowed portion 651a in the X direction becomes shorter as it approaches the base portion 640. In other words, the width of the narrowed portion 651a continuously decreases toward the base portion 640. The narrowed portion 651a of the relay wiring 65 has a tapered shape. This makes it easier to keep the distance between the relay wiring 65 and the extended portion 641 constant. In other words, the extended portion 641 can be brought closer to the relay wiring 65, making the PN current loop smaller. In addition, the width of the extended portion 641 can be increased, suppressing heat generation.

[0128] In this embodiment, the relay wiring 65 has a fixed-width portion 651b. The semiconductor element 40H is arranged in the fixed-width portion 651b. The relay wiring 65, having a reduced-width portion 651a and a fixed-width portion 651b, has the same or a similar shape to a baseball home plate in a plan view. This allows the width of the extended portion 641 to be wider compared to a configuration in which the semiconductor element 40H is arranged in the reduced-width portion 651a. Therefore, heat generation due to current flow can be suppressed without changing the size of the surface metal body 62, and consequently the substrate 60. In other words, heat generation can be suppressed while reducing inductance.

[0129] In this embodiment, the semiconductor device 20 comprises two semiconductor elements 40H and two semiconductor elements 40L. The two semiconductor elements 40H are arranged side by side in the X direction. Similarly, the two semiconductor elements 40L are arranged side by side in the X direction. In this way, the semiconductor elements 40 constituting a single arm are arranged side by side in a direction (X direction) perpendicular to the direction of alignment (Y direction) of the semiconductor elements 40H and 40L. In the X direction, a pair of extensions 641 sandwich the relay wiring 65. This makes it possible to suppress current unevenness.

[0130] The semiconductor device 20 may have a single N terminal 91N whose tip is branched into two so as to be individually connected to a pair of extensions 641. In this embodiment, the semiconductor device 20 has two N terminals 91N, and the N terminals 91N are individually connected to the pair of extensions 641. This makes it easy to place other external connection terminals 90 between the two N terminals 91N. Since it is not necessary to avoid the external connection terminals 90 placed in between, the size can be reduced.

[0131] The semiconductor device 20 may have only one P terminal 91P. In this embodiment, the semiconductor device 20 has two P terminals 91P. In the X direction, the terminals are arranged in the order of N terminal 91N, P terminal 91P, signal terminal 93H, P terminal 91P, and N terminal 91N. At both ends in the X direction, the P terminal 91P and N terminal 91N are arranged side by side. Therefore, it is easy to reduce the PN current loop. In addition, since the external connection terminals 90 are arranged regularly in the X direction, as described above, it is easy to ensure line symmetry with respect to the semiconductor element 40, the circuit patterns of the surface metal bodies 52 and 62, and the external connection terminals 90. This makes it possible to suppress current bias.

[0132] In this embodiment, the P terminal 91P and N terminal 91N protrude from the side surface 30c of the encapsulant 30, and the output terminal 92 protrudes from the side surface 30d. In this way, the P terminal 91P and N terminal 91N connected to the smoothing capacitor 5 are drawn out in the same direction, while the output terminal 92 is drawn out in the opposite direction. This improves connectivity with the smoothing capacitor 5 and the motor generator 3. Furthermore, the juxtaposition of the P terminal 91P and N terminal 91N reduces inductance. This terminal arrangement makes it easier to reduce the PN current loop.

[0133] <Variation> As an example of including a plurality of each of the semiconductor elements 40H and 40L, an example of including two of each has been shown, but it is not limited thereto. Three or more may be included. For example, a configuration in which three semiconductor elements 40H are arranged side by side in the X direction and three semiconductor elements 40L are arranged side by side in the X direction may be adopted. The circuit pattern of the surface metal body 62 and the arrangement of the semiconductor elements 40 are not limited to the above examples. For example, it may be as shown in FIGS. 21 and 22. In FIGS. 21 and 22, for the sake of convenience, the sealing body 30 on the back surface 30b side with respect to the insulating base material 51 is omitted from the illustration. Also, among the substrate 60, the insulating base material 61 and the back surface metal body 63 are omitted from the illustration. Similar to FIG. 17, the PN current loop is indicated by a solid arrow. In FIGS. 21 and 22, the semiconductor device 20 includes two signal terminals 93L.

[0134] In FIG. 21, the semiconductor device 20 includes two arm connection portions 80. The relay wiring 65 has a substantially rectangular planar shape. The two arm connection portions 80 are arranged side by side in the X direction in the vicinity of the end portion 650. The interval between the two semiconductor elements 40L is larger than that in the above example (see FIG. 17). The length of the arrangement region 640b of the semiconductor element 40L is longer than that in the above example. As a result, the relationship of L1 < L2 < L3 is satisfied. Therefore, current enters from the side 400 of the semiconductor element 40L and exits from the same side 400. Even with such a configuration, the current path by the N wiring 64 can be shortened and the PN current loop can be made smaller. However, in the configuration shown in FIG. 17, the width of the N wiring 64, particularly the width of the extension portion 641, can be made wider. Also, in the case of the configuration shown in FIG. 17, only one arm connection portion 80 may be provided.

[0135] In FIG. 22, the semiconductor device 20 includes only one semiconductor element 40H and one semiconductor element 40L respectively. In this example, the arrangement region 640b coincides with the outer contour of the semiconductor element 40L. The length of one semiconductor element 40H or 40L in the X direction is longer than that in the above example (see FIG. 17). Thus, the relationship of L1 < L2 < L3 is satisfied. Therefore, current enters from the side 400 of the semiconductor element 40L and exits from the same side 400. Even with such a configuration, the current path by the N wiring 64 can be shortened, and the PN current loop can be reduced.

[0136] The arrangement of the external connection terminals 90 is not limited to the above example. For example, the P terminal 91P may be arranged on the outer side in the X direction and the N terminal 91N may be arranged on the inner side. In this case, as shown in FIGS. 23 and 24, the semiconductor element 40 and the circuit pattern are also reversed. FIG. 23 shows the substrate 50. FIG. 24 shows the substrate 60.

[0137] As shown in FIG. 23, the circuit pattern of the surface metal body 52 of the substrate 50 is the same as the circuit pattern of the surface metal body 62 of the substrate 60 shown in FIG. 15. The P wiring 54 has the same pattern as the N wiring 64 shown in FIG. 15. The semiconductor element 40H is arranged on the N wiring 64. The relay wiring 55 has the same pattern as the relay wiring 65 shown in FIG. 15. The semiconductor element 40L and the arm connection portion 80 are arranged on the relay wiring 55.

[0138] As shown in FIG. 24, the circuit pattern of the surface metal body 62 of the substrate 60 is the same as the circuit pattern of the surface metal body 52 of the substrate 50 shown in FIG. 14. The N wiring 64 has the same pattern as the P wiring 54 shown in FIG. 14. The semiconductor element 40L is arranged on the N wiring 64. The relay wiring 65 has the same pattern as the relay wiring 55 shown in FIG. 14. The semiconductor element 40H and the arm connection portion 80 are arranged on the relay wiring 65.

[0139] In the configurations shown in Figures 23 and 24, the relationship between the first and second elements described above is reversed. Semiconductor element 40L is the first element, and semiconductor element 40H is the second element. Source electrode 40S is the first main electrode, and drain electrode 40D is the second main electrode. Substrate 60 is the first substrate, and substrate 50 is the second substrate. Insulating substrate 61 is the first insulating substrate, surface metal body 62 is the first surface metal body, and back metal body 63 is the first back metal body. Insulating substrate 51 is the second insulating substrate, surface metal body 52 is the second surface metal body, and back metal body 53 is the second back metal body.

[0140] (Second Embodiment) This embodiment is a modification based on a prior embodiment, and the description of the prior embodiment can be applied by reference. In order to suppress transient current imbalance during switching, the surface metal body on which multiple semiconductor elements are connected in parallel may be of a predetermined structure, as described in this embodiment.

[0141] <Semiconductor device> First, the semiconductor device 20 of this embodiment will be described based on Figure 25. Figure 25 is a cross-sectional view showing the semiconductor device 20 according to this embodiment. Figure 25 corresponds to Figure 8.

[0142] The semiconductor device 20 of this embodiment has the same configuration as the configuration described in the prior embodiment (see Figures 2 to 15). The semiconductor device 20 constitutes an upper and lower arm circuit 9 for one phase. As shown in Figure 25, the semiconductor device 20 includes a plurality of semiconductor elements 40, including two semiconductor elements 40H which are upper arm elements, substrates 50 and 60 arranged to sandwich the semiconductor elements 40 in the Z direction, and a encapsulant 30. The surface metal body 52 of the substrate 50 is connected to the drain electrode 40D, which is the first main electrode on the high-potential side of the semiconductor element 40. The surface metal body 62 of the substrate 60 is connected to the source electrode 40S, which is the second main electrode on the low-potential side of the semiconductor element 40. Although not shown, the semiconductor device 20 also includes two semiconductor elements 40L which are lower arm elements.

[0143] The surface metal body 62 is substantially symmetrical with respect to the imaginary line CL1, as in the previous embodiment. As shown in Figure 25, in this embodiment, the relay wiring 65 of the surface metal body 62 has a slit 653. As will be described later, the N wiring 64 has a slit 643.

[0144] <Effect of suppressing transient current imbalance> Next, the effect of suppressing transient current imbalance during switching will be explained based on Figures 26 and 27. Figure 26 is an equivalent circuit diagram of two semiconductor elements 40 (MOSFETs 11) that constitute one arm. Figure 27 is an illustrative diagram (potential diagram) that clearly shows the potential.

[0145] In Figures 26 and 27, one of the parallel-connected MOSFETs 11 is shown as MOSFET1, and the other as MOSFET2. The inductance of the drain electrode wiring (hereinafter referred to as drain wiring) is shown as Ld, and the inductance of the source electrode wiring (hereinafter referred to as source wiring) is shown as Ls. The gate potential is shown as Vg, the potential of the source electrode of MOSFET1 is shown as Vks1, the potential of the source electrode of MOSFET2 is shown as Vks1, and the common source potential is shown as Vs. The midpoint potential of potentials Vks1 and Vks2 is shown as Vm. The midpoint potential Vm is constant. Vm = (Vks1 + Vks2) / 2.

[0146] Furthermore, the gate voltage of MOSFET1 is denoted as Vgs1 and the gate voltage of MOSFET2 as Vgs2. The current flowing through MOSFET1 upon turn-on is denoted as I1, and the voltage generated across the inductance Ls when current I1 flows is denoted as ΔVs1. Similarly, the current flowing through MOSFET2 upon turn-on is denoted as I2, and the voltage generated across the inductance Ls when current I2 flows is denoted as ΔVs2. ΔVs1 = Ls × dI1 / dt. ΔVs² = Ls × dI² / dt.

[0147] Assuming that due to variations in the characteristics of MOSFET 11, a current I2 (I2 > I1) greater than the current I1 flows, as shown in Figure 26, the voltage ΔVs generated across the inductance Ls becomes ΔVs1 < ΔVs2. In other words, as shown in Figure 27, the potential Vks2 of the source electrode rises relative to the midpoint potential Vm, and the potential Vks1 falls. Therefore, the gate voltage Vgs1 > gate voltage Vgs2. Because the gate voltage Vgs2 is reduced, the current I2 becomes smaller. Thus, the inductance Ls of the source wiring has the function of suppressing transient current imbalance during switching due to variations in the characteristics of the parallel-connected semiconductor elements 40 (MOSFET 11).

[0148] However, if the inductance Ls of the source wiring is small, the function of suppressing the transient current imbalance described above is impaired. This leads to an imbalance in switching losses, necessitating a margin in the thermal design.

[0149] <Circuit board pattern> Next, the circuit pattern of the surface metal body 62 in the semiconductor device 20 of this embodiment will be described based on Figure 28. Figure 28 corresponds to Figure 15. In Figure 28, as in Figure 15, the source electrode 40S is indicated as S to clarify the main electrodes to be connected.

[0150] The N wiring 64 and the relay wiring 65 are source wirings to which the source electrode 40S of the semiconductor element 40 is connected. The N wiring 64 differs from the pattern of the prior embodiment in that it has a slit 643. Similarly, the relay wiring 65 differs from the pattern of the prior embodiment in that it has a slit 653. Except for the presence of slits 643 and 653, the configuration is the same as that described in the prior embodiment.

[0151] The slit 643 penetrates the N wiring 64 in its thickness direction (Z direction). The slit 643 is located in the base portion 640, overlapping the opposing regions of the two semiconductor elements 40L. The opposing region is the region where the semiconductor elements 40L face each other in the direction in which they are aligned. In other words, the slit 643 is located between the semiconductor elements 40L, which are the lower arm elements, in a plan view in the Z direction. The slit 643 is located in the base portion 640, between the electrical connection points with the semiconductor elements 40L. The slit 643 extends from between the semiconductor elements 40L in the Y direction, which is the direction in which the semiconductor elements 40H and 40L are aligned. The slit 643 opens on the opposing side 640a of the base portion 640. The slit 643 is located approximately in the center of the N wiring 64 in the X direction.

[0152] Thus, the slit 643 extends in the Y direction from the source electrode 40S of the semiconductor element 40L towards the side where the main terminal N terminal 91N is located, that is, the side through which current flows. The slit 643 does not open at the end 640c of the base 640. The slit 643 is provided up to near the lower end of the opposing region of the semiconductor element 40L. The slit 643 divides the N wiring 64 into a region to which one of the semiconductor elements 40L is connected and a region to which the other is connected. The slit 643 separates the current path of the source electrode 40S of the semiconductor element 40L, that is, the source current path.

[0153] The slit 653 penetrates the relay wiring 65 in its thickness direction (Z direction). The slit 653 is located in the relay wiring 65 at a position that overlaps with the opposing regions of the two semiconductor elements 40H. In other words, in a plan view, the slit 653 is located between the semiconductor elements 40H. The slit 653 is located in the relay wiring 65 between the electrical connection points with the semiconductor elements 40H. The slit 653 extends from between the semiconductor elements 40H in the Y direction. The slit 653 opens at the end 652. The slit 653 extends from the end 652 across the space between the semiconductor elements 40H (opposing region) to the vicinity of the arm connection 80. The slit 653 is located approximately in the center of the relay wiring 65 in the X direction.

[0154] Thus, the slit 653 extends from the source electrode 40S of the semiconductor element 40H toward the arm connection portion 80 in the Y direction. The slit 653 extends from the source electrode 40S of the semiconductor element 40H toward the side through which current flows. The slit 653 does not open at the end portion 650. The slit 643 is provided up to just before the arm connection portion 80. The slit 653 divides the relay wiring 65 into a region to which one of the semiconductor elements 40H is connected and a region to which the other is connected. The slit 653 separates the current path of the source electrode 40S of the semiconductor element 40H, i.e., the source current path.

[0155] <Summary of the second embodiment> Figure 29 shows the source current path. The solid arrows indicate the source current path on the semiconductor element 40H side, and the dashed arrows indicate the source current path on the semiconductor element 40L side. As described above, in this embodiment, slits 643 and 653 are provided in the surface metal body 62 to which the source electrode 40S, which is the main electrode on the low-potential side, is connected.

[0156] The slit 643 is provided between adjacent semiconductor elements 40L in an N wiring 64 where semiconductor elements 40L are connected in parallel. The slit 643 partitions the N wiring 64 and separates the source current path of each semiconductor element 40L. This prevents the current (source current) from the source electrode 40S of the semiconductor element 40L from converging near the source electrode 40S. In other words, the point where the source currents converge is moved away from the source electrode 40S in a plan view. Therefore, in a parallel circuit of two semiconductor elements 40L (MOSFET 11), the inductance Ls of the source wiring can be made larger compared to a configuration without the slit 643. Because the inductance Ls is large, transient current unbalance during switching can be suppressed even if there is variation (deviation) in the characteristics of the two semiconductor elements 40L. By providing the slit 643, transient current unbalance can be suppressed while maintaining high integration of the semiconductor elements 40L.

[0157] Similarly, the relay wiring 65 has a slit 653. The slit 653 is provided between two semiconductor elements 40H. The slit 653 partitions the relay wiring 65 and separates the source current paths of each semiconductor element 40H. This prevents the current (source current) from the source electrode 40S of the semiconductor element 40H from merging near the source electrode 40S. In other words, the point where the source currents merge is moved away from the source electrode 40S in a plan view. Therefore, in a parallel circuit of two semiconductor elements 40H, the inductance Ls of the source wiring can be made larger compared to a configuration without the slit 653. Because the inductance Ls is large, transient current unbalance during switching can be suppressed even if there is variation (deviation) in the characteristics of the two semiconductor elements 40H. By providing the slit 653, transient current unbalance can be suppressed while maintaining high integration of the semiconductor elements 40H.

[0158] In this embodiment, the slit 643 extends from between adjacent semiconductor elements 40L in the Y direction toward the N terminal 91N. The slit 643 extends from the source electrode 40S of the semiconductor element 40L toward the side through which current flows. This allows the source current path of each semiconductor element 40L to be separated over a longer distance. Therefore, in a parallel circuit of semiconductor elements 40L, the inductance Ls of the source wiring can be increased. In other words, the effect of suppressing transient current imbalance can be enhanced.

[0159] Similarly, the slit 653 extends from between adjacent semiconductor elements 40H in the Y direction toward the arm connection portion 80. The slit 653 extends from the source electrode 40S of the semiconductor element 40H toward the side through which current flows. This allows the source current path of each semiconductor element 40L to be separated over a longer distance. Therefore, in a parallel circuit of semiconductor elements 40H, the inductance Ls of the source wiring can be increased. In other words, the effect of suppressing transient current imbalance can be enhanced.

[0160] Figure 30 is a cross-sectional view taken along the line XXX-XXX in Figure 29. In this embodiment, the joint portion 81, the bonding material 103 connecting the joint portion 81 and the relay wiring 55, and the bonding material 103 connecting the joint portion 81 and the relay wiring 65 constitute the arm connection portion 80 which electrically connects the relay wirings 55 and 65. The joint portion 81 is a separate component from the substrates 50 and 60. The arm connection portion 80 electrically connects the relay wiring 65 connected to the source electrode 40S of the semiconductor element 40H and the relay wiring 55 connected to the drain electrode 40D of the semiconductor element 40L.

[0161] <Variation> In the example described above, the multiple semiconductor elements 40 are shown to include two semiconductor elements 40H and two semiconductor elements 40L, but the system is not limited to this. The configuration may include two of one of the semiconductor elements 40H and 40L, and one of the other. In this case, a slit should be provided in one of the two wirings (64, 65) of the surface metal body 62, where the multiple semiconductor elements 40 are connected in parallel to form a single arm. For example, in a configuration that includes two semiconductor elements 40H and one semiconductor element 40L, the slit 643 should not be provided in the N wiring 64, but rather in the relay wiring 65 to which the semiconductor element 40H is connected. Thus, the multiple semiconductor elements 40 may include two of at least one of the arm elements of the semiconductor elements 40H and 40L.

[0162] The number of semiconductor elements 40 connected in parallel is not limited to two. Three or more semiconductor elements 40 may be connected in parallel to form a single arm. For example, in a configuration including three semiconductor elements 40H, a slit 653 may be provided between adjacent semiconductor elements 40H in a plan view, for three semiconductor elements 40H arranged in a line in the X direction. Multiple semiconductor elements 40 may include multiple arm elements of at least one of the semiconductor elements 40H and 40L. They may also include multiple arm elements of both types, that is, multiple semiconductor elements 40H and multiple semiconductor elements 40L.

[0163] The arrangement of the N terminal 91N is not limited to the example described above. For example, the P terminal 91P may protrude from the side surface 30c of the encapsulant 30, and the N terminal 91N may protrude from the side surface 30d. In this case, the pattern of the N wiring 64 will be similar in shape to, for example, the P wiring 54 or the relay wiring 55. That is, the extension 641 extends from the base 640 to the side surface 30d of the encapsulant 30. In this configuration as well, the slit 643 only needs to be provided between the semiconductor elements 40L. Furthermore, by configuring the slit 643 to extend from the opposing region of the semiconductor element 40L to the outside of the opposing region and towards the N terminal 91N, the inductance Ls can be made larger.

[0164] Although the slits 643 and 653 between the semiconductor elements 40 are shown as one, the method is not limited to this. At least one of the slits 643 and 653 may be multiple.

[0165] While examples have been shown where slits 643 and 653 open at one end of the surface metal body 62, the examples are not limited to this. For example, in the examples shown in Figures 31 and 32, slit 643 extends in the Y direction from the opposite side 640a of the base 640 to the end 640c. Slit 643 divides the base 640, and consequently the N wiring 64, into two. Slit 643 crosses the opposing regions of the semiconductor element 40L. One semiconductor element 40L is placed in one of the divided N wirings 64, and the other semiconductor element 40L is placed in the other N wiring 64. Similarly, slit 653 extends in the Y direction from the end 652 to the end 650 of the relay wiring 65. Slit 653 divides the relay wiring 65 into two. One semiconductor element 40H is placed in one of the divided relay wirings 65, and the other semiconductor element 40H is placed in the other relay wiring 65.

[0166] Slits 643 and 653 are connected to each other, forming a single slit extending in the Y direction. The surface metal body 62 is approximately symmetrical with respect to the imaginary line CL1. Figure 33 shows the source current paths. Solid arrows indicate the source current paths of semiconductor element 40H, and dashed arrows indicate the source current paths of semiconductor element 40L. As described above, slit 643 divides the N wiring 64 into two. As a result, the source current of one semiconductor element 40L and the source current of the other do not merge on the substrate 60. Because the point of convergence of the source currents is further away, the inductance Ls of the source wiring can be further increased.

[0167] Similarly, the slit 653 divides the relay wiring 65 into two. As a result, the source current of the semiconductor element 40H and the other source current do not merge on the substrate 60. Because the point where the source currents merge is further away, the inductance Ls of the source wiring can be made even larger. In this way, the effect of suppressing transient current imbalance can be enhanced. Figures 31, 32, and 33 show modified examples. Figure 31 corresponds to Figure 28. Figure 32 corresponds to Figure 11. Figure 33 corresponds to Figure 29.

[0168] In the examples shown in Figures 31 to 33, the arm connection sections 80 are divided to the same number as the relay wiring 65, in accordance with the division of the relay wiring 65. The arm connection sections 80 are individually connected to the relay wiring 65. As a result, the source current does not merge in the arm connection sections 80, allowing the inductance Ls to be made larger.

[0169] In the modified configuration described above, a slit may be provided in the surface metal body 52 of the substrate 50. As shown in Figures 34 and 35, the relay wiring 55 of the surface metal body 52 has a slit 553. The slit 553 opens at the end 551a of the relay wiring 55. The end 551a faces the P wiring 54 in the Y direction. The slit 553 extends in the Y direction, crosses the two divided arm connection portion 80, and reaches the opposing region (between) of the semiconductor element 40L. The slit 553 is provided up to near the lower end of the opposing region of the semiconductor element 40L.

[0170] When this configuration is adopted, as shown in Figure 35, a first current path using one set of semiconductor elements 40H, 40L and a second current path using another set of semiconductor elements 40H, 40L are almost completely separated within the semiconductor device 20. The point where the currents merge is located outside the N terminal 91N. Therefore, the inductance Ls of the source wiring can be made even larger. Figures 34 and 35 show modified examples. Figure 34 corresponds to Figure 32. Figure 35 corresponds to Figure 33. The semiconductor device 20 may also be provided with an N busbar connecting multiple N terminals 91N. In this case, the currents merge at the N busbar. The N busbar connecting the N terminals 91N may be provided, for example, on the smoothing capacitor 5 side.

[0171] The example shown illustrates that the arm connection portion 80 is composed of a joint portion 81 and joining materials 103 arranged on both ends of the joint portion 81, but it is not limited to this. In the example shown in Figure 36, the joint portion 81 is provided integrally with the substrate 60. The joint portion 81 is provided as a projection extending in the Z direction from the relay wiring 65. The conductive spacer 70 is also provided integrally with the surface metal body 62 as a projection, similar to the joint portion 81.

[0172] The surface metal body 62 having protrusions may be formed, for example, by patterning a metal plate of an irregular shape by press working and attaching it to the insulating substrate 61. The surface metal body 62 having protrusions may also be formed by etching thick Cu. It may also be formed by directly joining a metal body made of a separate component from the substrate 60 to the surface metal body 62. In the configuration shown in Figure 36, the joint portion 81, which is a protrusion of the relay wiring 65, and the joining material 103 interposed between the tip of the joint portion 81 and the relay wiring 55 constitute the arm connection portion 80. Figure 36 is a diagram corresponding to Figure 30.

[0173] In the example shown in Figure 37, the joint portion 81 is omitted. The bonding material 103 electrically connects the relay wiring 55 and 65. The bonding material 103 constitutes the arm connection portion 80. In Figure 37, the conductive spacer 70 is also omitted, and the source electrode 40S of the semiconductor element 40 is connected to the surface metal body 62 via the bonding material 101. Although not shown, the arm connection portion 80 may be configured to have only the joint portion 81 and no bonding material 103. In this case, the joint portion 81 is directly bonded to the relay wiring 55 and 65.

[0174] The circuit patterns of substrates 50 and 60 are not limited to the examples described above. The substrate 60 shown in Figure 38 shows an example in which slits 643 and 653 are applied to the circuit pattern shown in Figure 24. In the example shown in Figure 38, slit 643 is provided between adjacent semiconductor elements 40L. Slit 643 extends from between the semiconductor elements 40L in the Y direction toward the N terminal 91N side, that is, the side through which the source current flows. Slit 653 is provided between adjacent semiconductor elements 40H. Slit 653 extends from between the semiconductor elements 40H in the Y direction toward the arm connection portion 80 side.

[0175] In this embodiment, the arrangement of the external connection terminals 90 is not limited to the illustrated example. The P terminal 91P may be connected to the P wiring 54 at both ends in the X direction, for example. The N terminal 91N may be connected to the N wiring 64 at both ends in the X direction, for example. In this case, the N terminal 91N may be connected to the extension 641. Alternatively, the extension 641 may be removed from the N wiring 64 and connected to the base 640. The output terminal 92 may be connected to the relay wiring 55 at both ends in the X direction, for example.

[0176] The configuration described in this embodiment can be combined with any of the configurations described in the first embodiment or its modified form.

[0177] (Third embodiment) This embodiment is a modification based on a prior embodiment, and the description of the prior embodiment can be referenced. In order to effectively dissipate heat from the semiconductor element, as described in this embodiment, the thickness above the semiconductor element and the thickness below it may satisfy a predetermined relationship.

[0178] <Warping at high temperatures> Through diligent investigation, it became clear that even when insulating substrates 51 and 61 made of resin are used, and the coefficient of thermal expansion is brought closer to that of metal bodies 52, 53, 62, and 63 by adding fillers, warping can still occur in the semiconductor device 20, as shown in Figure 39. Figure 39 shows the state of the semiconductor device 20 during operation of the semiconductor element 40, i.e., at high temperatures. The dashed line in the figure is a reference line indicating the direction of warping.

[0179] The configuration shown in Figure 39 is the same as the configuration described in the prior embodiment (see Figure 5). For convenience, the external connection terminal 90 is omitted in Figure 39. In Figure 39, the semiconductor device 20 and the heat exchange section 121 of the cooler 120 are arranged side by side in the predetermined direction, the Z direction. The heat exchange section 121 is arranged on both sides of the semiconductor device 20 in the Z direction, sandwiching the semiconductor device. A heat conductive member 130, such as silicone gel, is placed between each heat exchange section 121 and the semiconductor device 20. The cooler 120 cools the semiconductor device 20 by circulating a refrigerant through the flow path of the heat exchange section 121. As the refrigerant flowing through the flow path, a phase-changing refrigerant such as water or ammonia, or a phase-non-phase-changing refrigerant such as ethylene glycol, can be used. The heat conductive member 130 is sometimes referred to as a thermal interface material (TIM). The heat conductive member 130 follows the opposing surfaces of the heat exchange section 121 and the semiconductor device 20, filling the gap between the opposing surfaces.

[0180] As described above, in the semiconductor element 40, the drain electrode 40D, which is the main electrode on the high-potential side, has a larger electrode area than the source electrode 40S, which is the main electrode on the low-potential side. Furthermore, a conductive spacer 70 is interposed between the source electrode 40S and the substrate 60, whereas there is no conductive spacer 70 between the drain electrode 40D and the substrate 50. In other words, the thermal resistance is smaller in the heat transfer path from the semiconductor element 40 to the substrate 50 than in the heat transfer path from the semiconductor element 40 to the substrate 60. In a semiconductor device 20 with such a configuration, it is necessary to effectively dissipate heat towards the substrate 50.

[0181] As shown in Figure 39, when warping occurs with the substrate 50 side concave and the substrate 60 side convex, the distance between the exposed surface of the substrate 50 (back surface 50b) and the heat exchange section 121 increases, and the intervening heat conductive member 130 becomes thicker. This increases the thermal resistance between the substrate 50 and the heat exchange section 121, making it difficult to transfer (exchange) heat between the semiconductor device 20 and the cooler 120 (heat exchange section 121). The warping state shown in Figure 39 is undesirable for effectively dissipating heat from the semiconductor element 40, that is, for efficiently cooling the semiconductor device 20. Figure 39 shows an example of a double-sided cooling structure in which the cooler 120 (heat exchange section 121) is placed on both sides of the semiconductor device 20. However, a single-sided cooling structure in which the cooler 120 is placed only on the substrate 50 side in the Z direction also has similar problems.

[0182] <Structure of a semiconductor device> Through diligent research, it was discovered that the warping of the semiconductor device 20 can be controlled by the relationship between the thickness of the portion of the semiconductor device 40 closer to the substrate 50 and the thickness of the portion closer to the substrate 60. The semiconductor device 20 of this embodiment has a configuration based on this finding. Figure 40 is a cross-sectional view showing the semiconductor device 20 of this embodiment. Figure 40 shows an ideal state in which the semiconductor device 20 is not warped.

[0183] The semiconductor device 20 of this embodiment has the same configuration as described in the prior embodiment (see Figures 2 to 13). In Figure 40, as in Figure 39, the semiconductor device 20 is shown along with the heat exchange section 121 of the cooler 120 and the heat conductive member 130. In other words, Figure 40 shows a semiconductor module 140 comprising the semiconductor device 20, the cooler 120, and the heat conductive member 130. The semiconductor module 140 has, as an example, a double-sided cooling structure in which the semiconductor device 20 is sandwiched between a pair of heat exchange sections 121. The semiconductor device 20 is arranged side by side with the cooler 120 (heat exchange section 121) in a predetermined direction, the Z direction. The cooler 120 is arranged on both sides of the semiconductor device 20.

[0184] The back metal bodies 53 and 63 are exposed from the encapsulant 30 as the back surfaces 50b and 60b of the substrates 50 and 60. One of the heat exchange sections 121 of the cooler 120 is positioned opposite one surface 30a and the back surface 50b of the encapsulant 30, and the other heat exchange section 121 is positioned opposite the back surfaces 30b and 60b of the encapsulant 30. A heat conductive member 130 is positioned between the opposing surfaces of the semiconductor device 20 and the heat exchange section 121. The heat conductive member 130 is in close contact with the semiconductor device 20 and the heat exchange section 121.

[0185] The semiconductor device 20 is configured such that the thickness T1 on the substrate 50 side of the semiconductor element 40 and the thickness T2 on the substrate 60 side of the semiconductor element 40 satisfy the relationship T1 ≥ T2. The other configurations are the same as those described in the prior embodiment (see Figure 5). Thickness T1 is the total thickness of the bonding material 101, conductive spacer 70, bonding material 102, and substrate 60. Thickness T2 is the total thickness of the bonding material 100 and substrate 50. In order to satisfy the relationship T1 ≥ T2, substrate 50 is thicker than substrate 60. Substrate 50 is thicker than conductive spacer 70. On substrate 50, metal bodies 52 and 53 are thicker than insulating substrate 51. On substrate 60, metal bodies 62 and 63 are thicker than insulating substrate 61. The configurations other than the thickness relationship are the same as those described in the first embodiment.

[0186] <Simulation Results> Figures 41 to 43 show the results of the thermal stress simulation. Figure 41 shows the state of the semiconductor device 20 shown in Figure 40 at room temperature (RT). Figure 42 shows the state of the semiconductor device 20 shown in Figure 40 at high temperature. High temperature refers to the time when the semiconductor element 40 is generating heat due to the application of current, that is, when the semiconductor element 40 is operating. As shown in Figures 41 and 42, warping occurs in the semiconductor device 20 at high temperature. In this embodiment, as described above, the relationship T1 ≥ T2 is satisfied, so as shown by the dashed arrow in Figure 42, the amount of expansion on the substrate 50 side is greater than the amount of expansion on the substrate 60 side. This is because the linear expansion coefficient of Cu constituting the metal bodies 52, 53, 62, and 63 is the largest, and the substrate 50 is the thickest. As a result, a convex warp occurs on the first substrate 50 side and a concave warp occurs on the second substrate 60 side. The dashed line in Figure 42 is a reference line indicating the direction of the warp.

[0187] Figure 43 shows the relationship between the ratio of thicknesses T1 and T2 and the amount of warping at high temperatures. In this simulation, the semiconductor element 40, conductive spacer 70, and bonding materials 100, 101, and 102 were kept identical (common), and the thicknesses of substrates 50 and 60 were adjusted so that the thickness ratio T1:T2 was a predetermined value. The material composition was kept identical (common). The vertical axis in Figure 43 shows the amount of warping, in arbitrary units (au). A warping amount above 0 (zero) indicates convexity towards substrate 50 and concaveness towards substrate 60, while a warping amount below 0 (zero) indicates concaveness towards substrate 50 and convexity towards substrate 60. T1:T2 was set to four levels: 1:2, 1:1.3, 1:1, and 1.5:1.

[0188] As shown in FIG. 43, when T1:T2 = 1:2, a warp with a concave on the substrate 50 side and a convex on the substrate 60 side occurred, and the amount of convex warp on the substrate 60 side was the largest among the four levels. When T1:T2 = 1:1.3, a warp with a concave on the substrate 50 side and a convex on the substrate 60 side occurred, and the amount of convex warp on the substrate 60 side became smaller than that when T1:T2 = 1:2. When T1:T2 = 1:1, it changed to a warp with a convex on the substrate 50 side and a concave on the substrate 60 side. When T1:T2 = 1.5:1, a warp with a convex on the substrate 50 side and a concave on the substrate 60 side occurred, and the amount of convex warp on the substrate 50 side was the largest among the four levels.

[0189] Thus, it became clear that when T1 < T2, a warp with a concave on the substrate 50 side and a convex on the substrate 60 side occurred, and when T1 ≥ T2, a warp with a convex on the substrate 50 side and a concave on the substrate 60 side occurred. That is, it became clear that by satisfying the relationship of T1 ≥ T2, the warp generated at high temperature can be controlled to be a warp with a convex on the substrate 50 side and a concave on the substrate 60 side. Also, it became clear that the larger T2 is with respect to T1, the larger the amount of convex warp on the substrate 60 side becomes, and the larger T1 is with respect to T2, the larger the amount of convex warp on the substrate 50 side becomes.

[0190] <Summary of the Third Embodiment> In this embodiment, the semiconductor device 20 satisfies the relationship of the above-mentioned thickness T1 ≥ thickness T2. The thickness T1 on the side where the conductive spacer 70 is not provided between the semiconductor element 40 and the substrate 50 is equal to or greater than the thickness T2 on the side where the conductive spacer 70 is provided between the semiconductor element 40 and the substrate 60. As a result, when the semiconductor element 40 operates (at high temperature), a warp with a convex on the substrate 50 side and a concave on the substrate 60 side occurs in the semiconductor device 20. Therefore, the facing distance between the semiconductor device 20 and the cooler 120 (heat exchange part 121) on the substrate 50 side, which has a high contribution rate to heat dissipation, can be made narrower compared to a configuration that satisfies the relationship of thickness T1 < thickness T2. Since the facing distance becomes narrower, the thermal resistance between the semiconductor device 20 and the cooler 120 becomes smaller. As a result, the heat generated by the semiconductor element 40 can be efficiently released to the outside of the semiconductor device 20. In other words, the cooling efficiency of the semiconductor device 20 can be increased.

[0191] Specifically, the thickness of the heat conduction member 130 interposed between the semiconductor device 20 and the cooler 120 becomes thinner compared to a configuration satisfying the relationship of thickness T1 < thickness T2. As a result, the thermal resistance between the semiconductor device 20 and the cooler 120 becomes smaller, and heat exchange between the semiconductor device 20 and the cooler 120 becomes easier. Therefore, the heat generated by the semiconductor element 40 can be efficiently released to the outside of the semiconductor device 20.

[0192] In the present embodiment, the back surface metal body 53 is exposed from the sealing body 30. The heat dissipation can be enhanced compared to a configuration in which the back surface metal body 53 is covered by the sealing body 30. Similarly, the back surface metal body 63 is exposed from the sealing body 30. The heat dissipation can be enhanced compared to a configuration in which the back surface metal body 63 is covered by the sealing body 30.

[0193] <Modification example> Although an example of a double-sided heat dissipation structure has been shown, the present invention is not limited to this. The semiconductor device 20 mainly wants to efficiently release heat from the substrate 50 side. Therefore, the cooler 120 (heat exchange unit 121) may be arranged only on the substrate 50 side in the Z direction with respect to the semiconductor device 20. Even in such a single-sided heat dissipation structure, by satisfying the relationship of T1≧T2, a convex warp occurs on the substrate 50 side at high temperatures. As a result, the thermal resistance between the semiconductor device 20 and the cooler 120 becomes smaller. Therefore, the heat generated by the semiconductor element 40 can be efficiently released.

[0194] Although an example in which both the back surface metal bodies 53 and 63 are exposed from the sealing body 30 has been shown, the present invention is not limited to this. For example, only the back surface metal body 53 may be exposed.

[0195] Although an example in which the semiconductor device 20 includes the semiconductor element 40H that constitutes the upper arm 9H and the semiconductor element 40 that constitutes the lower arm 9L has been shown, the present invention is not limited to this. The semiconductor device 20 may include only the semiconductor element 40 that constitutes one of the arms. The semiconductor device 20 may include, for example, only one semiconductor element 40. The semiconductor device 20 may include the semiconductor element 40, a pair of substrates 50 and 60 arranged so as to sandwich the semiconductor element 40, and a conductive spacer 70 interposed between the semiconductor element 40 and the substrate 60.

[0196] In the substrate 50, the relationship between the thicknesses of the metal bodies 52 and 53 was not specifically mentioned. For example, as shown in Figure 44, the surface metal body 52 may be thicker than the back metal body 53. The drain electrode 40D, which is the first main electrode of the semiconductor element 40, is bonded to the surface metal body 52. ​​The thermal resistance between the surface metal body 52 and the semiconductor element 40 is small. By making the surface metal body 52 closer to the semiconductor element 40 thicker, the heat generated by the semiconductor element 40 can be effectively dissipated. In other words, the heat from the semiconductor element 40 can be efficiently dissipated. Figure 44 is a cross-sectional view showing a modified example. Figure 44 corresponds to Figure 41.

[0197] As shown in Figure 44, the surface metal body 62 may be thicker than the back metal body 63. By making the surface metal body 62, which is closer to the semiconductor element 40, thicker, the heat generated by the semiconductor element 40 can be effectively dissipated.

[0198] As described above, the heat from the semiconductor element 40, which has main electrodes on both sides, is mainly transferred to the substrate 50 side, which has lower thermal resistance. For this reason, as shown in Figure 45, the surface metal body 62 may be thinner than the back metal body 63. This makes it possible to reduce the thickness of the substrate 60 and, consequently, to miniaturize the semiconductor device 20. Since a thick metal body is not required, costs can also be reduced. Figure 45 is a cross-sectional view showing a modified example. Figure 45 corresponds to Figure 44. In Figure 45, the surface metal body 52 is thicker than the back metal body 53, and the surface metal body 62 is thinner than the back metal body 63. Therefore, it is possible to efficiently dissipate the heat from the semiconductor element 40 while miniaturizing the device and reducing costs.

[0199] The configuration described in this embodiment can be combined with any of the configurations described in the first embodiment, the second embodiment, and the modified form.

[0200] (Fourth Embodiment) This embodiment is a modification based on a prior embodiment, and the description of the prior embodiment can be referenced. To improve connection reliability, the substrate and the signal terminals may be arranged to satisfy a predetermined positional relationship, as described in this embodiment.

[0201] <Semiconductor device> First, the semiconductor device 20 of this embodiment will be described based on Figures 46 and 47. Figure 46 shows the area around the signal terminal 93 in the semiconductor device 20 according to this embodiment. In Figure 46, some elements of the semiconductor device 20 are omitted to show the positional relationship between the substrate 50 and the signal terminal 93. Figure 47 is a cross-sectional view along the line XLVII-XLVII in Figure 46. In Figures 46 and 47, the signal terminal 93L on the lower arm 9L side will be described as an example.

[0202] The semiconductor device 20 of this embodiment has the same configuration as the configuration described in the prior embodiment (see Figures 2 to 13). As shown in Figure 46, the semiconductor device 20 comprises two semiconductor elements 40L. Each semiconductor element 40L has a drain electrode 40D, which is the first main electrode, on one side, and a source electrode 40S, which is the second main electrode, and a signal pad 40P on the back side. The semiconductor device 20 comprises four signal terminals 93L. Each signal terminal 93L extends in the Y direction and protrudes to the outside from the side surface 30d of the encapsulant 30. The four signal terminals 93L are arranged in the X direction between the output terminals 92 in a plan view in the Z direction.

[0203] <Shape and arrangement of signal terminals> Next, the shape and arrangement of the signal terminal 93 will be described based on Figures 46 and 47.

[0204] As shown in Figure 46, each signal terminal 93L has an overlapping portion 930 that overlaps the substrate 50 in a plan view, and a non-overlapping portion 931 that does not overlap the substrate 50. The overlapping portion 930 faces the substrate 50 in the Z direction.

[0205] The overlapping portion 930 is a predetermined range from the end of the signal terminal 93L on the semiconductor element 40L side. The non-overlapping portion 931 is the portion excluding the overlapping portion 930. The overlapping portion 930 overlaps the insulating substrate 51 of the substrate 50 to which the drain electrode 40D is electrically connected. The entire area of ​​the overlapping portion 930 overlaps the insulating substrate 51. The overlapping portion 930 overlaps the exposed portion 510 of the insulating substrate 51 that is exposed from the surface metal body 52. ​​In this way, the signal terminal 93L extends onto the substrate 50. That is, the signal terminal 93L is inserted and positioned to overlap the substrate 50 in a plan view.

[0206] Of the four signal terminals 93L, two have an overlapping portion 930 which has a main portion 930a and a protruding portion 930b. The other two signal terminals 93L do not have a protruding portion 930b. The main portion 930a extends in the Y direction, which is the main extension direction of the signal terminal 93L. The protruding portion 930b is connected to the main portion 930a and protrudes from the main portion 930a. The protruding portion 930b extends in a direction different from the main portion 930a. The protruding portion 930b is sometimes called a branch portion. The planar shape of the main portion 930a can be a variety of shapes, such as a roughly L-shape, a roughly Y-shape, or a roughly T-shape. In the example shown in Figure 46, one of the signal terminals 93L has a roughly L-shape in planar form, and the other signal terminal 93L has a roughly T-shape in planar form.

[0207] As described in the prior embodiment (see Figure 11), the relay wiring 55 of the surface metal body 52 has a notch 550. The overlapping portion 930 of the signal terminals 93L overlaps the portion of the insulating substrate 51 that is exposed from the notch 550. The four signal terminals 93L are arranged in the X direction between the output terminals 92 in a plan view. Each signal terminal 93L has a tie bar mark 93a. The tie bar mark 93a is a mark left on the side of the signal terminal 93L when the tie bar 94a of the lead frame 94 is cut off, as described in the prior embodiment (see Figure 10). The tie bar mark 93a is sometimes referred to as a cutting mark. Each signal terminal 93L has tie bar marks 93a on both sides in the X direction. The tie bar marks 93a are provided at the non-overlapping portion 931, outside the sealing body 30.

[0208] Each signal terminal 93L has a joint portion 93b, a tip portion 93c, a bent portion 93d, and an extended portion 93e, as shown in Figure 47. The joint portion 93b is the portion to which the bonding wire 110, which is a connecting member, is joined. Preferably, the joint portion 93b includes a portion substantially parallel to the XY plane. The joint portion 93b is the portion of the signal terminal 93L closest to the surface of the insulating substrate 51 (exposed portion 510). In this embodiment, the joint portion 93b is floating relative to the surface of the insulating substrate 51. The joint portion 93b does not contact the insulating substrate 51, and the sealant 30 fills the gap between the lower surface of the joint portion 93b and the surface of the insulating substrate 51. The bonding wire 110 electrically connects the pad 40P, which is formed on the same plane as the source electrode 40S, to the signal terminal 93L.

[0209] The tip portion 93c is the part on the tip side of the joint portion 93b, that is, the part on the semiconductor element 40 (40L) side. The tip portion 93c is positioned above the joint portion 93b, that is, away from the surface of the insulating substrate 51 in the Z direction. The tip portion 93c rises upward as it moves away from the joint portion 93b. The tip portion 93c has an R shape in the ZY cross section. The bent portion 93d is provided between the joint portion 93b and the extended portion 93e, which is the part on the rear end side of the joint portion 93b. The bent portion 93d bends the extended portion 93e so that it is positioned above the joint portion 93b, that is, away from the surface of the insulating substrate 51. Due to the bending process, the bent portion 93d has a smaller cross-sectional area than the other parts of the signal terminal 93, specifically the joint portion 93b, the tip portion 93c, and the extended portion 93e. In other words, it is thin. The extended portion 93e is the part on the rear end side of the joint portion 93b. The extension portion 93e extends in the Y direction and is positioned both inside and outside the sealing body 30.

[0210] At least a portion of the joint portion 93b, the tip portion 93c, and the bent portion 93d is included in the overlapping portion 930 described above. At least a portion of the extension portion 93e is included in the non-overlapping portion 931. In this embodiment, the entire area of ​​the extension portion 93e is included in the non-overlapping portion 931. Each signal terminal 93L is formed by press punching. In the signal terminal 93L, the surface facing the insulating substrate 51 is a press R surface 93f, and the back surface of the facing surface is a burr surface 93g where burrs are generated by punching. The configuration other than that described above is the same as the configuration described in the first embodiment.

[0211] <Method for connecting bonding wires> Next, the method of connecting the signal terminal 93 of the above-described structure to the bonding wire 110 will be explained based on Figure 48. Figure 48 is a diagram illustrating wire bonding. Reference numeral 111 in Figure 48 indicates a jig that holds the signal terminal 93L. Reference numeral 112 indicates a tool for ultrasonic bonding. Tool 112 is sometimes referred to as an ultrasonic bonding device. The dashed line in Figure 48 indicates the position of the signal terminal 93L that is bent by being pressed by the jig 111.

[0212] As shown in Figure 48, first, the signal terminal 93L is positioned so that its overlapping portion 930 overlaps the insulating substrate 51, and then set in the area where the wire 110a will be joined. Then, the jig 111 is applied in the Z direction to elastically deform the signal terminal 93L, causing the overlapping portion 930 to come into contact with the surface of the insulating substrate 51. The jig 111 holds down the overlapping portion 930 of the signal terminal 93L or its vicinity.

[0213] Then, with the signal terminal 93L in contact with the insulating substrate 51, ultrasonic bonding is performed using the tool 112. Since the insulating substrate 51 supports the signal terminal 93L, it is not necessary to prepare a separate support jig. When the ultrasonic bonding is completed and the tool 112 and jig 111 are removed from the signal terminal 93L, it is released from its elastically deformed state and returns to its position before pressurization. The signal terminal 93L is part of the lead frame 94. Since the signal terminal 93L is supported on the outer frame 94b by the tie bar 94a, it returns to its original position when the pressurizing force is released.

[0214] In the above description, the signal terminal 93L has been described as an example. However, the above configuration may also be applied to the signal terminal 93H on the upper arm 9H side. The signal terminals 93H and 93L may both have the above configuration. In the configuration described in the previous embodiment (see FIG. 11), each of the signal terminals 93H and 93L overlaps with the exposed portion of the insulating base material 51. The P wiring 54 of the surface metal body 52 has a notch 540, and the signal terminal 93H overlaps with the surface of the insulating base material 51 exposed from the notch 540.

[0215] <Summary of the Fourth Embodiment> In this embodiment, the signal terminal 93 (93L) overlaps with the exposed portion 510 of the insulating base material 51. However, the signal terminal 93 is non-joint with respect to the exposed portion 510. That is, the signal terminal 93 is not fixed to the insulating base material 51 and thus to the substrate 50. Thereby, the signal terminal 93 can absorb dimensional variations within the tolerances of the respective elements constituting the semiconductor device 20, assembly variations when assembling the respective elements, and the like. Therefore, when the sealing body 30 is molded, it is possible to suppress stress from concentrating on the electrical connection portion (joint portion) between the signal terminal 93 and the semiconductor element 40. As a result, a semiconductor device 20 with high connection reliability can be provided.

[0216] In this embodiment, the signal terminal 93 is inserted and arranged up to a position overlapping the substrate 50, that is, onto the substrate 5 down. By adopting such an arrangement, the signal terminal 93 approaches the pad 40P of the semiconductor element 40 (40L) in the Y direction. Therefore, compared with the configuration in which the signal terminal 93 is arranged only at a position not overlapping the substrate 50, the length of the bonding wire 110, which is a connection member, can be shortened. Since the length of the bonding wire 110 can be shortened, it is possible to suppress the occurrence of wire flow, short circuits due to wire flow, disconnection of the wire, etc. when the sealing body 30 is molded by the transfer molding method or the like.

[0217] In this embodiment, the overlapping portion 930 of the signal terminal 93 is floating relative to the surface of the exposed portion 510 of the insulating substrate 51. The sealing body 30 is interposed between the lower surface of the overlapping portion 930 and the surface of the exposed portion 510. The sealing body 30 is also interposed between the joint portion 93b and the exposed portion 510. This allows for the absorption of variations even if there are large manufacturing variations in the plate thickness direction. Furthermore, since the signal terminal 93 is located above the insulating substrate 51, it becomes easier to secure an insulating distance from the back metal body 53.

[0218] In this embodiment, the surface metal body 52 has a notch 550 (540). The notch 550 opens at the end in the Y direction, which is one direction perpendicular to the Z direction. The overlapping portion 930 of the signal terminal 93 overlaps the surface of the exposed portion 510 that is exposed from the notch 550. By providing the notch 550 in the surface metal body 52 of the substrate 50 in this way, it is possible to ensure an insulating distance between the surface metal body 52 and the signal terminal 93 while suppressing an increase in the size of the substrate 50.

[0219] In this embodiment, the non-overlapping portion 931 of the signal terminal 93 has a tie bar mark 93a. As described above, the signal terminal 93L is part of the lead frame 94 and is supported by the tie bar 94a on the outer frame 94b. Therefore, by applying pressure, the signal terminal 93 is bent and brought into contact with the exposed portion 510 of the insulating substrate 51, and the bonding wire 110 can be joined by ultrasonic bonding in this contact state. Then, by releasing the pressure after bonding is complete, it returns to its original position.

[0220] In this embodiment, the signal terminal 93 has a bent portion 93d between the joint portion 93b and the extended portion 93e. Due to the bent portion 93d, the extended portion 93e is positioned further away from the exposed portion 510 (insulating substrate 51) than the joint portion 93b in the Z direction. By having the bent portion 93d in this way, it is possible to ensure an insulating distance between the signal terminal 93 and the back metal body 53 while suppressing an increase in size in the Z direction.

[0221] In this embodiment, the signal terminal 93 has a tip portion 93c. The tip portion 93c is further away from the exposed portion 510 (insulating substrate 51) in the Z direction than the joint portion 93b. This prevents the tip of the signal terminal 93 from damaging the insulating substrate 51 during bonding (such as ultrasonic bonding). In other words, it prevents a decrease in insulation performance. In particular, in this embodiment, the tip portion 93c is raised upward as it moves away from the joint portion 93b, making it difficult for the tip portion 93c to come into contact with the insulating substrate 51. Furthermore, since the tip portion 93c has an R shape in the ZY cross-section, even if contact occurs, it is possible to prevent damage to the insulating substrate 51.

[0222] If the opposing surface is a burred surface 93g, the insulating substrate 51 may be damaged, potentially reducing its insulating performance. In this embodiment, the signal terminal 93 is configured such that the side facing the exposed portion 510 is a pressed R surface 93f, and the back side of the opposing surface is a burred surface 93g. This makes it possible to suppress a decrease in the insulating performance of the insulating substrate 51.

[0223] <Variation> The non-connected configuration of the signal terminal 93 and the exposed portion 510 is not limited to the example described above. For example, in Figure 49, the overlapping portion 930 of the signal terminal 93 floats on the insulating substrate 51 with a small gap of just enough height between it and the surface of the exposed portion 510 so that the sealant does not get in between. The sealant 30 has an air gap 31 between the lower surface of the overlapping portion 930 and the surface of the exposed portion 510. The signal terminal 93 is not fixed to the insulating substrate 51 (exposed portion 510). Therefore, it can achieve the same effect as the configuration shown in Figure 47. Figure 49 is a cross-sectional view showing a modified example and corresponds to Figure 47.

[0224] In Figure 50, the overlapping portion 930 of the signal terminal 93 is in contact with the surface of the exposed portion 510. Although the signal terminal 93 is in contact with the insulating substrate 51 (exposed portion 510), it is not fixed. Therefore, it can achieve the same effect as the configuration shown in Figure 47. Figure 50 is a cross-sectional view showing a modified example and corresponds to Figure 47. In addition, a portion of the lower surface of the joint portion 93b may be in contact with the insulating substrate 51, while another portion may not be in contact.

[0225] In the example shown in Figure 47, the substrate 60 was positioned so as not to overlap with the signal terminals 93 in a plan view. In other words, the substrate 60 was not positioned above the signal terminals 93. Adopting such a positioning allows for a smaller substrate 60. It also makes it easier to ensure sufficient insulation distance between the surface metal body 62 and the signal terminals 93. However, the positional relationship between the signal terminals 93 and the substrate 60 is not limited to the example shown in Figure 47. For example, as shown in Figure 51, the overlapping portion 930 of the signal terminals 93 also overlaps with the substrate 60. In a plan view, the surface metal body 62 of the substrate 60 overlaps with the overlapping portion 930 and the exposed portion 510 of the insulating substrate 51. This improves heat dissipation. Figure 51 is a cross-sectional view showing a modified example and corresponds to Figure 47.

[0226] In Figure 52, the surface metal body 62 is patterned so as not to overlap with the overlapping portion 930 of the signal terminal 93, compared to Figure 51. The insulating substrate 61 and the back metal body 63 are located above the overlapping portion 930. This makes it easier to secure the insulation distance between the surface metal body 62 and the signal terminal 93 by making the surface metal body 62 smaller. The larger back metal body 63 improves heat dissipation. Figure 52 is a cross-sectional view showing a modified example and corresponds to Figure 47.

[0227] This example shows how the length of the bonding wire 110 (connecting member) can be shortened by inserting the signal terminal 93 onto the substrate 50. Alternatively, the length of the bonding wire 110 can be shortened by using the intermediate substrate 150 shown in Figures 53 to 55. Figure 53 is a plan view showing a modified example and corresponds to Figure 46. In Figure 53, some elements of the semiconductor device 20 are omitted to show the positional relationship between the substrate 50, the signal terminal 93, and the intermediate substrate 150. Figure 54 is a cross-sectional view showing the intermediate substrate. Figure 55 is a cross-sectional view along the LV-LV line in Figure 53. Here, as an example, the intermediate wiring 55 and signal terminal 93L are shown, but a similar configuration can be adopted for the P wiring 54 and signal terminal 93H.

[0228] The semiconductor device 20 further comprises a relay substrate 150. As shown in Figures 53 and 55, the relay substrate 150 is arranged on the surface metal body 52 (relay wiring 55) of the substrate 50. As shown in Figure 54, the relay substrate 150 has an insulating substrate 151 and a conductor portion 152 arranged on the insulating substrate 151. A portion of the conductor portion 152 provides a wiring function. The relay substrate 150 is sometimes referred to as a printed circuit board or a wiring board.

[0229] The conductor portion 152 has lands 152a and 152b. Lands 152a and 152b are exposed on one surface of the relay substrate 150. Specifically, they are exposed from the solder resist 153 provided on one surface 151a of the insulating substrate 151. Land 152a is electrically connected to the pad 40P via bonding wire 110. The signal terminal 93 overlaps with the substrate 50 in a plan view. The signal terminal 93 is connected to land 152b.

[0230] The conductor portion 152 has wiring 152c and via conductor 152d in addition to lands 152a and 152b. At least a portion of the wiring 152c is an inner layer wiring located inside the insulating substrate 151. Lands 152a and 152b are electrically connected via wiring 152c and via conductor 152d. The multiple lands 152a include two lands 152a individually connected to the gate electrode pads 40P of two semiconductor elements 40. The two gate electrode lands 152a are electrically connected to one gate electrode land 152b via wiring 152c and via conductor 152d.

[0231] In this way, using the intermediate substrate 150 allows the connection target (land 152a) of the bonding wire 110 to be brought closer to the pad 40P. This makes it possible to shorten the length of the bonding wire 110 that electrically connects the pad 40P and the signal terminal 93. In addition, the wiring 152c can be freely routed within the intermediate substrate 150. This makes it possible to avoid the bonding wires 110 crossing each other in a configuration in which semiconductor elements 40 are connected in parallel. Therefore, it is possible to suppress contact between wires when molding the encapsulant 30. Furthermore, by using fine wiring technology for printed circuit boards, it is possible to achieve a size reduction to the same extent as the configuration shown in Figure 47.

[0232] The conductor portion 152 further has fixing lands 152e. The fixing lands 152e are lands for fixing the intermediate substrate 150 to the substrate 50. The fixing lands 152e do not provide an electrical connection function, i.e., a wiring function. The fixing lands 152e are located on the back surface 151b of the insulating substrate 151. The fixing lands 152e (intermediate substrate 150) are bonded to the surface metal body 52 via a bonding material 154. For example, solder can be used as the bonding material 154.

[0233] In this way, the intermediate substrate 150 is fixed to the surface metal body 52, allowing for stable wire bonding. Solder containing Ni balls may be used as the bonding material 154. In this case, the thickness of the bonding material 154 can be controlled by the Ni balls. Furthermore, tilting of the intermediate substrate 150 can be suppressed.

[0234] The wiring function provided by the conductor portion 152 is electrically isolated from the surface metal body 52 by the insulating substrate 151. For example, the insulating substrate 151 may have a non-placement region 151c in the Z direction where the conductor portion 152 is not placed, and a placement region 151d where the conductor portion 152 is placed. In the Z direction, the non-placement region 151c is located in the center of the insulating substrate 151, and the placement region 151d is located on the surface layer on both sides. The non-placement region 151c is sometimes referred to as the core layer. In this way, by having a non-placement region 151c in the insulating substrate 151, the conductor portion 152 that provides the wiring function, which is located on one side 151a, can be electrically isolated from the fixing land 152e and, consequently, from the surface metal body 52.

[0235] The solder resist 153 has low adhesion to the sealant 30. Furthermore, delamination of the sealant 30 due to thermal stress progresses starting from the outer edge of the intermediate substrate 150. For example, the insulating substrate 151 may have an exposed portion 151e that is exposed from the solder resist 153. The exposed portion 151e is provided on the outer edge of one surface 151a of the insulating substrate 151. The insulating substrate 151 has higher adhesion to the sealant 30 compared to the solder resist 153. At the exposed portion 151e, the sealant 30 is in close contact with the intermediate substrate 150. This makes it possible to suppress delamination of the sealant 30 from the intermediate substrate 150. Because the sealant 30 is in close contact with the outer edge, the conductive portions 152 such as lands 152a and 152b that are exposed from the solder resist 153 can be protected.

[0236] As shown in Figure 55, the signal terminal 93 (93L) has a first extension 93h, a second extension 93i, and a bent portion 93j. The first extension 93h and the second extension 93i extend in the Y direction. The first extension 93h is located inside the sealing body 30. The second extension 93i is located both inside and outside the sealing body 30. The bent portion 93j is provided between the first extension 93h and the second extension 93i. The first extension 93h is the part closer to the tip than the bent portion 93j, and the second extension 93i is the part closer to the rear end than the bent portion 93j.

[0237] The signal terminal 93 may have a projection 93k. The projection 93k is provided near the tip of the signal terminal 93. The projection 93k protrudes from the first extension 93h in the Z direction toward the land 152b. The projection 93k is joined to the land 152b. In the signal terminal 93, the tip of the first extension 93h and the projection 93k overlap with the land 152b in a plan view in the Z direction. The portion where the tip of the first extension 93h and the projection 93k are connected is a thick-walled portion, while the other parts of the signal terminal 93 are thin-walled portions. By providing the projection 93k in this way, the signal terminal 93 (first extension 93h) is moved away from the surface metal body 52, making it easier to secure an insulation distance between it and the surface metal body 52.

[0238] Figure 56 shows a different example from Figure 54. Figure 56 corresponds to Figure 54. In Figure 56, the relay board 150 is fixed to the exposed portion 510 of the insulating substrate 51. In this case, the thickness of the bonding material 154 and the relay board 150 ensures an insulating distance between the signal terminal 93 and the back metal body 53. Using the above-mentioned Ni ball-containing solder as the bonding material 154 makes it easier to ensure the insulating distance because the required thickness can be secured. In addition, the tilt of the relay board 150 can be suppressed.

[0239] The surface metal body 52 (relay wiring 55) has a notch 550, as shown in Figure 46, for example, to expose the insulating substrate 51. For example, the surface metal body 52 may have a chamfered portion 554. The chamfered portion 554 is provided at least on the end face that defines the notch 550, on the face where a hypothetical straight line connecting the semiconductor element 40 and the relay substrate 150 intersects. The chamfered portion 554 is provided at the upper end of the end face. This ensures an insulating distance between the bonding wire 110 and the surface metal body 52.

[0240] An example was shown in which the semiconductor device 20 includes a substrate 60 electrically connected to the source electrode 40S. In other words, an example of a semiconductor device 20 with a double-sided heat dissipation structure comprising a pair of substrates 50 and 60 was shown. However, the example is not limited to this. It can also be applied to a semiconductor device 20 with a single-sided heat dissipation structure comprising only the substrate 50 to which the drain electrode 40D (first main electrode) is connected. An example was shown in which both the back metal bodies 53 and 63 are exposed from the sealant 30, but the example is not limited to this.

[0241] The semiconductor device 20 is shown as comprising semiconductor elements 40H that constitute the upper arm 9H and semiconductor elements 40 that constitute the lower arm 9L, but it is not limited to this. It may also comprise only one semiconductor element 40 that constitutes one of the arms. The semiconductor device 20 may comprise, for example, only one semiconductor element 40.

[0242] The configuration described in this embodiment can be combined with any of the configurations described in the first embodiment, the second embodiment, the third embodiment, and the modified form.

[0243] (Fifth embodiment) This embodiment is a modification based on a prior embodiment, and the description of the prior embodiment can be applied. In order to achieve both insulation reliability and miniaturization, the connection between the metal member and the surface metal body via a bonding material may be made of a predetermined structure, as described in this embodiment.

[0244] <Semiconductor device> First, the semiconductor device 20 of this embodiment will be described based on Figure 57. Figure 57 corresponds to Figure 5.

[0245] The semiconductor device 20 of this embodiment has the same configuration as the configuration described in the prior embodiment (see Figures 2 to 13). As shown in Figure 57, the semiconductor device 20 comprises semiconductor elements 40 (40H, 40L), substrates 50 and 60 arranged to sandwich the semiconductor elements 40 in the Z direction, and a sealant 30. The surface metal body 52 of substrate 50 is connected to the drain electrode 40D, which is the main electrode of the semiconductor element 40. The surface metal body 52 is connected to the main terminals, P terminal 91P and output terminal 92, via a bonding material 104. The surface metal body 62 of substrate 60 is electrically connected to the source electrode 40S, which is the main electrode of the semiconductor element 40. The surface metal body 62 is connected to the main terminal, N terminal 91N (not shown), via a bonding material 104. The sealant 30 seals the semiconductor elements 40, substrates 50 and 60, a part of each of the main terminals, and the bonding material 104.

[0246] <Main terminal connection structure> Next, the connection structure of the main terminal will be described based on Figures 57 to 60. Figure 58 is a plan view of the area around the output terminal 92 in Figure 57, viewed from the LVIII direction. In Figure 58, some hatching has been added for clarity. Figure 59 is an enlarged view of the LVIX region shown by the dashed line in Figure 57. Figure 60 is a view of Figure 59 with the connection material 104 removed. In Figures 59 and 60, the sealant 30 is omitted for convenience.

[0247] As shown in Figure 57, the bonding structure of the main terminal P terminal 91P and the output terminal 92 to the substrate 50 is different from the configuration described in the prior embodiment (see Figure 5). Although not shown, the bonding structure of the main terminal N terminal 91N is also different. The other configurations are the same as those described in the prior embodiment. Below, the output terminal 92 will be used as an example. The bonding material 104 wets and spreads across the metal surface during bonding. As an example, the bonding material 104 is solder.

[0248] As shown in Figure 57, the substrate 50 has ends 50c and 50d in the Y direction. End 50c is the end on the side 30c side of the sealant 30, and end 50d is the end on the side 30d side. The output terminal 92 extends in the Y direction, straddling the end 50d of the substrate 50. In a plan view in the Z direction, a portion of the output terminal 92 overlaps with the surface metal body 52 (relay wiring 55), while another portion does not overlap. As shown in Figures 58 to 60, the output terminal 92 has an opposing surface 920 and a housing portion 921.

[0249] The opposing surface 920 is the portion of the lower surface of the output terminal 92 that faces the surface metal body 52 (relay wiring 55) of the substrate 50 in the Z direction. Macroscopically, the opposing surface 920 is a flat surface and ideally contacts the upper surface 52a of the surface metal body 52 over its entire surface. Microscopically, the opposing surface 920 has minute irregularities on its surface, and at least a portion of it contacts the upper surface 52a. The opposing surface 920 is sometimes referred to as the metal-touch surface. In a plan view, the opposing surface 920 is a predetermined range in the Y direction from the position where it overlaps with the end portion 52b of the surface metal body 52. ​​The end portion 52b is the end face (side surface) on the side surface 30d side of the sealant 30 in the Y direction and is connected to the upper surface 52a. The end portion 52b forms a part of the end portion 50d. The opposing surface 920 has a roughly rectangular shape in plan.

[0250] The housing portion 921 is provided adjacent to the opposing surface 920 and provides a space for housing the joining material 104. For example, the housing portion 921 is a recess that is recessed in the direction away from the upper surface 52a relative to the opposing surface 920. The housing portion 921, being a recess, is a surface that includes a component in the Z direction and has a side surface 921a connected to the opposing surface 920 and a bottom surface 921b connected to the side surface 921a. The side surface 921a is, for example, a surface substantially parallel to the Z direction. The housing portion 921 opens to the tip surface 922, which is the side surface on the prior art side of the output terminal 92, in the Y direction. The housing portion 921 opens to the side surfaces 923 and 924 on both sides of the output terminal 92, in the X direction. The housing portion 921 is provided within a predetermined range from the tip surface 922 of the output terminal 92, in the Y direction. The housing portion 921 has a substantially rectangular shape in plan. The housing portion 921 is provided in the Y direction alongside the X direction.

[0251] The output terminal 92 has its opposing surface 920 in contact with the surface metal body 52, and the bonding material 104 is housed within the housing portion 921. The bonding material 104 may be placed only within the housing portion 921, or, as shown in Figure 59, a part of the bonding material 104 may be placed outside the housing portion 921. In Figure 59, the bonding material 104 forms a fillet with respect to the tip surface 922. The output terminal 92 is connected (bonded) to the surface metal body 52 via the bonding material 104 located in the housing portion 921.

[0252] <Method of connecting the main terminals> The bonding structure between the output terminal 92 and the surface metal body 52 is formed, for example, as follows: With the bonding material 104 (solder) placed in the housing portion 921, the upper portion of the opposing surface 920 of the output terminal 92 is pressed in the Z direction toward the substrate 50 so that the opposing surface 920 makes strong contact with the upper surface 52a. Reflow is performed with the opposing surface 920 in strong contact with the upper surface 52a. Therefore, during reflow, the bonding material 104 does not wet and spread toward the opposing surface 920, or if it does wet and spread, it only fills into the depressions of the minute irregularities on the surface of the opposing surface 920.

[0253] <Summary of the Fifth Embodiment> In this embodiment, the opposing surface 920 of the output terminal 92, which is a metal component, contacts (metal-to-metal contact) the upper surface 52a of the surface metal body 52. ​​This suppresses the overflow of the bonding material 104 from the housing portion 921 to the opposing surface 920. This suppresses the wetting and spreading of the bonding material 104 in unintended directions, thereby ensuring insulation reliability. Furthermore, the output terminal 92, which is a single component, has both a housing portion 921 and an opposing surface 920. As a result, a semiconductor device 20 that can achieve both insulation reliability and miniaturization can be provided.

[0254] In a configuration with a substrate 50, when the bonding material 104 wets and spreads over the end 52b (end face) of the surface metal body 52, and consequently over the insulating substrate 51, the portion at the same potential as the surface metal body 52 expands, bringing it closer to the back metal body 53. The bonding material 104 may come into contact with the back metal body 53. In this embodiment, the opposing surface 920 is positioned closer to the end 50d of the substrate 50, that is, closer to the end 52b of the surface metal body 52, than to the housing portion 921. By positioning the opposing surface 920 on the end 52b side, it is possible to suppress the bonding material 104 from wetting and spreading over the surface of the output terminal 92 and / or the surface metal body 52, and reaching the end 52b, and consequently the insulating substrate 51. This makes it possible to improve insulation reliability without increasing the size.

[0255] As described above, the metal member having an opposing surface and a housing can also be applied to other main terminals, namely the P terminal 91P and the N terminal 91N. The P terminal 91P is connected to the surface metal body 52 (P wiring 54) of the substrate 50 via the bonding material 104. By the opposing surface of the P terminal 91P contacting the surface metal body 52, overflow of the bonding material 104 from the housing of the P terminal 91P to the opposing surface can be suppressed. As shown in Figure 57, by providing the opposing surface on the end 50c side of the substrate 50, it is possible to suppress the bonding material 104 from wetting and spreading onto the end of the surface metal body 52 or onto the insulating substrate 51.

[0256] The N terminal 91N is connected to the surface metal body 62 (N wiring 64) of the substrate 60 via the bonding material 104. By having the opposing surface of the N terminal 91N contact the surface metal body 62, overflow of the bonding material 104 from the housing of the N terminal 91N to the opposing surface can be suppressed. Furthermore, by providing the opposing surface on the end 60c side of the substrate 60 as shown in Figure 57, it is possible to suppress the bonding material 104 from wetting and spreading onto the end of the surface metal body 62 or onto the insulating substrate 61. The end 60c is the end face (side surface) on the side surface 30c side of the sealant 30 in the Y direction.

[0257] <Variation> The arrangement of the opposing surface 920 and the housing portion 921 is not limited to the example described above. For example, the configurations shown in Figures 61 and 62 may be adopted. Figure 61 is a plan view showing a modified example and corresponds to Figure 58. Figure 62 is a plan view taken from the LXII direction shown in Figure 61. In this example, the housing portion 921 does not open on the side surfaces 923 and 924, but only on the front end surface 922. The housing portion 921 has an opening 921c on the front end surface 922, which is a side surface.

[0258] The opposing surface 920 has a first opposing portion 920a and a second opposing portion 920b. The first opposing portion 920a is provided on the side opposite to the opening 921c relative to the housing portion 921. In the Y direction, which is the extension direction of the output terminal 92, the first opposing portion 920a is adjacent to the housing portion 921. The second opposing portion 920b is adjacent to the housing portion in the X direction. In the example shown in Figures 61 and 62, the opposing surface 920 has a pair of second opposing portions 920b. The pair of second opposing portions 920b sandwich the housing portion 921 in the X direction. The opposing surface 920 has a planar shape that is roughly U-shaped. Because the opposing surface 920 is arranged on three sides relative to the housing portion 921, the direction of overflow of the bonding material 104 from the housing portion 921 can be restricted to one direction toward the opening 921c. This further improves insulation reliability.

[0259] The opposing surface 920 may also be configured to have only one second opposing portion 920b. In this case, the opposing surface 920 has a substantially L-shape in plan. Since the opposing surface 920 is arranged on two sides with respect to the housing portion 921, the direction in which the bonding material 104 overflows from the housing portion 921 can be restricted compared to the arrangement in Figure 58. This improves insulation reliability.

[0260] An example has been shown in which the housing portion 921 opens on the side of the output terminal 92, but it is not limited to this. Also, the planar shape of the housing portion 921 is not limited to a substantially rectangular shape. For example, as shown in Figure 63, a housing portion 921 without an opening on the side may be provided. Figure 63 is a plan view showing a modified example and corresponds to Figure 58. In Figure 63, the housing portion 921 has a substantially circular planar shape. The housing portion 921 is a hole that opens on the lower surface of the output terminal 92. The housing portion 921 shown in Figure 63 is an unpenetrating hole. The unpenetrating housing portion 921 has a side surface 921a and a bottom surface 921b that are connected to the opposing surface 920, similar to the housing portion 921 described above. Alternatively, a through hole that opens on the upper surface of the output terminal 92 may be used. The through hole housing portion 921 does not have a bottom surface 921b, but has a side surface 921a.

[0261] The metal member having the opposing surface and housing portion is not limited to the main terminal. For example, as shown in Figures 64 and 65, in the semiconductor device 20 constituting the upper and lower arm circuit 9, the joint portion 81 may be provided with the opposing surface and housing portion. Figure 64 is a cross-sectional view showing a modified example and corresponds to Figure 57. Figure 65 is an enlarged view of the region LXV shown by the dashed line in Figure 64. In Figure 65, for convenience, the sealant 30 is omitted from the illustration.

[0262] As described in the prior embodiment, the semiconductor device 20 includes a semiconductor element 40H, which is a first semiconductor element constituting the upper arm 9H, and a semiconductor element 40L, which is a second semiconductor element constituting the lower arm 9L. The joint portion 81 electrically connects the source electrode 40S of the semiconductor element 40H and the drain electrode 40D of the semiconductor element 40L. The joint portion 81 is a metal columnar body extending in the Z direction. The end portion 81a of the joint portion 81 is connected to the relay wiring 55, which is the first wiring of the substrate 50, via a bonding material 103. The end portion 81b opposite to the end portion 81a is connected to the relay wiring 65, which is the third wiring of the substrate 60, via a bonding material 103. The surface metal body 52 has a P wiring 54, which is a second wiring, provided at a predetermined distance from the relay wiring 55. The surface metal body 62 has an N wiring 64, which is a fourth wiring, provided at a predetermined distance from the relay wiring 65.

[0263] In the examples shown in Figures 64 and 65, an opposing surface 810 and a housing portion 811 are provided at the ends 81a and 81b of the joint portion 81, respectively. The configuration of the opposing surface 810 and the housing portion 811 is the same as that of the opposing surface 920 and housing portion 921 described above. At end 81a, the opposing surface 810 faces the upper surface 52a of the surface metal body 52 (relay wiring 55). The opposing surface 810 is in contact with the upper surface 52a. The housing portion 811 is a recessed portion that is recessed relative to the opposing surface 810. The housing portion 811 has a side surface 811a connected to the opposing surface 810 and a bottom surface 811b. The housing portion 811 houses the joining material 103.

[0264] The opposing surface 810 and the housing portion 811 are arranged side by side in the Y direction. The opposing surface 810 is located on the side of the wiring gap 52G separating the relay wiring 55 and the P wiring 54, that is, close to the P wiring 54, which is a different wiring from the relay wiring 55 to which the joint portion 81 is connected. The housing portion 811 opens on the side surface 812 of the joint portion 81 in the Y direction, but does not open on the side surface 813 opposite to the side surface 812. The housing portion 811 may open only on the side surface 812, or it may open on three sides, including the two sides adjacent to the side surface 812.

[0265] In this way, the opposing surface 810 of the joint portion 81 comes into contact (metal-to-metal contact) with the surface metal body 52. ​​This suppresses the overflow of the bonding material 103 from the housing portion 811 to the opposing surface 810. Thus, it is possible to provide a semiconductor device 20 that achieves both insulation reliability and miniaturization.

[0266] Furthermore, if the bonding material 103 wets and spreads within the wiring gap 52G of the surface metal body 52, the portion at the same potential as the relay wiring 55 expands, and the distance to the P wiring 54 decreases. There is a risk that the bonding material 103 may come into contact with the P wiring 54. In contrast, in the example described above, the opposing surface 810 is positioned closer to the P wiring 54, that is, the wiring gap 52G, than to the housing portion 811. This makes it possible to suppress the bonding material 103 from reaching the wiring gap 52G. Thus, insulation reliability can be improved without increasing the size.

[0267] The configuration of end 81b is the same as that of end 81a. At end 81b, the opposing surface 810 faces the upper surface 62a of the surface metal body 62 (relay wiring 65). The opposing surface 810 is in contact with the upper surface 52a. The housing portion 811 is a recess. The housing portion 811 houses the joining material 103. The opposing surface 810 and the housing portion 811 are arranged side by side in the Y direction. The opposing surface 810 is located on the wiring gap 62G side that separates the relay wiring 65 and the N wiring 64, that is, close to the N wiring 64, which is a different wiring from the relay wiring 65 to which the joint portion 81 is connected. The housing portion 811 opens to the side surface 813 of the joint portion 81 in the Y direction, but does not open to the side surface 812. The housing portion 811 may open only to the side surface 813, or it may open to three sides including the two sides adjacent to the side surface 813.

[0268] In this way, the opposing surface 810 of the joint portion 81 makes contact (metal-to-metal contact) with the surface metal body 62. This suppresses the overflow of bonding material 103 from the housing portion 811 to the opposing surface 810. Therefore, a semiconductor device 20 that can achieve both insulation reliability and miniaturization can be provided. Furthermore, the opposing surface 810 is located closer to the N wiring 64, that is, the wiring gap 62G, than to the housing portion 811. This suppresses the bonding material 103 from reaching the wiring gap 62G. Therefore, insulation reliability can be improved without increasing the size.

[0269] In the example described above, overflow of the bonding material was suppressed by contact between the opposing surfaces of the metal members and the surface metal bodies. The function of suppressing overflow may be further enhanced by adding an uneven oxide film formed by laser irradiation to this configuration. An example is shown in Figures 66 and 67. Figure 66 is a cross-sectional view corresponding to Figure 65, and for convenience, the sealing body 30 is omitted. Figure 67 is an enlarged view of the region LXVII shown by the dashed line in Figure 66, and only the surface metal body 52 is shown.

[0270] In the example shown in Figure 66, the surface metal bodies 52 and 62 are each provided with uneven oxide films 520 and 620, corresponding to the joint portion 81. The following explanation will use the uneven oxide film 520 as an example. As shown in Figure 67, the surface metal body 52 has a base material 521 and a metal film 522 and an uneven oxide film 520 provided on the surface of the base material 521. The base material 521 constitutes the main part of the surface metal body 52. ​​The base material 521 is formed using, for example, a Cu-based material. The metal film 522 is formed using a material that has higher wettability to solder than the base material 521. The metal film 522 is formed over the entire upper surface 52a. In this embodiment, the metal film 522 is formed over the entire surface of the base material 521. The uneven oxide film 520 is formed locally on the upper surface 52a.

[0271] The uneven oxide film 520 is formed locally on the upper surface 52a of the metal film 522 by irradiating the metal film 522 with laser light. The metal film 522 has an underlayer mainly composed of Ni (nickel) and an upper layer mainly composed of Au (gold). In this embodiment, an electroless Ni plating film containing P (phosphorus) is used as the underlayer. When the bonding material 103 is solder, the upper layer (Au) of the metal film 522 exposed from the uneven oxide film 520 that comes into contact with the bonding material 103 diffuses into the solder during reflow. The upper layer (Au) of the metal film 522 in the area where the uneven oxide film 520 is formed is removed by laser light irradiation when forming the uneven oxide film 520. The uneven oxide film 520 is an oxide film mainly composed of Ni. For example, of the components that make up the uneven oxide film 520, 80% is NI2O3, 10% is NiO, and 10% is Ni.

[0272] The depressions 523 on the surface of the metal film 522 are formed by irradiation with pulsed laser light. One depression 523 is formed with each pulse. The uneven oxide film 520 is formed when the surface portion of the metal film 522 melts, vaporizes, and is deposited by irradiation with laser light. The uneven oxide film 520 is an oxide film derived from the metal film 522. The uneven oxide film 520 is a film of oxide of the metal (Ni), which is the main component of the metal film 522. The uneven oxide film 520 is formed following the surface irregularities of the metal film 522 having depressions 523. The surface of the uneven oxide film 520 has irregularities formed at a pitch finer than the width of the depressions 523. In other words, very fine irregularities (roughened areas) are formed.

[0273] Such an uneven oxide film 520 can be formed by the following process. First, the upper surface 52a of the surface metal body 52 on which the metal film 522 is formed on the base material 521 is irradiated with pulsed laser light to melt and evaporate the surface of the metal film 522. The pulsed laser light is adjusted so that its energy density is greater than 0 J / cm2 and 100 J / cm2 or less, and its pulse width is 1 μs or less. To satisfy these conditions, YAG lasers, YVO4 lasers, fiber lasers, etc., can be used. For example, in the case of a YAG laser, an energy density of 1 J / cm2 or more is sufficient. In the case of electroless Ni plating, for example, the metal film 522 can be processed even with an energy density of about 5 J / cm2.

[0274] At this time, the laser beam is scanned and irradiated sequentially at multiple positions by relatively moving the laser light source and the surface metal body 52. ​​By irradiating with laser light and melting and vaporizing the surface of the metal film 522, recesses 523 are formed on the surface of the metal film 522. The average thickness of the part of the metal film 522 irradiated with laser light becomes thinner than the average thickness of the part that is not irradiated with laser light. In addition, the multiple recesses 523 formed corresponding to the laser beam spots are connected, for example, forming a scale-like pattern. A spot is the irradiation area of ​​one pulse. For example, the laser beam is scanned so that adjacent laser beam spots in the X direction partially overlap, and adjacent laser beam spots in the Y direction partially overlap.

[0275] Next, the molten metal film 522 is solidified. Specifically, the molten and vaporized metal film 522 is deposited onto the area irradiated by the laser light and its surrounding areas. By depositing the molten and vaporized metal film 522 in this way, an uneven oxide film 520 is formed on the surface of the metal film 522.

[0276] In Figure 66, the uneven oxide film 520 is not provided in the first region 524 of the upper surface 52a of the surface metal body 52, which overlaps with the housing portion 811 of the joint portion 81 in a plan view. The uneven oxide film 520 is selectively provided in the second region 525, which overlaps with the opposing surface 810. The configuration of the surface metal body 62 and the uneven oxide film 620 is the same as that of the surface metal body 52 and the uneven oxide film 520. The uneven oxide film 620 is not provided in the first region 624 of the upper surface 62a of the surface metal body 62, which overlaps with the housing portion 811 of the joint portion 81 in a plan view. The uneven oxide film 620 is selectively provided in the second region 625, which overlaps with the opposing surface 810.

[0277] The oxide films (textured oxide films 520, 620) have lower wettability with respect to the bonding material 103 compared to the metal film. Because the textured oxide films 520, 620 have fine irregularities on their surfaces, the contact area with the bonding material 103 is reduced, and a portion of the bonding material 103 becomes spherical due to surface tension. In other words, the contact angle increases. This results in low wettability with respect to the bonding material 103. Therefore, due to the effect of reduced wettability by the textured oxide films 520, 620 and the effect of contact by the opposing surface 810, the bonding material 103 has difficulty passing between the opposing surface 810 and the second regions 525, 625. This makes it possible to more effectively suppress overflow of the bonding material 103. As described above, laser light is used to form the textured oxide films 520, 620, making patterning easy.

[0278] As shown in Figure 68, the uneven oxide films 520 and 620 may be provided in the peripheral regions 526 and 626. Peripheral region 526 is the region surrounding the second region 525 in a plan view, excluding the first region 524. Peripheral region 626 is the region surrounding the second region 625 in a plan view, excluding the first region 624. Even if the joining material 103 passes directly below the opposing surface 810 of the joint portion 81, it can be blocked by the uneven oxide films 520 and 620. Furthermore, because very fine irregularities are formed on the surface of the uneven oxide films 520 and 620, the sealant 30 becomes entangled, creating an anchoring effect. Also, the contact area with the sealant 30 increases. Therefore, the adhesion force of the surface metal bodies 52 and 62 to the sealant 30 can be increased.

[0279] Furthermore, the uneven oxide films 520 and 620 may be provided in the second regions 525 and 625 and the peripheral regions 526 and 626. Only one of the uneven oxide films 520 and 620 may be provided. The uneven oxide films 520 and 620 may also be used at the joints with the main terminals, which are metal members, namely the P terminal 91P, N terminal 91N, and output terminal 92.

[0280] An example is shown in which the semiconductor device 20 includes a substrate 60 electrically connected to the source electrode 40S (second main power station). In other words, an example of a semiconductor device 20 with a double-sided heat dissipation structure comprising a pair of substrates 50 and 60 is shown. However, the example is not limited to this. It can also be applied to a semiconductor device 20 with a single-sided heat dissipation structure comprising only the substrate 50 to which the drain electrode 40D (first main electrode) is connected. In a semiconductor device 20 comprising a pair of substrates 50 and 60, the above structure may be applied only to the joint between one of the substrates 50 and 60 and the metal member. An example is shown in which both back metal bodies 53 and 63 are exposed from the sealant 30, but the example is not limited to this.

[0281] An example has been shown in which the semiconductor device 20 includes semiconductor elements 40H and 40L, but it is not limited to this. It may include only one semiconductor element 40 that constitutes one of the arms. The semiconductor device 20 may include, for example, only one semiconductor element 40.

[0282] The configuration described in this embodiment can be combined with any of the configurations described in the first embodiment, the second embodiment, the third embodiment, the fourth embodiment, and the modified form.

[0283] (Sixth Embodiment) This embodiment is a modification based on a prior embodiment, and the description of the prior embodiment can be referenced. In order to improve the reliability of the semiconductor device, the physical properties of the encapsulant and the physical properties of the insulating substrate may be made to satisfy a predetermined relationship, as described in this embodiment.

[0284] <Semiconductor devices and heat dissipation structures> The semiconductor device 20 and its heat dissipation structure according to this embodiment will be described based on Figure 69. Figure 69 is a cross-sectional view showing the semiconductor device 20 according to this embodiment. Figure 69 is an enlarged view of a part of Figure 5. For convenience, the external connection terminal 90 is omitted in Figure 69.

[0285] The semiconductor device 20 of this embodiment has a structure similar to that described in the prior embodiment (see Figures 2 to 13). As shown in Figure 69, the semiconductor device 20 comprises a semiconductor element 40 (40H), substrates 50 and 60 arranged to sandwich the semiconductor element 40 in the Z direction, and a sealant 30. The surface metal body 52 of substrate 50 is connected to the drain electrode 40D, which is the main electrode of the semiconductor element 40. The surface metal body 62 of substrate 60 is connected to the source electrode 40S, which is the main electrode of the semiconductor element 40. The back metal bodies 53 and 63 are exposed from the sealant 30. The insulating substrates 51 and 61 contain resin. The sealant 30 contains resin. Although not shown, the semiconductor device 20 also includes a semiconductor element 40L.

[0286] Figure 69 shows the semiconductor device 20, along with the heat exchange section 121 of the cooler 120 and a heat conductive member 130 such as a heat dissipation gel. In other words, Figure 69 shows a semiconductor module 140 comprising the semiconductor device 20, the cooler 120, and the heat conductive member 130. The semiconductor module 140 has, as an example, a double-sided cooling structure in which the semiconductor device 20 is sandwiched between a pair of heat exchange sections 121. The semiconductor device 20 is arranged side by side with the cooler 120 (heat exchange section 121) in a predetermined direction, the Z direction. The cooler 120 is arranged on both sides of the semiconductor device 20.

[0287] The back metal bodies 53 and 63 are exposed from the encapsulant 30 as the back surfaces 50b and 60b of the substrates 50 and 60. One of the heat exchange sections 121 of the cooler 120 is positioned opposite one surface 30a and the back surface 50b of the encapsulant 30, and the other heat exchange section 121 is positioned opposite the back surfaces 30b and 60b of the encapsulant 30. A heat conductive member 130 is positioned between the opposing surfaces of the semiconductor device 20 and the heat exchange section 121. The heat conductive member 130 is in close contact with the semiconductor device 20 and the heat exchange section 121.

[0288] <Relationship with glass transition temperatures> Next, the relationship between the glass transition points of the sealant 30 and the insulating substrates 51 and 61 will be explained based on Figures 69 and 70.

[0289] Figure 70 shows an example of the relationship between the glass transition temperature Tgs and linear expansion coefficient αs of the sealant 30, and the glass transition temperature Tgi and linear expansion coefficient αi of the insulating substrates 51 and 61. In Figure 70, the vertical axis represents the linear expansion coefficient α, and the horizontal axis represents temperature. In Figure 70, the solid line represents the linear expansion coefficient αs of the sealant 30, and the dashed line represents the linear expansion coefficient αi of the insulating substrates 51 and 61. Of the linear expansion coefficient αs, α1s represents the linear expansion coefficient at temperatures lower than the glass transition temperature Tgs, i.e., the linear expansion coefficient in the α1 region. α2s represents the linear expansion coefficient at temperatures higher than the glass transition temperature Tgs, i.e., the linear expansion coefficient in the α2 region. The same applies to the linear expansion coefficient αi, where α1i represents the linear expansion coefficient in the α1 region, and α2s represents the linear expansion coefficient in the α2 region.

[0290] As shown in Figure 69, the encapsulant 30 is in close contact with the semiconductor element 40. The insulating substrates 51 and 61 are thermally connected to the semiconductor element 40 via the bonding materials 100, 101, and 102 and the surface metal bodies 52 and 62. Therefore, when the semiconductor element 40 is operating (when it generates heat), the temperature at the peripheral position MP1 of the encapsulant 30 is higher than the temperature at the overlapping positions MP2 and MP3 of the insulating substrates 51 and 61 with the semiconductor element 40. Thus, the encapsulant 30 is hotter than the insulating substrates 51 and 61.

[0291] When the temperature of the sealant 30 exceeds the glass transition temperature Tgs, the Young's modulus decreases, and the sealing function of the sealant 30 deteriorates. Due to the deterioration of the sealing function, thermal stress concentrates on the drain electrode 40D, the source electrode 40S, and their joints, which may cause cracks or other damage. In other words, the reliability of the connection may decrease. In contrast, in this embodiment, as shown in Figure 70, the relationship Tgs > Tgi is satisfied.

[0292] <Relationship with linear expansion coefficient> Next, the relationship between the coefficients of linear expansion of the encapsulant 30 and the insulating substrates 51 and 61 will be explained based on Figures 70 to 72. Figures 71 and 72 are illustrative diagrams showing the warping of the semiconductor device 20. In Figures 71 and 72, only the resin elements constituting the semiconductor device 20 are shown, that is, only the encapsulant 30 and the insulating substrates 51 and 61.

[0293] When the semiconductor element 40 is operating (generating heat), if the linear expansion coefficient αs of the encapsulant 30 is greater than the linear expansion coefficient αi of the insulating substrates 51 and 61, the expansion amount of the encapsulant 30 will be greater than the expansion amount of the insulating substrates 51 and 61, as shown by the dashed arrows in Figure 71. In other words, the expansion amount is greater in the center in the Z direction and smaller at both ends. Consequently, a concave shape is formed with both ends in the Z direction being recessed.

[0294] In this embodiment, as shown in FIG. 70, the relationship of αi > αs is satisfied. Specifically, in the α1 region, the relationship of α1i > α1s is satisfied, and in the α2 region, the relationship of α2i > α2s is satisfied. As described above, since the relationship of Tgs > Tgi is satisfied, the relationship of αi > αs is satisfied throughout the operating temperature range. Therefore, during the operation (heat generation) of the semiconductor element 40, as indicated by the dashed arrow in FIG. 72, the expansion amount of the insulating base materials 51 and 61 is larger than the expansion amount of the sealing body 30. That is, the expansion amount becomes smaller at the center in the Z direction and larger at both ends. Therefore, as shown in FIG. 72, the shape of the semiconductor device 20 is convex at both ends in the Z direction.

[0295] <Summary of the Sixth Embodiment> According to this embodiment, the glass transition point Tgs of the sealing body 30 is higher than the glass transition points Tgi of the insulating base materials 51 and 61. As a result, for the sealing body 30 that reaches a higher temperature during the operation of the semiconductor element 40, it becomes difficult for the temperature to exceed the glass transition point Tgs. The temperature of the sealing body 30 does not exceed the glass transition point Tgs or exceeds it only slightly. Therefore, the Young's modulus of the sealing body 30 can be reduced, and a decrease in the sealing function can be suppressed. Since a decrease in the sealing function can be suppressed, stress concentration at the drain electrode 40D, source electrode 40S, and their joints, which are the main electrodes, can be suppressed. That is, the connection reliability can be improved.

[0296] The glass transition point Tgs of the sealing body 30 may be made substantially equal to the glass transition points Tgi of the insulating base materials 51 and 61. Compared with Tgs < Tgi, it becomes difficult for the temperature of the sealing body 30, which reaches a higher temperature during heat generation, to exceed the glass transition point Tgs.

[0297] Furthermore, the coefficient of linear expansion αi of the insulating substrates 51 and 61 is greater than the coefficient of linear expansion αs of the sealant 30. As a result, when the semiconductor element 40 is in operation, the amount of expansion of the insulating substrates 51 and 61 is greater than the amount of expansion of the sealant 30. In other words, the amount of expansion is small in the center in the Z direction and large at both ends. This causes the semiconductor device 20 to warp outward in the Z direction. Therefore, the distance between the semiconductor device 20 and the cooler 120 (121) is reduced, and the thermal resistance between the semiconductor device 20 and the cooler 120 is reduced. Specifically, the thickness of the heat conductive member 130 is reduced, and the thermal resistance is reduced. Because the heat of the semiconductor element 40 can be efficiently dissipated, it is possible to suppress the semiconductor element 40 from becoming overheated. In other words, heat dissipation can be improved.

[0298] The coefficient of linear expansion αi of the insulating substrates 51 and 61 may be approximately equal to the coefficient of linear expansion αs of the sealant 30. In this case, the amount of expansion will be approximately equal at the center and both ends in the Z direction, and it will be possible to suppress the formation of a concave shape where both ends in the Z direction are recessed. In other words, it will be possible to suppress the increase in thermal resistance between the semiconductor device 20 and the cooler 120 that would result from the formation of a concave shape.

[0299] In this way, by satisfying the relationships Tgs≧Tgi and αi≧αs, a highly reliable semiconductor device 20 can be provided.

[0300] <Variation> An example of a semiconductor device 20 with a double-sided heat dissipation structure comprising a pair of substrates 50 and 60 has been shown, but it is not limited to this. It can also be applied to a semiconductor device 20 with a single-sided heat dissipation structure comprising only the substrate 50 to which the drain electrode 40D (first main electrode) is connected.

[0301] An example has been shown in which the semiconductor device 20 includes semiconductor elements 40H and 40L, but it is not limited to this. It may include only one semiconductor element 40 that constitutes one of the arms. The semiconductor device 20 may include, for example, only one semiconductor element 40.

[0302] The configuration described in this embodiment can be combined with any of the configurations described in the first embodiment, the second embodiment, the third embodiment, the fourth embodiment, the fifth embodiment, and the modified form.

[0303] (Seventh Embodiment) This embodiment is a modification based on a prior embodiment, and the description of the prior embodiment can be referenced. In order to suppress peeling of the sealant, the surface metal body may be made into a predetermined structure, as described in this embodiment.

[0304] <Semiconductor device> Figure 73 is a cross-sectional view showing the semiconductor device 20 according to this embodiment. Figure 73 corresponds to Figure 8.

[0305] The semiconductor device 20 of this embodiment has the same configuration as the configuration described in the prior embodiment (see Figures 2 to 13). As shown in Figure 73, the semiconductor device 20 comprises two semiconductor elements 40 (40H), substrates 50 and 60 arranged to sandwich the semiconductor elements 40 in the Z direction, and a encapsulant 30. The surface metal body 52 of the substrate 50 is connected to the drain electrode 40D, which is the main electrode of the semiconductor element 40, via a bonding material 100. The surface metal body 62 of the substrate 60 is electrically connected to the source electrode 40S, which is the main electrode of the semiconductor element 40, via a bonding material 102. The encapsulant 30 encapsulates the semiconductor elements 40, the substrates 50 and 60, and the bonding materials 100 and 102. Of the substrates 50 and 60, the back surface metal bodies 53 and 63 are exposed from the encapsulant 30. Although not shown, the semiconductor device 20 comprises two semiconductor elements 40L.

[0306] As shown in Figure 73, the surface metal bodies 52 and 62 have roughened portions 527 and 627 and unroughened portions 528 and 628.

[0307] <Uneven oxide film> Next, the uneven oxide film 520 constituting the roughened portion 527 will be described in detail based on Figures 74 and 75. Figure 74 is an enlarged view of region LXXIV in Figure 73. Figure 75 is a diagram showing the method for forming the roughened portion.

[0308] The surface metal bodies 52 and 62 have uneven oxide films 520 and 620, similar to the configuration described in the modified example of the fifth embodiment (see Figures 66 and 67). The uneven oxide films 520 and 620 provide roughened portions 527 and 627 on the surface of the surface metal bodies 52 and 62. The portions of the surface of the surface metal bodies 52 and 62 where the uneven oxide films 520 and 620 are not formed provide unroughened portions 528 and 628. The following description will use the surface metal body 52 as an example.

[0309] As shown in Figure 74, the surface metal body 52 has a base material 521 and a plating film 522p and an uneven oxide film 520 provided on the surface of the base material 521. The base material 521 constitutes the main part of the surface metal body 52. ​​The base material 521 is formed using, for example, a Cu-based material. The plating film 522p is formed using a material that has a higher wettability to a bonding material 100 such as solder than the base material 521. The plating film 522p is formed over the entire upper surface 52a and the entire side surface 52c of the surface metal body 52. ​​The side surface 52c is the surface of the surface metal body 52 that connects the upper surface 52a and the lower surface 52d facing the insulating substrate 51.

[0310] The uneven oxide film 520 is formed by irradiating the plating film 522p with laser light, as described in the modified example of the fifth embodiment. In this embodiment, the upper surface 52a and the side surface 52c of the surface metal body 52 are irradiated with laser light. The roughened portion 527 provided by the uneven oxide film 520 is the portion of the upper surface 52a excluding the non-roughened portion 528. As an example, the roughened portion 527 is formed over the entire area of ​​the side surface 52c. At the end of the surface metal body 52, the roughened portion 527 is provided continuously from the side surface 52c to the upper surface 52a. The roughened portion 527 is provided on a part of the upper surface 52a and on the side surface 52c. The roughened portion 527 may be provided only on the edge of the upper surface 52a. The non-roughened portion 528 is provided on a part of the upper surface 52a and includes at least the area where the bonding material 100 is placed (bonding area). The non-roughened portion 528 may be provided only in the bonding region, or it may include regions other than the bonding region. The roughened portion 527 is provided on at least a part of the side surface 52c. The roughened portion 527 may be provided on only a part of the side surface 52c. For example, the roughened portion 527 may be provided on only a part of the side surface 52c so that the uneven oxide film 520 does not come into contact with the insulating substrate 51.

[0311] The plating film 522p of this embodiment has an underlayer mainly composed of Ni (nickel) and an overlayer mainly composed of Au (gold). Specifically, an electroless Ni plating film containing P (phosphorus) is used as the underlayer. When the bonding material 100 is solder, the overlayer (Au) of the plating film 522p exposed from the uneven oxide film 520 that comes into contact with the bonding material 100 diffuses into the solder during reflow. The overlayer (Au) of the plating film 522p in the area where the uneven oxide film 520 is formed is removed by laser irradiation when the uneven oxide film 520 is formed. The uneven oxide film 520 is an oxide film mainly composed of Ni. The uneven oxide film 520 is continuously provided at the end of the surface metal body 52, extending from the side surface 52c to the top surface 52a.

[0312] As described in the modified version of the fifth embodiment, the uneven oxide film 520 is formed by the melting, vaporization, and deposition of the surface layer of the plating film 522p upon irradiation with laser light. The uneven oxide film 520 is an oxide film derived from the plating film 522p. The uneven oxide film 520 is a film of oxide of the metal (Ni), which is the main component of the plating film 522p. Fine irregularities (roughened areas) are always formed on the surface of the uneven oxide film 520. The surface of the uneven oxide film 520 has a continuous uneven surface.

[0313] In this embodiment, the surface metal body 52 has a larger area on its lower surface 52d than on its upper surface 52a. Therefore, as shown in Figure 74, the lower surface 52d protrudes beyond the upper surface 52a. In other words, in a plan view in the Z direction, at least a portion of the side surface 52c is located outside the upper surface 52a. Thus, as shown in Figure 75, by irradiating laser light in the Z direction, an uneven oxide film 520 can be formed on the upper surface 52a and the side surface 52c.

[0314] <Summary of Embodiment 7> In a configuration where a plating film 522p is provided on the upper surface 52a and side surface 52c of the surface metal body 52, thermal stress makes it easy for the sealant 30 to peel off from the edges of the surface metal body 52, i.e., from the side surface 52c. In contrast, in this embodiment, roughened portions 527 are provided on the upper surface 52a and side surface 52c, excluding the non-roughened portion 528. As a result, the adhesion force between the sealant 30 and the side surface 52c of the surface metal body 52 is higher compared to a configuration without roughened portions 527. Therefore, it is possible to suppress the peeling of the sealant 30 from the side surface 52c of the surface metal body 52. ​​By suppressing peeling, it is possible to suppress the concentration of thermal stress at the joint portion of the surface metal body 52, such as the bonding material 100. As a result, a highly reliable semiconductor device 20 can be provided.

[0315] The surface metal body 62 has the same structure as the surface metal body 52. ​​The surface metal body 62 has roughened portions 627 on the upper surface 62a and side surface 62c, excluding the non-roughened portion 628. This makes it possible to suppress the peeling of the sealant 30 on the side surface 62c of the surface metal body 62.

[0316] In this embodiment, the roughened portions 527, 627 are continuously provided across the side surfaces 52c, 62c and the upper surfaces 52a, 62a. This makes it possible to suppress the peeling of the sealant 30 near the ends of the surface metal bodies 52, 62.

[0317] Possible roughening treatments for forming the roughened portions 527 and 627 include roughening plating, sandblasting, and chemical treatment. In this embodiment, laser roughening is employed. By irradiating the plated film with laser light, uneven oxide films 520 and 620 are formed. The surface metal bodies 52 and 62 have uneven oxide films 520 and 620 on the roughened portions 527 and 627.

[0318] The surfaces of the uneven oxide films 520 and 620 have continuous irregularities, causing the sealant 30 to entangle and create an anchoring effect. This also increases the contact area with the sealant 30. Therefore, the adhesion force to the sealant 30 can be increased in the roughened portions 527 and 627. Furthermore, the uneven oxide films 520 and 620 have lower wettability with respect to the bonding materials 100 and 102 compared to the plating film (plating film 522p). Because the uneven oxide films 520 and 620 have fine irregularities on their surfaces, the contact area with the bonding materials 100 and 102 is reduced, and some of the bonding materials 100 and 102 become spherical due to surface tension. In other words, the contact angle increases. Therefore, overflow of the bonding materials 100 and 102 can be suppressed. Thus, by using the uneven oxide films 520 and 620, the adhesion force to the sealant 30 can be increased, and overflow of the bonding materials 100 and 102 from the joint can be suppressed.

[0319] In this embodiment, the area of ​​the surface metal bodies 52 and 62 is larger on the lower surfaces 52d and 62d than on the upper surfaces 52a and 62a. The lower surfaces 52d and 62d protrude over the upper surfaces 52a and 62a. Therefore, physical roughening can be easily performed on the side surfaces 52c and 62c from the Z direction. In the case of the laser roughening described above, by irradiating laser light in the Z direction, uneven oxide films 520 and 620 can be formed not only on the upper surfaces 52a and 62a but also on the side surfaces 52c and 62c.

[0320] <Variation> The side shapes of the surface metal bodies 52 and 62 are not limited to the examples described above. When patterning the surface metal bodies 52 and 62 by pressing, etching, cutting, etc., the sides can be processed into a predetermined shape. Figure 76 is a cross-sectional view showing a modified side shape. In Figure 76, the surface metal body 52 is shown as an example, and for convenience, the plating film 522p is omitted from the illustration. Although not shown, a similar configuration can be adopted for the surface metal body 62.

[0321] In the example shown in Figure 76, the surface metal body 52 has a side surface 52c that is substantially parallel to the Z direction. That is, the area of ​​the surface metal body 52 is almost constant in the Z direction. To physically roughen such a surface metal body 52, for example, the roughening can be carried out separately on the top surface 52a and the side surface 52c. In the case of laser roughening, the laser beam is irradiated onto the side surface 52c from a direction different from the direction of laser beam irradiation to the top surface 52a, for example, from a direction tilted with respect to the Z direction. This makes it possible to create an uneven oxide film 520 on the side surface 52c.

[0322] Figure 77 is a cross-sectional view showing a modified side shape, corresponding to Figure 76. In the example shown in Figure 77, the area of ​​the surface metal body 52 perpendicular to the Z direction increases as it approaches the bottom surface 52d. The side surface 52c has an R shape. In this case, in a plan view, the entire area of ​​the side surface 52c is located outside the top surface 52a. Therefore, physical roughening of the side surface 52c from the Z direction, such as laser roughening, is easier than in the configuration shown in Figure 75.

[0323] Figure 78 is a cross-sectional view showing a modified side shape, corresponding to Figure 76. In the example shown in Figure 78, the area of ​​the surface metal body 52 perpendicular to the Z direction increases as it approaches the bottom surface 52d. The surface metal body 52 is, for example, roughly trapezoidal in the ZY plane. In this case as well, since the entire area of ​​the side surface 52c is located outside the top surface 52a in a plan view, the side surface 52c is easily physically roughened from the Z direction.

[0324] An example of a semiconductor device 20 with a double-sided heat dissipation structure comprising a pair of substrates 50 and 60 has been shown, but it is not limited to this. It can also be applied to a semiconductor device 20 with a single-sided heat dissipation structure comprising only the substrate 50 to which the drain electrode 40D (first main electrode) is connected. In a configuration comprising a pair of substrates 50 and 60, the roughened surface structure including the above-described side surface may be applied to only one of the substrates 50 and 60.

[0325] An example has been shown in which the semiconductor device 20 includes semiconductor elements 40H and 40L, but it is not limited to this. It may include only one semiconductor element 40 that constitutes one of the arms. The semiconductor device 20 may include, for example, only one semiconductor element 40.

[0326] The configuration described in this embodiment can be combined with any of the configurations described in the first embodiment, the second embodiment, the third embodiment, the fourth embodiment, the fifth embodiment, the sixth embodiment, and the modified forms.

[0327] (Eighth embodiment) This embodiment is a modification based on a prior embodiment, and the description of the prior embodiment can be applied by reference. In order to reduce inductance, as described in this embodiment, the thickness of the surface metal body and the spacing of the wiring may be made to satisfy a predetermined relationship.

[0328] <Semiconductor device> First, the circuit patterns of the semiconductor device 20 according to this embodiment, particularly the surface metal bodies 52 and 62, will be described based on Figure 79. Figure 79 is a cross-sectional view showing the semiconductor device 20 according to this embodiment. Figure 79 shows a part of the configuration described in the prior embodiment (see Figure 8).

[0329] The semiconductor device 20 of this embodiment has the same configuration as the configuration described in the prior embodiment (see Figures 2 to 13). As shown in Figure 79, the semiconductor device 20 comprises a semiconductor element 40 (40H), substrates 50 and 60 arranged to sandwich the semiconductor element 40 in the Z direction, and a sealant 30. The surface metal body 52 of substrate 50 is electrically connected to the drain electrode 40D, which is the main electrode of the semiconductor element 40. The surface metal body 62 of substrate 60 is electrically connected to the source electrode 40S, which is the main electrode of the semiconductor element 40. The sealant 30 seals the semiconductor element 40, the substrates 50 and 60, and the bonding materials 100 and 102. Of the substrates 50 and 60, the back surface metal bodies 53 and 63 are exposed from the sealant 30. Although not shown, the semiconductor device 20 includes a semiconductor element 40L that constitutes the lower arm 9L.

[0330] <Relationship between wiring spacing and thickness> Next, the relationship between wiring spacing and thickness will be explained based on Figures 79 and 80. Figure 80 is an enlarged view of region LXXX in Figure 79. In Figure 80, only the substrate 60 is shown.

[0331] The surface metal bodies 52 and 62 have wiring gaps 52G and 62G, similar to the configuration described in the prior embodiment (see Figure 65). As shown in Figures 79 and 80, the wiring gap 62G separates adjacent N wiring 64 and relay wiring 65. The wiring gap 62G is a predetermined air gap provided in the surface metal body 62 between wirings with different potentials.

[0332] As shown in FIG. 80, in the present embodiment, the distance L10 between the N wiring 64 and the relay wiring 65 is equal to or less than the thickness T10 of the surface metal body 62 (L10≦T10). The distance L10 is the length of the wiring gap 62G, that is, the pattern distance between the N wiring 64 and the relay wiring 65. In FIGS. 79 and 80, the distance L10 and the thickness T10 in the surface metal body 62 satisfy the relationship of L10<T10. Although not shown, the substrate 50 provided with the surface metal body 52 has the same configuration as the substrate 60. In the surface metal body 52, the distance L10 between the P wiring 54 and the relay wiring 55 is equal to or less than the thickness T10 of the surface metal body 52 (L10≦T10).

[0333] <Simulation results> FIGS. 81 to 83 show the results of electromagnetic field simulation. FIG. 81 is a diagram summarizing the simulation results in terms of the relationship between the length (distance, thickness) and the inductance. The circles (○) at the measurement points show the results of three levels of the thickness T10 (0.3 mm, 1.5 mm, 2.5 mm) when the distance L10 is fixed at 1.5 mm. The solid line in the figure shows the change in inductance accompanying the change in the thickness T10 when the distance L10 is fixed. The squares (□) at the measurement points show the results of three levels of the distance L10 (0.5 mm, 1.5 mm, 2.5 mm) when the thickness T10 is fixed at 1.5 mm. The broken line in the figure shows the change in inductance accompanying the change in the distance L10 when the thickness T10 is fixed. The length on the horizontal axis shown in FIG. 81 indicates the length of the thickness T10 when the distance L10 is fixed, and indicates the length of the distance L10 when the thickness T10 is fixed.

[0334] FIG. 82 is a diagram showing the simulation results when L10>T10. FIG. 82 shows the simulation results under the first condition C1 shown in FIG. 81, specifically, when the distance L10 = 1.5 mm and the thickness T10 = 0.3 mm. FIG. 83 is a diagram showing the simulation results when L10<T10. FIG. 83 shows the simulation results under the second condition C2 shown in FIG. 81, specifically, when the distance L10 = 1.5 mm and the thickness T10 = 2.5 mm. In the simulation, the conditions other than the distance L10 and the thickness T10 are common.

[0335] From the results shown in FIG. 81, it is clear that the inductance can be reduced in the range satisfying the relationship L10≦T10. In particular, it is clear that the inductance can be effectively reduced in the range satisfying the relationship L10<T10.

[0336] As shown in FIG. 82, when L10>T10, although the current is dispersed in the width direction in the extended portion 641 of the N wiring 64, it flows biased toward the end side of the surface metal body 62 (substrate 60). For this reason, the PN current loop (see FIG. 17) described in the previous embodiment is large. Since the current path flowing through the extended portion 421 is far from the relay wiring 65, the canceling effect of the magnetic flux by the current in the reverse direction component is weakened. FIG. 82 shows that the inductance becomes larger as compared with the case where the relationship L10≦T10 is satisfied.

[0337] As shown in FIG. 83, when L10<T10, the current flows biased toward the end on the side of the relay wiring 65 in the width direction of the extended portion 641. For this reason, the PN current loop is small. Since the current path flowing through the extended portion 421 is close to the relay wiring 65, the canceling effect of the magnetic flux by the current in the reverse direction component is enhanced. FIG. 83 shows that the inductance becomes smaller as compared with the case where the relationship L10>T10 is satisfied.

[0338] <Summary of the Eighth Embodiment> In the present embodiment, the surface metal body 52 has a P wiring 54 which is a first wiring and a relay wiring 55 which is a second wiring having a different potential from the first wiring. And the interval L10 between the P wiring 54 and the relay wiring 55 and the thickness T1 of the surface metal body 52 satisfy the relationship L10≦T10. Similarly, the surface metal body 62 has an N wiring 64 which is a first wiring and a relay wiring 65 which is a second wiring having a different potential from the first wiring. And the interval L10 between the N wiring 64 and the relay wiring 65 and the thickness T1 of the surface metal body 62 satisfy the relationship L10≦T10.

[0339] When the relationship of L10 ≤ T10 is satisfied, since the distance between adjacent wirings is narrow, the cancellation effect between the magnetic flux due to the current flowing through the first wiring and the magnetic flux due to the current flowing through the second wiring is enhanced, and the inductance can be reduced. Also, since the surface metal body is thick, the cross-sectional area of the current path becomes large, and the inductance can be reduced. As described above, the semiconductor device 20 of the present embodiment can reduce the inductance. In particular, when the relationship of L1 < T10 is satisfied, the above-described effects are enhanced, and the inductance can be reduced more effectively.

[0340] <Modified Example> Although an example of the semiconductor device 20 having a double-sided heat dissipation structure including a pair of substrates 50 and 60 has been shown, it is not limited thereto. It is also applicable to a semiconductor device 20 having a single-sided heat dissipation structure including only the substrate 50 to which the drain electrode 40D (first main electrode) is connected. In a configuration including a pair of substrates 50 and 60, only one of the surface metal bodies 52 and 62 may satisfy the above-described relationship of L10 ≤ T10. That is, in at least one substrate electrically connected to the main electrode of the semiconductor element, the surface metal body may have a first wiring and a second wiring and satisfy the relationship of L10 ≤ T10. Also, although an example in which the relationship of L10 ≤ T10 is satisfied in all of the opposing regions between the N wiring 64 as the first wiring and the relay wiring 65 as the second wiring having a different potential from the first wiring has been shown, it is not limited thereto. The relationship of L10 ≤ T10 may be satisfied in at least a part of the opposing region. The same applies to the opposing region between the P wiring 54 as the first wiring and the relay wiring 55 as the second wiring having a different potential from the first wiring.

[0341] Although an example in which the semiconductor device 20 includes the semiconductor elements 40H and 40L has been shown, it is not limited thereto. It may include only the semiconductor element 40 that constitutes one arm. The semiconductor device 20 may include, for example, only one semiconductor element 40.

[0342] The configuration described in the present embodiment can be combined with any of the configurations described in the first embodiment, the second embodiment, the third embodiment, the fourth embodiment, the fifth embodiment, the sixth embodiment, the seventh embodiment, and the modified example.

[0343] (Ninth Embodiment) This embodiment is a modification based on a prior embodiment, and the description of the prior embodiment can be referenced. To improve heat dissipation and reliability, the side shape of the substrate may be set to a predetermined shape, as described in this embodiment.

[0344] <Semiconductor device> First, the semiconductor device 20 according to this embodiment will be described based on Figure 84. Figure 84 is a cross-sectional view corresponding to Figure 5. For convenience, the external connection terminal 90 is not shown in Figure 84.

[0345] The semiconductor device 20 of this embodiment has the same configuration as the configuration described in the prior embodiment (see Figures 2 to 13). As shown in Figure 84, the semiconductor device 20 comprises semiconductor elements 40 (40H, 40L), substrates 50, 60 arranged to sandwich the semiconductor elements 40 in the Z direction, and a sealant 30. The surface metal body 52 of substrate 50 is electrically connected to the drain electrode 40D, which is the main electrode of the semiconductor element 40. The surface metal body 62 of substrate 60 is electrically connected to the source electrode 40S, which is the main electrode of the semiconductor element 40. The sealant 30 seals the semiconductor elements 40, substrates 50, 60, and bonding materials 100, 102.

[0346] <Circuit board> Next, the substrates 50 and 60 will be described based on Figures 84 to 86. Figure 85 is a plan view showing the center of the substrate. Figure 85 corresponds to Figure 12. Figure 86 is an enlarged view of the region LXXXVI shown by the dashed line in Figure 84. In the following, "inside" and "outside" refer to the relative positional relationship with the centers 50sc and 60sc of the substrates 50 and 60 as the reference position in a plan view in the Z direction. The side closer to the center is the inside, and the side further from the center is the outside. In Figure 85, the center 50sc of substrate 50 is shown as an example. Figure 84 is a cross-sectional view, but for the sake of explanation, the centers 50sc and 60sc are shown.

[0347] In the substrates 50 and 60 of this embodiment, the insulating substrates 51 and 61 contain resin. The surface metal bodies 52 and 62 are arranged on the surfaces 51a and 61a of the insulating substrates 51 and 61. The surface metal bodies 52 and 62 are patterned as described in the prior embodiment. As a result, the insulating substrates 51 and 61 have exposed portions 510 and 610 that are exposed from the surface metal bodies 52 and 62. The exposed portion 510 of the first exposed portion of the insulating substrate 51 and the exposed portion 610 of the second exposed portion of the insulating substrate 61 overlap each other in a plan view in the Z direction. The exposed portions 510 and 610 overlap. That is, at least a portion of the exposed portion 510 faces the exposed portion 610 in the Z direction.

[0348] The back metal bodies 53 and 63 are positioned on the back surfaces 51b and 61b of the insulating substrates 51 and 61. The back metal bodies 53 and 63 are exposed from the encapsulant 30. On the back metal bodies 53 and 63, the surfaces opposite to the surfaces 53a and 63a facing the insulating substrate 51 are the exposed surfaces 53b and 63b. The exposed surface 53b is exposed substantially flush with one surface 30a of the encapsulant 30. The exposed surface 63b is exposed substantially flush with the back surface 30b of the encapsulant 30. The exposed surfaces 53b and 63b form the back surfaces 50b and 60b of the substrates 50 and 60. The encapsulant 30 has a side surface 30e as a second surface connected to the first surface 30a and back surface 30b. The side surface 30e includes the Y-direction side surfaces 30c and 30d, as well as the X-direction side surface. The side surface 30e includes all sides. The second surface, side surface 30e, is a tapered surface inclined with respect to the Z direction for mold removal during molding. Side surface 30e has a draft angle. In the prior embodiment, for convenience, the draft angle is omitted in the illustration. Side surface 30e has a bent portion near the approximate center in the Z direction, and as it approaches the first surface 30a and the back surface 30b from the bent portion, it approaches the semiconductor element 40 in a plan view in the Z direction. In other words, in a plan view, the bent portion is on the outside, and the first surface 30a and the back surface 30b are on the inside. Hereinafter, the first surface 30a and the back surface 30b of the encapsulant 30 may be referred to as the first surface 30a and 30b.

[0349] As shown in Figures 84 and 86, the substrates 50 and 60 have laminates 500 and 600. Laminate 500 is a two-layer laminate consisting of an insulating substrate 51 and a back metal body 53. Similarly, laminate 600 is a two-layer laminate consisting of an insulating substrate 61 and a back metal body 63. In laminates 500 and 600, the sides connecting the surfaces 51a, 61a of the insulating substrates 51 and 61 to the exposed surfaces 53b, 63b of the back metal bodies 53 and 63 have a so-called V-cut shape. The sides of laminates 500 and 600 have a shape where the central portion is convex outward relative to the upper surfaces 51a, 61a and the lower exposed surfaces 53b, 63b.

[0350] The sides of the laminates 500 and 600 have first inclined sections 501 and 601, second inclined sections 502 and 602, and intermediate sections 503 and 603. First, the laminate 500 will be described.

[0351] The first inclined portion 501 is a portion within a predetermined range from the surface 51a. In a plan view, the first inclined portion 501 has an inclination where the distance from the center 50sc is closest at the upper end on the surface 51a side and further away at the lower end than at the upper end. In other words, in the first inclined portion 501, the lower end is located outside the upper end. As shown in Figure 85, the first inclined portion 501 is provided on the edge of the substrate 50. The first inclined portion 501 is annular in shape so as to surround the surface metal body 52.

[0352] In this embodiment, the first inclined portion 501 has an inclination that, in the Z direction, moves away from the surface 51a, and in the plan view, moves away from the center 50sc. That is, in the upper part of the laminate 500 including the first inclined portion 501, the area perpendicular to the Z direction on the surface 51a is smallest, and the area increases as it moves away from the surface 51a. The inclination of the first inclined portion 501 can tolerate manufacturing variations. Macroscopically, the first inclined portion 501 has the inclination described above. The first inclined portion 501 is a tapered surface.

[0353] The second inclined portion 502 is a portion within a predetermined range from the exposed surface 53b. In a plan view, the second inclined portion 502 has an inclination where the distance from the center 50sc is closest at the lower end on the exposed surface 53b side, and further away at the upper end than at the lower end. In other words, in the second inclined portion 502, the upper end is located outside the lower end. The second inclined portion 502, like the first inclined portion 501, is provided on the edge of the substrate 50. The second inclined portion 502 is annular in shape so as to surround the back surface metal body 53.

[0354] In this embodiment, the second inclined portion 502 has an inclination that, in the Z direction, moves away from the exposed surface 53b and away from the center 50sc in a plan view. That is, in the lower part of the laminate 500 including the second inclined portion 502, the area is smallest at the exposed surface 53b and increases as it moves away from the exposed surface 53b. The inclination of the second inclined portion 502 can tolerate manufacturing variations. Macroscopically, the second inclined portion 502 has the inclination described above. The second inclined portion 502 is a tapered surface. If the first inclined portion 501 is a forward taper, then the second inclined portion 502 is a reverse taper.

[0355] The intermediate section 503 is connected to the first inclined section 501 and the second inclined section 502. The intermediate section 503 is the part that connects the first inclined section 501 and the second inclined section 502 and has a predetermined length in the Z direction. The intermediate section 503 is the vertex portion of the side surface of the laminate 500. The side surface of the laminate 500 is furthest from the center 50sc at the intermediate section 503. The intermediate section 503 is the outermost part of the laminate 500 in a plan view. At the intermediate section 503, the area of ​​the laminate 500 perpendicular to the Z direction is the largest. At the intermediate section 503, the area of ​​the laminate 500 is approximately constant. The distance of the first inclined section 501 from the center 50sc in a plan view decreases as it moves away from the intermediate section 503. The distance of the second inclined section 502 from the center 50sc in a plan view decreases as it moves away from the intermediate section 503.

[0356] The laminate 600 has the same configuration as the laminate 500. The first inclined portion 601 is a predetermined range from the surface 61a. In a plan view, the first inclined portion 601 has an inclination where the distance from the center 60sc is closest at the upper end on the surface 61a side and further away at the lower end than at the upper end. In other words, in the first inclined portion 601, the lower end is located outside the upper end. The first inclined portion 601 is provided on the edge of the substrate 60. The first inclined portion 601 is annular in shape so as to surround the surface metal body 62.

[0357] In this embodiment, the first inclined portion 601 has an inclination that, as it moves away from the surface 61a in the Z direction, it moves away from the center 60sc in a plan view. In other words, in the upper part of the laminate 600 including the first inclined portion 601, the area perpendicular to the Z direction on the surface 61a is smallest, and the area increases as it moves away from the surface 61a. The inclination of the first inclined portion 601 can tolerate manufacturing variations. Macroscopically, the first inclined portion 601 has the inclination described above. The first inclined portion 601 is a tapered surface.

[0358] The second inclined portion 602 is a portion within a predetermined range from the exposed surface 63b. In a plan view, the second inclined portion 602 has an inclination where the distance from the center 60sc is closest at the lower end on the exposed surface 63b side and further away at the upper end than at the lower end. In other words, in the second inclined portion 602, the upper end is located outside the lower end. The second inclined portion 602 is provided on the edge of the substrate 60, similar to the first inclined portion 501. The second inclined portion 602 is annular in shape so as to surround the back surface metal body 63.

[0359] In this embodiment, the second inclined portion 602 has an inclination that, in the Z direction, moves away from the exposed surface 63b and away from the center 60sc in a plan view. In other words, in the lower part of the laminate 600 including the second inclined portion 602, the area is smallest at the exposed surface 63b and increases as it moves away from the exposed surface 63b. The inclination of the second inclined portion 602 can tolerate manufacturing variations. Macroscopically, the second inclined portion 602 has the inclination described above. The second inclined portion 602 is a tapered surface. If the first inclined portion 601 is a forward taper, then the second inclined portion 602 is a reverse taper.

[0360] The intermediate section 603 is connected to the first inclined section 601 and the second inclined section 602. The intermediate section 603 is the part that connects the first inclined section 601 and the second inclined section 602 and has a predetermined length in the Z direction. The intermediate section 603 is the vertex of the side surface of the laminate 600. The side surface of the laminate 600 is furthest from the center 60sc at the intermediate section 603. The intermediate section 603 is the outermost part of the laminate 600 in a plan view. The laminate 600 has the largest area at the intermediate section 603. The area of ​​the laminate 600 is approximately constant at the intermediate section 603. The distance of the first inclined section 601 from the center 60sc in a plan view decreases as it moves away from the intermediate section 603. The distance of the second inclined section 602 from the center 60sc in a plan view decreases as it moves away from the intermediate section 603.

[0361] <Dimensions and angles> Next, the dimensions and angles of laminates 500 and 600 will be explained based on Figure 87. Figure 87 corresponds to Figure 86 and shows the dimensions and angles. In the following explanation, laminate 500 will be used as an example.

[0362] The length L11 shown in FIG. 87 is the length of the first inclined portion 501 in plan view, that is, the width of the annular first inclined portion 501. The length L12 is the length of the second inclined portion 502 in plan view, that is, the width of the annular second inclined portion 502. The length L21 is the length of the first inclined portion 501 in the Z direction, that is, the height of the first inclined portion 501. The length L22 is the length of the second inclined portion 502 in the Z direction, that is, the height of the second inclined portion 502. The length L23 is the length of the intermediate portion 503 in the Z direction, that is, the height of the intermediate portion 503. The length L24 is the length of the insulating base material 51 in the Z direction, that is, the thickness of the insulating base material 51. The length L25 is the length of the back surface metal body 53 in the Z direction, that is, the thickness of the back surface metal body 53.

[0363] The angle R1 is the inclination angle of the back surface metal body 53 with respect to the Z direction, which is the thickness direction of the semiconductor element 40, in the first inclined portion 501. The angle R2 is the inclination angle of the back surface metal body 53 with respect to the Z direction in the second inclined portion 502. The angle R3 is the inclination angle of the insulating base material 51 with respect to the Z direction in the first inclined portion 501. The angle R4 is the inclination angle of the second inclined portion 502 with respect to the exposed surface 53b of the back surface metal body 53. The angle R5 is the inclination angle of the side surface 30e with respect to the one surface 30a of the sealing body 30.

[0364] As shown in FIG. 87, in the present embodiment, the length of the second inclined portion 502 is shorter than the length of the first inclined portion 501. That is, the relationship L11>L12 is satisfied. The angle R1 satisfies the relationship 0°<R1≦45°, and the angle R2 satisfies the relationship 0°<R2<45°. The closer the angle R1 is to 45°, the more effectively the heat generated by the semiconductor element 40 can be diffused. The closer the angle R2 is to 45°, the lower the thermal resistance can be, as will be described later.

[0365] Furthermore, the first inclined portion 501 is provided from the insulating base material 51 to the back surface metal body 53, and the second inclined portion 502 is provided on the back surface metal body 53. That is, the relationship of L21 > L24 and L22 < L25 is satisfied. In the configuration including the intermediate portion 503, the intermediate portion 503 is provided on the back surface metal body 53. That is, the relationship of L24 < (L24 + L25 - L23) / 2 is satisfied.

[0366] Furthermore, in the configuration where the first inclined portion 501 is provided from the insulating base material 51 to the back surface metal body 53, the inclination angle of the back surface metal body 53 and the inclination angle of the insulating base material 51 are substantially equal. That is, the relationship of R1 = R3 is satisfied.

[0367] Furthermore, the inclination angle of the second inclined portion 502 with respect to the exposed surface 53b of the back surface metal body 53 is smaller than the inclination angle of the side surface 30e (second surface) with respect to the one surface 30a (first surface) of the sealing body 30. That is, the relationship of R4 < R5 is satisfied. Although the description is omitted, the laminate 600 also has the same configuration as the laminate 500.

[0368] <Method for manufacturing a laminate> Next, an example of the method for manufacturing the above-described laminate 500 will be described. First, a mother substrate having a two-layer structure of an insulating base material 51 containing resin and a back surface metal body 53 is formed. Next, the surface 51a of the insulating base material 51 and both sides of the exposed surface 53b are simultaneously cut (V-cut) with a blade. In this cutting, the first inclined portion 501 and the second inclined portion 502 are formed without completely separating the mother substrate. In the mother substrate, adjacent laminates 500 are connected at the intermediate portion 503. Then, by separating (cutting) the adjacent laminates 500 at the intermediate portion 503, a laminate 500 having a V-cut-shaped side surface can be obtained.

[0369] Figure 88 is a side view of the laminate 500 obtained by the manufacturing method described above. Due to cutting (machining) with a blade, the first inclined portion 501 has cutting marks 501a along the circumferential direction. Similarly, the second inclined portion 502 has cutting marks 502a along the circumferential direction. In order to separate adjacent laminates 500 at the intermediate portion 503, the intermediate portion 503 has an uneven portion 503a. Although not explained here, the laminate 600 is also formed by the same method as the laminate 500.

[0370] <Summary of the 9th Embodiment> In this embodiment, the sides of the laminates 500 and 600 have first inclined portions 501 and 601 and second inclined portions 502 and 602. In other words, the sides have a bent shape (approximately V-shape). As a result, even if delamination that occurs in the sealant 30 starting from the interface with the exposed surfaces 53b and 63b progresses along the second inclined portions 502 and 602, the bent shape can suppress its progression to the first inclined portions 501 and 601. Therefore, it is possible to suppress the progression of delamination to the surface metal bodies 52 and 62, the semiconductor element 40, and the joints between the surface metal bodies 52 and 62 and the semiconductor element 40. In other words, it is possible to suppress the concentration of thermal stress on the surface metal bodies 52 and 62 and the semiconductor element 40, and prevent a decrease in connection reliability. Thus, reliability can be ensured.

[0371] Because it has second inclined portions 502 and 602, it is also possible to suppress the back metal bodies 53 and 63 from falling off (detaching) from the sealant 30 when the above-mentioned peeling occurs.

[0372] Heat ideally spreads at a 45-degree angle. In this embodiment, the laminates 500 and 600 have first inclined portions 501 and 601 on the semiconductor element 40 side in the Z direction. As a result, the heat generated by the semiconductor element 40 diffuses above the bent portion, i.e., in the portion corresponding to the first inclined portions 501 and 601. On the other hand, by having second inclined portions 502 and 602, the heat transfer path in the portion corresponding to the second inclined portions 502 and 602 is narrower than the heat transfer path in the portion corresponding to the first inclined portions 501 and 601. A narrower heat transfer path results in greater thermal resistance. In this embodiment, the length L12 of the second inclined portions 502 and 602 is made shorter than the length L11 of the first inclined portions 501 and 601 (L11 > L12). As a result, compared to a configuration that satisfies L11 ≤ L12, the Z-direction length L22 of the second inclined portions 502 and 602 can be shortened, and consequently the thermal resistance below the bent portion can be reduced. In other words, the heat diffused in the upper portion of the laminate 500 and 600 can be efficiently dissipated from the exposed surfaces 53b and 63b. Therefore, the semiconductor device 20 of this embodiment can ensure reliability while improving heat dissipation.

[0373] The first inclined portions 501 and 601 may be provided on the insulating substrates 51 and 61, and the second inclined portions 502 and 602 may be provided on the back metal bodies 53 and 63. Alternatively, the first inclined portions 501 and 601 may be provided on the insulating substrates 51 and 61, and the second inclined portions 502 and 602 may be provided across the insulating substrates 51 and 61 and the back metal bodies 53 and 63. In this embodiment, the first inclined portions 501 and 601 are provided across the insulating substrates 51 and 61 and the back metal bodies 53 and 63, and the second inclined portions 502 and 602 are provided on the back metal bodies 53 and 63. In other words, the bent portions are located within the back metal bodies 53 and 63. Therefore, even if peeling that occurs on the sealant 30 starting from the interface with the exposed surfaces 53b and 63b progresses along the second inclined portions 502 and 602, it is possible to suppress the peeling from progressing to the interface with the insulating substrates 51 and 61. This prevents thermal stress from concentrating on the insulating substrates 51 and 61, thereby suppressing a decrease in insulation reliability. In other words, reliability can be further enhanced.

[0374] The first inclined portions 501 and 601 and the second inclined portions 502 and 602 may be configured to be continuous. In the present embodiment, intermediate portions 503 and 603 are provided between the first inclined portions 501 and 601 and the second inclined portions 502 and 602. In this configuration, the intermediate portions 503 and 603 form bent portions. By providing the intermediate portions 503 and 603, as described above, even when cutting (machining) simultaneously from both the front surfaces 51a and 61a of the insulating substrates 51 and 61 and the exposed surfaces 53b and 63b of the back surface metal bodies 53 and 63, contact between the blades can be avoided. Further, since the intermediate portions 503 and 603 are provided on the back surface metal bodies 53 and 63, progress of peeling to the interface with the insulating substrates 51 and 61 can be suppressed as described above.

[0375] In a configuration in which the first inclined portions 501 and 601 are provided from the insulating substrates 51 and 61 to the back surface metal bodies 53 and 63, the inclination angle R1 of the back surface metal bodies 53 and 63 and the inclination angle R3 of the insulating substrates 51 and 61 may be made different. For example, when R1 < R3, since thermal stress concentrates at the ends of the insulating substrates 51 and 61 containing resin, there is a risk of deterioration of the insulation performance. When R1 > R3, thermal stress concentrates at the interface between the insulating substrates and the back surface metal bodies 53 and 63, and there is a risk of interface peeling. In the present embodiment, the inclination angle R1 and the inclination angle R3 are made substantially equal (R1 = R3). That is, in the first inclined portions 501 and 601, the inclined surfaces of the insulating substrates 51 and 61 and the inclined surfaces of the back surface metal bodies 53 and 63 are substantially flush and continuous. The inclined surfaces of the insulating substrates 51 and 61 and the inclined surfaces of the back surface metal bodies 53 and 63 are continuous and form one flat surface. Thereby, concentration of thermal stress at the triple point of the sealing body 30, the insulating substrates 51 and 61, and the back surface metal bodies 53 and 63 can be suppressed.

[0376] The inclination angles R4 of the second inclined portions 502 and 602 with respect to the exposed surfaces 53b and 63b may be set to be greater than or equal to the inclination angle R5 of the side surface 30e (second surface) with respect to the first surfaces 30a and 30b of the sealing body 30. In the present embodiment, the inclination angle R4 is made smaller than the inclination angle R5 (R4 < R5). As described in the previous embodiment (see, for example, FIG. 72), when the semiconductor element 40 generates heat, the semiconductor device 20 is warped. As described above, if a configuration that forms a warp shape with high heat dissipation is adopted, peeling is likely to occur at the interface between the back surface metal bodies 53 and 63 and the sealing body 30 due to the warp convex in the Z direction. By adopting a configuration that satisfies the relationship of R4 < R5, even if peeling occurs, it is possible to suppress the back surface metal bodies 53 and 63 from falling off the sealing body 30.

[0377] In the present embodiment, the exposed portion 510 of the insulating base material 51, which is the first exposed portion, and the exposed portion 610 of the insulating base material 61, which is the second exposed portion, overlap each other in a plan view in the Z direction. Thereby, it is possible to suppress the imbalance in the arrangement of the surface metal body 52 of the substrate 50, which is the first substrate, and the surface metal body 62 of the substrate 60, which is the second substrate, and thus suppress the imbalance in the warp of the semiconductor device 20. It is possible to suppress the occurrence of interfacial peeling between the back surface metal bodies 53 and 63 and the sealing body 30 on the side where the deformation is large due to the uneven warp.

[0378] In the present embodiment, the first inclined portion 501 and the second inclined portion 502 have cutting marks 501a and 502a along the circumferential direction. By having the cutting marks 501a and 502a, an anchor effect occurs and the adhesive force with the sealing body 30 is increased. Thereby, it is possible to suppress the sealing body 30 from peeling off from the laminated bodies 500 and 600. Note that cutting marks along the circumferential direction may be provided only on one of the first inclined portion 501 and the second inclined portion 502. In the present embodiment, since the intermediate portion 503 also has the concavo-convex portions 503a, it is possible to expect suppression of peeling due to the anchor effect.

[0379] <Modification Example> An example of a semiconductor device 20 with a double-sided heat dissipation structure comprising a pair of substrates 50 and 60 has been shown, but it is not limited to this. It can also be applied to a semiconductor device 20 with a single-sided heat dissipation structure comprising only the substrate 50 to which the drain electrode 40D (first main electrode) is connected. In a configuration comprising a pair of substrates 50 and 60, the above-described structure (V-cut shape) may be applied to only one of the substrates 50 and 60.

[0380] An example has been shown in which the semiconductor device 20 includes semiconductor elements 40H and 40L, but it is not limited to this. It may include only one semiconductor element 40 that constitutes one of the arms. The semiconductor device 20 may include, for example, only one semiconductor element 40.

[0381] The configuration described in this embodiment can be combined with any of the configurations described in the first embodiment, second embodiment, third embodiment, fourth embodiment, fifth embodiment, sixth embodiment, seventh embodiment, eighth embodiment, and modified examples.

[0382] (Tenth embodiment) This embodiment is a modification based on the prior embodiment, and the description of the prior embodiment can be referenced. To improve connection reliability, the sintered members, which are the joining material, may be arranged in a predetermined configuration, as described in this embodiment.

[0383] <Semiconductor device> First, the semiconductor device 20 according to this embodiment will be described based on Figure 89. Figure 89 is a cross-sectional view corresponding to Figure 5. For convenience, the external connection terminal 90 is not shown in Figure 89.

[0384] The semiconductor device 20 of this embodiment has the same configuration as the configuration described in the prior embodiment (see Figures 2 to 13). As shown in Figure 89, the semiconductor device 20 comprises semiconductor elements 40 (40H, 40L), substrates 50 and 60 which are wiring members arranged to sandwich the semiconductor elements 40 in the Z direction, and a sealant 30. The surface metal body 52 of the substrate 50, which is the first wiring member, is connected to the drain electrode 40D, which is the first main electrode of the semiconductor element 40. The surface metal body 62 of the substrate 60, which is the second wiring member, is connected to the source electrode 40S, which is the second main electrode of the semiconductor element 40, via a conductive spacer 70, which is the second wiring member. The sealant 30 seals the semiconductor elements 40, the substrates 50 and 60, and the conductive spacer 70. The source electrode 40S and the conductive spacer 70 are joined by a sintered member 101A, which is a bonding material 101.

[0385] <Semiconductor elements> Next, the semiconductor element 40 will be described based on Figures 90 and 91. Figure 90 is a plan view showing the semiconductor element 40 (40H). Figure 91 is an enlarged view of region XCI in Figure 89. Figure 91 is a cross-sectional view corresponding to the XCI-XCI line in Figure 90. Although Figure 91 shows semiconductor element 40H as an example, semiconductor element 40L has a similar configuration, so it will be described as semiconductor element 40 below.

[0386] As described above, the semiconductor element 40 has a semiconductor substrate 41 on which a switching element is formed. The semiconductor substrate 41 has a substantially rectangular planar shape. The drain electrode is provided on one side of the semiconductor substrate 41, and the source electrode 40S and pad 40P are provided on the back side of the semiconductor substrate 41. The source electrode 40S has a multilayer structure. The source electrode 40S has a base electrode 42 and a connecting electrode 43. The pad 40P has a similar configuration to the source electrode 40S.

[0387] The semiconductor element 40 further has a protective film 44. The protective film 44 is an insulating film provided on the back surface of the semiconductor substrate 41 so as to cover the peripheral edge of the source electrode 40S. For example, polyimide or silicon nitride can be used as the material for the insulating film. The protective film 44 has an opening 440 that defines the connection region of the source electrode 40S. The opening 440 exposes the source electrode 40S so that it can be joined. The protective film 44 also has an opening 441 that defines the connection region of the pad 40P. Both openings 440 and 441 are through holes that penetrate the protective film 44 in the Z direction. Of the source electrode 40S (connecting electrode 43), the portion exposed from the opening 440 of the protective film 44 forms a joint with the sintered member 101A.

[0388] The protective film 44 in this embodiment is made of polyimide. The protective film 44 covers the peripheral edge 420 of the base electrode 42, which will be described later. The protective film 44 is not provided in a predetermined range of scribe regions from the outer peripheral edge of the semiconductor substrate 41, for example. The opening shape of the opening 440, that is, the inner circumferential surface 442 of the protective film 44 that defines the opening 440, is substantially rectangular in plan. The inner circumferential surface 442 is sometimes referred to as the inner circumferential edge or opening edge.

[0389] The base electrode 42 is a metal layer formed adjacent to the semiconductor substrate 41 in the multilayer source electrode 40S. The base electrode 42 may also be referred to as the lower electrode, lower layer electrode, wiring electrode, base layer, or first metal layer. The base electrode 42 is connected to the back surface of the semiconductor substrate 41. The base electrode 42 is formed using a material mainly composed of Al (aluminum), for example. In this embodiment, an AlSi-based alloy such as AlSi or AlSiCu is used as the material.

[0390] In a plan view, the base electrode 42 encloses an element region (active region) of the semiconductor substrate 41 (not shown) and extends to the outer peripheral region surrounding the element region. The peripheral edge 420 of the base electrode 42 has a roughly rectangular annular shape in plan. The peripheral edge 420 is covered by a protective film 44.

[0391] The connecting electrode 43 is stacked on the base electrode 42. The connecting electrode 43 is also referred to as the upper electrode, upper electrode, upper layer electrode, upper layer, or second metal layer. The connecting electrode 43 contains at least a precious metal such as Au (gold), Ag (silver), Pt (platinum), or Pd (palladium) for bonding with the sintered member 101A. The connecting electrode 43 may also contain base metals along with the precious metals.

[0392] The connecting electrode 43 in this embodiment contains Ni (nickel). Ni is harder than the Al alloy that constitutes the base electrode 42. The connecting electrode 43 contains Ni and a noble metal, such as Au or Ag. The connecting electrode 43 is formed in multiple layers, for example by a plating method. At least a portion of the noble metal in the connecting electrode 43 diffuses into the sintered member 101A during bonding.

[0393] The connecting electrode 43 is stacked on the base electrode 42 at the opening 440 of the protective film 44. The outer peripheral end of the connecting electrode 43 is in contact with the inner peripheral surface 442 of the protective film 44 all around.

[0394] <Joining structure> Next, the junction structure of the semiconductor element 40 will be described based on Figures 90 to 92. In Figure 90, the outer edge of the sintered member 101A is shown by a dashed line, and the outer edge of the conductive spacer 70 is shown by a dashed line. Figure 92 is a cross-sectional view showing the arrangement of the sintered member 101A. Figure 92 corresponds to Figure 91. In the following, "inside" and "outside" refer to the relative positional relationship with the center of the semiconductor element 40 as the reference position. The side closer to the center is the inside, and the side further from the center is the outside.

[0395] In this embodiment, the substrate 60 and the conductive spacer 70 are wiring members (second wiring members) electrically connected to the source electrode 40S. As shown in Figures 90 and 91, the sintered member 101A is interposed between the source electrode 40S of the semiconductor element 40 and the conductive spacer 70. The sintered member 101A joins the source electrode 40S and the conductive spacer 70.

[0396] The sintered member 101A is made of Ag or Cu. The sintered member 101A is a sintered body made of Ag particles or Cu particles. The sintered member 101A can be joined at a lower temperature compared to solder. As shown in Figure 92, the sintered member 101A is positioned with a predetermined distance L30 between it and the inner circumferential surface 442 of the protective film 44. As shown in Figures 90 to 92, the sintered member 101A is positioned inside the inner circumferential surface 442. The sintered member 101A has, for example, a substantially rectangular shape in plan. The outer circumferential edge of the sintered member 101A is not in contact with the protective film 44 around its entire circumference. In other words, the inner circumferential surface 442 of the protective film 44 encloses the sintered member 101A in plan view.

[0397] The conductive spacer 70 has a metal film (not shown) on the bonding surface with the sintered member 101A. The metal film, like the connecting electrode 43, contains at least a noble metal. In this embodiment, the metal film is a plating film containing Ni and a noble metal, such as Au or Ag.

[0398] As shown in Figures 90 to 92, the conductive spacer 70 is positioned inside the inner circumferential surface 442. The conductive spacer 70 has, for example, a roughly rectangular shape in plan view. The outer circumferential end of the conductive spacer 70 is positioned outside the outer circumferential end of the sintered member 101A in plan view, or approximately coincides with it. In other words, the conductive spacer 70 encloses the sintered member 101A in plan view, or is positioned approximately coincides with the sintered member 101A. In this embodiment, the conductive spacer 70 encloses the sintered member 101A.

[0399] <Joining method> Next, the method for forming the above-described joint structure, that is, the joining method, will be explained based on Figure 93. Figure 93 is a cross-sectional view showing the joining method. Figure 93 corresponds to Figure 91.

[0400] In this embodiment, a sintered sheet 105 is used to form the sintered member 101A. The sintered sheet 105 is sometimes referred to as a sintered film. The sintered sheet 105 contains Ag or Cu. As shown in Figure 93, the sintered sheet 105 is placed on the source electrode 40S (connecting electrode 43) of the semiconductor element 40. The sintered sheet 105 has a predetermined size that does not come into contact with the protective film 44 in a plan view.

[0401] Next, the conductive spacer 70 is placed on the sintered sheet 105. Then, while heating, pressure is applied from the conductive spacer 70 side using a pressurizing device (not shown). As a result, the sintered sheet 105 is pushed and expanded between the opposing surfaces of the connecting electrode 43 and the conductive spacer 70, reducing its thickness and sintering to become the sintered member 101A. The size of the sintered sheet 105 is determined so that the sintered member 101A is in the predetermined positional relationship described above with respect to the inner circumferential surface 442 of the protective film 44 and the conductive spacer 70.

[0402] <Simulation Results> Figure 94 shows the results of a thermal stress simulation. In this simulation, the strain amplitude generated in the base electrode 42 was measured during a power cycle test that alternately repeated temperatures between room temperature and 150°C. Figure 94 shows the relationship between the distance L30 and the strain amplitude. In Figure 94, a distance L30 of 0 (zero) corresponds to a position that coincides with the inner surface 442 of the protective film 44 in a plan view. Negative values ​​for distance L30 indicate the distance inward from the inner surface 442, while positive values ​​indicate the distance outward.

[0403] As shown in Figure 94, it was found that when the distance L30 is 5 μm or more, the strain amplitude generated in the base electrode 42 becomes almost 0 (zero). In this embodiment, based on this finding, the predetermined distance L30 is set to 5 μm.

[0404] <Summary of the 10th Embodiment> Figure 95 shows a connection structure using solder 101B as the bonding material 101. Figure 95 corresponds to Figure 93. In the case of solder 101B, bonding is performed by reflowing the solder 101B. During bonding, the molten solder 101B wets and spreads on the surface of the connecting electrode 43. As a result, as shown by the dashed line in Figure 95, a triple point is formed between the sealant 30, the source electrode 40S (connecting electrode 43), and the solder 101B (bonding material 101). Thermal stress concentrates at the triple point due to the difference in coefficients of linear expansion. The thermal stress concentrates in the base electrode 42 directly below the outer edge of the connecting electrode 43. Therefore, there is a risk of cracks forming in the base electrode 42, and consequently, damage to the semiconductor substrate 41.

[0405] In this embodiment, a sintered member 101A is used instead of solder 101B. The sintered member 101A is formed by heating at a temperature lower than its melting point. Unlike solder 101B, the sintered member 101A does not become molten during joining. Compared to solder 101B, the sintered member 101A has lower wettability to the connecting electrode 43 and the conductive spacer 70. Therefore, during joining, the sintered member 101A does not wet and spread across the surface of the connecting electrode 43 and the conductive spacer 70 like solder 101B.

[0406] Because the sintered member 101A is easily held in a predetermined position, it can be positioned with a predetermined distance L30 between it and the inner circumferential surface 442 of the protective film 44. As a result, a triple point is not formed between the sealant 30, the source electrode 40S (connecting electrode 43), and the sintered member 101A (joining material 101). Therefore, thermal stress concentration is suppressed, and a semiconductor device 20 with high connection reliability can be provided. In addition, the sintered member 101A has a higher thermal conductivity than the solder 101B. This also improves heat dissipation.

[0407] The distance L30 is not particularly limited. The sintered member 101A only needs to be at least separated from the inner circumferential surface 442. In this embodiment, the distance L30 between the sintered member 101A and the inner circumferential surface 442 of the protective film 44 is set to 5 μm or more. This effectively reduces the strain amplitude of the base electrode 42 due to thermal stress. In other words, connection reliability can be further improved.

[0408] In a plan view, the positional relationship between the conductive spacer 70 and the sintered member 101A is not particularly limited. For example, in a plan view, the sintered member 101A may protrude from the conductive spacer 70. As described above, the sintered member 101A is formed by sintering Ag particles or Cu particles through heating and pressurization. The portion that protrudes from the conductive spacer 70 is not pressurized and remains unsintered, potentially falling off as conductive foreign matter. In other words, there is a risk of short circuits occurring.

[0409] In this embodiment, in a plan view, the inner circumferential surface 442 of the protective film 44 encloses the conductive spacer 70, and the conductive spacer 70 coincides with or encloses the sintered member 101A. This allows pressure to be applied to the entire surface of the sintered member 101A (sintered sheet 105) before sintering via the conductive spacer 70. Therefore, contact between the sintered member 101A and the protective film 44 can be avoided while suppressing the generation of sintering residue.

[0410] <Variation> An example has been shown in which a sintered sheet 105 is used to form the sintered member 101A, but the method is not limited to this. For example, a sintered paste in which Ag particles or Cu particles are dispersed in a solvent may be used. The sintered sheet 105 is easier to hold in a predetermined position than the sintered paste.

[0411] In the example shown, the second wiring member to which the source electrode 40S is connected comprises a substrate 60, which is a wiring board, and a conductive spacer 70, but it is not limited to this. Instead of the conductive spacer 70, a protrusion may be provided on the surface metal body 62. In other words, the second wiring member may be configured to have only the substrate 60 and no conductive spacer 70. In this case, the sintered member 101A is interposed between the tip surface of the protrusion on the surface metal body 62 and the source electrode 40S (connecting electrode 43).

[0412] An example of a substrate 50 is shown as the first wiring member, but it is not limited to this. A metal plate (lead frame) may be used instead of the substrate 50. An example of a substrate 60 is shown as the second wiring member, but it is not limited to this. A metal plate (lead frame) may be used instead of the substrate 60. The second wiring member may have a metal plate and a conductive spacer 70, or a protrusion may be provided on the metal plate instead of the conductive spacer 70.

[0413] An example has been shown in which the semiconductor device 20 includes semiconductor elements 40H and 40L, but it is not limited to this. It may include only one semiconductor element 40 that constitutes one of the arms. The semiconductor device 20 may include, for example, only one semiconductor element 40.

[0414] The configuration described in this embodiment can be combined with any of the configurations described in the first embodiment, second embodiment, third embodiment, fourth embodiment, fifth embodiment, sixth embodiment, seventh embodiment, eighth embodiment, ninth embodiment, and modified examples.

[0415] (11th embodiment) This embodiment is a modification based on the prior embodiment, and the description of the prior embodiment can be applied by reference. To improve heat dissipation, a sintered member may be used at the joint between the main electrode and the wiring member, as described in this embodiment.

[0416] <Semiconductor device> First, the semiconductor device 20 according to this embodiment will be described based on Figure 96. Figure 96 is a cross-sectional view corresponding to Figure 5. For convenience, the external connection terminal 90 is not shown in Figure 96.

[0417] The semiconductor device 20 of this embodiment has the same configuration as the configuration described in the prior embodiment (see Figures 2 to 13). As shown in Figure 96, the semiconductor device 20 comprises semiconductor elements 40 (40H, 40L), substrates 50 and 60 which are wiring members arranged to sandwich the semiconductor elements 40 in the Z direction, and a sealant 30. The surface metal body 52 of the substrate 50 is connected to the drain electrode 40D, which is the first main electrode of the semiconductor element 40. The surface metal body 62 of the substrate 60 is connected to the source electrode 40S, which is the second main electrode of the semiconductor element 40, via a conductive spacer 70. The sealant 30 seals the semiconductor elements 40, the substrates 50 and 60, and the conductive spacer 70. The drain electrode 40D and the surface metal body 52 of the substrate 50 are joined by a sintered member 100A which is a bonding material 100.

[0418] <Arrangement of sintered member and uneven oxide film> Next, the arrangement of the sintered member 100A and the uneven oxide film 520 relative to the semiconductor element 40 will be described based on Figures 97 to 99. Figure 97 is an enlarged view of region XCVII in Figure 96. Figure 98 is a plan view showing the positional relationship between the semiconductor element 40, the sintered member 100A, and the uneven oxide film 520. Figure 99 is an enlarged view of region XCVIX in Figure 97.

[0419] As shown in Figures 97 and 98, the upper surface 52a of the surface metal body 52 has a mounting portion 529a, an outer peripheral portion 529b, and an intermediate portion 529c. The uneven oxide film 520 is not provided on the mounting portion 529a, but is provided on the outer peripheral portion 529b and the intermediate portion 529c.

[0420] The mounting portion 529a includes a portion that overlaps with the semiconductor element 40 (drain electrode 40D) in a plan view in the Z direction, and is the portion to which the drain electrode 40D is joined via the sintered member 100A. The outer peripheral portion 529b includes a portion that is outside the outer peripheral edge 402 of the semiconductor element 40 in a plan view, and is the portion that surrounds the semiconductor element 40. The intermediate portion 529c is the portion between the mounting portion 529a and the outer peripheral portion 529b, and surrounds the mounting portion 529a. In this embodiment, the mounting portion 529a substantially coincides with the semiconductor element 40 (drain electrode 40D) in a plan view. The intermediate portion 529c has a substantially rectangular annular shape in plan, and the inner peripheral edge of the intermediate portion 529c substantially coincides with the outer peripheral edge 402 of the semiconductor element 40. The entire area of ​​the intermediate portion 529c is located outside the semiconductor element 40 in a plan view.

[0421] As shown in Figures 97 to 99, the surface metal body 52 of the substrate 50 has an uneven oxide film 520, similar to the configuration described in the prior embodiment (see Figures 67 and 74). As shown in Figure 99, the surface metal body 52 has a base material 521 and a metal film 522 and an uneven oxide film 520 provided on the surface of the base material 521.

[0422] The metal film 522 of this embodiment has a base film mainly composed of Ni and a top film mainly composed of a noble metal, such as Au or Ag, that can be bonded to the sintered member 100A. Specifically, a Ni plating film containing P and an Au plating film are used as the base film. Multiple recesses 523 are formed on the outer peripheral portion 529b of the upper surface 52a of the metal film 522. No recesses 523 are formed on the mounting portion 529a and the intermediate portion 529c. In the portion where no recesses 523 are formed, the thickness of the metal film 522 is, for example, about 10 μm. That is, the thickness of the film before irradiation with laser light is about 10 μm. The recesses 523 are formed by irradiation with pulsed laser light. One recess 523 is formed for each pulse. On the outer peripheral portion 529b, the surface of the metal film 522 has a scale-like appearance due to the multiple recesses 523. The outer periphery 529b is the laser beam irradiation area, while the mounting area 529a and the intermediate area 529c are non-irradiated areas.

[0423] The uneven oxide film 520 is formed on the metal film 522. The uneven oxide film 520 is not formed on the mounting portion 529a, but is formed on the outer peripheral portion 529b and the intermediate portion 529c, which are the parts surrounding the mounting portion 529a. As described in the prior embodiment, the uneven oxide film 520 is formed by irradiating the metal film 522 with laser light. The uneven oxide film 520 is a laser-irradiated film formed by irradiation with laser light. The main component of the uneven oxide film 520 is an oxide of the main component metal of the metal film 522.

[0424] In the outer peripheral region 529b, i.e., the laser light irradiation area, the average thickness of the uneven oxide film 520 is said to be 10 nm to several hundred nm. The uneven oxide film 520 is formed to conform to the surface irregularities of the metal film 522, which has recesses 523. Furthermore, the surface of the uneven oxide film 520 has irregularities formed at a pitch finer than the width of the recesses 523. In other words, very fine irregularities (roughened areas) are formed. To put it another way, multiple protrusions 520a (columnar bodies) are formed at a fine pitch. For example, the average width of the protrusions 520a is 1 nm to 300 nm, and the average spacing between the protrusions 520a is 1 nm to 300 nm. Also, the average height of the protrusions 520a is 10 nm to several hundred nm.

[0425] The uneven oxide film 520 is formed by irradiating the metal film 522 with laser light, causing melting and deposition of the surface layer of the metal film 522. Therefore, it is formed not only in the outer peripheral portion 529b, which is the laser light irradiation area, but also in the vicinity of the outer peripheral portion 529b. In this embodiment, the uneven oxide film 520 is formed over the entire area of ​​the intermediate portion 529c, which is not irradiated by the laser light, while the uneven oxide film 520 is not formed on the mounting portion 529a. The width of the intermediate portion 529c, which has the uneven oxide film 520 over its entire area, is, for example, 0.2 mm to 0.3 mm.

[0426] The average thickness of the uneven oxide film 520 in the intermediate section 529c is thinner than the average thickness of the uneven oxide film 520 in the outer peripheral section 529b, but thicker than the native oxide film, because the intermediate section 529c is not directly irradiated with laser light. Specifically, it is between 0.1 nm and 10 nm. In addition, the height of the protrusions 520a on the surface of the uneven oxide film 520 is lower than that of the outer peripheral section 529b. Specifically, it is between 0.1 nm and 10 nm. The average width and average spacing of the protrusions 520a are about the same as those in the outer peripheral section 529b.

[0427] Thus, the uneven oxide film 520 has a thick film portion 520X and a thin film portion 520Y. The thick film portion 520X is the portion of the uneven oxide film 520 that is located in the laser light irradiation area, i.e., the outer peripheral portion 529b. The thin film portion 520Y is the portion of the uneven oxide film 520 that is located in the non-irradiated area of ​​the laser light, i.e., the intermediate portion 529c. The thin film portion 520Y has a thinner film thickness than the thick film portion 520X, and the height of the protrusions 520a is lower. The thick film portion 520X is located in the outer peripheral portion 529b. The thin film portion 520Y is located in the intermediate portion 529c.

[0428] Because the height of the protrusions 520a is greater in the thick film portion 520X than in the thin film portion 520Y, the sealant 30 becomes entangled, creating an anchoring effect. Furthermore, the contact area with the sealant 30 increases. As a result, the sealant 30 adheres tightly to the outer peripheral portion 529b. The thick film portion 520X is sometimes referred to as the roughened portion or the adhesion portion.

[0429] The sintered member 100A is made of Ag or Cu, similar to the sintered member 101A described in the prior embodiment. The sintered member 100A is a sintered body made of Ag particles or Cu particles. The sintered member 100A can be joined at a lower temperature compared to solder. The sintered member 100A is formed by heating and pressurizing a sintered sheet or sintered paste. In a plan view, the sintered member 100A protrudes outward from the outer peripheral edge 402 of the semiconductor element 40. In a plan view, the sintered member 100A is positioned to overlap with the mounting portion 529a and the intermediate portion 529c. In this embodiment, the outer peripheral edge of the sintered member 100A substantially coincides with the outer peripheral edge of the intermediate portion 529c. In a plan view, the sintered member 100A overlaps with the entire area of ​​the mounting portion 529a and the entire area of ​​the intermediate portion 529c.

[0430] <Summary of the 11th Embodiment> As described above, the intermediate portion 529c has a thin film portion 520Y of the uneven oxide film 520. Due to the presence of the thin film portion 520Y, the wettability of the intermediate portion 529c to solder is lower than that of the mounting portion 529a. As a result, the solder is less likely to spread from the mounting portion 529a to the intermediate portion 529c.

[0431] In this embodiment, a sintered member 100A is used instead of solder. The sintered member 100A is formed by heating at a temperature lower than its melting point. The sintered member 100A does not become molten like solder during joining. The sintered member 100A does not wet and spread across the surface of the surface metal body 52 like solder during joining.

[0432] During pressure sintering, the sintered member 100A is expanded between the opposing surfaces of the drain electrode 40D and the surface metal body 52. ​​This expansion allows the sintered member 100A to be positioned not only on the mounting portion 529a but also on the intermediate portion 529c. The sintered member 100A does not spread by wetting, but is expanded by pressure and comes into contact with the thin film portion 520Y. As a result, not only the joint between the sintered member 100A and the mounting portion 529a, but also the contact portion between the sintered member 100A and the intermediate portion 529c functions as a heat dissipation path. This provides a semiconductor device 20 with high heat dissipation. Furthermore, the sintered member 100A has a higher thermal conductivity than solder. This also enhances heat dissipation.

[0433] Furthermore, the height of the protrusion 520a of the thin film portion 520Y is lower than that of the thick film portion 520X. In other words, the adhesion force of the intermediate portion 529c to the sealant 30 is lower than that of the outer peripheral portion 529b. As a result, the sealant 30 does not adhere well to the intermediate portion 529c. In this embodiment, the sintered member 100A is in contact with the intermediate portion 529c. The sintered member 100A covers the portion with low adhesion force on the upper surface 52a. Therefore, it is possible to suppress the peeling of the sealant 30 from the upper surface 52a around (near) the semiconductor element 40. This suppresses the concentration of thermal stress on the joint portion of the sintered member 100A and the drain electrode 40D, thereby improving connection reliability.

[0434] In this embodiment, the entire intermediate portion 529c is located outside the semiconductor element 40. This allows for a larger junction between the sintered member 100A and the mounting portion 529a. Furthermore, the contact area between the sintered member 100A located outside the semiconductor element 40 and the intermediate portion 529c also functions as a heat dissipation path. Therefore, heat dissipation can be further enhanced.

[0435] <Variation> While an example has been shown where the sintered member 100A overlaps with the entire intermediate portion 529c, the method is not limited to this. The sintered member 100A only needs to overlap with at least a portion of the intermediate portion 529c. In other words, the sintered member 100A only needs to be in contact with at least a portion of the thin film portion 520Y of the uneven oxide film 520. This expands the heat dissipation path and improves heat dissipation.

[0436] The arrangement of the intermediate portion 529c is not limited to the example described above. The intermediate portion 529c may be located outside the semiconductor element 40 only in a portion of its width. By providing at least a portion of the intermediate portion 529c outside the semiconductor element 40 in the width direction, the junction can be enlarged and the heat dissipation path can be enlarged. Therefore, heat dissipation can be improved.

[0437] Furthermore, at least a portion of the intermediate portion 529c may be located inside the outer peripheral edge 402 of the semiconductor element 40 in the width direction. This allows the sintered member 100A to contact the thin film portion 520Y (intermediate portion 529c) to improve heat dissipation, while also bringing the outer peripheral portion 529b closer to the semiconductor element 40. In other words, it is possible to suppress the peeling of the sealant 30 around the semiconductor element 40.

[0438] In the examples shown in Figures 100 and 101, the intermediate portion 529c straddles the outer peripheral edge 402 of the semiconductor element 40 in a plan view. That is, a portion of the widthwise intermediate portion 529c is located outside the outer peripheral edge 402, and another portion is located inside the outer peripheral edge 402. The sintered member 100A overlaps with the entire area of ​​the mounting portion 529a and the entire area of ​​the intermediate portion 529c in a plan view. As described above, this makes it possible to improve heat dissipation while suppressing the peeling of the encapsulant 30 around the semiconductor element 40. Figures 100 and 101 show modified examples. Figure 100 corresponds to Figure 97, and Figure 101 corresponds to Figure 98.

[0439] In the examples shown in Figures 102 and 103, the outer edge of the intermediate portion 529c substantially coincides with the outer edge 402 of the semiconductor element 40 in a plan view. The outer edge of the sintered member 100A also substantially coincides with the outer edge 402 of the semiconductor element 40 in a plan view. As a result, the outer edge 529b (thick film portion 520X) is located adjacent to the semiconductor element 40 in a plan view. Therefore, while improving heat dissipation through contact of the sintered member 100A with the intermediate portion 529c, peeling of the sealant 30 around the semiconductor element 40 can be more effectively suppressed. Figures 102 and 103 show modified examples. Figure 102 corresponds to Figure 97, and Figure 103 corresponds to Figure 98.

[0440] In the example shown in Figure 104, a portion of the outer peripheral portion 529b overlaps with the semiconductor element 40 in a plan view. The intermediate portion 529c is located inside the outer peripheral edge 402 of the semiconductor element 40. Figure 104 shows a modified example. Figure 104 corresponds to Figure 98. In this case, the sintered member 100A may contact only the thin film portion 520Y. The sintered member 100A may contact both the thin film portion 520Y and the portion directly below the semiconductor element 40 in the thick film portion 520X.

[0441] An example has been shown in which the uneven oxide film 520 is provided only on the surface metal body 52 to which the drain electrode 40D is connected, but it is not limited to this. In addition to the surface metal body 52, it may also be provided on the side surface of the conductive spacer 70 to which the source electrode 40S is connected, and / or on the surface metal body 62 of the substrate 60. As described above, the thick film portion 520X of the uneven oxide film 520 has the function of increasing the adhesion force with the sealant 30 and the function of suppressing the wetting spread of the solder, which is the bonding material. The uneven oxide film 520 is best provided in places where you want to suppress solder overflow or where you want to increase the adhesion force with the sealant 30.

[0442] While a circuit board 50 is shown as an example of a wiring component, the circuit is not limited to this. A metal plate (lead frame) may be used instead of the circuit board 50. Similarly, a metal plate (lead frame) may be used instead of the circuit board 60. Instead of the conductive spacer 70, a protrusion may be provided on the metal plate on the source electrode 40S side.

[0443] An example has been shown in which the semiconductor device 20 includes semiconductor elements 40H and 40L, but it is not limited to this. It may include only one semiconductor element 40 that constitutes one of the arms. The semiconductor device 20 may include, for example, only one semiconductor element 40.

[0444] The configuration described in this embodiment can be combined with any of the configurations described in the first embodiment, second embodiment, third embodiment, fourth embodiment, fifth embodiment, sixth embodiment, seventh embodiment, eighth embodiment, ninth embodiment, tenth embodiment, and modified examples.

[0445] (12th embodiment) This embodiment is a modification based on a prior embodiment, and the description of the prior embodiment can be referenced. In order to suppress cracks occurring in the main electrode, the sintered member, which is the bonding material, may be made into a multilayer structure, as described in this embodiment.

[0446] <Semiconductor device> First, the semiconductor device 20 according to this embodiment will be described based on Figure 105. Figure 105 is a cross-sectional view corresponding to (part of) Figure 7. For convenience, the external connection terminals 90 and bonding wires 110 are omitted from the illustration in Figure 105.

[0447] The semiconductor device 20 of this embodiment has the same configuration as the configuration described in the prior embodiment (see Figures 2 to 13). As shown in Figure 105, the semiconductor device 20 comprises a semiconductor element 40 (40H), substrates 50 and 60 which are wiring members arranged to sandwich the semiconductor element 40 in the Z direction, and a encapsulant 30. The semiconductor element 40 has a drain electrode 40D, which is a first main electrode, on one side of the semiconductor substrate 41, and a source electrode 40S, which is a second main electrode, on the back side. The drain electrode 40D is the main electrode on the high-potential side, and the source electrode 40S is the main electrode on the low-potential side. The source electrode 40S is provided on the same side as the pad 40P.

[0448] The surface metal body 52 of the substrate 50, which is the first wiring member, is connected to the drain electrode 40D. The substrate 60 and conductive spacer 70, which are the second wiring members, are connected to the source electrode 40S. The encapsulant 30 encapsulates the semiconductor element 40, the substrates 50 and 60, and the conductive spacer 70. Although not shown, the semiconductor device 20 includes the semiconductor element 40L.

[0449] The drain electrode 40D and the surface metal body 52 of the substrate 50 are joined by a sintered member 100A, which is a bonding material 100, similar to the configuration described in the prior embodiment (see Figure 97). The source electrode 40S and the conductive spacer 70 are joined by a multilayer bonding material 101C, which is a bonding material 101.

[0450] <Multilayer bonding material and its surrounding structure> Next, the multilayer bonding material 101C and its surrounding structure will be described based on Figures 106 and 107. Figure 106 is an enlarged view of region CVI in Figure 105. For convenience, the pad is not shown in Figure 106. Figure 107 shows the relationship between the Young's modulus and yield stress of the base electrode 42, the sintered layer 106, and the fragile layer 107. In the strain-stress diagram shown in Figure 107, the solid line represents the fragile layer 107, the dashed line represents the sintered layer 106, and the dotted line represents the base elec...

Claims

[Claim 1] A semiconductor element (40) comprising an upper arm element (40H) constituting the upper arm of an upper arm circuit and a lower arm element (40L) constituting the lower arm of the upper arm circuit, having a first main electrode (40D) provided on one surface and a second main electrode (40S) provided on the back surface opposite to the one surface in the thickness direction, A first wiring member (50) is arranged on the first main electrode side in the thickness direction of the plate so as to enclose the semiconductor element in a plan view in the thickness direction of the plate, and has a first insulating substrate (51) and a first surface metal body (52) arranged on the first insulating substrate and electrically connected to the first main electrode, A second wiring member (60) is arranged on the second main electrode side in the thickness direction of the plate so as to enclose the semiconductor element in the plan view, and has a second insulating substrate (61) and a second surface metal body (62) arranged on the second insulating substrate and electrically connected to the second main electrode, A conductive spacer (70) electrically connects the second main electrode and the second surface metal body, A joint portion (81) electrically connects the second main electrode of the upper arm element and the first main electrode of the lower arm element, The device comprises the semiconductor element, at least a portion of the first wiring member including the surface facing the semiconductor element, and a sealing body (30) that seals at least a portion of the second wiring member including the surface facing the semiconductor element, The first surface metal body has a first power supply wiring (54) connected to the first main electrode of the upper arm element, and a first relay wiring (55) connected to the first main electrode of the lower arm element and the joint portion. A gap filled with the sealing material is formed between the first power supply wiring and the first relay wiring. The second surface metal body has a second power supply wiring (64) connected to the second main electrode of the lower arm element via the conductive spacer, and a second relay wiring (65) connected to the second main electrode of the upper arm element via the joint and the conductive spacer. A gap filled with the sealing material is formed between the second power supply wiring and the second relay wiring. A semiconductor device in which the distance between the joint portion and the conductive spacer connected to the second main electrode of the lower arm element is narrower than the distance between the joint portion and the conductive spacer connected to the second main electrode of the upper arm element.

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