Manufacturing method for semiconductor devices
The method addresses the challenge of forming recesses with varying dimensions under semiconductor electrodes by using chlorine-based plasma etching to create narrower and deeper gate recesses, enhancing transistor performance and reducing resistance.
Patent Information
- Authority / Receiving Office
- JP · JP
- Patent Type
- Patents
- Current Assignee / Owner
- MITSUBISHI ELECTRIC CORP
- Filing Date
- 2025-10-15
- Publication Date
- 2026-06-30
AI Technical Summary
Existing methods struggle to simultaneously form recesses of different widths and depths under the gate, source, and drain electrodes in semiconductor devices, leading to separate design requirements and limitations in improving gain characteristics and reducing resistance.
A manufacturing method involving dry etching with a chlorine-based plasma gas using a resist mask to form recesses of varying widths and depths simultaneously, where the gate electrode recess is narrower and deeper than the source and drain electrode recesses, allowing for improved transistor performance and reduced resistance.
This method enhances transistor gain characteristics and reduces resistance by forming recesses with precise control over width and depth, improving switching characteristics and productivity while maintaining precise electrode spacing.
Smart Images
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Abstract
Description
Technical Field
[0001] The present disclosure relates to a semiconductor device and a method for manufacturing the same.
Background Art
[0002] Techniques have been proposed for embedding the lower part of a gate electrode in a recess to improve the gain characteristics of a transistor (see, for example, Patent Document 1). In addition, techniques have been proposed for embedding the lower parts of source and drain electrodes in a recess to reduce resistance (see, for example, Patent Document 2).
[0003] Conventionally, recesses have been formed by F-based plasma etching such as CF4 + H2 (see, for example, Patent Document 3). In this manufacturing method, the etching rate becomes slower as the opening width of the mask becomes smaller. Therefore, when forming recesses of different widths simultaneously, the depth of the recess becomes shallower as the width of the recess becomes narrower.
Prior Art Documents
Patent Documents
[0004]
Patent Document 1
Patent Document 2
Patent Document 3
Summary of the Invention
Problems to be Solved by the Invention
[0005] The width and depth of the recess under the gate electrode need to be designed separately from the width and depth of the recesses under the source and drain electrodes. Therefore, it has not been possible to form both recesses simultaneously.
[0006] This disclosure was made to solve the problems described above, and its purpose is to provide a semiconductor device and a method for manufacturing the same that can reduce resistance while improving gain characteristics. [Means for solving the problem]
[0007] Regarding this disclosure Manufacturing method for semiconductor devices teeth, The method comprises the steps of: forming a barrier layer on a channel layer; forming a resist mask on the barrier layer having a first opening, a second opening wider than the first opening, and a third opening; dry etching the barrier layer with a chlorine-based plasma gas using the resist mask to simultaneously form a first recess, a second recess, and a third recess at positions corresponding to the first opening, the second opening, and the third opening, respectively; and forming a gate electrode, a source electrode, and a drain electrode on the barrier layer, wherein the lower part of the gate electrode is embedded in the first recess, the lower part of the source electrode is embedded in the second recess, the lower part of the drain electrode is embedded in the third recess, the width of the first recess is narrower than the widths of the second and third recesses, and the depth of the first recess is deeper than the depths of the second and third recesses. It is characterized by the following: [Effects of the Invention]
[0008] In this disclosure, the gain characteristics of the transistor can be improved by forming a first recess at the bottom of the gate electrode. Furthermore, the resistance can be reduced by forming a second recess and a third recess at the bottom of the source electrode and drain electrode. [Brief explanation of the drawing]
[0009] [Figure 1] This is a cross-sectional view showing a semiconductor device according to an embodiment. [Figure 2] This is a cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment. [Figure 3] This is a cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment. [Figure 4] This is a cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment. [Figure 5] This is a diagram showing a dry etching apparatus. [Figure 6] This diagram shows the relationship between the opening width of the mask and the depth of the recess. [Modes for carrying out the invention]
[0010] Figure 1 is a cross-sectional view showing a semiconductor device according to an embodiment. A channel layer 2, a barrier layer 3, and a cap layer 4 are formed in order on a substrate 1. A first recess 5a, a second recess 5b, and a third recess 5c are formed in the barrier layer 3, penetrating the cap layer 4. A gate electrode 6a, a source electrode 6b, and a drain electrode 6c are formed on the barrier layer 3 and the cap layer 4. The lower part of the gate electrode 6a is embedded in the first recess 5a. The lower part of the source electrode 6b is embedded in the second recess 5b. The lower part of the drain electrode 6c is embedded in the third recess 5c.
[0011] The substrate 1 is made of SiC. The channel layer 2 and cap layer 4 are made of GaN. The barrier layer 3 is made of AlGaN. The gate electrode 6a has a multilayer structure of Ti, Pt, Au, and Ta. The source electrode 6b and drain electrode 6c have a multilayer structure of Ti, Nb, and Pt. A two-dimensional electron gas 2DEG is formed in the channel layer 2.
[0012] The width w1 of the first recess 5a at the bottom of the gate electrode 6a is narrower than the widths w2 of the second recess 5b and the third recess 5c at the bottom of the source electrode 6b and the drain electrode 6c. Specifically, the width w1 of the first recess 5a is 0.5 μm or less. The widths w2 of the second recess 5b and the third recess 5c are 2 to 10 μm.
[0013] The depth d1 of the first recess 5a is deeper than the depths d2 of the second recess 5b and the third recess 5c. The bottom of the first recess 5a, the second recess 5b, and the third recess 5c are located within the barrier layer 3. The thickness of the barrier layer 3 is 20 nm or less. The depths of the second recess 5b and the third recess 5c are the same.
[0014] Next, the method for manufacturing the semiconductor device described above will be explained. Figures 2 to 4 are cross-sectional views showing the method for manufacturing a semiconductor device according to the embodiment. First, as shown in Figure 2, a channel layer 2, a barrier layer 3, and a cap layer 4 are formed in order on a substrate 1. Next, a resist mask 7 is formed on the cap layer 4, having a first opening 7a and a second opening 7b and a third opening 7c that are wider than the first opening 7a.
[0015] Next, as shown in FIG. 3, the cap layer 4 and the barrier layer 3 are dry-etched with a chlorine-based plasma gas using the resist mask 7. As a result, as shown in FIG. 4, first recesses 5a, second recesses 5b, and third recesses 5c are simultaneously formed at positions corresponding to the first opening 7a, the second opening 7b, and the third opening 7c, respectively. Then, the resist mask 7 is removed, and as shown in FIG. 1, gate electrodes 6a, source electrodes 6b, and drain electrodes 6c are formed on the cap layer 4 and the barrier layer 3.
[0016] Subsequently, the dry etching for forming the above-described first recesses 5a, second recesses 5b, and third recesses 5c will be described. FIG. 5 is a diagram showing a dry etching apparatus. A lower electrode 9 is disposed inside a chamber 8. A coil 10 is wound around the chamber 8. A wafer 11 having a channel layer 2, a barrier layer 3, and a cap layer 4 is placed on the lower electrode 9.
[0017] A chlorine-based gas is supplied into the chamber 8. The chlorine-based gas is a mixed gas of BCl3 and Cl2. A gas obtained by diluting the chlorine-based gas with a stable gas such as Ar or N2 is often used, and the proportion of the chlorine-based gas is relatively high in that gas.
[0018] RF power is supplied from an RF power source 12 to the lower electrode 9. RF power is supplied from an RF power source 13 to the coil 10. The chlorine-based gas supplied to the chamber 8 is plasmaized by high-frequency energy, and the cap layer 4 and the barrier layer 3 on the surface of the wafer 11 are etched with the chlorine-based plasma gas. Note that this dry etching apparatus is of an ICP (Inductively Coupled Plasma) type, but a CCP (Capacitively Coupled Plasma) type may also be used. In the case of the CCP type, the uniformity of the plasma can be ensured by sandwiching the wafer between a lower electrode and an upper electrode.
[0019] By setting the RF output of the lower electrode 9 to 20W or less, chemical etching becomes more dominant than physical etching when etching GaN-based materials with chlorine-based plasma gas. As a result, areas of the resist mask 7 with narrower apertures are etched more deeply. Figure 6 shows the relationship between the aperture width of the mask and the depth of the recess.
[0020] Therefore, the RF output of the lower electrode 9 is set to 20W or less, and the cap layer 4 and barrier layer 3 are dry-etched with a chlorine-based plasma gas. It is even more preferable to set the RF output of the lower electrode 9 to 10W or less. As a result, when the first recess 5a, the second recess 5b, and the third recess 5c are formed simultaneously, the width of the first recess 5a can be made narrower than the widths of the second recess 5b and the third recess 5c, and the depth of the first recess 5a can be made deeper than the depths of the second recess 5b and the third recess 5c.
[0021] The width w1 of the first recess 5a at the bottom of the gate electrode 6a is determined according to the desired transistor characteristics. On the other hand, the etching depth is determined by the opening width of the resist mask 7. Therefore, if you want to adjust the relative recess depth between the source / drain side and the gate side, adjust the recess width w2 on the source / drain side. Also, the recess depth depends on the etching time.
[0022] As described above, in this embodiment, the threshold voltage is reduced by forming a first recess 5a below the gate electrode 6a, thereby improving the gain characteristics of the transistor and reducing power consumption. Furthermore, the contact resistance can be reduced by forming a second recess 5b and a third recess 5c below the source electrode 6b and drain electrode 6c. In addition, since the width of the first recess 5a is narrower than the widths of the second recess 5b and the third recess 5c, the gate length of the gate electrode 6a is reduced, improving the switching characteristics.
[0023] Furthermore, since the first recess 5a, the second recess 5b, and the third recess 5c are formed simultaneously, productivity is improved compared to forming them separately. In addition, by performing etching using the same resist mask 7, the distance between the gate electrode 6a and the source electrode 6b, which affects the transistor characteristics, can be precisely set. [Explanation of symbols]
[0024] 2 Channel layer, 3 Barrier layer, 4 Cap layer, 5a First recess, 5b Second recess, 5c Third recess, 6a Grid electrode, 6b Source electrode, 6c Drain electrode, 7 Resist mask, 7a First opening, 7b Second opening, 7c Third opening, 9 Bottom electrode
Claims
1. A step of forming a barrier layer on top of a channel layer, A step of forming a resist mask on the barrier layer having a first opening, a second opening wider than the first opening, and a third opening, A step of dry etching the barrier layer with a chlorine-based plasma gas using the resist mask to simultaneously form a first recess, a second recess, and a third recess at positions corresponding to the first opening, the second opening, and the third opening, respectively. The process includes forming a gate electrode, a source electrode, and a drain electrode on the barrier layer. The lower part of the gate electrode is embedded in the first recess. The lower part of the source electrode is embedded in the second recess. The lower part of the drain electrode is embedded in the third recess. The width of the first recess is narrower than the widths of the second recess and the third recess. A method for manufacturing a semiconductor device, characterized in that the depth of the first recess is deeper than the depths of the second recess and the third recess.
2. A wafer having the channel layer and the barrier layer is placed on the lower electrode. The method for manufacturing a semiconductor device according to claim 1, characterized in that the RF output of the lower electrode is set to 20W or less and the barrier layer is dry-etched with the chlorine-based plasma gas to simultaneously form the first recess, the second recess and the third recess.
3. The method for manufacturing a semiconductor device according to claim 2, characterized in that the RF output of the lower electrode is set to 10W or less and the barrier layer is dry-etched with the chlorine-based plasma gas to simultaneously form the first recess, the second recess and the third recess.