CDS circuit and its operating method, and image sensor including CDS circuit

Abstract

To provide a CDS (Correlated Double Sampling) circuit, an operating method of the same, and an image sensor including the CDS circuit.SOLUTION: A CDS circuit includes: a first comparator that operates on the basis of a first bias current during a first period and a fourth period in which pixels operate in a low conversion gain mode, and compares pixel voltages output from the pixels with a ramp signal; and a second comparator that operates on the basis of a second bias current during a second period and a third period in which pixels operate in a high conversion gain mode, and compares the pixel voltages output from the pixels with the ramp signal. The first comparator operates on the basis of a third bias current lower than the first bias current during the second period and the third period. The second comparator operates on the basis of a fourth bias current lower than the second bias current during the first period and the fourth period.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] The present invention relates to an image sensor, and more particularly to a CDS circuit and its operating method, as well as an image sensor including a CDS circuit. [Background technology]

[0002] An image sensor is a device that captures (acquires) a two-dimensional or three-dimensional image of an object. An image sensor generates an image of an object by utilizing a photoelectric conversion element that responds to the intensity of light reflected from the object. In recent years, with the development of CMOS (Complementary Metal-Oxide Semiconductor) technology, CMOS image sensors utilizing CMOS have become widely used. Recently, dual conversion gain technology, where one pixel has two conversion gains, has been developed to increase the dynamic range of image sensors. Research is needed on CDS (Correlated Double Sampling) circuits and their operating methods for processing signals from pixels with dual conversion gains. [Overview of the project] [Problems that the invention aims to solve]

[0003] The problem that the present invention aims to solve is to provide a CDS circuit and a method of operating the same that can process the pixel signals of pixels having dual conversion gains within one frame and reduce power consumption, as well as an image sensor including the CDS circuit. [Means for solving the problem]

[0004] To achieve the above objective, a CDS circuit according to the technical concept of the present invention includes: a first comparator that operates on a first bias current during first and fourth periods when the pixel operates in low conversion gain (LCG) mode and compares the pixel voltage output from the pixel with a ramp signal; and a second comparator that operates on a second bias current during second and third periods when the pixel operates in high conversion gain (HCG) mode and compares the pixel voltage output from the pixel with the ramp signal, wherein during the second and third periods the first comparator can operate on a third bias current lower than the first bias current, and during the first and fourth periods the second comparator can operate on a fourth bias current lower than the second bias current. [Effects of the Invention]

[0005] According to the CDS circuit, operating method of the CDS circuit, and image sensor including the CDS circuit based on the technical concept of the present invention, the first comparator of the CDS circuit processes the LCG signal output when the pixel is operating in LCG mode, and the second comparator processes the HCG signal output when the pixel is operating in HCG mode. When the second comparator processes the HCG signal, the bias current of the first comparator is reduced, and when the first comparator processes the LCG signal, the bias current of the second comparator is reduced. As a result, the constant current of the CDS circuit is reduced, and the power consumption of the CDS circuit and the image sensor is reduced. [Brief explanation of the drawing]

[0006] [Figure 1] This is a block diagram showing an image sensor according to an embodiment of the present invention. [Figure 2] This is a circuit diagram showing an example of a pixel embodiment according to an exemplary embodiment of the present invention. [Figure 3] This is a timing diagram of an image sensor according to an exemplary embodiment of the present invention. [Figure 4]A block diagram showing a CDS circuit according to an exemplary embodiment of the present invention. [Figure 5] A flowchart showing an operation method of an image sensor according to an exemplary embodiment of the present invention. [Figure 6A] A circuit diagram showing a first comparator according to an exemplary embodiment of the present invention. [Figure 6B] A circuit diagram showing a second comparator according to an exemplary embodiment of the present invention. [Figure 7A] A drawing exemplarily showing a bias circuit 163L of the first comparator in FIG. 6A. [Figure 7B] A drawing exemplarily showing a bias circuit 163L of the first comparator in FIG. 6A. [Figure 8] A timing diagram showing an operation method of an image sensor according to an exemplary embodiment of the present invention. [Figure 9A] A timing diagram showing a bias current control method for a first comparator and a second comparator of a CDS circuit according to an exemplary embodiment of the present invention. [Figure 9B] A timing diagram showing a bias current control method for a first comparator and a second comparator of a CDS circuit according to an exemplary embodiment of the present invention. [Figure 10] A circuit diagram showing an embodiment example of a pixel according to an exemplary embodiment of the present invention. [Figure 11A] A plan view of a pixel according to an exemplary embodiment of the present invention. [Figure 11B] A vertical cross-sectional view of the pixel in FIG. 11A. [Figure 12] A timing diagram showing an operation method of an image sensor according to an exemplary embodiment of the present invention. [Figure 13A] A circuit diagram showing an embodiment example of a pixel according to an exemplary embodiment of the present invention. [Figure 13B] A plan view of the pixel in FIG. 13A. [Figure 14] A block diagram of an electronic device including a multi-camera module. [Figure 15] A block diagram of an electronic device including a multi-camera module. [Figure 16] Figures 14 and 15 are detailed block diagrams of the camera module. [Modes for carrying out the invention]

[0007] Figure 1 is a block diagram showing an image sensor according to an embodiment of the present invention.

[0008] The image sensor 100 can be mounted on electronic devices that have image or light sensing capabilities. For example, the image sensor 100 can be used in cameras, smartphones, wearable devices, the Internet of Things (IoT), tablet PCs (Personal Computers), PDAs (Personal Digital Assistants), and PMPs (Portable Multimedia Devices). The image sensor 100 can be mounted on electronic devices such as players and navigation systems. Furthermore, the image sensor 100 can be mounted as a component in electronic devices such as vehicles, furniture, manufacturing equipment, doors, and various measuring instruments.

[0009] The image sensor 100 includes a pixel array 110, a row driver 120, a ramp signal generator 130, a counting code generator 140, an analog-to-digital conversion circuit 150 (hereinafter referred to as the ADC circuit), a data output circuit 180, and a timing controller 190. The image sensor 100 may further include a signal processing unit 195.

[0010] The pixel array 110 includes multiple row lines RL, multiple column lines CL, and multiple pixels PX connected to the multiple row lines RL and the multiple column lines CL and arranged in a matrix.

[0011] Each of the multiple pixels PX includes at least one photoelectric conversion element, which can use to sense light and output an image signal, which is an electrical signal from the sensed light. For example, the photoelectric conversion element may include a photodiode, phototransistor, photogate, or pinned photodiode.

[0012] Each of the multiple pixels PX can sense light in a specific spectral region. For example, multiple pixels PX may include a red pixel for converting light in the red spectral region into an electrical signal, a green pixel for converting light in the green spectral region into an electrical signal, and a blue pixel for converting light in the blue spectral region into an electrical signal. However, it is not limited to these, and multiple pixels may also include white pixels. As another example, multiple pixels may also include pixels combined in different color configurations, such as yellow pixels, cyan pixels, and green pixels.

[0013] A color filter array is positioned above multiple pixels PX to transmit light in a specific spectral region, and the hue that each pixel can perceive is determined by the color filter positioned above each of the multiple pixels. However, it is not limited to this, and in one embodiment, in the case of a particular photoelectric conversion element, the level of the electrical signal applied to the photoelectric conversion element can also convert light in a specific wavelength band into an electrical signal.

[0014] In the pixel array 110 according to this embodiment, the pixel PX may have a dual conversion gain. This dual conversion gain includes a low conversion gain and a high conversion gain. Here, the conversion gain refers to the rate at which the charge stored in the floating diffusion node FD (Figure 2) is converted into voltage. The charge generated by the photoelectric conversion element is transmitted to and stored in the floating diffusion node FD, and the charge stored in the floating diffusion node FD is also converted into voltage by the conversion gain. At that time, the conversion gain is also variable by the capacitance of the floating diffusion node FD; if the capacitance increases, the conversion gain decreases, and if the capacitance decreases, the conversion gain increases.

[0015] Pixel PX can operate in either a low conversion gain mode (hereinafter referred to as LCG mode) where the capacitance of the floating diffusion node FD is high, or a high conversion gain mode (hereinafter referred to as HCG mode) where the capacitance of the floating diffusion node FD is low. Even if the charge stored in the floating diffusion node FD is the same, the voltage of the floating diffusion node FD in HCG mode is higher than the voltage of the floating diffusion node FD in LCG mode. The configuration of Pixel PX and its operation in each conversion gain mode will be described in detail later with reference to Figures 2 and 3.

[0016] In the first image data generated by multiple pixels PX of the pixel array 110 operating in HCG mode, dark areas are clearly represented, and in the second image data generated by multiple pixels PX of the pixel array 110 operating in LCG mode, bright areas are clearly represented.

[0017] In one embodiment, within one frame in which the pixel array 110 receives light once (i.e., one exposure of the image sensor 100) and is scanned, each of a plurality of pixels PX can operate consecutively in HCG mode and LCG mode during the corresponding reading period (or horizontal period), thereby enabling the generation of the first image data and the second image data within one frame period. The first and second images are merged to generate an image having a high dynamic range in which bright areas (high-illumination areas) and dark areas (low-illumination areas) are clearly depicted. Thus, dual conversion gain within one frame is referred to as intra-scene dual conversion gain, and hereafter, dual conversion gain as referred to in this invention means intra-scene dual conversion gain.

[0018] The row driver 120 drives the pixel array 110 row by row. The row driver 120 decodes a row control signal (e.g., an address signal) received from the timing controller 190 and, in response to the decoded row control signal, can select at least one row line from among the row lines constituting the pixel array 110. For example, the row driver 120 can generate a selection signal to select one of several rows. The pixel array 110 then outputs a pixel signal, for example, a pixel voltage, from the row selected by the selection signal provided by the row driver 120. The pixel signal may include a reset signal and an image signal.

[0019] The row driver 120 can transmit control signals for outputting pixel signals to the pixel array 110, and the pixel PX can output pixel signals by operating in response to the control signals. In one embodiment, the row driver 120 can generate and provide control signals to the pixel array 110 that control the pixel PX to operate continuously in HCG mode and LCG mode during the reading period.

[0020] The ramp signal generator 130 can generate a ramp signal (e.g., ramp voltage) whose level rises or falls at a predetermined gradient under the control of the timing controller 190. The ramp signal RAMP is provided to each of the multiple CDS (Correlated Double Sampling) circuits 160 provided in the ADC circuit 150.

[0021] The counting code generator 140 can generate a counting code CCD under the control of the timing controller 190. The counting code CCD is provided to each of the multiple counter circuits 170. In one embodiment, the counting code generator 140 is also embodied by a Gray code generator. The counting code generator 140 can generate multiple code values ​​having a resolution based on a set number of bits as a counting code CCD. For example, if a 10-bit code is set, the counting code generator 140 can generate a counting code CCD containing 1024 code values ​​that increase or decrease sequentially.

[0022] The ADC circuit 150 includes multiple CDS circuits 160 and multiple counter circuits 170. The ADC circuit 150 can convert pixel signals (e.g., pixel voltages) input from the pixel array 110 into pixel values, which are digital signals. Each pixel signal received through each of the multiple column lines CL is converted into a pixel value, which is a digital signal, by the CDS circuit 160 and the counter circuit 170.

[0023] The CDS circuit 160 can compare a pixel signal, such as the pixel voltage, received through the column line CL with a ramp signal RAMP and output the comparison result as a comparison result signal. When the levels of the ramp signal RAMP and the pixel signal are the same, the CDS circuit 160 can output a comparison signal that transitions from a first level (e.g., logic high) to a second level (e.g., logic low). The timing of the comparison signal level transition is also determined by the level of the pixel signal.

[0024] The CDS circuit 160 can sample the pixel signal provided from the pixel PX using the correlated double sampling (CDS) method. The CDS circuit 160 can sample the reset signal received as the pixel signal, compare the reset signal with the ramp signal RAMP, and generate a comparison signal based on the reset signal. The CDS circuit 160 can store the reset signal. Subsequently, the CDS circuit 160 can sample the image signal correlated with the reset signal, compare the image signal with the ramp signal RAMP, and generate a comparison signal based on the image signal.

[0025] In one embodiment, the CDS circuit 160 may include two comparators. For example, the two comparators may also be embodied by an OTA (Operational Transconductance Amplifier) ​​(or differential amplifier). As described above, the image sensor 100 supports the intra-scene dual conversion gain of the pixel PX and can receive a reset signal in LCG mode (hereinafter referred to as the LCG reset signal) and a reset signal in HCG mode (hereinafter referred to as the HCG reset signal) from the pixel PX during the reading period. At that time, the levels of the LCG reset signal and the HCG reset signal are different, and therefore, the CDS circuit 160 includes two comparators, for example, a first comparator and a second comparator, to store the LCG reset signal and the HCG reset signal, respectively. The first comparator can process the LCG reset signal and the LCG image signal received from the pixel PX when the pixel PX is operating in LCG mode, and the second comparator can process the HCG reset signal and the HCG image signal received from the pixel PX when the pixel PX is operating in HCG mode.

[0026] In one embodiment, the bias currents of the first comparator and the second comparator are adjustable, and the second comparator can operate based on a low bias current during the period when the first comparator processes the LCG reset signal and the LCG image signal, and the first comparator can operate based on a low bias current during the period when the second comparator processes the HCG reset signal and the HCG image signal.

[0027] The counter circuit 170 can count the point in time when the level of the comparison result signal output from the CDS circuit 160 changes, and output a count value. In one embodiment, the counter circuit 170 may include a latch circuit and an arithmetic circuit. The latch circuit receives the counting code CCD from the counting code generator 140 and the comparison signal from the CDS circuit 160, and can latch the code value of the counting code CCD at the point in time when the level of the comparison signal changes. The latch circuit can latch the code value corresponding to the reset signal, for example, the reset value, and the code value corresponding to the image signal, for example, the image signal value. The arithmetic circuit can calculate the reset value and the image signal value and generate an image signal value from which the reset level of the pixel PX has been removed. The counter circuit 170 can output the image signal value from which the reset level has been removed as a pixel value.

[0028] In this embodiment, the image sensor 100 is described as including a counting code generator 140, and the counter circuit 170 includes a circuit for latching the code value of the counting code CCD received from the counting code generator 140, but is not limited thereto. In one embodiment, the image sensor 100 does not include a separate counting code generator 140, and the counter circuit 170 is also embodied by an up counter and an arithmetic circuit, which sequentially increment the count value based on a counting clock signal provided by a timing controller 190, as well as by an up / down counter and by a bit-wise inversion counter.

[0029] The data output circuit 180 can output the pixel values ​​output from the ADC circuit 150 after temporarily storing them. The data output circuit 180 includes a plurality of column memories 181 and a column decoder 182. The column memories 181 store the pixel values ​​received from the counter circuit 170. In one embodiment, each of the plurality of column memories 181 may be provided in the counter circuit 170. The plurality of pixel values ​​stored in the plurality of column memories 181 are also output as image data IDTA under the control of the column decoder 181.

[0030] The timing controller 190 outputs control signals to the row driver 120, ramp signal generator 130, counting code generator 140, ADC circuit 150, and data output circuit 180, respectively, and can control the operation or timing of the row driver 120, ramp signal generator 130, counting code generator 140, ADC circuit 150, and data output circuit 180.

[0031] The signal processing unit 195 can perform noise reduction processing, gain adjustment, waveform shaping processing, interpolation processing, white balance processing, gamma processing, edge enhancement processing, binning, and the like on the image data. In one embodiment, as the pixel array 110 operates in HCG mode and LCG mode for one frame period, the signal processing unit 195 receives first image data in HCG mode and second image data in LCG mode from the data output circuit 180, and can merge the first image data and the second image data to generate an image with a high dynamic range. In one embodiment, the signal processing unit 195 may be provided in an external processor of the image sensor 100.

[0032] Figure 2 is a circuit diagram showing an example of a pixel embodiment according to an exemplary embodiment of the present invention.

[0033] Pixel PX consists of a photodiode PD, multiple transistors such as a transmission transistor TX, a reset transistor RX, a drive transistor DX, a selection transistor SX, and a gain control transistor CGX (or a conversion gain control transistor), and a capacitor C L This includes a floating diffusion node FD, which allows capacitor C to be used. H For example, a parasitic capacitor can be formed. Capacitor C L This is a passive element having a fixed or variable capacitance, or a parasitic capacitor formed by the source / drain of the gain control transistor CGX, or a parasitic capacitor formed on another pixel PX that can be connected to the source / drain of the gain control transistor CGX.

[0034] A photodiode (PD) can convert light incident from an external source into an electrical signal. The photodiode (PD) generates an electric charge depending on the intensity of the light. The amount of charge generated by the photodiode (PD) is variable depending on the image capture environment (low or high light). For example, in a high-light environment, the amount of charge generated by the photodiode (PD) can reach its full well capacity (FWC), while in a low-light environment, this may not be the case.

[0035] The transmission transistor TX, reset transistor RX, drive transistor DX, selection transistor SX, and gain control transistor CGX can each operate in response to control signals provided by the low driver 120, such as the reset control signal RS, the transmission control signal TS, the selection signal SEL, and the gain control signal CGS.

[0036] The reset transistor RX is turned on in response to the reset control signal RS applied to its gate terminal, allowing the floating diffusion node FD to be reset based on the pixel power supply voltage VDDP. At the same time, the gain control transistor CGX is also turned on based on the gain control signal CGS received at its gate terminal, thereby applying the pixel power supply voltage VDDP to the floating diffusion node FD and resetting it.

[0037] The transmission transistor TX is turned on in response to the transmission control signal TS applied to its gate terminal, and can transmit the charge generated by the photodiode PD to the floating diffusion node FD. Charge is accumulated in the floating diffusion node FD. That is, a capacitor C is formed by the floating diffusion node FD. H When charge is accumulated in capacitor C, or when the conversion control transistor CGX is turned on, H and capacitor C L Charge accumulates there.

[0038] The charge accumulated in a floating diffusion node (FD) can generate a voltage. In other words, the charge accumulated in the floating diffusion node (FD) can be converted into a voltage. The conversion gain (the unit of conversion gain is, for example, uV / e) is determined by the capacitance of the floating diffusion node (FD) and can be inversely proportional to the magnitude of the capacitance. If the capacitance of the floating diffusion node (FD) increases, the conversion gain decreases, and if the capacitance decreases, the conversion gain increases.

[0039] The driving transistor DX can operate as a source follower based on the bias current Ibs generated by the current source CS connected to the column line CL, and can output the voltage corresponding to the voltage of the floating diffusion node FD as the pixel voltage VPIX through the selection transistor SX.

[0040] The selection transistor SX can select the pixel PX. The selection transistor SX is turned on in response to the selection signal SEL applied to the gate terminal, and can output the pixel voltage VPIX (or current) output from the driving transistor DX to the column line CL. The pixel voltage VPIX is provided to the ADC circuit 150 (FIG. 1) through the column line CL.

[0041] The gain control transistor CGX is turned on or off based on the gain control signal CGS received at the gate terminal. If the gain control transistor CGX is turned off, the floating diffusion node FD has the capacitance due to the capacitor C H and if the gain control transistor CGX is turned on, the capacitor C L is connected to the floating diffusion node FD, and the floating diffusion node FD has the capacitance due to the capacitor C H and the capacitor C L so that the capacitance increases. The conversion gain when the gain control transistor CGX is in the off state is higher than the conversion gain when the gain control transistor CGX is in the on state. When the gain control transistor CGX is in the off state, it is called the HCG mode, and when the gain control transistor CGX is in the on state, it is called the LCG mode.

[0042] Thus, the pixel PX can operate in either HCG mode or LCG mode by turning on and off the gain control transistor CGX. In HCG mode, the conversion gain of the pixel PX increases, so the gain of the circuit for processing the pixel voltage VPIX output from the pixel PX (e.g., ADC circuit 150) is relatively reduced. Therefore, the signal-to-noise ratio (SNR) of the image sensor 100 (Figure 1) increases, the minimum detectable light level decreases, and the low-light sensing performance of the image sensor 100 improves. In LCG mode, the capacitance of the floating diffusion node FD of the pixel PX is high, so the FWC increases. Therefore, the high-light sensing performance of the image sensor 100 improves.

[0043] Thus, the pixel PX provides dual conversion gains, enabling sensing of both low and high light levels, thereby expanding (or increasing) the dynamic range of the image sensor 100. Furthermore, as described with reference to Figure 1, the pixel PX can operate continuously in HCG mode and LCG mode during the reading period, allowing the image sensor 100, for example, the signal processing unit 195 (Figure 1), to merge a first image from HCG mode and a second image from LCG mode to generate an image with a high dynamic range.

[0044] Figure 3 shows a timing diagram of an image sensor according to an exemplary embodiment of the present invention. Figure 3 is a timing diagram of the image sensor when the pixel voltage is read from pixel PX in Figure 2.

[0045] During one reading period (or horizontal period), multiple pixel voltages VPIX (or multiple currents) are read from multiple pixels PX located in at least one row of the pixel array 110 (Figure 1). That is, during the reading period, each of the multiple pixels PX outputs a pixel voltage VPIX, and the pixel voltages VPIX can be converted from analog to digital by the corresponding CDS circuit 160 and counter circuit 170 of the ADC circuit 150.

[0046] Referring to both Figures 2 and 3, during the reading period, the selection signal SEL is also at an activation level, for example, logic high, and in response to the selection signal SEL, the selection transistor SX is turned on, and the pixel PX can be coupled to the column line CL. Here, the activation level of the signal means the level at which the transistor to which the signal is applied is turned on. In this invention, logic high is assumed to be the activation level, and logic low is assumed to be the deactivation level.

[0047] The reading period is divided into first to fourth sub-periods SP1 to SP4 (or first to fourth periods) by the pixel voltage VPIX output from the pixel PX. At that time, the gain control signal CGS allows the pixel PX to operate in LCG mode during the first and fourth sub-periods SP1 and SP4, and in HCG mode during the second and third sub-periods SP2 and SP3. In this way, the pixel PX can have dual conversion gains.

[0048] During the first subperiod SP1, a reset signal corresponding to the reset level of pixel PX (for example, the voltage of the reset floating diffusion node FD) is read, and at that time, when pixel PX is operating in LCG mode, an LCG reset signal representing the reset level in LCG mode is read.

[0049] In response to the activation levels of the reset control signal RS and the gain control signal CGS, the reset transistor RX and the gain control transistor CGX are turned on, and the floating diffusion node FD is reset. The HCG reset signal corresponding to the voltage of the reset floating diffusion node FD is output as the pixel voltage VPIX, and the HCG reset signal is analog-to-digital convertible. When the CDS circuit 160 (Figure 1) compares the ramp signal RAMP and the pixel voltage VPIX and outputs the comparison result signal, the counter circuit 170 (Figure 1) can generate a count value corresponding to the HCG reset signal, for example, an LCG reset value, by latching the received counting code based on the comparison result signal.

[0050] During the second sub-period SP2, a reset signal corresponding to the reset level of pixel PX is read. At that time, pixel PX operates in HCG mode, and an HCG reset signal representing the reset level in HCG mode is read.

[0051] As the gain control signal CGS transitions to an inactive level, for example, logic low, the gain control transistor CGX is turned off, and pixel PX can be switched to HCG mode. As the gain control signal CGS transitions from logic high to logic low, the coupling capacitance of the floating diffusion node FD changes, thereby changing the voltage of the floating diffusion node FD. For example, a coupling capacitor is formed between the low line RL to which the gain control signal CGS is applied and the floating diffusion node FD, and as the gain control signal CGS changes, the coupling capacitance changes. This results in an offset voltage ΔV in the voltage of the floating diffusion node FD due to the change in coupling capacitance. FD This will be added, and at that time, the offset voltage ΔV FDThis is either a positive voltage or a negative voltage.

[0052] As shown in Figure 3, the offset voltage ΔV of the floating diffusion node FD FD This causes the pixel voltage VPIX to rise or fall. That is, the pixel voltage VPIX in the second subperiod SP2, i.e., the HCG reset signal, is affected by the offset voltage ΔV of the floating diffusion node FD in relation to the LCG reset signal in the first subperiod SP1. FD It can have a value to which a negative offset voltage (for example) has been added.

[0053] During the third sub-period SP3, pixel PX operates in HCG mode, and the HCG image signal corresponding to the signal level of pixel PX is read. As the transmission control signal TS is toggled to an active level, for example, logic high, the charge generated by the photodiode PD is transmitted to and stored in the floating diffusion node FD. Based on the voltage of the floating diffusion node FD due to the amount of charge transmitted from the photodiode PD, the drive transistor DX can output an image signal. Since pixel PX operates in HCG mode, the HCG image signal is output as the pixel voltage VPIX, and the HCG image signal is analog-to-digital convertible.

[0054] During the fourth subperiod SP4, pixel PX operates in LCG mode, and the LCG image signal corresponding to the signal level of pixel PX is read. As the gain control signal CGS transitions to an active level, for example, logic high, the gain control transistor CGX is turned on, and pixel PX is changed to LCG mode. At that time, the coupling capacitance of the floating diffusion node FD is changed again. That is, the coupling capacitance of the floating diffusion node FD becomes the same as in the first subperiod SP1, and the offset voltage ΔV that was applied to the voltage of the floating diffusion node FD in the second subperiod SP2 is changed.FD It will be removed.

[0055] As the transmission control signal TS is toggled to an active level, for example, logic high, any remaining charge generated in the photodiode PD (for example, charge that remained untransmitted to the floating diffusion node FD during the third sub-period SP3) is transmitted to and stored in the floating diffusion node FD. The voltage of the floating diffusion node FD can be changed by the change in the conversion gain and the amount of charge further transmitted to the photodiode PD during the fourth sub-period SP4, and the LCG image signal corresponding to the voltage of the floating diffusion node FD is output as the pixel voltage VPIX, and the LCG image signal is analog-to-digital convertible.

[0056] The reset levels of pixel PXs differ for each individual pixel PX and also differ over time. Furthermore, the conversion circuits that convert pixel voltages to digital values, such as the CDS circuit 160 and the counter circuit 170, have different offsets between columns. This can result in deviations in the read image signal, i.e., between pixel values.

[0057] The image sensor 100 can generate an actual image signal, i.e., a pixel value representing the amount of charge generated by the photodiode PD, by first reading the reset signal during the reading period, then reading the image signal based on the reset signal using a correlated double sampling method, and subtracting the reset signal from the read image signal. This reduces the deviation between pixel values. If intra-scene dual conversion gain is provided, during the reading period, the reset signal and image signal corresponding to the HCG mode and LCG mode, respectively, can be read from the pixel PX, and actual image signals for the HCG mode and LCG mode, e.g., HCG pixel value and LCG pixel value, can be generated.

[0058] During the first sub-period SP1, the pixel PX operates in HCG mode and the LCG reset signal is read (referred to as the LCG reset ADC). During the second sub-period SP2, the pixel PX operates in HCG mode and the HCG reset signal is read (referred to as the HCG reset ADC). During the third sub-period SP3, the HCG image signal (e.g., the HCG signal voltage) is read (referred to as the HCG signal ADC). During the fourth sub-period SP4, the pixel PX operates in LCG mode and the LCG image signal (e.g., the LCG signal voltage) is read (referred to as the LCG signal ADC). In this way, the LCG reset signal, HCG reset signal, HCG image signal, and LCG image signal are read sequentially during the reading period, and such a reading method is called the RRSS (reset-reset-signal-signal) reading method.

[0059] As mentioned above, the HCG reset level and the LCG reset level are different. Therefore, in order to read the HCG image signal and the LCG image signal using a correlated double sampling method, the CDS circuit 160 is equipped with a first comparator and a second comparator. The first comparator samples and holds the LCG reset signal received as pixel voltage VPIX during the first subperiod SP1, and the second comparator samples and holds the HCG reset signal received as pixel voltage VPIX during the second subperiod SP2. Then, during the third subperiod SP3, the second comparator samples the HCG image signal received as pixel voltage VPIX in correlation with the HCG reset signal, and during the fourth subperiod SP4, the second comparator samples the LCG image signal received as pixel voltage VPIX in correlation with the LCG reset signal.

[0060] In one embodiment, the first comparator performs an auto-zero operation in the first sub-period SP1 based on the LCG reset signal, and can sample and hold the auto-zero level as the LCG reset signal. The second comparator also performs an auto-zero operation in the second sub-period SP2 based on the HCG reset signal, and can sample and hold the auto-zero level as the HCG reset signal. The auto-zero operation of both the first and second comparators eliminates noise from the reset signal and internal offsets within each of them. Furthermore, the auto-zero operation ensures that the voltage level of the pixel voltage VPXI is within the range of the voltage level at which the ramp signal RAMP changes, allowing for accurate sampling based on the ramp signal RAMP. That is, the precise moment when the voltage levels of the ramp signal RAMP and the pixel voltage VPIX coincide is determined.

[0061] Figure 4 is a block diagram showing a CDS circuit according to an exemplary embodiment of the present invention. For convenience of explanation, both the pixel PX and the counter circuit 170 are shown.

[0062] Referring to Figure 4, the CDS circuit 160 includes a first comparator (COMPL) 160L, a second comparator (COMPH) 160H, a first input switch SWI1, and a second input switch SWI2. The first comparator 160L and the second comparator 160H can also be realized by an OTA, a differential amplifier, etc. The first input switch SWI1 and the second input switch SWI2 are referred to as input switching circuits.

[0063] The first input switch SWI1 is turned on in response to the first enable signal ENL and can transmit a pixel signal, such as the pixel voltage VPIX, received from the pixel PX through the column line CL to the first comparator 160L. The pixel voltage VPIX may include a reset signal and an image signal. In this case, the first input switch SWI1 is turned on when the pixel PX is operating in LCG mode, and the first comparator 160L can compare the first reset signal and the first image signal in LCG mode with the ramp signal RAMP. The counter circuit 170 can convert the comparison result signal output from the first comparator 160L into a digital signal.

[0064] The second input switch SWI2 is turned on in response to the second enable signal ENH, and can transmit the pixel voltage VPIX to the second comparator 160H. At that time, the second input switch SWI2 is turned on when the pixel PX is operating in HCG mode, and the second comparator 160H can compare the second reset signal and the second image signal in HCG mode with the ramp signal RAMP. The counter circuit 170 can convert the comparison result signal output from the second comparator 160H into a digital signal. In Figure 4, one counter circuit 170 is shown receiving the comparison result signals from the first comparator 160L and the second comparator 160H, but it is not limited to this, and two counter circuits 170 may be provided with the CDS circuit 160, and the two counter circuits 170 may each receive the comparison result signals from the first comparator 160L and the second comparator 160H, and the received comparison result signals can be converted from analog to digital.

[0065] On the other hand, since the first comparator 160L and the second comparator 160H each operate based on a constant current, i.e., a bias current, power consumption increases compared to when the system operates based on a single comparator. As described later, the CDS circuit 160 according to an embodiment of the present invention can reduce the constant current by adjusting the bias current of the first comparator 160L and the bias current of the second comparator 160H based on the operating states of the first comparator 160L and the second comparator 160H, respectively. This reduces the power consumption of the CDS circuit 160 and the image sensor 100.

[0066] Figure 5 is a flowchart showing how an image sensor operates according to an exemplary embodiment of the present invention. The method in Figure 5 is performed in the pixel PX of the image sensor 100 and the CDS circuit 160.

[0067] Referring to Figures 2, 4, and 5, the floating diffusion node FD is reset at pixel PX (S110). As explained with reference to Figure 2, the reset transistor RX and the gain selection transistor CGX are turned on, and the pixel power supply voltage VDDP is applied to the floating diffusion node FD.

[0068] In LCG mode, the LCG reset signal of pixel PX is read using the first comparator 160L (S120). In step S120, the reset transistor RX is turned off, and the gain selection transistor CGX can remain turned on. This allows pixel PX to operate in LCG mode and output an LCG reset signal via LCG. The first comparator 160L receives the LCG reset signal of pixel PX, compares the LCG reset signal with the ramp signal RAMP, and outputs the comparison result. This comparison result is counted as the LCG reset value by the counter circuit 170.

[0069] Next, in HCG mode, the HCG reset signal of pixel PX is read using the second comparator 160H (S130). In step S130, the gain selection transistor CGX is turned off, thereby allowing pixel PX to operate in HCG mode. The voltage across the floating diffusion node FD can be changed by the change in capacitance of the floating diffusion node FD, and the HCG reset signal is in phase with the LCG reset signal. For example, the HCG reset signal will be lower than the LCG reset signal.

[0070] The HCG can output an HCG reset signal, and the second comparator 160H receives the HCG reset signal from pixel PX, compares the HCG reset signal with the ramp signal RAMP, and outputs the comparison result. This comparison result is counted as the HCG reset value by the counter circuit 170.

[0071] Next, electrons generated by the photodiode are transmitted to the floating diffusion node FD (S140). The transmission transistor TX is turned on, and electrons generated by the photodiode can be stored in the floating diffusion node FD. As a result, the voltage level of the floating diffusion node FD decreases.

[0072] In HCG mode, the HCG image signal of pixel PX is read using the second comparator 160H (S150). Similar to step S130, in step S140 the gain selection transistor CGX is turned off, thereby allowing pixel PX to operate in HCG mode. However, the pixel voltage VPIX, which is the voltage level of the floating diffusion node FD that changed in step S140, is also output as the HCG image signal.

[0073] The second comparator 160H receives the HCG image signal of pixel PX, compares the HCG image signal with the ramp signal RAMP, and outputs the comparison result. This comparison result is counted as an HCG image value by the counter circuit 170, and the HCG reset value counted in step S130 is subtracted from the HCG image value to generate an HCG pixel value that represents the level based on the amount of light received by the photodiode PD.

[0074] In LCG mode, the LCG image signal of pixel PX is read using the first comparator 160L (S160). In step S160, the gain selection transistor CGX is turned on again, allowing pixel PX to operate in LCG mode. Also, as the transmission control signal TS is toggled to an active level, for example, logic high, the charge generated and remaining in the photodiode PD is transmitted and stored to the floating diffusion node FD.

[0075] The pixel voltage VPIX, determined by the voltage level of the floating diffusion node FD, is also output as the LCG image signal. The LCG image signal represents the image signal in LCG mode.

[0076] The first comparator 160L receives the LCG image signal of pixel PX, compares the LCG image signal with the ramp signal RAMP, and outputs a comparison result signal. This comparison result signal is counted as an LCG image value by the counter circuit 170, and the LCG reset value counted in step S120 is subtracted from the LCG image value to generate an LCG pixel value that represents the level based on the amount of light received by the photodiode PD.

[0077] Through the process described above, LCG image data and HCG image data can be generated by multiple pixels PX of the pixel array 110, and the HCG image data is relatively lower in brightness than the LCG image data.

[0078] Figures 6A and 6B are circuit diagrams showing a first comparator and a second comparator according to exemplary embodiments of the present invention.

[0079] Referring to Figures 6A and 6B, the first comparator 160L and the second comparator 160H are also realized by OTA.

[0080] Referring to Figure 6A, the first comparator 160L includes an input stage 161L, an output stage 162L, a bias circuit 163L, a switching circuit 164L, and capacitors C1a and C2a. The input stage 161L, output stage 162L, and bias circuit 163L are part of the first OTA OTA1 can be configured.

[0081] The input stage 161L includes transistors T1a and T2a, which receive the ramp signal RAMP and the pixel voltage VPIX, respectively. A capacitor C1a is connected to the gate terminal of transistor T1a, and a DC-blocked ramp signal RAMP is applied to transistor T1a through capacitor C1a. A capacitor C2a is connected to the gate terminal of transistor T2a, and a DC-blocked pixel voltage VPIX is applied through capacitor C2a. For example, the LCG reset signal and LCG image signal in LCG mode are also received as the pixel voltage VPIX.

[0082] The output stage 162L includes transistors T3a and T4a and can also be realized by a current mirror. However, it is not limited to this, and the structure of the output stage 162L can be changed.

[0083] The switching circuit 164L includes switches SW1a and SW2a that are turned on in response to a first auto-zero signal AZL. Switches SW1a and SW2a are turned on during the first auto-zero interval before the first comparator 160L performs its comparison operation, allowing the gate terminals of transistors T1a and T2a to be connected to their output terminals, for example, the source terminals of transistors T3a and T4a, respectively. Such auto-zero operation initializes the first comparator 160L and eliminates the offset of the first comparator 160L. This eliminates the first OTA The voltage levels of the first input node INL, the second input node IPL, the output node NO1, and the comparison node NC1 of OTA1 become identical, and this identical voltage level is referred to as the first auto-zero level. This first auto-zero level is the voltage level of the ramp signal RAMP and the LCG reset signal, and the first OTA It is also determined by the internal offset voltage of OTA1. The first input node INL and the second input node IPL are the positive and negative input nodes of the first OTA OTA1, and the comparison node NC1 and the output node NO1 are the first OTA These are the positive and negative output nodes of OTA1. Output node NO1 outputs the output voltage VOUT, for example, the comparison result signal.

[0084] The bias circuit 163L includes a first current source CS1a, a second current source CS2a, a first bias switch SWB1a, and a second bias switch SWB2a. The current Ia supplied from the first current source CS1a is equal to the current I supplied from the second current source CS2a. L It is lower than [value]. The first current source CS1a is connected to the input stage 161L via the first bias switch SWB1a, and the second current source CS2a is connected to the input stage 161L via the second bias switch SWB2a.

[0085] For example, the first bias switch SWB1a and the second bias switch SWB2a can also be realized by transistors, such as NMOS transistors or transmission gates. The first bias switch SWB1a and the second bias switch SWB2a can have the same size.

[0086] Figures 7A and 7B illustrate the bias circuit 163L of the first comparator in Figure 6A.

[0087] Referring to Figure 7A, the first current source CS1a and the second current source CS2a are also realized by transistors, for example, the first bias transistor and the second bias transistors TB1 and TB2, respectively. The first bias transistor TB1 is controlled by the first bias voltage VB1 and generates current Ia, and the second bias transistor TB2 is controlled by the second bias voltage VB2 and generates current Ia L This can generate the following. In one embodiment, the sizes of the first bias transistor TB1 and the second bias transistor TB2 are the same. The first bias voltage VB1 and the second bias voltage VB2 are different. As a result, the current Ia generated by the first current source CS1a and the current I generated by the second current source CS2a can be generated. L They are different.

[0088] Referring to Figure 7B, the first current source CS1a is embodied by multiple transistors TB1 and TB3, and the second current source CS2a is embodied by multiple transistors TB2 and TB4. In Figure 7B, the first current source CS1a and the second current source CS2a are shown to each contain two transistors, but are not limited to this, and the first current source CS1a and the second current source CS2a may also contain three or more transistors.

[0089] The multiple transistors constituting the first current source CS1a and the second current source CS2a are also diode-connected transistors, and one of the multiple transistors, for example, transistor TB1 in the first current source CS1a, is controlled by the first bias voltage VB1, and transistor TB2 in the second current source CS2a is controlled by the second bias voltage VB2.

[0090] As explained with reference to Figures 7A and 7B, the first current source CS1a and the second current source CS2a have bias currents, i.e., currents Ia and I, based on bias voltages, for example, the first bias voltage VB1 and the second bias voltage VB2, respectively. L The amount of current can be adjusted.

[0091] Referring to Figure 6A, the first bias switch SWB1a is turned on in response to the always-on signal AON. The always-on signal AON can always have an active level during the reading period. Therefore, the first current source CS1a can be connected to the input stage 161L during the reading period, regardless of the conversion mode of the pixel PX. In one embodiment, the bias circuit 163L does not have to include the first bias switch SWB1a, and the first current source CS1a can be connected directly to the input stage 161L.

[0092] The second bias switch SWB2a is turned on or off in response to the first enable signal ENL. The first enable signal ENL can have an active level (e.g., logic high) when pixel PX (Figure 2) is operating in LCG mode (hereinafter referred to as LCG mode), and an inactive level (e.g., logic low) when pixel PX is operating in HCG mode (hereinafter referred to as HCG mode). Thus, in LCG mode, the bias current supplied from the bias circuit 163L is Ia + I LTherefore, in HCG mode, the bias current supplied from the bias circuit 163L is Ia, which is lower than in LCG mode.

[0093] As explained with reference to Figures 4 and 5, in LCG mode, the first comparator 160L receives the pixel signal in LCG mode and performs the comparison operation, while in HCG mode, the first comparator 160L does not receive the pixel signal. That is, in HCG mode, the first comparator 160L can be in a standby state without performing the comparison operation. Therefore, the bias current of the bias circuit 163L can be adjusted depending on the mode, and in HCG mode, the first bias switch SWB1a is turned off, reducing the bias current. This reduces the power consumption of the first comparator 160L. However, if the bias current is interrupted in HCG mode, a longer settling time is required for the first comparator 160L to operate normally when switching from HCG mode to LCG mode. Therefore, even in HCG mode, the first current source CS1a provides current Ia, allowing the first comparator 160L to maintain a standby state that allows it to quickly return to the normal operating state in which it performs the comparison operation.

[0094] Referring to Figure 6B, the second comparator 160H includes the input stage 161H, the output stage 162H, the bias circuit 163H, the switching circuit 164H, and capacitors C1b and C2b. The input stage 161H, the output stage 162H, and the bias circuit 163H are the second OTA OTA2 can be configured. The structure of the second comparator 160H is similar to the structure of the first comparator 160L in Figure 6A. However, the bias current of the bias circuit 163H, for example, Ib and Ib, can be configured. H This is the bias current of the bias circuit 163L of the first comparator 160L, for example, Ia and I L This is in contrast to the above.

[0095] The input stage 161H includes transistors T1b and T2b, which receive a ramp signal RAMP and a pixel voltage VPIX, respectively. A capacitor C1b is connected to the gate terminal of transistor T1b, and a DC-blocked ramp signal RAMP is applied to transistor T1b through capacitor C1b. A capacitor C2b is connected to the gate terminal of transistor T2b, and a DC-blocked pixel voltage VPIX is applied through capacitor C2b. For example, the first reset signal and the first image signal in HCG mode are also received as the pixel voltage VPIX.

[0096] The output stage 162H includes transistors T3b and T4b and can also be realized by a current mirror. However, it is not limited to this, and the structure of the output stage 162b can be changed.

[0097] The switching circuit 164H includes switches SW1b and SW2b, which are turned on in response to the second auto-zero signal AZH. Switches SW1b and SW2b are turned on during the second auto-zero interval before the second comparator 160H performs its comparison operation, and can connect the gate terminals of transistors T1b and T2b to their output terminals, for example, the source terminals of transistors T3b and T4b. This allows the second OTA to be formed. The voltage levels of the first input node INH, the second input node IPH, the output node NO2, and the comparison node NC2 of OTA2 become identical, and this identical voltage level is referred to as the second auto-zero level. The second auto-zero level is the voltage level of the ramp signal RAMP and the HCG reset signal, and the second OTA It is also determined by the internal offset voltage of the OTA2.

[0098] The bias circuit 163H includes a first current source CS1b, a second current source CS2b, a first bias switch SWB1b, and a second bias switch SWB2b. The current Ib supplied from the first current source CS1b is the current I supplied from the second current source CS2b. HLower than. The first current source CS1b and the second current source CS2b can be implemented similarly to the bias circuits described with reference to Figures 6A and 6B, and at least one transistor provided in each of the first current source CS1b and the second current source CS2b is controlled by a bias voltage applied to its gate terminal, thereby controlling the bias current, for example, current Ib and current I H It is adjustable.

[0099] The first current source CS1b is connected to the input stage 161H via the first bias switch SWB1b, and the second current source CS2b is connected to the input stage 161H via the second bias switch SWB2b.

[0100] The first bias switch SWB1b is always turned on during the reading period in response to the always-on signal AON. In one embodiment, the bias circuit 163H does not have to include the first bias switch SWB1b, and the first current source CS1b can be directly connected to the input stage 161H.

[0101] The second bias switch SWB2b is turned on in response to the second enable signal ENH. For example, the second enable signal ENH can have an active level (e.g., logic high) in HCG mode and an inactive level (e.g., logic low) in LCG mode. Thus, in HCG mode, the bias current supplied from the bias circuit 163H is Ib + I H Therefore, in LCG mode, the bias current supplied from bias circuit 163H is Ib, which is lower than in HCG mode.

[0102] As explained with reference to Figures 4 and 5, in HCG mode, the second comparator 160H receives the pixel signal in HCG mode and performs the comparison operation, while in LCG mode, the second comparator 160H does not receive the pixel signal. That is, in LCG mode, the second comparator 160H can maintain a standby state without performing the comparison operation. Therefore, depending on the mode, the bias current of the bias circuit 163H can be adjusted, and in LCG mode, the second bias switch SWB2b can be turned off to reduce the bias current. This reduces the power consumption of the second comparator 160H. However, if the bias current is interrupted in LCG mode, a longer settling time is required for the second comparator 160H to operate normally when switching from LCG mode to HCG mode. Therefore, even in LCG mode, the first current source CS1b provides current Ib, allowing the second comparator 160H to maintain a standby state that allows it to quickly return to the normal operating state in which it performs the comparison operation normally.

[0103] As explained with reference to Figures 6A and 6B, the bias current is reduced during periods when the first comparator 160L and the second comparator 160H are not performing comparison operations. When the first comparator 160L performs comparison operations, the bias current of the second comparator 160H is reduced, and when the second comparator 160H performs comparison operations, the bias current of the first comparator 160L is reduced. As a result, the power consumption of the CDS circuit 160, including the first comparator 160L and the second comparator 160H, is reduced while the comparison operation for the pixel voltage output from the pixel PX is performed normally. In addition, the power consumption of the image sensor 100 (Figure 1), which includes multiple CDS circuits 160, is reduced.

[0104] Figure 8 is a timing diagram showing the operation method of an image sensor according to an exemplary embodiment of the present invention. Figure 8 shows the operation of pixel PX in Figure 2, CDS circuit 160 in Figure 4, and the first comparator 160L and second comparator 160H in Figures 6A and 6B. Control signals provided to pixel PX, such as the reset control signal RS, the gain control signal CGS, and the transmission control signal TS, are received from the low driver 120, and control signals provided to the CDS circuit 160, such as the always-on signal AON, the first enable signal ENL, the second enable signal ENH, the first auto-zero signal AZL, and the second auto-zero signal AZH, are provided from the timing controller 190.

[0105] As explained with reference to Figure 3, during the reading period, a signal is read from pixel PX using the RRSS reading method.

[0106] During the first sub-period SP1, the first enable signal ENL is at an active level, e.g., logic high, and the second enable signal ENH is at an inactive level, e.g., logic low.

[0107] Referring to Figure 4, the first input switch SWI1 is turned on in response to the first enable signal ENL, and the pixel voltage VPIX is applied to the first comparator 160L. Of the first comparator 160L and the second comparator 160H, the first comparator 160L can perform the comparing operation. In response to the activation levels of the always-on signal AON and the first enable signal ENL, the first and second bias switches SWB1a and SWB2a of the first comparator 160L are turned on, and the first comparator 160L receives a bias current Ia + I L It can operate based on the following: In response to the activation level of the always-on signal AON and the deactivation level of the second enable signal ENH, respectively, the first bias switch SWB1b of the second comparator 160H is turned on and the second bias switch SWB2b is turned off, and the second comparator 160H can operate based on the bias current Ib. For example, the second comparator 160H is also in a standby state.

[0108] During the reading period, the always-on signal AON is always at the active level, and the first bias switch SWB1a of the first comparator 160L and the first bias switch SWB1b of the second comparator 160H can continuously remain turned on, as in the first sub-period SP1. Therefore, the following explanation of the first bias switch SWB1a of the first comparator 160L and the first bias switch SWB1b of the second comparator 160H will be omitted.

[0109] Time point t0 or time point t1 is the first autozero interval AZ1, and the first autozero signal AZL is at an active level in the first autozero interval AZ1. In response to the first autozero signal AZL, the first OTA provided in the first comparator 160L OTA1 can perform auto-zero operation. The levels of the first input node INL and the second input node IPL of the first OTA OTA1 become the same as the first auto-zero level. Thereafter, the first OTA The levels of the first input node INL and the second input node IPL of OTA1 also change due to changes in the levels of the pixel voltage VPIX and the ramp signal RAMP. As a result, from time t1 to time t2, the first comparator 160L compares the LCG reset signal received as the pixel voltage VPIX with the ramp signal RAMP and outputs a comparison result signal based on the comparison result.

[0110] During the second subperiod SP2 and the third subperiod SP3, the first enable signal ENL is at an inactive level, e.g., logic low, and the second enable signal ENH is at an active level, e.g., logic high. In Figure 4, the second input switch SWI2 is turned on in response to the second enable signal ENH, and the pixel voltage VPIX is applied to the second comparator 160H. Of the first comparator 160L and the second comparator 160H, the second comparator 160H can perform the comparator operation. In response to the active level of the second enable signal ENH, the second bias switch SWB2b of the second comparator 160H is turned on, and the second comparator 160H receives a bias current Ib+I HIt can operate based on the following: In response to the deactivation level of the first enable signal ENL, the second bias switch SWB1a of the first comparator 160L is turned off, and the first comparator 160L can operate based on the bias current Ia. For example, the first comparator 160L is also in a standby state.

[0111] Time points t2 to t3 are the second autozero interval AZ2, and the second autozero signal AZH is at an active level during the second autozero interval AZ2. In response to the second autozero signal AZH, the second OTA provided in the second comparator 160H OTA2 can perform auto-zero operation. The levels of the first input node INH and the second input node IPH of the second OTA2 become the same as the second auto-zero level. Thereafter, the second OTA The levels of the first input node INH and the second input node IPH of OTA2 also change with changes in the levels of the pixel voltage VPIX and the ramp signal RAMP. As a result, from time t3 to time t4, the second comparator 160H compares the HCG reset signal received as the pixel voltage VPIX with the ramp signal RAMP and outputs a comparison result signal based on the comparison result. Furthermore, during the third sub-period SP3, i.e., from time t4 to time t5, the second comparator 160H compares the HCG image signal (e.g., HCG signal voltage) received as the pixel voltage VPIX with the ramp signal RAMP and outputs a comparison result signal based on the comparison result.

[0112] During the fourth subperiod SP4, the first enable signal ENL is at an active level, e.g., logic high, and the second enable signal ENH is at an inactive level, e.g., logic low. In Figure 4, the first input switch SWI1 is turned on in response to the first enable signal ENL, and the pixel voltage VPIX is applied to the first comparator 160L. The first comparator 160L can perform comparing operations. Similar to the first subperiod SP1, in response to the active level of the first enable signal ENL, the second bias switch SWB2a of the first comparator 160L is turned on, and the first comparator 160L receives a bias current Ia + IL It can operate based on the following: In response to the deactivation level of the second enable signal ENH, the second bias switch SWB2b of the second comparator 160H is turned off, and the second comparator 160H can operate based on the bias current Ib.

[0113] Thus, the first comparator 160L can perform comparison operations based on the LCG reset signal and the LCG image signal during the first subperiod SP1 and the fourth subperiod SP4, and the second comparator 160H can perform comparison operations based on the HCG reset signal and the HCG image signal during the second subperiod SP2 and the third subperiod SP3. The bias current of the first comparator 160L is reduced during the second subperiod SP2 and the third subperiod SP3, when it does not perform comparison operations, and the bias current of the second comparator 160H is reduced during the first subperiod SP1 and the fourth subperiod SP4, when it does not perform comparison operations.

[0114] For example, the bias currents Ib and I of the second comparator 160H H However, the bias currents Ia and I of the first comparator 160L L If they are the same, and the bias currents of the first comparator 160L and the second comparator 160H are not adjusted by the conversion gain mode, then during the reading period, the total bias current of the CDS circuit 160 is 2 × (Ia + I L ) However, in the CDS circuit 160 according to an embodiment of the present invention, during the reading period, the total bias current of the CDS circuit 160 is 2 × Ia + I L Therefore, the power consumption of the CDS circuit 160 and the image sensor 100 is reduced.

[0115] Figures 9A and 9B are timing diagrams showing a method for controlling the bias current of the first and second comparators of a CDS circuit according to an exemplary embodiment of the present invention.

[0116] Referring to Figures 9A and 9B, the levels of the first enable signal ENL and the second enable signal ENH transition from an active level to an inactive level, or from an inactive level to an active level, due to the level transition of the gain control signal CGS. At that time, as shown in Figure 9A, both the first enable signal ENL and the second enable signal ENH are at the active level in some sections before and after the level transition of the gain control signal CGS, for example, in sections PON1 and PON2. As a result, in the first sub-period SP1 and the second sub-period SP2, the bias current of the second comparator 160H increases, and then the bias current of the first comparator 160L decreases. Also, in the third sub-period SP3 and the fourth sub-period SP4, the bias current of the first comparator 160L increases, and then the bias current of the second comparator 160H decreases.

[0117] Conversely, as shown in Figure 9B, both the first enable signal ENL and the second enable signal ENH are at an inactive level during certain intervals before and after the transition point of the gain control signal CGS level, for example, during intervals POFF1 and POFF2. As a result, during the third sub-period SP3 and the fourth sub-period SP4, the bias current of the first comparator 160L decreases, followed by an increase in the bias current of the second comparator 160H, and similarly, during the third sub-period SP3 and the fourth sub-period SP4, the bias current of the second comparator 160H decreases, followed by an increase in the bias current of the first comparator 160L.

[0118] Figure 10 is a circuit diagram showing an example of a pixel embodiment according to an exemplary embodiment of the present invention. Pixel PXa in Figure 10 is a modified example of pixel PX in Figure 2.

[0119] Referring to Figure 10, pixel PXa consists of two photodiodes PD1 and PD2, multiple transistors such as two transmission transistors TX1 and TX2, a reset transistor RX, a drive transistor DX, a selection transistor SX, and a gain control transistor CGX (or a conversion gain control transistor), and a capacitor C LThis includes the following: Here, the two photodiodes PD1 and PD2 represent photodiodes placed beneath a single microlens.

[0120] The first photodiode PD1, the first transmission transistor TX1, the second photodiode PD2, and the second transmission transistor TX2 can share a floating diffusion node FD. The first transmission transistor TX1 is turned on in response to the first transmission control signal TS1 and can transmit the charge generated in the first photodiode PD1 to the floating diffusion node FD. The second transmission transistor TX2 is turned on in response to the second transmission control signal TS2 and can transmit the charge generated in the second photodiode PD2 to the floating diffusion node FD. The first transmission transistor TS1 and the second transmission transistor TS2 can operate independently of the first and second transmission control signals TS1 and TS2, respectively.

[0121] Figure 11A is a plan view of a pixel according to an exemplary embodiment of the present invention, and Figure 11B is a vertical cross-sectional view.

[0122] Referring to Figures 11A and 11B, the pixel PXa includes a microlens ML, a color filter CF, first and second photodiodes PD1 and PD2, a floating diffusion node FD, and a wiring layer WL.

[0123] A color filter CF is positioned below the microlens ML, and first and second photodiodes PD1 and PD2 are positioned below the color filter CF. The first and second photodiodes PD1 and PD2 are formed on the substrate SUB, and a floating diffusion node FD is also formed on the substrate SUB. Although not shown, transistors such as first and second transmission transistors TX1 and TX2, a reset transistor RX, a drive transistor DX, a selection transistor SX, and a gain control transistor CGX can be formed on the substrate SUB, and wiring for connecting the transistors and low lines for transmitting control signals of the transistors can be formed on the wiring layer WL.

[0124] In this embodiment, a first photodiode PD1 and a second photodiode PD2 can be arranged side by side below the microlens ML. The first photodiode PD1 and the second photodiode PD2 can be positioned to the left / right (or above / below) the optical axis MLX of the microlens ML, respectively. The first photodiode PD1 can receive a first optical signal L1 collected through the right side of the optical axis MLX, and the second photodiode PD2 can receive a second optical signal L2 collected through the left side of the optical axis MLX.

[0125] The image sensor 100 can generate autofocus data for the autofocus of the imaging device, and the pixels PXa in Figures 11A and 11B are also focus pixels that generate autofocus data. For example, focus pixels can be placed between multiple pixels PX of the pixel array 110. Alternatively, multiple pixels PX of the pixel array 110 can all be embodied by focus pixels, and multiple pixels PX can generate autofocus data.

[0126] Figure 12 is a timing diagram showing the operation method of an image sensor according to an exemplary embodiment of the present invention. Figure 12 shows the operation of pixel PXa in Figure 10, CDS circuit 160 in Figure 4, and the first comparator 160L and second comparator 160H in Figures 6A and 6B.

[0127] Referring to Figure 12, the reading period for pixel PXa includes the first to fifth subperiods SP1 to SP5. In the first subperiod SP1, the LCG reset signal is read; in the second subperiod SP2, the HCG reset signal is read; in the third subperiod SP3, the HCG left image signal (or HCG right image signal) is read; in the fourth subperiod, the HCG combined image signal is read; and in the fifth subperiod SP5, the LCG combined image signal is read. Here, the left image signal is the image signal generated in pixel PXa based on the charge generated by the first photodiode PD1, and the combined image signal represents the image signal generated in pixel PXa based on the charges generated by the first photodiode PD1 and the second photodiode PD2.

[0128] The operation of the first sub-period SP1 and the second sub-period SP2 is the same as the operation of the first sub-period SP1 and the second sub-period SP2 in Figure 8, so a redundant explanation will be omitted.

[0129] During the third subperiod SP3, pixel PXa operates in HCG mode in response to the deactivation level of the gain control signal CGS. The first transmission control signal TS1 is toggled to the activation level, and the charge generated in the first photodiode PD1 is transmitted to and stored in the floating diffusion node FD. Thereafter, the HCG left image signal (e.g., HCG left signal voltage) is read.

[0130] During the fourth subperiod SP4, the second transmission control signal TS2 is toggled to an active level, and the charge generated in the second photodiode PD2 is transmitted to and stored in the floating diffusion node FD. The floating diffusion node FD can store the charges generated in the first photodiode PD1 and the second photodiode PD2, thereby allowing the HCG aggregate image signal (e.g., HCG aggregate signal voltage) to be read.

[0131] During the fifth subperiod SP5, pixel PXa operates in LCG mode in response to the activation level of the gain control signal CGS. The first and second transmission control signals TS1 and TS2 are toggled to their activation levels, and the remaining charge in the first and second photodiodes PD1 and PD2 is transmitted to and stored in the floating diffusion node FD. The LCG aggregate image signal (e.g., LCG aggregate signal voltage) is read from the voltage of the floating diffusion node FD.

[0132] The HCG right image value can be calculated by subtracting the counting value for the HCG left image signal, for example, the HCG left image value, from the counting value for the HCG combined image signal, for example, the HCG combined image value. Based on the HCG left image value and HCG right image value generated from multiple focal pixels of the pixel array 110, autofocus data can be generated.

[0133] During the first subperiod SP1 and the fifth subperiod SP5, processing of LCG signals, such as the LCG reset signal and the LCG sum signal, is performed by the first comparator 160L, and during the second to fourth subperiods SP2 to SP4, processing of HCG signals, such as the HCG reset signal, the HCG left image signal, and the HCG sum signal, can be performed by the second comparator 160H. During the first subperiod SP1 and the fifth subperiod SP5, when the first comparator 160L performs comparison operation, the second comparator 160H is in standby mode, and the bias current is reduced. Also, during the second to fourth subperiods SP2 to SP4, when the second comparator 160H performs comparison operation, the first comparator 160L is in standby mode, and the bias current is reduced.

[0134] Figure 13A is a circuit diagram showing an example of a pixel according to an exemplary embodiment of the present invention, and Figure 13B is a plan view of the pixel in Figure 13A. Pixel PXb in Figure 13A is a modified example of pixel PX in Figure 2.

[0135] Referring to Figure 13A, pixel PXb consists of four photodiodes PD1, PD2, PD3, and PD4, multiple transistors, such as four transmission transistors TX1, TX2, TX3, and TX4, a reset transistor RX, a drive transistor DX, a selection transistor SX, and a gain control transistor CGX (or a conversion gain control transistor), and a capacitor C L This includes the following: Here, the two photodiodes PD1 and PD2 represent photodiodes placed beneath a single microlens.

[0136] The first photodiode PD1, the first transmission transistor TX1, the second photodiode PD2, the second transmission transistor TX2, the third photodiode PD3, the third transmission transistor TX3, the fourth photodiode PD4, and the fourth transmission transistor TX4 can share a floating diffusion node FD.

[0137] The first transmission transistor TX1 is turned on in response to the first transmission control signal TS1 and can transmit the charge generated in the first photodiode PD1 to the floating diffusion node FD. The second transmission transistor TX2 is turned on in response to the second transmission control signal TS2 and can transmit the charge generated in the second photodiode PD2 to the floating diffusion node FD. The third transmission transistor TX3 is turned on in response to the third transmission control signal TS3 and can transmit the charge generated in the third photodiode PD3 to the floating diffusion node FD. The fourth transmission transistor TX4 is turned on in response to the fourth transmission control signal TS4 and can transmit the charge generated in the fourth photodiode PD4 to the floating diffusion node FD. Each of the first to fourth transmission transistors TS1 to TS4 can operate independently in response to the first to fourth transmission control signals TS1 to TS4.

[0138] Referring to Figure 13B, the first to fourth photodiodes PD1 to PD4 can be arranged side by side below the microlens ML. For example, the first and third photodiodes PD1 and PD3 can be placed on the left, the second and fourth photodiodes PD2 and PD4 on the right, the first and second photodiodes PD1 and PD2 on the top, and the third and fourth photodiodes PD3 and PD4 on the bottom. Pixel PXb can function as a focal pixel.

[0139] All or some of the multiple pixels PX of the pixel array 110 (Figure 1) are embodied by pixels PXb. The image sensor 100 is operable as shown in Figure 12, and the first and third transmission control signals TS1 and TS3 are the same as the first transmission control signal TS1 in Figure 12, and the second and fourth transmission control signals TS2 and TS4 are the same as the second transmission control signal TS2 in Figure 12. Thereafter, an HCG left image signal can be generated based on the charge generated by the first photodiode PD1 and the third photodiode PD3, and an HCG aggregate image signal can be generated based on the charge generated by the first to fourth photodiodes PD1 to PD4.

[0140] In one embodiment, the first and second transmission control signals TS1 and TS2 are the same as the first transmission control signal TS1 in Figure 12, and the third and fourth transmission control signals TS3 and TS4 are the same as the second transmission control signal TS2 in Figure 12. As a result, an HCG upper image signal can be generated based on the charge generated by the first photodiode PD1 and the second photodiode PD2, and an HCG aggregate image signal can be generated based on the charge generated by the first to fourth photodiodes PD1 to PD4. The HCG lower image value can be calculated by subtracting the counting value of the HCG upper image signal, for example, the HCG upper image value, from the counting value of the HCG aggregate image signal, for example, the HCG aggregate image value. The HCG upper image value and HCG lower image value of the focal pixel of the pixel array 110 can be used as autofocus data.

[0141] Figures 14 and 15 are block diagrams of an electronic device including a multi-camera module. Figure 16 is a detailed block diagram of the camera module shown in Figures 14 and 15.

[0142] Referring to Figure 14, the electronic device 1000 includes a camera module group 1100, an application processor 1200, a PMIC (power management integrated circuit) 1300, and an external memory 1400.

[0143] The camera module group 1100 includes multiple camera modules 1100a, 1100b, and 1100c. Figure 14 shows an embodiment in which three camera modules 1100a, 1100b, and 1100c are arranged, but the embodiment is not limited thereto. In some embodiments, the camera module group 1100 can be modified to include only two camera modules. Also, in some embodiments, the camera module group 1100 can be modified to include k camera modules (where k is a natural number greater than or equal to 4).

[0144] The detailed configuration of camera module 1100b will be described in more detail below with reference to Figure 15, but the following description is also applicable to other camera modules 1100a and 1100c depending on the embodiment.

[0145] Referring to Figure 15, the camera module 1100b includes a prism 1105, an OPFE (Optical Path Folding Element) 1110, an actuator 1130, an image sensing device 1140, and a storage unit 1150.

[0146] The prism 1105 includes a reflective surface 1107 made of a light-reflecting material, which can deform the path of light L incident from the outside.

[0147] In some embodiments, the prism 1105 can change the path of light L incident in a first direction X to a second direction Y perpendicular to the first direction X. Alternatively, the prism 1105 can rotate the reflective surface 1107 of the light-reflecting material in direction A around the central axis 1106, or rotate the central axis 1106 in direction B, thereby changing the path of light L incident in a first direction X to the perpendicular second direction Y. In this case, OPFE 1110 can also move in a third direction Z, which is perpendicular to the first direction X and the second direction Y.

[0148] In some embodiments, as shown in Figure 16, the maximum rotation angle of the prism 1105 in the A direction is 15° or less in the positive (+) A direction and greater than 15° in the negative (-) A direction, but embodiments are not limited thereto.

[0149] In some embodiments, the prism 1105 is rotatable in the positive (+) or negative (-)B direction by approximately 20°, between 10° and 20°, or between 15° and 20°, where the rotation angle is either the same angle in the positive (+) or negative (-)B direction, or to approximately similar angles within a range of approximately 1°.

[0150] In some embodiments, the prism 1105 can move the reflective surface 1107 of the light-reflecting material in a third direction (e.g., the Z direction) parallel to the extension direction of the central axis 1106.

[0151] The OPFE 1110 includes, for example, a group of m optical lenses (where m is a natural number). The m lenses can move in a second direction Y, thereby changing the optical zoom magnification of the camera module 1100b. For example, if the basic optical zoom magnification of the camera module 1100b is Z, the OPFE By moving the m optical lenses included in 1110, the optical zoom magnification of the camera module 1100b can be changed to 3Z, 5Z, or more.

[0152] The actuator 1130 can move the OPFE 1110 or the optical lens group (hereinafter referred to as the optical lens) to a specific position. For example, the actuator 1130 can adjust the position of the optical lens so that the image sensor 1142 is positioned at the focal length of the optical lens for accurate sensing.

[0153] The image sensing device 1140 includes an image sensor 1142, control logic 1144, and memory 1146. The image sensor 1142 can sense an image to be sensed using light L provided through an optical lens. The image sensor 100 and its components, described with reference to Figures 1 to 13B, such as the pixel PX (Figure 2) and CDS circuit 160 (Figure 4) that support dual conversion gain, are applicable to the image sensor 1142. The image sensor 1142 can merge HCG image data and LCG image data to generate image data with a high dynamic range.

[0154] The control logic 1144 can control the overall operation of the camera module 1100b. For example, the control logic 1144 can control the operation of the camera module 1100b by control signals provided through the control signal line CSLb.

[0155] Memory 1146 can store information necessary for the operation of the camera module 1100b, such as calibration data 1147. Calibration data 1147 includes information necessary for the camera module 1100b to generate image data using light L supplied from an external source. Calibration data 1147 may include, for example, information relating to the degree of rotation, information relating to the focal length, and information relating to the optical axis. If the camera module 1100b is implemented as a multi-state camera configuration in which the focal length changes depending on the position of the optical lens, calibration data 1147 may include the focal length values ​​for each position (or state) of the optical lens and information relating to autofocusing.

[0156] The storage unit 1150 can store image data sensed through the image sensor 1142. The storage unit 1150 can be located outside the image sensing device 1140, and can also be implemented in a stacked configuration with the sensor chip that constitutes the image sensing device 1140.

[0157] In some embodiments, the storage unit 1150 is implemented by an EEPROM (Electrically Erasable Programmable Read-Only Memory), but the embodiments are not limited thereto. In some embodiments, the image sensor 1142 is composed of a pixel array, and the control logic 1144 includes an analog-to-digital converter and an image signal processing unit for processing the sensed image.

[0158] Referring to both Figures 14 and 15, in some embodiments, each of the multiple camera modules 1100a, 1100b, and 1100c includes an actuator 1130. Thus, each of the multiple camera modules 1100a, 1100b, and 1100c includes identical or different calibration data 1147 due to the operation of the actuator 1130 contained within it.

[0159] In some embodiments, one of the multiple camera modules 1100a, 1100b, and 1100c (for example, 1100b) is configured to use the aforementioned prism 1105 and OPFE The camera module is in a folded lens form and includes the 1110, while the remaining camera modules (e.g., 1100a, 1100c) use the prism 1105 and OPFE. A vertical camera module that does not include 1110, but the embodiments are not limited thereto.

[0160] In some embodiments, one of the multiple camera modules 1100a, 1100b, and 1100c (for example, 1100c) is also a vertical depth camera that extracts depth information using, for example, IR (Infrared Ray). In that case, the application processor 1200 can merge the image data provided by the depth camera with the image data provided by the other camera modules (for example, 1100a or 1100b) to generate a three-dimensional depth image.

[0161] In some embodiments, at least two of the multiple camera modules 1100a, 1100b, and 1100c (e.g., 1100a and 1100b) may have different fields of view (angles of view). In such cases, for example, the optical lenses of at least two of the multiple camera modules 1100a, 1100b, and 1100c (e.g., 1100a and 1100b) may be different, but are not limited to this.

[0162] Furthermore, in some embodiments, the field of view of each of the multiple camera modules 1100a, 1100b, and 1100c is different. For example, camera module 1100a is an ultrawide camera, camera module 1100b is a wide camera, and camera module 1100c is a telecamera, but is not limited to this. In that case, the optical lenses included in each of the multiple camera modules 1100a, 1100b, and 1100c are also different, but is not limited to this.

[0163] In some embodiments, the multiple camera modules 1100a, 1100b, and 1100c can be physically separated from each other. That is, the sensing area of ​​a single image sensor 1142 is not divided and used by the multiple camera modules 1100a, 1100b, and 1100c, but rather an independent image sensor 1142 can be placed inside each of the multiple camera modules 1100a, 1100b, and 1100c.

[0164] Referring again to Figure 14, the application processor 1200 includes an image processing unit 1210, a memory controller 1220, and internal memory 1230. The application processor 1200 can be implemented separately from the multiple camera modules 1100a, 1100b, and 1100c. For example, the application processor 1200 and the multiple camera modules 1100a, 1100b, and 1100c can be implemented separately from each other by a separate semiconductor chip.

[0165] The image processing device 1210 includes a plurality of sub-image processors 1212a, 1212b, 1212c, an image generator 1214, and a camera module controller 1216.

[0166] The image processing device 1210 includes multiple sub-image processors 1212a, 1212b, and 1212c, in a number corresponding to the number of camera modules 1100a, 1100b, and 1100c.

[0167] Image data generated from each camera module 1100a, 1100b, and 1100c can be provided to the corresponding sub-image processors 1212a, 1212b, and 1212c through the mutually separated image signal lines ISLa, ISLb, and ISLc. For example, image data generated from camera module 1100a is provided to sub-image processor 1212a through the image signal line ISLa, image data generated from camera module 1100b is provided to sub-image processor 1212b through the image signal line ISLb, and image data generated from camera module 1100c is provided to sub-image processor 1212c through the image signal line ISLc. Such image data transmission is performed, for example, using a Camera Serial Interface (CSI) based on MIPI (Mobile Industry Processor Interface), but the embodiments are not limited thereto.

[0168] On the other hand, in some embodiments, it is also possible to arrange a single sub-image processor to support multiple camera modules. For example, sub-image processors 1212a and 1212c are not realized separately from each other as shown in Figure 14, but are realized integrated into a single sub-image processor, and the image data provided by camera modules 1100a and 1100c are selected through a selection element (e.g., a multiplexer) and then provided to the integrated sub-image processor. In this case, sub-image processor 1212b is not integrated and receives image data from camera module 1100b.

[0169] In some embodiments, image data generated from camera module 1100a is provided to sub-image processor 1212a via image signal line ISLa, image data generated from camera module 1100b is provided to sub-image processor 1212b via image signal line ISLb, and image data generated from camera module 1100c is provided to sub-image processor 1212c via image signal line ISLc. The image data processed by sub-image processor 1212b is immediately provided to image generator 1214, but the image data processed by sub-image processor 1212a and the image data processed by sub-image processor 1212c are selected one by one via a selection element (e.g., a multiplexer) before being provided to image generator 1214.

[0170] Each of the sub-image processors 1212a, 1212b, and 1212c can perform image processing such as bad pixel correction, 3A adjustment (auto-focus correction, auto-white balance, auto-exposure), noise reduction, sharpening, gamma adjustment, and remosaic on the image data provided by the camera modules 1100a, 1100b, and 1100c.

[0171] In some embodiments, the remosaic signal processing can be performed in each camera module 1100a, 1100b, and 1100c before being provided to the sub-image processors 1212a, 1212b, and 1212c.

[0172] The image data processed by each sub-image processor 1212a, 1212b, and 1212c can be provided to the image generator 1214. The image generator 1214 can generate an output image using the image data provided by each sub-image processor 1212a, 1212b, and 1212c, based on generating information or mode signals.

[0173] Specifically, the image generator 1214 can generate an output image by merging at least a portion of the image data generated from camera modules 1100a, 1100b, and 1100c having different field of view angles, based on image generation information or a mode signal. Alternatively, the image generator 1214 can also generate an output image by selecting any one of the image data generated from camera modules 1100a, 1100b, and 1100c having different field of view angles, based on image generation information or a mode signal.

[0174] In some embodiments, the image generation information may also include a zoom signal (or zoom factor). In some embodiments, the mode signal may also be a signal based on a mode selected by the user, for example.

[0175] If the image generation information is a zoom signal (zoom factor), and each camera module 1100a, 1100b, and 1100c has a different field of view (field of view angle), the image generator 1214 can perform different operations depending on the type of zoom signal. For example, if the zoom signal is a first signal, the image generator 1214 can generate an output image using the image data output from sub-image processor 1212a and the image data output from sub-image processor 1212c, specifically the image data output from sub-image processor 1212a and the image data output from sub-image processor 1212b. If the zoom signal is a second signal different from the first signal, the image generator 1214 can generate an output image using the image data output from sub-image processor 1212a and the image data output from sub-image processor 1212c, specifically the image data output from sub-image processor 1212c and the image data output from sub-image processor 1212b. If the zoom signal is a third signal different from the first and second signals, the image generator 1214 can select one of the image data output from each of the sub-image processors 1212a, 1212b, and 1212c and generate an output image without performing such image data merging. However, the embodiment is not limited thereto, and the method of processing the image data can be modified in various ways as needed.

[0176] Referring to Figure 15, in some embodiments, the image processing device 1210 may further include a selection unit 1213 that selects the outputs of the sub-image processors 1212a, 1212b, and 1212c and transmits them to the image generator 1214.

[0177] In that case, the selection unit 1213 can perform different operations depending on the zoom signal or zoom factor. For example, if the zoom signal is the fourth signal (for example, the zoom magnification is the first magnification), the selection unit 1213 can select one of the outputs of the sub-image processors 1212a, 1212b, and 1212c and transmit it to the image generator 1214.

[0178] Furthermore, if the zoom signal is a fifth signal different from the fourth signal (for example, a zoom magnification of 2x), the selection unit 1213 can sequentially transmit p outputs (where p is a natural number greater than or equal to 2) from the outputs of sub-image processors 1212a, 1212b, and 1212c to the image generator 1214. For example, the selection unit 1213 can sequentially transmit the outputs of sub-image processor 1212b and sub-image processor 1212c to the image generator 1214. Alternatively, the selection unit 1213 can sequentially transmit the outputs of sub-image processor 1212a and sub-image processor 1212b to the image generator 1214. The image generator 1214 can also merge the sequentially provided p outputs to generate a single output image.

[0179] Here, image processing such as demosaicing, downscaling to video / preview resolution size, gamma correction, and HDR (High Dynamic Range) processing is performed in advance by sub-image processors 1212a, 1212b, and 1212c, and then the processed image data is transmitted to the image generator 1214. Therefore, even if the processed image data is provided to the image generator 1214 from the selection unit 1213 through a single signal line, the image merging operation of the image generator 1214 is performed at high speed.

[0180] In some embodiments, the image generator 1214 can also receive multiple image data with different exposure times from at least one of the multiple sub-image processors 1212a, 1212b, and 1212c, and perform HDR processing on the multiple image data to generate merged image data with an increased dynamic range.

[0181] The camera module controller 1216 can provide control signals to the respective camera modules 1100a, 1100b, and 1100c. The control signals generated by the camera module controller 1216 can be provided to the corresponding camera modules 1100a, 1100b, and 1100c through the mutually separated control signal lines CSLa, CSLb, and CSLc.

[0182] One of the multiple camera modules 1100a, 1100b, and 1100c is designated as the master camera (e.g., 1100b) by image generation information including a zoom signal or a mode signal, while the remaining camera modules (e.g., 1100a and 1100c) are designated as slave cameras. Such information is included in the control signals and can be provided to the corresponding camera modules 1100a, 1100b, and 1100c through the mutually isolated control signal lines CSLa, CSLb, and CSLc.

[0183] The camera modules operating as master and slave can be changed by the zoom factor or operating mode signal. For example, if the field of view of camera module 1100a is wider than that of camera module 1100b, and the zoom factor represents a lower zoom magnification, camera module 1100b can operate as the master and camera module 1100a can operate as the slave. Conversely, if the zoom factor represents a higher zoom magnification, camera module 1100a can operate as the master and camera module 1100b can operate as the slave.

[0184] In some embodiments, the control signals provided from the camera module controller 1216 to each of the camera modules 1100a, 1100b, and 1100c may include a sync enable signal. For example, if camera module 1100b is the master camera and camera modules 1100a and 1100c are slave cameras, the camera module controller 1216 can transmit a sync enable signal to camera module 1100b. Upon receiving the sync enable signal, camera module 1100b can generate a sync signal based on the provided sync enable signal and provide the generated sync signal to camera modules 1100a and 1100c via the sync signal line SSL. Camera modules 1100b and camera modules 1100a and 1100c can then synchronize with the sync signal and transmit image data to the application processor 1200.

[0185] In some embodiments, the control signals provided from the camera module controller 1216 to the multiple camera modules 1100a, 1100b, and 1100c may also include mode information via mode signals. Based on this mode information, the multiple camera modules 1100a, 1100b, and 1100c can operate in a first operating mode and a second operating mode, in relation to the sensing speed.

[0186] Multiple camera modules 1100a, 1100b, and 1100c can, in a first operating mode, generate an image signal at a first speed (for example, an image signal at a first frame rate), encode it at a second speed higher than the first speed (for example, encode an image signal at a second frame rate higher than the first frame rate), and transmit the encoded image signal to the application processor 1200. At that time, the second speed is also 30 times or less the first speed.

[0187] The application processor 1200 stores the received image signal, i.e., the encoded image signal, in its internal memory 1230 or its external memory 1400. Then, it reads the encoded image signal from the internal memory 1230 or external memory 1400, decodes it, and can display the image data generated based on the decoded image signal. For example, one of the multiple subprocessors 1212a, 1212b, and 1212c of the image processing device 1210 can perform decoding and also perform image processing on the decoded image signal.

[0188] Multiple camera modules 1100a, 1100b, and 1100c can generate image signals at a third speed lower than the first speed in a second operating mode (for example, generating image signals at a third frame rate lower than the first frame rate) and transmit these image signals to the application processor 1200. The image signals provided to the application processor 1200 are also unencoded signals. The application processor 1200 can perform image processing on the received image signals or store the image signals in internal memory 1230 or external memory 1400.

[0189] The PMIC 1300 can supply power, for example, power supply voltage, to each of the multiple camera modules 1100a, 1100b, and 1100c. Under the control of the application processor 1200, the 1300 can supply first power to camera module 1100a via power signal line PSLa, second power to camera module 1100b via power signal line PSLb, and third power to camera module 1100c via power signal line PSLc.

[0190] The PMIC 1300 can generate power corresponding to each of the multiple camera modules 1100a, 1100b, and 1100c in response to a power control signal PCON from the application processor 1200, and can adjust the power level. The power control signal PCON may also include power adjustment signals for each operating mode of the multiple camera modules 1100a, 1100b, and 1100c. For example, the operating mode may include a low-power mode, in which case the power control signal PCON may include information about the camera modules operating in low-power mode and the power levels to be set. The power levels provided to each of the multiple camera modules 1100a, 1100b, and 1100c are either identical or different. Furthermore, the power levels can be dynamically changed.

[0191] As described above, exemplary embodiments have been disclosed in the drawings and specification. While specific terms have been used to describe embodiments in this specification, these are solely for the purpose of illustrating the technical idea of ​​the invention and not to limit its meaning or the scope of the invention as defined in the claims. Therefore, a person with ordinary skill in the art will understand that various modifications and equivalent other embodiments are possible therefrom. Accordingly, the true technical scope of protection of the invention must be determined by the technical idea of ​​the claims. [Industrial applicability]

[0192] The present invention is applicable, for example, to the field of image sensors. [Explanation of symbols]

[0193] CL Column Line ENL (Enable Signal No. 1) ENH 2nd Enable Signal PX pixels RAMP lamp signal SWI1 First Input Switch SWI2 Second Input Switch VPIX Pixel Voltage 160 CDS circuit 160L 1st comparator 160H 2nd comparator 170 Counter Circuit

Claims

1. During the first and fourth periods in which the pixel operates in low conversion gain (LCG) mode, a first comparator operates based on a first bias current and compares the pixel voltage output from the pixel with a ramp signal. The system includes a second comparator, different from the first comparator, which operates based on a second bias current and compares the pixel voltage output from the pixel with the ramp signal during the second and third periods in which the pixel operates in high conversion gain (HCG) mode, The second period follows the first period, the third period follows the second period, the fourth period follows the third period, and the first through fourth periods are continuous within one frame. During the second and third periods, the first comparator operates based on a third bias current lower than the first bias current. During the first and fourth periods, the second comparator operates based on a fourth bias current lower than the second bias current. A Correlated Double Sampling (CDS) circuit further comprising an input switch circuit that provides the pixel voltage output from the pixel to the first comparator during the first and fourth periods, and provides the pixel voltage of the pixel as input to the second comparator during the second and third periods.

2. The first comparator is, The first capacitor and the second capacitor, An input stage that receives the pixel voltage through the first capacitor and the lamp signal through the second capacitor, A first current source that generates the first current, A second current source that generates a second current, A first switch connected between the first current source and the input stage, The system includes a second switch connected between the second current source and the input stage, The CDS circuit according to claim 1, characterized in that the first switch is always turned on, and the second switch is turned on during the first period and the fourth period.

3. During the first and fourth periods, the sum of the first current and the second current is provided as the first bias current. The CDS circuit according to claim 2, characterized in that the first current is provided as the third bias current during the second and third periods.

4. The first comparator is, The input stage includes a first auto-zero switch connected between the first input node and the first output node, and a second auto-zero switch connected between the second input node and the second output node, The CDS circuit according to claim 2, characterized in that the first auto-zero switch and the second auto-zero switch are turned on during the initial interval of the first period to perform auto-zero operation.

5. The first comparator is, The CDS circuit according to any one of claims 1 to 4, characterized in that, during the first period, an LCG reset signal representing the reset level of the pixel is received as the pixel voltage, and during the fourth period, an LCG image signal due to the charge generated by the pixel is received as the pixel voltage.

6. The first comparator is, The CDS circuit according to claim 5, characterized in that, in the initial section of the first period, a first auto-zero operation is performed based on the lamp signal and the LCG reset signal.

7. The second comparator is, The CDS circuit according to any one of claims 1 to 6, characterized in that, during the second period, an HCG reset signal representing the reset level of the pixel is received as the pixel voltage, and during the third period, an HCG image signal due to the charge generated by the pixel is received as the pixel voltage.

8. The second comparator is, The CDS circuit according to claim 7, characterized in that, in the initial section of the second period, a second auto-zero operation is performed based on the lamp signal and the HCG reset signal.

9. The aforementioned pixel is A photoelectric conversion element that converts received light into electric charge, A floating diffusion node that stores the charge received from the photoelectric conversion element, A transmission transistor connecting the photoelectric conversion element and the floating diffusion node, A reset transistor for resetting the floating diffusion node, A drive transistor that converts the potential of the floating diffusion node into the pixel voltage, The CDS circuit according to any one of claims 1 to 8, comprising a transistor that is turned on to the LCG mode, increases the capacitance of the floating diffusion node, and is turned off to the HCG mode.

10. A pixel that outputs a first pixel signal in the first conversion gain mode and a pixel that outputs a second pixel signal in the second conversion gain mode, A ramp signal generator that generates a ramp signal in which the level decreases at a predetermined gradient, The system includes a CDS (Correlated Double Sampling) circuit that receives the first pixel signal and the second pixel signal from the pixel through a column line, compares the ramp signal with the received first pixel signal to generate a first comparison result signal, and compares the ramp signal with the received second pixel signal to generate a second comparison result signal, The CDS circuit described above is During a first sub-period of the reading period for the pixel, a first comparator operates based on a first bias current and compares the first pixel signal received from the pixel with the ramp signal, During the second subperiod of the reading period, a second comparator different from the first comparator is included, which operates based on a second bias current and compares the second pixel signal received from the pixel with the ramp signal, wherein the second subperiod follows the first subperiod, and the first and second subperiods are consecutive. During the second sub-period, the first comparator operates based on a third bias current lower than the first bias current, and during the first sub-period, the second comparator operates based on a fourth bias current lower than the second bias current. The aforementioned pixel is An image sensor characterized in that, during the first sub-period, it outputs a first reset signal according to the first conversion gain mode, and during the second sub-period, it outputs a second reset signal according to the second conversion gain mode, and the second sub-period is continuous with the first sub-period.

11. The image sensor according to claim 10, further comprising a counting circuit that generates a first pixel value and a second pixel value based on the first comparison result signal and the second comparison result signal.

12. The first comparator is, An input stage that receives the first pixel signal through the first capacitor and the ramp signal through the second capacitor, A first current source that generates a first current and is connected to the input stage, A second current source that generates a second current, A switch connected between the second current source and the input stage, The image sensor according to claim 10 or 11, characterized in that the switch is turned on during the first sub-period and turned off during the second sub-period.

13. The second comparator is, An input stage that receives the second pixel signal through a third capacitor and the ramp signal through a fourth capacitor, A third current source is connected to the input stage and generates a third current. A fourth current source that generates a fourth current, A switch connected between the fourth current source and the input stage, The image sensor according to any one of claims 10 to 12, characterized in that the switch is turned on during the second sub-period and turned off during the first sub-period.

14. In a method for operating a CDS circuit including a first comparator and a second comparator different from the first comparator, During the first period, the first comparator is used to generate a first reset value using a first reset signal output from a pixel; In the second period, the second comparator is used to generate a second reset value using the second reset signal output from the pixel; In the third period, the second comparator is used to generate a second image value using the second image signal output from the pixel; The fourth period includes the step of generating a first image value using the first comparator with respect to the first image signal output from the pixel, The second period follows the first period, the third period follows the second period, the fourth period follows the third period, and the first through fourth periods are continuous within one frame. A method for operating a CDS circuit, characterized in that, during the first and fourth periods, the first comparator operates based on a first bias current, and during the second and third periods, the first comparator operates based on a second bias current lower than the first bias current.

15. The method for operating a CDS circuit according to claim 14, characterized in that during the second and third periods, the second comparator operates based on a third bias current, and during the first and fourth periods, the second comparator operates based on a fourth bias current lower than the third bias current.

16. The first comparator is, A first input stage includes a first input transistor and a second input transistor, wherein the first input transistor sequentially receives the first reset signal and the first image signal, and the second input transistor receives a ramp signal that is compared with the first reset signal and the first image signal. A first current is generated that flows through the first input stage, and a first current source is connected to the first input stage, A second current source that generates a second current that flows through the first input stage, A switch connected between the second current source and the first input stage, The method of operating a CDS circuit according to claim 14 or 15, characterized in that the switch is turned on during the first and fourth periods, and the switch is turned off during the second and third periods.

17. The aforementioned pixel is A method for operating a CDS circuit according to any one of claims 14 to 16, characterized in that it operates in low conversion gain (LCG) mode during the first and fourth periods, and in high conversion gain (HCG) mode during the second and third periods.

18. A method for operating a CDS circuit according to any one of claims 14 to 17, characterized in that a first pixel value is generated based on the first reset value and the first image value, and a second pixel value is generated based on the second reset value and the second image value.