Phase-change memory device and method for manufacturing a crossbar-type phase-change memory cell.

Abstract

A phase change memory cell having a pillar bottom electrode with improved thermal insulation. A phase change memory device includes a bottom electrode; a stack of alternating conductive layers in direct contact with a top surface of the bottom electrode; a metal pillar in direct contact with a top surface of the stack; a phase change material element in direct contact with a top surface of the metal pillar; and a top electrode on the phase change material element, wherein a lateral dimension of the metal pillar is smaller than a lateral dimension of the stack.

Description

Technical Field

[0001] The present disclosure generally relates to phase change memory (PCM) cells.

Background Art

[0002] PCM is a new non-volatile (NV) random access memory (RAM) that offers several advantages over existing non-volatile memories (NVM). It has potential for both conventional memory applications and neuromorphic computing.

[0003] One of the main considerations in PCM devices is their programming current, which can become very large during the power-consuming reset step. By reducing the contact area between the heater element and the phase change element, it is possible to easily reduce the set / reset current.

[0004] Furthermore, most of the heat is generated at the interface between the patterned contact and the phase change layer due to current confinement. Most of the heat generated within the cell will ultimately heat the nearby dielectric and metal electrodes. The thermal energy is usually lost through the bottom electrode because it is the most thermally conductive path from the interface.

[0005] Therefore, a new bottom electrode integration technique is needed to reduce the programming current and heat loss within the PCM device.

Summary of the Invention

[0006] According to one aspect of the present invention, there is provided a phase change memory device including a bottom electrode; a stack of alternating conductor layers in direct contact with the upper surface of the bottom electrode; a metal pillar in direct contact with the upper surface of the stack; a phase change material element in direct contact with the upper surface of the metal pillar; and an upper electrode on the phase change material element, wherein the lateral dimension of the metal pillar is smaller than the lateral dimension of the stack.

[0007] According to another aspect of the present invention, a method is provided for manufacturing a crossbar-type phase-change memory cell, comprising the steps of: providing a lower electrode to be placed on a lower layer; forming a multilayer stack comprising a plurality of alternating conductive layers; depositing an uppermost metal layer formed from a material different from the material of the multilayer stack on the multilayer stack; forming a hard mask pillar on the uppermost metal layer; etching the uppermost metal layer to form a metal pillar; forming an internal spacer surrounding the metal pillar; patterning the multilayer stack using the hard mask pillar; forming a dielectric layer having the same height as the upper surface of the metal pillar; removing the hard mask pillar; and forming a phase-change material element on the metal pillar.

[0008] As used herein, “facilitating” an action includes performing an action, making an action easier, assisting in the performance of an action, or causing an action to be performed. Therefore, as an example, and not an limitation, an instruction running on one processor may facilitate an action performed by an instruction running on a remote processor by sending appropriate data or commands that trigger or assist in the performance of the action. To avoid doubt, even when an agent facilitates an action by means other than performing the action itself, the action is still performed by some entity or combination of entities.

[0009] One or more embodiments or elements of the present invention can be implemented in the form of a computer program product including a computer-readable storage medium with computer-usable program code for performing the method steps shown. Furthermore, one or more embodiments or elements of the present invention can be implemented in the form of a system (or device) including memory and at least one processor coupled to the memory and operable to perform the exemplary method steps. Furthermore, in another embodiment, one or more embodiments of the present invention or elements can be implemented in the form of means for performing one or more of the method steps described herein; such means may include (i) a hardware module, (ii) a software module stored in a computer-readable storage medium (or more such media) and implemented on a hardware processor, or (iii) a combination of (i) and (ii); any of (i) to (iii) implements the particular techniques described herein.

[0010] The technology of the present invention can yield highly beneficial technical effects. Some embodiments may not have these potential advantages, and these potential advantages are not necessarily required in all embodiments. For example, one or more embodiments may have: A metal pillar with a small width that reduces the programming current required to perform a phase change; The lateral dimensions of the metal pillar are smaller than the lithography capability configured to achieve a low programming current; Internal spacers surrounding metal pillars to reduce lateral heat loss of metal nanopillars; and A stack of alternating conductive layers beneath a metal pillar reduces downward heat loss. You may provide it.

[0011] These and other features and advantages of the present invention will become apparent from the following detailed description of exemplary embodiments, which should be read in conjunction with the accompanying drawings. [Brief explanation of the drawing]

[0012] Preferred embodiments of the present invention will be described in further detail below with reference to the attached drawings.

[0013] [Figure 1] This invention provides a method for forming PCM cells according to one or more embodiments of the present invention.

[0014] [Figure 2] This is a cross-sectional view of a PCM at different steps in a manufacturing process according to one or more embodiments of the present invention. [Figure 3] This is a cross-sectional view of a PCM at different steps in a manufacturing process according to one or more embodiments of the present invention. [Figure 4] This is a cross-sectional view of a PCM at different steps in a manufacturing process according to one or more embodiments of the present invention. [Figure 5] This is a cross-sectional view of a PCM at different steps in a manufacturing process according to one or more embodiments of the present invention. [Figure 6] This is a cross-sectional view of a PCM at different steps in a manufacturing process according to one or more embodiments of the present invention. [Figure 7] This is a cross-sectional view of a PCM at different steps in a manufacturing process according to one or more embodiments of the present invention. [Figure 8] This is a cross-sectional view of a PCM at different steps in a manufacturing process according to one or more embodiments of the present invention. [Figure 9] This is a cross-sectional view of a PCM at different steps in a manufacturing process according to one or more embodiments of the present invention. [Figure 10] This is a cross-sectional view of a PCM at different steps in a manufacturing process according to one or more embodiments of the present invention. [Figure 11] This is a cross-sectional view of a PCM at different steps in a manufacturing process according to one or more embodiments of the present invention. [Figure 12]Cross-sectional views of a PCM at different steps of a manufacturing process, according to one or more embodiments of the present invention.

[0015] [Figure 13] Cross-sectional views of a PCM at different steps of a directional etching process, according to one or more embodiments of the present invention. [Figure 14] Cross-sectional views of a PCM at different steps of a directional etching process, according to one or more embodiments of the present invention.

[0016] [Figure 15] A diagram of a PCM cell stack, according to one or more embodiments of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0017] According to an embodiment of the present invention, a method and structure for forming a phase change memory (PCM) cell having a metal pillar / heater on a multi-layer metal electrode (i.e., a pillar bottom electrode) are provided. According to some embodiments, the width dimension of the metal pillar is smaller than the current lithography limit. According to some aspects, a metal pillar having a width dimension smaller than the lithography limit is a metal nanopillar. According to some embodiments, a self-aligned internal spacer surrounds the metal nanopillar / heater, and the self-aligned internal spacer is a thermal and electrical insulator.

[0018] [[ID=2,6]] Here, the present application will be described in more detail by referring to the following discussion and the accompanying drawings of the present application. Note that the drawings of the present application are provided for illustrative purposes only, so the drawings are not to scale. Also note that similar elements and corresponding elements are referred to by similar reference numerals.

[0019] The following description includes numerous specific details, such as particular structures, components, materials, dimensions, processing steps, and techniques, in order to provide an understanding of the various embodiments of the present application. However, those skilled in the art will understand that the various embodiments of the present application can be carried out without these specific details. In other examples, well-known structures or processing steps are not described in detail to avoid obscuring the present application.

[0020] The manufacturing of semiconductor devices involves various steps in the device patterning process. For example, the manufacturing of a semiconductor chip may begin with multiple device patterns generated by, for example, CAD (computer-aided design), followed by the task of replicating these device patterns on a substrate. The replicating process may involve the use of various exposure techniques and various subtractive (etching) and / or additive (deposition) material processing procedures. For example, in the photolithography process, a layer of photoresist material is first applied onto a substrate and then selectively exposed according to a predetermined device pattern or multiple patterns. In the photoresist, the portion exposed to light or other ionizing radiation (e.g., ultraviolet light, electron beam, X-rays, etc.) may undergo some changes in its solubility in a particular solution. The photoresist is then developed in a developer, thereby removing the unirradiated portion (in the case of negative resist) or the irradiated portion (in the case of positive resist) of the resist layer, thereby creating a photoresist pattern or photomask. The photoresist pattern or photomask can then be copied or transferred to the substrate beneath the photoresist pattern.

[0021] Numerous techniques are used by those skilled in the art to remove material at various stages in the formation of semiconductor structures. As used herein, these processes are collectively referred to as “etching.” For example, etching includes techniques such as wet etching, dry etching, reactive ion etching (COR) etching, and reactive ion etching (RIE), all of which are known techniques for removing selected material when forming semiconductor structures. Standard Clean 1 (SC1) contains a strong base, typically ammonium hydroxide, and hydrogen peroxide. SC2 contains a strong acid, such as hydrochloric acid and hydrogen peroxide. Etching techniques and applications are well understood by those skilled in the art, and therefore, a more detailed description of such processes is not presented herein.

[0022] While the overall fabrication method and the resulting structures are novel, the specific individual processing steps required to carry out the method can utilize conventional semiconductor fabrication techniques and tools. These techniques and tools will be well known to those skilled in the art, given the teachings herein. Although several individual processing steps are described herein, these steps are merely illustrative, and it should be emphasized that those skilled in the art may be familiar with several equally suitable alternatives that are applicable.

[0023] Please understand that the various layers and / or regions shown in the attached drawings may not be depicted to scale. Furthermore, one or more semiconductor layers of types commonly used in such integrated circuit devices may be omitted from the given drawings for the sake of simplicity. This does not imply that the omitted semiconductor layers will be omitted in actual integrated circuit devices.

[0024] Referring to Figure 12, in some embodiments, in a crossbar-type phase-change material (PCM) array having an upper electrode and a lower electrode, each PCM cell 1200 has a mushroom-shaped PCM element 1201 connected to an upper electrode 1202 and a metal nanopillar 1203 having small dimensions (e.g., smaller than the lithography limit). In some embodiments, the metal nanopillar 1203 is a heater. The small contact area between the metal nanopillar and the mushroom-shaped PCM element reduces the total heat required for the phase change, and consequently reduces the current required for each set or reset operation. In some embodiments, an internal spacer 1204 surrounding the metal nanopillar can act as an insulating layer to prevent heat from moving away from the contact area and into the surrounding material.

[0025] Figure 1 shows a method 100 for manufacturing a crossbar-type PCM array having an upper electrode and a lower electrode, according to one or more embodiments of the present invention.

[0026] According to some embodiments of the present invention and with reference to Figure 1, a method 100 for forming a phase-change memory (PCM) cell having a lower electrode (pillar type) on a multilayer metal electrode comprises the steps of: providing a lower layer in step 101; and forming an interlevel dielectric (ILD) to be placed on the lower layer, and a lower electrode to be placed in the ILD and on the lower layer in step 102. The lower layer may comprise a semiconductor substrate, and it should be understood that the semiconductor substrate itself may include other devices such as transistors, isolation structures, and contacts.

[0027] According to some embodiments, the electrodes of the PCM cell (e.g., upper and lower electrodes) can be formed from TiN, TaN, tungsten (W), aluminum (Al), Ti, Ta, titanium silicon nitride (TiSiN), titanium aluminum nitride (TiAlN), tungsten nitride (WN), and other suitable metals.

[0028] According to some embodiments, a multilayer stack is formed in step 103. The multilayer stack may include a titanium nitride (TiN) / tantalum nitride (TaN) multilayer stack. According to some embodiments, the first TiN layer may have a greater thickness than any of the other multilayers.

[0029] In some embodiments, an uppermost metal layer is deposited in step 104, and this uppermost metal layer is different from the TiN or TaN layer. Optionally, the lower TiN layer may have the same thickness as the subsequent TiN layer.

[0030] According to exemplary embodiments, in step 105, a hard mask pillar can be formed on the uppermost metal layer. According to some embodiments, the uppermost metal layer can be selectively etched using the hard mask pillar as a mask.

[0031] According to some embodiments, in step 106, isotropic (lateral) etching of the top metal layer is performed to remove the edges of the top metal layer and to form metal nanopillars beneath the hard mask pillars. According to some embodiments, the isotropic etching process can be selective for TaN and TiN, thereby preventing damage to the multilayer stack.

[0032] According to exemplary embodiments, the dimensions of the metal nanopillars can exceed (i.e., be smaller than) the dimensions that can be formed by lithography, thereby reducing the contact area with the upper phase change material, reducing the total amount of heat required for the phase change, and consequently reducing the current required for each set or reset operation.

[0033] According to some embodiments, in step 107, a dielectric liner is deposited and etched back using a hard mask pillar as a mask to form an internal spacer.

[0034] According to some embodiments, in step 108, directional reactive ion etching (RIE) of the multilayer stack is performed, which stops at the bottom electrode.

[0035] According to some embodiments, in step 109, a dielectric layer (e.g., an oxide) is deposited, and chemical mechanical polishing (CMP) is performed, which stops at the top of the metal nanopillar.

[0036] According to some embodiments, in step 110, a phase change material such as Ge2Se2Te5(GST) is deposited.

[0037] According to some embodiments, in step 111, a TiN hard mask is formed and used to pattern the phase change material.

[0038] According to some embodiments, in step 112, an encapsulation layer such as SiN is deposited, a second dielectric layer is deposited, and CMP is performed.

[0039] According to some embodiments, in step 113, vias are formed in the encapsulation layer and the second dielectric layer to expose the hard mask, and the upper electrode and upper electrode contact are formed by metallization. The width dimension of the metal pillar can be smaller than the lithography capability / limit, resulting in a reduced contact area with the upper phase change material, thereby reducing the programming current.

[0040] Figures 2 to 12 are cross-sectional views of the PCM at different steps of the manufacturing process shown in Figure 1, according to one or more embodiments of the present invention.

[0041] According to some embodiments of the present invention and with reference to Figure 2, a lower layer 201 is provided. The lower layer 201 may include a semiconductor substrate, which itself may include other devices, such as transistors, isolation structures, contacts, etc. According to some embodiments, an ILD 202 is deposited on the lower layer 201, and a lower electrode 203 is placed on the lower layer 201 and within the ILD 202. For example, the ILD 202 can be patterned to expose the lower layer 201 by forming an opening therein, and a metallic material can be deposited by metallization. The excess metallic material can be removed by CMP to form the lower electrode 203.

[0042] According to some embodiments, the lower electrode 203 can be formed from TiN, TaN, W, Al, Ti, Ta, TiSiN, TiAlN, WN, and other suitable metals.

[0043] According to several embodiments and with reference to Figure 3, the multilayer stack 300 may comprise alternating layers of TiN 301a, 301b, 301c and TaN 302a, 302b, 302c. According to several embodiments, the bottom TiN layer 301a of the multilayer stack 300 may have a thickness greater than the combined thickness of the remaining TiN and TaN layers. According to several embodiments, the bottom TiN layer 301a may have the same thickness as the other TiN layers in the multilayer stack 300. It should be understood that any number of layers can be formed. According to several embodiments, an uppermost metal layer 303 is deposited, and this uppermost metal layer is formed from a different material than the TiN or TaN layers.

[0044] According to some embodiments and with reference to Figure 4, hard mask pillars 401 can be formed on the uppermost metal layer 303. According to some embodiments, the uppermost metal layer 303 can be selectively etched with respect to the hard mask pillars 401.

[0045] According to some embodiments and with reference to Figure 5, isotropic (lateral) etching of the top metal layer is performed to remove the edges of the top metal layer and form metal nanopillars 1203 beneath the hard mask pillars 401. According to some embodiments, the isotropic etching process can be selective for TaN or TiN.

[0046] According to an exemplary embodiment, the dimensions of the metal nanopillar 1203 can be smaller than the dimensions that can be formed by lithography, resulting in a smaller contact area with the upper phase change material, a reduction in the total heat required for the phase change, and consequently a reduction in the current required for each set or reset operation.

[0047] According to several embodiments and with reference to Figure 6, a dielectric liner (not shown) is deposited and etched back using a hard mask pillar 401 as a mask to form internal spacers 1204 around a metal nanopillar 1203. The internal spacers 1204 may be formed from materials including, but not limited to, oxide materials such as silicon nitride (SixNy), silicon oxynitride (SiON), and / or silicon carbide nitride (SiCN), and / or silicon oxide (SiOx).

[0048] According to some embodiments and with reference to Figure 7, a directional RIE of a multilayer stack is performed, which stops at the bottom electrode 203 to form a patterned multilayer stack 701 including patterned layers of TiN, e.g., 702 and TaN, e.g., 703.

[0049] According to some embodiments and with reference to Figure 8, a dielectric layer 801 (e.g., an oxide) is deposited, and chemical mechanical polishing (CMP) is performed, which stops on top of the metal nanopillar 1203.

[0050] According to some embodiments and with reference to Figure 9, a PCM901 such as Ge2Se2Te5(GST) is deposited on the dielectric layer 801. The PCM901 may be formed from, for example, a Ge-Sb-Te (germanium-antimony-tellurium or "GST", e.g., Ge2Sb2Te5) alloy. Other suitable materials for PCM901 include Si-Sb-Te (silicon-antimony-tellurium) alloys, Ga-Sb-Te (gallium-antimony-tellurium) alloys, Ge-Bi-Te (germanium-bismuth-tellurium) alloys, In-Te (indium-tellurium) alloys, As-Sb-Te (arsenic-antimony-tellurium) alloys, Ag-In-Sb-Te (silver-indium-antimony-tellurium) alloys, Ge-In-Sb-Te alloys, Ge-Sb alloys, Sb-Te alloys, Si-Sb alloys, and combinations thereof. In some embodiments, PCM901 may further contain nitrogen, carbon, and / or oxygen. In some embodiments, PCM901 can be doped with dielectric materials including, but not limited to, aluminum oxide (Al2O3), silicon oxide (SiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), zirconium oxide (ZrO2), cerium oxide (CeO2), silicon nitride (SiN), silicon oxynitride (SiON), and others.

[0051] According to some embodiments and with reference to Figure 10, for example, an upper hard mask 1001 formed from TiN is formed and used to pattern the PCM 901, and a mushroom-shaped PCM element 1201 is formed.

[0052] According to some embodiments and with reference to Figure 11, an encapsulation layer 1101 such as SiN is deposited, a second dielectric layer 1102 is deposited, and CMP is performed to planarize the second dielectric layer.

[0053] According to some embodiments and with reference to Figure 12, vias are formed in the encapsulation layer 1101 and the second dielectric layer 1102 to expose the upper surface of the upper hard mask 1001, and metallization is performed to form the upper electrode 1202 and upper electrode contact 1205. The dimensions of the metal nanopillar 1203 can be smaller than the limits of lithography, resulting in a smaller contact area with the mushroom-shaped PCM element 1201 and a reduction in programming current.

[0054] Referring to Figure 12, in some embodiments, the PCM cell 1200 includes a mushroom-shaped PCM element 1201 connected to an upper electrode 1202 and a metal nanopillar 1203 having small dimensions (e.g., smaller than the lithography limit). The small contact area between the metal nanopillar and the mushroom-shaped PCM element 1201 reduces the total heat required for phase transitions, and consequently reduces the current required for each set or reset operation. In some embodiments, an internal spacer 1204 surrounding the metal nanopillar can act as a thermal insulation layer to prevent heat from moving away from the contact area and into the surrounding material.

[0055] Figures 13 and 14 are cross-sectional views of a PCM cell at different steps of a directional etching process according to one or more embodiments of the present invention.

[0056] According to several embodiments and with reference to Figure 13, directional RIE of a multilayer stack can be performed following the formation of the hard mask pillar 401 in step 105. The directional RIE of the multilayer stack stops at the lower electrode 203 and forms a patterned multilayer stack 1301 including patterned layers of TiN, e.g. 702 and TaN, e.g. 703, and a patterned top metal layer 1302.

[0057] According to some embodiments and with reference to Figure 14, in step 106, isotropic (lateral) etching is performed on the top metal layer 1302 to be patterned to remove the edges of the top metal layer to be patterned and to form metal nanopillars beneath the hard mask pillars. According to some embodiments, the isotropic etching process can be selective for TaN, TiN, and the material forming the metal nanopillars. Following the isotropic etching in step 106, a dielectric liner (not shown) is deposited and etched back to form internal spacers around the metal nanopillars 1203 (see, for example, internal spacer 1204 in Figure 7). The method can proceed to step 109, in which a dielectric layer is deposited and chemical mechanical polishing (CMP) is performed, which removes the hard mask pillars 401 and stops at the top of the metal nanopillars 1203.

[0058] Figure 15 shows a PCM cell 1501 according to one or more embodiments of the present invention. The first lateral dimension d0 of the metal nanopillar 1203 is smaller than the lateral dimension of conventional lithography capabilities. The lateral dimension d0 is related to the reduction of programming current. The internal spacer 1204 surrounding the metal nanopillar 1203 can act as an insulating layer to reduce or prevent lateral heat loss.

[0059] According to some embodiments, alternating conductive layers having a second transverse dimension d1 (e.g., patterned layers of TiN, e.g. 702, and TaN, e.g. 703) beneath the metal nanopillar 1203 further reduce downward heat loss.

[0060] According to some embodiments, metal nanopillars 1203 that reduce programming current, internal spacers 1204 that reduce lateral heat loss, and alternating conductive layers (e.g., patterned layers of TiN, e.g. 702, and TaN, e.g. 703) that reduce downward heat loss improve the overall efficiency of the PCM cell 1501.

[0061] Summary

[0062] According to embodiments of the present invention, the phase-change memory device includes a lower electrode 203; a stack of alternating conductive layers 701 in direct contact with the upper surface of the lower electrode; a metal pillar 1203 in direct contact with the upper surface of the stack; a phase-change material element 1201 in direct contact with the upper surface of the metal pillar; and an upper electrode 1202 on the phase-change material element, wherein the lateral dimension of the metal pillar is smaller than the lateral dimension of the stack.

[0063] According to some embodiments, a method 100 for manufacturing a crossbar-type phase-change memory cell includes the steps of: providing a lower electrode to be placed on a lower layer in step 101; forming a multilayer stack comprising a plurality of alternating conductive layers in step 103; depositing an uppermost metal layer formed from a material different from the multilayer stack material in step 104; forming hard mask pillars on the uppermost metal layer in step 105; etching the uppermost metal layer to form metal pillars in step 106; forming internal spacers surrounding the metal pillars in step 107; patterning the multilayer stack using the hard mask pillars in step 108; forming a dielectric layer having the same height as the upper surface of the metal pillars in step 109; removing the hard mask pillars, also in step 109; and forming a phase-change material element on the metal pillars in step 111.

[0064] According to some embodiments, the steps of forming a phase change material element include: step 110, depositing a phase change material; step 111, forming an upper hard mask on the phase change material; and step 111, patterning the phase change material using the upper hard mask to form a phase change material element.

[0065] According to some embodiments, the method includes the steps of: depositing an encapsulation layer to cover a phase-change material element in step 112; depositing a second dielectric layer on the encapsulation layer in step 112; forming vias in the encapsulation layer and the second dielectric layer to expose an upper hard mask in step 113; and performing metallization in step 113 to form an upper electrode and an upper electrode contact that contacts the upper hard mask.

[0066] According to some embodiments, the step of forming the internal spacer in step 107 includes the steps of depositing a dielectric liner on a multilayer stack and etching back the dielectric liner to the width of the hard mask pillar.

[0067] According to some embodiments, the patterning of the multilayer stack using hard mask pillars in step 108 is performed before the step in step 106 in which the top metal layer is etched to form metal pillars, and before the step in step 107 in which internal spacers are formed.

[0068] The terms used herein are intended to describe only specific embodiments and are not intended to limit the invention. Where used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms similarly, unless the context explicitly indicates otherwise. Where used herein, the terms “comprise” and / or “comprising” identify the presence of the described features, integers, steps, actions, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, actions, elements, components, and / or groups thereof.

[0069] Any means-plus-function element or step-plus-function element in the following claims, corresponding structures, materials, actions, and equivalents, are intended to include any structures, materials, or actions for performing a function in combination with any other claimed element specifically claimed. The descriptions of various embodiments of the present invention are presented for illustrative purposes only and are not intended to be exhaustive or limitful to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope of the described embodiments. The terms used herein have been selected to best describe the principles of the embodiments, their practical applications, or any technical improvements beyond the technology available on the market, or to enable those else skilled in the art to understand the embodiments disclosed herein.

Claims

1. Lower electrode; A stack of alternating conductive layers in direct contact with the upper surface of the lower electrode; A metal pillar in direct contact with the upper surface of the aforementioned stack; A phase change material element in direct contact with the upper surface of the metal pillar; and Upper electrode on the aforementioned phase-change material device The lateral dimension of the metal pillar is smaller than the lateral dimension of the stack, The stack of alternating conductive layers The bottom titanium nitride (TiN) layer; and Topmost tantalum nitride (TaN) layer Includes, The thickness of the bottom TiN layer is greater than the thickness of any other layer in the stack. Phase-change memory device.

2. The lower layer below the lower electrode; and The interlayer dielectric located on the lower layer and surrounding the lower electrode. The phase-change memory device according to claim 1, further comprising:

3. A thermally and electrically insulating spacer located on the stack and surrounding the metal pillar beneath the phase-change material element. The phase-change memory device according to claim 1, further comprising:

4. The phase-change memory device according to claim 3, wherein the thermally and electrically insulating spacer has a width equal to the width of the stack.

5. A first dielectric layer surrounding the stack; An encapsulation layer formed to cover the phase-change material element and the first dielectric layer; and Second dielectric layer formed on the encapsulation layer The phase change memory device according to claim 1, further comprising: the upper electrode being formed on the second dielectric layer; and the upper electrode further comprising an upper electrode contact that electrically connects the upper electrode to the phase change material element.

6. The phase change memory device according to claim 5, further comprising an upper hard mask between the phase change material element and the upper electrode contact.

7. The phase change memory device according to claim 5, wherein the upper electrode contact extends through the encapsulation layer.

8. The phase change memory device according to claim 1, further comprising an upper hard mask on the phase change material element having the same width as the phase change material element.

9. The phase change memory device according to any one of claims 1 to 8, wherein the metal pillar is formed from a material other than TiN and TaN.

10. The phase change memory device according to any one of claims 1 to 8, wherein the metal pillar is formed from a material different from the material of the stack of alternating conductive layers.

11. The phase change memory device according to any one of claims 1 to 8, wherein the metal pillar is a heater.

12. The phase change memory device according to any one of claims 1 to 8, wherein the metal pillar is a heater configured to heat the phase change material element.

13. A method for manufacturing a crossbar-type phase-change memory cell, A step of providing a lower electrode to be placed on the lower layer; The step of forming a multilayer stack containing multiple alternating conductive layers; A step of depositing an uppermost metal layer, formed from a material different from the material of the multilayer stack, onto the multilayer stack; The step of forming a hard mask pillar on the uppermost metal layer; The step of etching the uppermost metal layer to form a metal pillar; The step of forming an internal spacer surrounding the aforementioned metal pillar; The step of patterning the multilayer stack using the hard mask pillar; A step of forming a dielectric layer having the same height as the upper surface of the metal pillar; The step of removing the hard mask pillar; and The step of forming a phase change material element on the metal pillar. A method that includes [a certain feature].

14. The step of forming the aforementioned phase change material element is: The stage of depositing phase change material; The step of forming an upper hard mask on the phase change material; and The method according to claim 13, further comprising the step of patterning the phase change material using the upper hard mask to form the phase change material element.

15. A step of depositing an encapsulation layer so as to cover the aforementioned phase change material element; A step of depositing a second dielectric layer on the aforementioned encapsulation layer; A step of forming vias in the encapsulation layer and the second dielectric layer to expose the upper hard mask; and Steps to perform metallization to form the upper electrode and the upper electrode contact that contacts the upper hard mask. The method according to claim 14, further comprising:

16. The step of forming the internal spacer is, A step of depositing a dielectric liner on the multilayer stack; and The step of etching back the dielectric liner to the width of the hard mask pillar. The method according to claim 13, further comprising:

17. The method according to claim 13, wherein the patterning of the multilayer stack using the hard mask pillar is performed before the step of etching the top metal layer to form the metal pillar and the step of forming the internal spacer.

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