Method for manufacturing a substrate with a chip, and a substrate processing apparatus.
Patent Information
- Authority / Receiving Office
- JP · JP
- Patent Type
- Patents
- Current Assignee / Owner
- TOKYO ELECTRON LTD
- Filing Date
- 2025-05-21
- Publication Date
- 2026-06-30
Smart Images
Figure 0007883021000002 
Figure 0007883021000003 
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Abstract
Description
Technical Field
[0001] The present disclosure relates to a method for manufacturing a substrate with chips and a substrate processing apparatus.
Background Art
[0002] In FIG. 20 of Patent Document 1, a manufacturing process of chips on a wafer is illustrated. In this manufacturing process, the individual first memory chips are bonded one by one to a base wafer on which a plurality of second memory chips are formed.
Prior Art Documents
Patent Documents
[0003]
Patent Document 1
Summary of the Invention
Problems to be Solved by the Invention
[0004] One aspect of the present disclosure provides a technique for reusing alignment marks used for alignment during bonding of a chip and a substrate or for measurement of positional deviation after bonding.
Means for Solving the Problems
[0005] The method for manufacturing a substrate with chips according to one aspect of the present disclosure is as follows The process includes preparing a laminated substrate comprising a plurality of chips, a first substrate to which the plurality of chips are temporarily bonded, and a second substrate bonded to the first substrate via the plurality of chips. The plurality of chips bonded to the first substrate and the second substrate are separated from the first substrate by dividing the first substrate in the thickness direction at a dividing line. The first substrate includes alignment marks used for measuring the alignment of the first substrate and the chips during bonding, or for measuring misalignment after bonding. The dividing line is located between the chips and the alignment marks. The separation of the plurality of chips from the first substrate includes irradiating the first substrate with a laser beam.
Effects of the Invention
[0006] According to one aspect of the present disclosure, alignment marks can be reused.
Brief Description of the Drawings
[0007] [Figure 1] FIG. 1 is a flowchart showing a method for manufacturing a substrate with chips according to an embodiment. [Figure 2]Figure 2 is a flowchart showing the details of S1 in Figure 1. [Figure 3] Figure 3 is a flowchart showing the details of S6 in Figure 1. [Figure 4] Figure 4 is a cross-sectional view showing the intermediate state of S1 in Figure 1. [Figure 5] Figure 5 is a cross-sectional view showing the state at the completion of S1 in Figure 1. [Figure 6] Figure 6 is a cross-sectional view showing the state at the completion of step S2 in Figure 1. [Figure 7] Figure 7 is a cross-sectional view showing the state at the completion of S3 in Figure 1. [Figure 8] Figure 8 is a cross-sectional view showing the intermediate state of S4 in Figure 1. [Figure 9] Figure 9 is a cross-sectional view showing the state at the completion of S4 in Figure 1. [Figure 10] Figure 10 is a cross-sectional view showing the state at the completion of S5 in Figure 1. [Figure 11] Figure 11 is a cross-sectional view showing the state upon completion of S61 in Figure 3, which is included in S6 in Figure 1. [Figure 12] Figure 12 is a cross-sectional view showing the state upon completion of S62 in Figure 3, which is included in S6 in Figure 1. [Figure 13] Figure 13 is a cross-sectional view showing the state upon completion of S63 in Figure 3, which is included in S6 in Figure 1. [Figure 14] Figure 14 is a cross-sectional view showing the state at the completion of step S7 in Figure 1. [Figure 15A] Figure 15A is a cross-sectional view showing an example of the first step in the method for forming a Ge film. [Figure 15B] Figure 15B is a cross-sectional view showing an example of the second step in the Ge film formation method. [Figure 15C] Figure 15C is a cross-sectional view showing an example of the third step in the Ge film formation method. [Figure 15D] Figure 15D is a cross-sectional view showing an example of the fourth step in the Ge film formation method. [Figure 15E] Figure 15E is a cross-sectional view showing an example of the fifth step in the Ge film formation method. [Figure 15F] FIG. 15F is a cross-sectional view showing an example of the sixth step of the method for forming a Ge film. [Figure 16] FIG. 16 is a diagram showing an example of the transmittance of a SiGe film. [Figure 17A] FIG. 17A is a cross-sectional view showing an example of the first step of the method for forming a metal silicide film. [Figure 17B] FIG. 17B is a cross-sectional view showing an example of the second step of the method for forming a metal silicide film. [Figure 17C] FIG. 17C is a cross-sectional view showing an example of the third step of the method for forming a metal silicide film. [Figure 17D] FIG. 17D is a cross-sectional view showing an example of the fourth step of the method for forming a metal silicide film. [Figure 17E] FIG. 17E is a cross-sectional view showing an example of the fifth step of the method for forming a metal silicide film. [Figure 17F] FIG. 17F is a cross-sectional view showing an example of the sixth step of the method for forming a metal silicide film. [Figure 17G] FIG. 17G is a cross-sectional view showing an example of the seventh step of the method for forming a metal silicide film. [Figure 18] FIG. 18 is a diagram showing an example of the absorption rate of a metal silicide film. [Figure 19A] FIG. 19A is a cross-sectional view showing an example of the first step of the method for forming an AlN film. [Figure 19B] FIG. 19B is a cross-sectional view showing an example of the second step of the method for forming an AlN film. [Figure 19C] FIG. 19C is a cross-sectional view showing an example of the third step of the method for forming an AlN film. [Figure 19D] FIG. 19D is a cross-sectional view showing an example of the fourth step of the method for forming an AlN film. [Figure 19E] FIG. 19E is a cross-sectional view showing an example of the fifth step of the method for forming an AlN film. [Figure 19F] FIG. 19F is a cross-sectional view showing an example of the sixth step of the method for forming an AlN film. [Figure 19G] Figure 19G is a cross-sectional view showing an example of the seventh step in the AlN film formation method. [Figure 20] Figure 20 shows an example of the transmittance of an AlN film. [Figure 21] Figure 21 is a plan view showing a substrate processing apparatus according to one embodiment. [Modes for carrying out the invention]
[0008] Embodiments of this disclosure will be described below with reference to the drawings. In each drawing, the same or corresponding components are denoted by the same reference numerals, and their descriptions may be omitted.
[0009] A method for manufacturing a substrate with a chip includes, for example, steps S1 to S7 shown in Figure 1. Step S1 in Figure 1 includes, for example, steps S11 to S14 shown in Figure 2. Also, step S6 in Figure 1 includes, for example, steps S61 to S63 shown in Figure 3.
[0010] First, in step S1 of Figure 1, the first substrate 1 and chips 2A and 2B are joined together, as shown in Figures 4 and 5. In step S11 of Figure 2, which is included in step S1 of Figure 1, the first substrate 1 and chips 2A and 2B are prepared.
[0011] The first substrate 1 includes, for example, a silicon wafer 11, an absorption layer 12, and a bonding layer 13. The absorption layer 12 may also serve as the bonding layer 13, as will be described later, and the first substrate 1 only needs to have a silicon wafer 11 and an absorption layer 12. A compound semiconductor wafer may be used instead of the silicon wafer 11. The compound semiconductor wafer is not particularly limited, but examples include GaAs wafers, SiC wafers, GaN wafers, InP wafers, or AlN wafers.
[0012] The absorption layer 12 is placed between the silicon wafer 11 and chips 2A and 2B. As will be described in more detail later, as shown in Figure 11, the laser beam LB2 passes through the silicon wafer 11 and is absorbed by the absorption layer 12. Since the laser beam LB2 is absorbed by the absorption layer 12 and does not hit chips 2A and 2B, damage to chips 2A and 2B can be suppressed. The absorption layer 12 is, for example, a silicon oxide layer and is formed by thermal oxidation or CVD (Chemical Vapor Deposit) method.
[0013] The absorption layer 12 only needs to be able to absorb the laser beam LB2 to the extent that it can suppress damage to the chips 2A and 2B, and may be a silicon nitride layer or a silicon carbonitride layer. The silicon nitride layer is formed by thermal nitriding or CVD. The silicon carbonitride layer is formed by CVD.
[0014] As shown in Figure 4, the bonding layer 13 is positioned between the absorption layer 12 and the chips 2A and 2B, and is in contact with the chips 2A and 2B. The bonding layer 13 is an insulating layer, such as a silicon oxide layer. The bonding layer 13 may be made of a different material than the absorption layer 12, or it may be made of the same material. In the latter case, the absorption layer 12 may also serve as the bonding layer 13.
[0015] The first substrate 1 includes alignment marks 15. The alignment marks 15 are used for positioning the first substrate 1 and chips 2A and 2B during bonding, or for measuring misalignment after bonding. The alignment marks 15 may be used for both positioning and measuring misalignment. The measurement results of misalignment after bonding can be used, for example, for positioning the first substrate 1 and chips during subsequent bonding. The measurement results of misalignment after bonding can also be used for quality control, such as identifying defective products.
[0016] As shown in Figure 12, the alignment marks 15 are formed between the silicon wafer 11 and the absorption layer 12, and are formed on the opposite side from chips 2A and 2B with respect to the dividing surface D. By dividing the first substrate 1 at the dividing surface D, the silicon wafer 11 can be separated from chips 2A and 2B. The silicon wafer 11 separated from chips 2A and 2B has the alignment marks 15. Therefore, when reusing the silicon wafer 11, it is not necessary to reform the alignment marks 15, and the alignment marks 15 can be reused.
[0017] The alignment mark 15 absorbs infrared light used for imaging the alignment mark 15. The infrared camera images the alignment mark 15 by receiving infrared light that has passed through the silicon wafer 11. The wavelength of the infrared light used for imaging is different from the wavelength of the laser beam LB2, and is, for example, 1000 nm to 2000 nm. The absorption rate of the infrared light used for imaging the alignment mark 15 is, for example, 45% to 100%, preferably 50% to 100%, and more preferably 60% to 100%.
[0018] As shown in Figure 11, the alignment mark 15 transmits the laser beam LB2. The laser beam LB2 passes through the silicon wafer 11 and the alignment mark 15, forming a modified layer M in the absorption layer 12. The modified layer M is formed when the absorption layer 12 absorbs the laser beam LB2. Multiple modified layers M are formed on the dividing surface D. The division is performed starting from the multiple modified layers M. The wavelength of the laser beam LB2 is, for example, 8800 nm to 11000 nm. The transmittance of the laser beam LB2 through the alignment mark 15 is, for example, 45% to 100%, preferably 50% to 100%, and more preferably 60% to 100%.
[0019] As described above, the alignment mark 15 is formed from a material that absorbs infrared light used for imaging the alignment mark 15 and transmits the laser beam LB2. Specifically, for example, the alignment mark 15 includes a Ge film, a SiGe film, a metal silicide film, or an AlN film. Unlike the SiO2 film and metal films, the Ge film absorbs infrared light for imaging and transmits the laser beam LB2. Incidentally, the SiO2 film transmits infrared light for imaging and absorbs the laser beam LB2. Also, while metal films can absorb infrared light for imaging, they also absorb the laser beam LB2. The method for forming the alignment mark 15 will be described later.
[0020] Chip 2A comprises a silicon wafer 21A and a device layer 22A. The device layer 22A is formed on the surface of the silicon wafer 21A. The device layer 22A includes semiconductor elements, circuits, or terminals. After the formation of the device layer 22A, the silicon wafer 21A is fragmented into multiple chips 2A.
[0021] Chip 2B, like chip 2A, has a silicon wafer 21B and a device layer 22B. The device layer 22B has a different function from the device layer 22A and has a different thickness from chip 2A and chip 2B. After the formation of the device layer 22B, the silicon wafer 21B is fragmented into multiple chips 2B.
[0022] In step S12 in Figure 2, which is included in step S1 in Figure 1, the bonding surface 14 of the first substrate 1 is surface modified using plasma or the like. Specifically, the SiO2 bonds on the bonding surface 14 are broken, unbonded Si bonds are formed, and the bonding surface 14 becomes hydrophilic.
[0023] For example, under a reduced pressure atmosphere, oxygen gas, which is the processing gas, is excited, turned into plasma, and ionized. Oxygen ions are irradiated onto the bonding surface 14, and the bonding surface 14 is modified. The processing gas is not limited to oxygen gas; for example, nitrogen gas may also be used.
[0024] In step S12 above, not only the bonding surface 14 of the first substrate 1, but also the bonding surfaces 24A and 24B of the chips 2A and 2B may be surface modified. At least one of the bonding surface 14 of the first substrate 1 and the bonding surfaces 24A and 24B of the chips 2A and 2B is surface modified.
[0025] In step S13 in Figure 2, which is included in step S1 in Figure 1, the bonding surface 14 of the first substrate 1 is made hydrophilic. For example, the first substrate 1 is held by a spin chuck, and pure water such as DIW (deionized water) is supplied to the bonding surface 14 of the first substrate 1, which rotates with the spin chuck. OH groups attach to the unbonded Si atoms on the bonding surface 14, making the bonding surface 14 hydrophilic.
[0026] In step S13 above, not only the bonding surface 14 of the first substrate 1, but also the bonding surfaces 24A and 24B of the chips 2A and 2B may be made hydrophilic. At least one of the bonding surface 14 of the first substrate 1 and the bonding surfaces 24A and 24B of the chips 2A and 2B is made hydrophilic.
[0027] In step S14 in Figure 2, which is included in step S1 in Figure 1, chips 2A and 2B are temporarily bonded one by one to the bonding surface 14 of the first substrate 1. Chips 2A and 2B are bonded to the first substrate 1 with their device layers 22A and 22B facing the first substrate 1.
[0028] Chips 2A and 2B and the first substrate 1 are joined by van der Waals forces (intermolecular forces) and hydrogen bonds between OH groups. Subsequently, heat treatment may be performed to increase the bonding strength. Heat treatment causes a dehydration reaction. Since solids are directly bonded together without using liquid adhesive, positional displacement due to adhesive deformation and tilting due to uneven adhesive thickness can be prevented.
[0029] Incidentally, in the above-mentioned Patent Document 1, unlike the technology of this disclosure, chips 2A and 2B are permanently bonded to the third substrate 6, which will be described later, without taking the step of temporarily bonding the chips 2A and 2B to the first substrate 1. Therefore, during bonding, it is necessary to simultaneously suppress the inclusion of air bubbles and foreign matter, and to perform precise position control.
[0030] As described in Patent Document 1 above, when joining chips 2A and 2B one by one to the third substrate 6, in order to suppress the inclusion of air bubbles during joining, chips 2A and 2B can be deformed one by one. The joining surfaces 24A and 24B of chips 2A and 2B are deformed into downwardly convex curved surfaces, and are gradually joined to the third substrate 6 from the center to the periphery, eventually returning to a flat surface.
[0031] Deforming the joint surfaces 24A and 24B of chips 2A and 2B into a convex curved surface involves fixing the respective peripheries of chips 2A and 2B and pressing down on the respective centers of chips 2A and 2B. However, since the individual sizes of chips 2A and 2B are small, the distance between the fixing point and the pressing point is narrow. Therefore, it is difficult to deform chips 2A and 2B one by one.
[0032] According to this embodiment, chips 2A and 2B are temporarily bonded to the first substrate 1 and later separated from the first substrate 1. Therefore, even if air bubbles get trapped during bonding of chips 2A and 2B to the first substrate 1, it does not pose a problem. Accordingly, in S14, the bonding surfaces 24A and 24B of chips 2A and 2B can be bonded to the bonding surface 14 of the first substrate 1 while remaining flat. Since chips 2A and 2B are not deformed, the accuracy of position control of chips 2A and 2B can be improved, and chips 2A and 2B can be accurately placed in the desired position.
[0033] Furthermore, according to this embodiment, chips 2A and 2B are temporarily bonded to the first substrate 1 and later separated from the first substrate 1. Therefore, even if particles get caught during the bonding of chips 2A and 2B to the first substrate 1, it does not pose a problem. Consequently, the bonding surface 14 of the first substrate 1 and the bonding surfaces 24A and 24B of chips 2A and 2B may be dirty to a degree that does not hinder bonding. A lower level of cleanliness is required.
[0034] Next, in step S2 of Figure 1, as shown in Figure 6, multiple chips 2A and 2B are thinned to make their thickness uniform. In Figure 6, the dashed line shows the state immediately before S2, and the solid line shows the state after S2 is completed. Of the chips 2A and 2B, the silicon wafers 21A and 21B are thinned, while the device layers 22A and 22B are not. Thinning includes grinding or laser processing.
[0035] Next, in step S3 of Figure 1, a bonding layer 3 is formed on the surfaces of chips 2A and 2B, as shown in Figure 7. The bonding layer 3 is an insulating layer such as a silicon oxide layer, similar to the bonding layer 13 of the first substrate 1, and is formed by CVD or similar methods. Chips 2A and 2B are placed at intervals from each other, and since the surface beneath the bonding layer 3 has irregularities, the surface of the bonding layer 3 also has irregularities.
[0036] Next, in S4 of Figure 1, the surface of the bonding layer 3 is planarized as shown in Figures 8 and 9. Since the bonding layer 3 is a silicon oxide layer and has high hardness, polishing such as CMP (Chemical Mechanical Polishing) takes time to planarize it.
[0037] First, as shown in Figure 8, the laser beam LB1 is irradiated onto the protrusions 31 of the bonding layer 3. The protrusions 31 absorb the laser beam LB1 and either change state from solid to gas and scatter, or scatter while remaining in the solid state. The laser beam LB1 may also be irradiated onto the recesses 32 of the bonding layer 3. If the irradiation intensity of the recesses 32 is lower than that of the protrusions 31, the surface of the bonding layer 3 can be flattened.
[0038] The irradiation point of the laser beam LB1 is moved by a galvanometer scanner or an XYθ stage. The galvanometer scanner moves the laser beam LB1. The XYθ stage moves the first substrate 1 horizontally (in the X-axis and Y-axis directions) and rotates it around the vertical axis. An XYZθ stage may be used instead of the XYθ stage.
[0039] Next, as shown in Figure 9, the surface of the bonding layer 3 is further flattened using CMP or the like. Since the protrusions 31 have been selectively removed before CMP, the waviness remaining on the surface of the bonding layer 3 after CMP can be reduced.
[0040] Next, in step S5 of Figure 1, the chips 2A and 2B are bonded to the second substrate 5, as shown in Figure 10. The second substrate 5 comes into contact with the flattened surface of the bonding layer 3 and is bonded to the chips 2A and 2B via the bonding layer 3.
[0041] The second substrate 5 includes, for example, a silicon wafer 51 and a bonding layer 53. The bonding layer 53 is an insulating layer, such as a silicon oxide layer, similar to the bonding layer 13 of the first substrate 1, and is formed by a CVD method or the like.
[0042] At least one of the bonding surface 54 of the second substrate 5 and the bonding surface 34 of the bonding layer 3 may be subjected to surface modification and hydrophilization before bonding. The second substrate 5 and the bonding layer 3 are bonded together by van der Waals forces (intermolecular forces) and hydrogen bonds between OH groups. Since solids are directly bonded together without using a liquid adhesive, positional displacement due to deformation of the adhesive can be prevented. In addition, tilting due to uneven thickness of the adhesive can be prevented.
[0043] The second substrate 5 is joined to the first substrate 1 via the bonding layer 3, with its bonding surface 54 facing downwards. In other words, the substrates are bonded together. At this time, the bonding surface 54 of the second substrate 5 is deformed into a curved surface that is convex downwards to prevent air bubbles from getting trapped, and the bonding is gradually performed from the center to the periphery, eventually returning to a flat surface.
[0044] The deformation of the second substrate 5 can be achieved by fixing its periphery and pressing down on its center. When deforming the second substrate 5, the distance between the fixing point and the pressing point is wider compared to deforming chips 2A and 2B one by one, making deformation easier. The ease of deformation is due to the bonding of the substrates together.
[0045] Note that the arrangement of the second substrate 5 and the first substrate 1 may be reversed, the second substrate 5 may be positioned below the first substrate 1, and the bonding surface 54 of the second substrate 5 may face upward. In this case, the bonding surface 54 of the second substrate 5 is deformed into an upwardly convex curved surface to prevent air bubbles from getting trapped, and is gradually bonded from the center to the periphery, eventually returning to a flat surface.
[0046] The bonding of the second substrate 5 and the first substrate 1 is carried out gradually from the center to the periphery, with the second substrate 5 being bent and deformed first, although the first substrate 1 may be bent and deformed first. In this case as well, the substrates will be bonded together. However, from the viewpoint of protecting chips 2A and 2B, it is preferable to hold the first substrate 1 flat and the chips 2A and 2B flat.
[0047] Next, in step S6 of Figure 1, chips 2A and 2B are separated from the first substrate 1, as shown in Figures 11, 12, and 13. In step S61 of Figure 3, which is included in step S6 of Figure 1, multiple modified layers M are formed on the dividing surface D, which is intended to divide the first substrate 1 in the thickness direction, using a laser beam LB2, as shown in Figure 11. The modified layers M are formed in a point-like manner, for example, at or above the focal point.
[0048] The laser beam LB2 passes through the silicon wafer 11 of the first substrate 1, forming a modified layer M on the absorption layer 12 of the first substrate 1. The absorption layer 12 is positioned between the silicon wafer 11 and the chips 2A and 2B, and absorbs the laser beam LB2. Since the laser beam LB2 hardly hits the chips 2A and 2B, damage to the chips 2A and 2B can be suppressed.
[0049] The laser beam LB2 has a wavelength of, for example, 8800 nm to 11000 nm so that it passes through the silicon wafer 11 and alignment marks 15 and is absorbed by the absorption layer 12. The light source for the laser beam LB2 is, for example, a CO2 laser. The wavelength of the CO2 laser is approximately 9300 nm. The laser beam LB2 is pulsed.
[0050] The formation position of the modified layer M is moved by a galvanometer scanner or an XYθ stage. The galvanometer scanner moves the laser beam LB2. The XYθ stage moves the first substrate 1 horizontally (in the X-axis and Y-axis directions) and rotates it around the vertical axis. An XYZθ stage may be used instead of the XYθ stage.
[0051] Multiple modified layers M are formed on the first substrate 1 at intervals in the circumferential and radial directions. During the formation of the modified layers M, cracks CR are also formed that connect the modified layers M to each other.
[0052] In step S62 in Figure 3, which is included in step S6 in Figure 1, the first substrate 1 is divided starting from the modified layer M, as shown in Figure 12. First, the upper chuck 131 holds the first substrate 1 and the lower chuck 132 holds the second substrate 5. However, the arrangement of the first substrate 1 and the second substrate 5 may be reversed, with the upper chuck 131 holding the second substrate 5 and the lower chuck 132 holding the first substrate 1. Next, as the upper chuck 131 rises relative to the lower chuck 132, the crack CR spreads planarly starting from the modified layer M, and the first substrate 1 is divided at the dividing surface D.
[0053] In step S62 above, the upper chuck 131 may be rotated around its vertical axis along with its upward movement. The first substrate 1 can be threaded at the dividing surface D. Alternatively, instead of raising the upper chuck 131, or in addition to raising the upper chuck 131, the lower chuck 132 may be lowered. The lower chuck 132 may also be rotated around its vertical axis.
[0054] In step S63 in Figure 3, which is included in step S6 in Figure 1, the residue 16 of the first substrate 1 adhering to chips 2A and 2B is removed by CMP or the like, as shown in Figure 13. The residue 16 includes a part of the absorption layer 12 and the bonding layer 13. After the removal of the residue 16, the device layers 22A and 22B of chips 2A and 2B are exposed again. The device layers 22A and 22B are, for example, semiconductor memory.
[0055] Next, in step S7 of Figure 1, as shown in Figure 14, chips 2A and 2B are bonded to one side 64 of the third substrate 6, including the device layer 62, while they are bonded to the second substrate 5. The third substrate 6 includes a silicon wafer 61 and a device layer 62.
[0056] The device layer 62 is formed on the surface of the silicon wafer 61. The device layer 62 includes semiconductor elements, circuits, or terminals, and is electrically connected to the device layers 22A and 22B of chips 2A and 2B. The device layer 62 is, for example, a peripheral circuit (also called "peripheral") or an I / O circuit (also called "IO") of a semiconductor memory.
[0057] At least one of the bonding surfaces 64 of the third substrate 6 and the bonding surfaces 24A and 24B of the chips 2A and 2B may be subjected to surface modification and hydrophilization before bonding. The third substrate 6 and the chips 2A and 2B are bonded together by van der Waals forces (intermolecular forces) and hydrogen bonds between OH groups. Since solids are directly bonded together without using liquid adhesive, misalignment due to deformation of the adhesive can be prevented. In addition, tilting due to uneven thickness of the adhesive can be prevented.
[0058] The third substrate 6 is bonded to the second substrate 5 via chips 2A and 2B, with its bonding surface 64 facing downwards. In other words, the substrates are bonded together. At this time, the bonding surface 64 of the third substrate 6 is deformed into a downwardly convex curved surface to prevent air bubbles from getting trapped, and the bonding is gradually performed from the center to the periphery, eventually returning to a flat surface.
[0059] The deformation of the third substrate 6 can be achieved by fixing its periphery and pressing down on its center. When deforming the third substrate 6, the distance between the fixing point and the pressing point is wider compared to when deforming chips 2A and 2B one by one, making deformation easier. The ease of deformation is due to the bonding of the substrates together.
[0060] Note that the arrangement of the third substrate 6 and the second substrate 5 may be reversed, the third substrate 6 may be positioned below the second substrate 5, and the bonding surface 64 of the third substrate 6 may face upward. In this case, the bonding surface 64 of the third substrate 6 is deformed into an upwardly convex curved surface to prevent air bubbles from getting trapped, and the bonding is gradually performed from the center to the periphery, eventually returning to a flat surface. In this case as well, the substrates are bonded together.
[0061] Furthermore, the bonding of the third substrate 6 and the second substrate 5 is carried out gradually from the center to the periphery, with the third substrate 6 being bent and deformed first. However, the second substrate 5 may be bent and deformed first. In this case as well, the substrates will be bonded together.
[0062] As described in S7 above, a substrate with chips 7 is obtained. The substrate with chips 7 includes a third substrate 6 and a plurality of chips 2A and 2B. The substrate with chips 7 further includes a second substrate 5. Note that the second substrate 5 may be separated from the chips 2A and 2B, and the substrate with chips 7 only needs to include the third substrate 6 and the chips 2A and 2B.
[0063] As explained above, according to this embodiment, in order to obtain the chip-equipped substrate 7, instead of bonding multiple chips 2A and 2B one by one to one side of the third substrate 6, they are first temporarily bonded to one side of the first substrate 1. Since air bubbles are not a problem at this stage, the bonding surfaces 24A and 24B of the chips 2A and 2B can be bonded to the bonding surface 14 of the first substrate 1 while remaining flat. Since the chips 2A and 2B do not need to be forcibly deformed, the accuracy of position control of the chips 2A and 2B can be improved, and the chips 2A and 2B can be accurately placed in the desired position.
[0064] Subsequently, the multiple chips 2A and 2B bonded to the first substrate 1 are bonded to the surface of the second substrate 5 facing the first substrate 1. Next, the multiple chips 2A and 2B bonded to the first substrate 1 and the second substrate 5 are separated from the first substrate 1. Then, with the multiple chips 2A and 2B separated from the first substrate 1 still bonded to the second substrate 5, they are bonded to one side 64 of the third substrate 6, including the device layer 62.
[0065] In this process, the bonding surface 64 of the third substrate 6 is deformed into a downwardly convex curved surface to prevent air bubbles from getting trapped, and is gradually bonded from the center to the periphery, finally returning to a flat surface. Deforming the third substrate 6 is easier than deforming the chips 2A and 2B one by one, because it is a bonding of substrates. Therefore, compared to the case where chips 2A and 2B are permanently bonded to the third substrate 6 without taking the step of temporarily bonding the chips 2A and 2B to the first substrate 1 as in Patent Document 1, a substrate 7 with chips attached is obtained that is free from air bubbles and has good positional accuracy.
[0066] Furthermore, according to this embodiment, the silicon wafer 11 separated from chips 2A and 2B has alignment marks 15. Therefore, when reusing the silicon wafer 11, it is not necessary to reform the alignment marks 15, and the alignment marks 15 can be reused. The silicon wafer 11 separated from chips 2A and 2B is bonded to a chip other than chips 2A and 2B.
[0067] Next, with reference to Figures 15A to 15F, a method for forming the Ge film, which is an alignment mark, will be described. This formation method includes steps 1 to 6. In the first step, a silicon wafer 11 is prepared as shown in Figure 15A.
[0068] In the second step, as shown in Figure 15B, the surface of the silicon wafer 11 is etched to form trenches. The depth of the trenches is not particularly limited, but is, for example, 100 nm.
[0069] In the third step, as shown in Figure 15C, an SiO2 film 17 is formed on the surface of the silicon wafer 11, and the trenches are filled with the SiO2 film 17. The SiO2 film 17 is formed, for example, by CVD using TEOS (tetraethoxysilane). The thickness of the SiO2 film 17 is not particularly limited, but is, for example, 100 nm.
[0070] In the fourth step, as shown in Figure 15D, the SiO2 film 17 is planarized by CMP or the like, exposing a portion of the surface of the silicon wafer 11. The remaining surface of the silicon wafer 11 is covered with the SiO2 film 17. The thickness of the remaining SiO2 film 17 is not particularly limited, but is, for example, 100 nm.
[0071] In the fifth step, as shown in Figure 15E, the exposed surface of the silicon wafer 11 is etched to form trenches between the SiO2 films 17. The depth of the trenches is not particularly limited, but is, for example, 100 nm.
[0072] In the sixth step, as shown in Figure 15F, a SiGe film 15A is epitaxially grown on the bottom surface of the trench in the silicon wafer 11, and a Ge film 15B is epitaxially grown on top of the SiGe film 15A. Alignment marks are formed, including the SiGe film 15A and the Ge film 15B. The thickness of the SiGe film 15A is not particularly limited, but is, for example, 20 nm. The thickness of the Ge film 15B is not particularly limited, but is, for example, 80 nm.
[0073] Table 1 shows an example of the optical properties of a Ge film with a thickness of 80 nm.
[0074] [Table 1]
[0075] As shown in Table 1, a Ge film with a thickness of 80 nm has an absorption rate of 59.0% for infrared light at a wavelength of 1000 nm, and can absorb the infrared light used for imaging. Furthermore, a Ge film with a thickness of 80 nm has a transmittance of 63.0% for laser light at a wavelength of 9300 nm, and can transmit the laser light used to form the modified layer.
[0076] Next, the method for forming the SiGe film, which serves as the alignment mark, will be described. The method for forming the SiGe film is similar to the method for forming the Ge film shown in Figures 15A to 15F, except that in the sixth step, after epitaxial growth of a 100 nm thick SiGe film 15A, the Ge film 15B is not epitaxially grown. Alignment marks consisting only of the SiGe film 15A are formed. This shortens the process compared to the case where the alignment mark includes both the SiGe film 15A and the Ge film 15B. Note that the thickness of the SiGe film 15A is not limited to 100 nm.
[0077] Figure 16 shows an example of the optical properties of a SiGe film with a thickness of 100 nm. In Figure 16, the solid line shows the optical properties of the SiGe film, and the dashed line shows the optical properties of bare silicon. A SiGe film with a thickness of 100 nm has a transmittance of approximately 48% for laser light at a wavelength of 9300 nm, and can transmit the laser light used to form the modified layer.
[0078] Next, with reference to Figures 17A to 17G, the method for forming the metal silicide film, which serves as the alignment mark, will be described. This method includes steps 1 to 7. Steps 1 to 4, shown in Figures 17A to 17D, are the same as steps 1 to 4, shown in Figures 15A to 15D, so their explanation will be omitted.
[0079] In the fifth step, as shown in Figure 17E, a Ni film 18 is formed on the surface of the silicon wafer 11. The Ni film 18 covers not only the exposed surface of the silicon wafer 11 but also the surface of the SiO2 film 17. The thickness of the Ni film 18 is not particularly limited, but is, for example, 20 nm.
[0080] In the sixth step, as shown in Figure 17F, the silicon wafer 11 is heated to react with the Ni film 18 to form a NiSi2 film 15C. The heating temperature of the silicon wafer 11 is not particularly limited, but is, for example, 500°C.
[0081] In the seventh step, as shown in Figure 17G, the Ni film 18 is removed using SPM or the like to expose the NiSi2 film 15C. SPM is an aqueous solution containing sulfuric acid and hydrogen peroxide. The mixing ratio is, for example, 1:1:5 by mass (H2SO4:H2O2:H2O=1:1:5). The etching time for the Ni film 18 with SPM is, for example, 15 minutes.
[0082] Alignment marks containing the NiSi2 film 15C are formed. Note that the metal silicide is not limited to NiSi2, but may be, for example, TiSi2 or CoSi. The film thickness of NiSi2 is, for example, 20 nm to 40 nm. The film thickness of TiSi2 is, for example, 50 nm to 80 nm. The film thickness of CoSi is, for example, 30 nm to 50 nm.
[0083] Figure 18 shows an example of the absorption rate of a TiSi2 film with a thickness of 210 nm. As shown in Figure 18, a TiSi2 film with a thickness of 210 nm has an absorption rate of approximately 90% for infrared light with wavelengths of 1000 nm to 2000 nm, and can absorb the infrared light used for imaging. In addition, a TiSi2 film with a thickness of 210 nm has an absorption rate of approximately 15% for laser light with a wavelength of 9300 nm, and can transmit the laser light used to form the modified layer.
[0084] Generally, the thinner the film thickness, the lower the absorption rate and the higher the transmittance. Therefore, a TiSi2 film with a thickness of 50 nm to 80 nm has an absorption rate of less than approximately 15% for laser light with a wavelength of 9300 nm, and can transmit the laser light used to form the modified layer.
[0085] Next, the method for forming the AlN film, which serves as the alignment mark, will be described with reference to Figures 19A to 19G. The formation method includes steps 1 to 7. Steps 1 to 5, shown in Figures 19A to 19E, are the same as steps 1 to 5, shown in Figures 15A to 15E, so their explanation will be omitted.
[0086] In the sixth step, as shown in Figure 19F, an AlN film 15D is formed on the surface of the silicon wafer 11, and the trenches are filled with the AlN film 15D. The AlN film 15D is formed, for example, by the ALD (Atomic Layer Deopsiton) method using TMA (trimethylsilane).
[0087] Specifically, an AlN film is formed by repeatedly supplying a plasma-enhanced mixed gas (a mixed gas containing Ar gas, H2 gas, and N2 gas), Ar gas, TMA gas, and Ar gas in this order. The mixing ratio of the mixed gas is, for example, 1:6:3 by volume (Ar:H2:N2 = 1:6:3). The supply of the plasma-enhanced mixed gas forms NH groups on the surface of the silicon wafer 11. The NH groups react with the TMA gas to form an AlN film. The AlN film formed by this method is blue in color and will therefore be referred to as a blue AlN film. The blue AlN film is blue because it contains impurities. The thickness of the blue AlN film is not particularly limited, but is, for example, 100 nm.
[0088] In the seventh step, as shown in Figure 19G, the AlN film 15D is planarized by CMP or the like to expose a portion of the surface of the silicon wafer 11. The remaining surface of the silicon wafer 11 is covered with the AlN film 15D. The thickness of the remaining AlN film 15D is not particularly limited, but is, for example, 100 nm. Alignment marks including the AlN film 15D are formed.
[0089] Figure 20 shows an example of the transmittance of a blue AlN film with a thickness of 100 nm. A blue AlN film with a thickness of 100 nm has a transmittance of approximately 60% for infrared light at a wavelength of 1000 nm, and can absorb the infrared light used for imaging. Compared to ordinary AlN films, blue AlN films have a lower transmittance for infrared light at a wavelength of 1000 nm, making them suitable as alignment marks.
[0090] Next, with reference to Figure 21 and the like, the substrate processing apparatus 100 that carries out S61 and S62 in Figure 3 will be described. In Figure 21, the X-axis, Y-axis, and Z-axis directions are perpendicular to each other, the X-axis and Y-axis directions are horizontal, and the Z-axis direction is vertical. The substrate processing apparatus 100 has a loading / unloading unit 101, a transport unit 110, a laser processing unit 120, a dividing unit 130, and a control unit 140.
[0091] The loading / unloading section 101 has a mounting section 102 on which the cassette C is placed. The cassette C accommodates multiple laminated substrates 8, as shown in Figure 10, etc., spaced apart in the vertical direction. The laminated substrate 8 includes multiple chips 2A, 2B, a first substrate 1, and a second substrate 5. As shown in Figure 12, the laminated substrate 8 is divided into a first divided body 81 and a second divided body 82 at the dividing surface D. Thereafter, the first divided body 81 and the second divided body 82 are separately housed in the cassette C. The first divided body 81 includes a silicon wafer 11 and, after being unloaded from the substrate processing apparatus 100, can be reused as a new first substrate 1. In order to reuse the silicon wafer 11 as the first substrate 1, an absorption layer 12 or the like may be re-formed on the surface of the silicon wafer 11. On the other hand, the second divided body 82, which includes chips 2A and 2B, is transported outside the substrate processing apparatus 100 and then subjected to steps S63 in Figure 3 and S7 in Figure 1, etc. Note that the number of mounting sections 102 and the number of cassettes C are not limited to those shown in Figure 21.
[0092] The transport unit 110 is located next to the loading / unloading unit 101, the laser processing unit 120, and the dividing unit 130, and transports the laminated substrate 8 and the like to these units. The transport unit 110 has a holding mechanism for holding the laminated substrate 8 and the like. The holding mechanism is capable of movement in the horizontal direction (both in the X-axis and Y-axis directions) and the vertical direction, as well as rotation around the vertical axis.
[0093] As shown in Figure 11, the laser processing unit 120 forms a plurality of modified layers M with a laser beam LB2 on the dividing surface D of the first substrate 1 which is to be divided in the thickness direction. The modified layers M are formed in a point-like manner, for example, at or above the focal point. The laser processing unit 120 includes, for example, a stage 121 that holds the first substrate 1 and an optical system 122 that irradiates the first substrate 1 held by the stage 121 with the laser beam LB2. The stage 121 is, for example, an XYθ stage or an XYZθ stage. The optical system 122 includes, for example, a focusing lens. The focusing lens focuses the laser beam LB2 toward the first substrate 1. The optical system 122 may further include a galvanometer scanner.
[0094] As shown in Figure 12, the splitting section 130 splits the first substrate 1 starting from the modified layer M. The splitting section 130 includes, for example, an upper chuck 131 and a lower chuck 132. The upper chuck 131 holds the first substrate 1, and the lower chuck 132 holds the second substrate 5. However, the arrangement of the first substrate 1 and the second substrate 5 may be reversed. Next, when the upper chuck 131 rises relative to the lower chuck 132, the crack CR spreads planarly starting from the modified layer M, and the first substrate 1 is split at the splitting surface D. In other words, the laminated substrate 8 is split into a first divided body 81 and a second divided body 82 at the splitting surface D. Along with the rising of the upper chuck 131, rotation of the upper chuck 131 around its vertical axis may be performed. The first substrate 1 can be twisted off at the splitting surface D.
[0095] The control unit 140 is, for example, a computer, and as shown in Figure 21, comprises a CPU (Central Processing Unit) 141 and a storage medium 142 such as memory. The storage medium 142 stores programs that control various processes performed in the substrate processing device 100. The control unit 140 controls the operation of the substrate processing device 100 by causing the CPU 141 to execute the programs stored in the storage medium 142.
[0096] The embodiments of the method for manufacturing a chip-equipped substrate and the substrate processing apparatus described above have been explained, but this disclosure is not limited to the embodiments described above. Various changes, modifications, substitutions, additions, deletions, and combinations are possible within the scope of the claims. These also naturally fall within the technical scope of this disclosure.
[0097] This application claims priority based on Japanese Patent Application No. 2021-013785, filed with the Japan Patent Office on January 29, 2021, and the entire contents of Japanese Patent Application No. 2021-013785 are incorporated herein by reference. [Explanation of Symbols]
[0098] 1. First circuit board 2A, 2B chips 5. Second board 6. Third substrate 7. Circuit board with chip 8. Multilayer substrate 15 Alignment Marks 100 Substrate Processing Equipment 110 Conveying section 120 Laser Processing Section 130 Split section LB2 laser beam D split plane M Modified layer
Claims
1. To prepare a laminated substrate including a plurality of chips, a first substrate to which the plurality of chips are temporarily bonded, and a second substrate bonded to the first substrate via the plurality of chips, By dividing the first substrate in the thickness direction at the dividing plane, the plurality of chips bonded to the first substrate and the second substrate are separated from the first substrate, It has, The first substrate includes alignment marks used for measuring the positional alignment during bonding of the first substrate and the chip, or for measuring misalignment after bonding. The dividing surface is located between the chip and the alignment mark. A method for manufacturing a substrate with chips, comprising separating the plurality of chips from the first substrate by irradiating the first substrate with a laser beam.
2. The method for manufacturing a chip-equipped substrate according to claim 1, comprising irradiating the first substrate with the laser beam to form a plurality of modified layers on the first substrate.
3. The method for manufacturing a chip-equipped substrate according to claim 2, wherein the separation of the plurality of chips from the first substrate includes dividing the first substrate starting from the plurality of modified layers.
4. The method for manufacturing a chip-equipped substrate according to claim 1, wherein the first substrate includes a wafer and an absorption layer that absorbs the laser beam between the wafer and the chip.
5. The method for manufacturing a chip-equipped substrate according to claim 4, wherein the wafer is a silicon wafer, and the laser beam passes through the silicon wafer and is absorbed by the absorption layer.
6. The method for manufacturing a chipped substrate according to claim 4 or 5, wherein the first substrate includes a bonding layer between the absorption layer and the plurality of chips for bonding the first substrate and the plurality of chips.
7. The method for manufacturing a chip-equipped substrate according to claim 4 or 5, wherein the absorption layer also serves as a bonding layer for bonding the first substrate and the plurality of chips.
8. The method for manufacturing a chip-equipped substrate according to claim 4 or 5, wherein the alignment marks transmit the laser beam and absorb infrared light of a different wavelength than the laser beam.
9. The method for manufacturing a chip-attached substrate according to claim 8, wherein the alignment marks include a Ge film, a SiGe film, a metal silicide film, or a blue AlN film.
10. The method for manufacturing a chip-equipped substrate according to claim 8, wherein the wavelength of the laser beam is 8800 nm to 11000 nm.
11. The method for manufacturing a chip-equipped substrate according to claim 8, wherein the wavelength of the infrared radiation is 1000 nm to 2000 nm.
12. A method for manufacturing a chip-equipped substrate according to claim 4 or 5, comprising bonding a plurality of chips separated from the first substrate to one side of the third substrate including the device layer.
13. The method for manufacturing a substrate with a chip according to claim 4 or 5, further comprising bonding a chip other than the chip to the first substrate separated from the chip.
14. A transport unit for transporting a laminated substrate including a plurality of chips, a first substrate to which the plurality of chips are temporarily bonded, and a second substrate bonded to the first substrate via the plurality of chips, A laser processing unit that irradiates the first substrate with a laser beam, A dividing section that divides the first substrate irradiated with the laser beam in the thickness direction at the dividing surface, Equipped with, The first substrate includes alignment marks used for measuring the positional alignment during bonding of the first substrate and the chip, or for measuring misalignment after bonding. The substrate processing apparatus divides the first substrate at the dividing plane located between the alignment mark and the chip.