Manufacturing method of printed circuit boards

Abstract

To provide a method for manufacturing a printed wiring board having high quality.SOLUTION: A method for manufacturing a printed wiring board includes: forming a resin insulation layer having a first surface and a second surface opposite to the first surface on a first conductor layer; forming a protective film on the first surface; forming an opening for a via conductor; cleaning the inside of the opening; removing the protective film from the resin insulation layer; forming a second conductor layer on the first surface of the resin insulation layer; and forming a via conductor. The formation of the second conductor layer includes: forming a seed layer; forming a plating resist; forming an electrolytic plating layer; removing the plating resist; and removing the seed layer exposed from the electrolytic plating layer. The formation of the seed layer includes: forming a first layer composed of an alloy containing copper and specific base metal on the first surface by sputtering; and forming a second layer composed of copper on the first layer by sputtering.SELECTED DRAWING: Figure 1

Description

Technical Field

[0005] , ,

[0001] The technology disclosed by this specification relates to a method for manufacturing a printed wiring board.

Background Art

[0002] Patent Document 1 discloses a printed wiring board including a resin insulating layer and a conductor circuit. The conductor circuit includes an alloy layer formed on the resin insulating layer, an electroless copper plating film formed on the alloy layer, and an electrolytic plating film formed on the electroless copper plating film. The alloy layer is formed of an alloy of copper and nickel, an alloy of copper and molybdenum, an alloy of copper and titanium, etc.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

[0004] [Problems of Patent Document 1] Generally, the electroless copper plating film is formed in the atmosphere. The electroless copper plating film is formed by immersing the intermediate substrate in a solution. Therefore, it is considered that the alloy layer is likely to be oxidized in the electroless copper plating process. When the alloy layer is oxidized, it is considered that the adhesion between the alloy layer and the electroless copper plating film decreases. When the printed wiring board has a via conductor composed of a copper alloy layer, an electroless copper plating film, and an electrolytic plating film, if the diameter of the opening for the via conductor is small, it is considered that the connection reliability between the via conductor and the conductor circuit decreases.

Means for Solving the Problems

[0005] <The present invention provides a method for manufacturing a printed circuit board, comprising: forming a resin insulating layer having a first surface and a second surface opposite to the first surface on a first conductor layer having a conductor circuit; forming a protective film on the first surface of the resin insulating layer; forming an opening for a via conductor that penetrates the resin insulating layer and reaches the first conductor layer; cleaning the opening with plasma; removing the protective film from the resin insulating layer after the cleaning; forming a second conductor layer on the first surface of the resin insulating layer; and forming a via conductor in the opening that connects the first conductor layer and the second conductor layer. The formation of the second conductor layer includes forming a seed layer on the first surface of the resin insulating layer; forming a plating resist on the seed layer; forming an electroplating layer on the seed layer exposed from the plating resist; removing the plating resist; and removing the seed layer exposed from the electroplating layer. Forming the seed layer includes forming a first layer made of an alloy containing copper and a specific base metal on the first surface by sputtering, and forming a second layer made of copper on the first layer by sputtering. The specific base metal is a base metal other than copper.

[0006] In the manufacturing method of the embodiment of the present invention, the first and second layers are formed by sputtering. Since sputtering is performed in a vacuum, oxidation of the first layer is unlikely to occur when the second layer is formed. The first and second layers adhere well to each other. The second layer is unlikely to peel off from the first layer. Even with a small diameter for the via conductor opening, the connection reliability between the via conductor and the first conductor layer is high. A printed circuit board of high quality is provided. [Brief explanation of the drawing]

[0007] [Figure 1] A schematic cross-sectional view showing a printed circuit board of the embodiment. [Figure 2] A schematic, enlarged cross-sectional view showing a portion of the printed circuit board of the embodiment. [Figure 3] A schematic, enlarged cross-sectional view showing a portion of the printed circuit board of the embodiment. [Figure 4A]A schematic cross-sectional view illustrating the manufacturing method of a printed circuit board according to this embodiment. [Figure 4B] A schematic cross-sectional view illustrating the manufacturing method of a printed circuit board according to this embodiment. [Figure 4C] A schematic cross-sectional view illustrating the manufacturing method of a printed circuit board according to this embodiment. [Figure 4D] An enlarged cross-sectional view schematically showing the manufacturing method of the printed circuit board according to the embodiment. [Figure 4E] A schematic cross-sectional view illustrating the manufacturing method of a printed circuit board according to this embodiment. [Figure 4F] An enlarged cross-sectional view schematically showing the manufacturing method of the printed circuit board according to the embodiment. [Figure 4G] A schematic cross-sectional view illustrating the manufacturing method of a printed circuit board according to this embodiment. [Figure 5] A schematic cross-sectional view showing a printed circuit board of a modified embodiment. [Modes for carrying out the invention]

[0008] [Embodiment] Figure 1 is a cross-sectional view showing a printed circuit board 2 of an embodiment. Figures 2 and 3 are enlarged cross-sectional views showing a portion of the printed circuit board 2 of an embodiment. As shown in Figure 1, the printed circuit board 2 has an insulating layer 4, a first conductor layer 10, a resin insulating layer 20, a second conductor layer 30, and via conductors 40.

[0009] The insulating layer 4 is formed using resin. The insulating layer 4 may contain inorganic particles such as silica. The insulating layer 4 may also contain reinforcing materials such as glass cloth. The insulating layer 4 has a third surface 6 (top surface in the figure) and a fourth surface 8 (bottom surface in the figure) opposite to the third surface 6.

[0010] The first conductor layer 10 is formed on the third surface 6 of the insulating layer 4. The first conductor layer 10 includes signal wiring 12 and pads 14. Although not shown in the figure, the first conductor layer 10 also includes conductor circuits other than signal wiring 12 and pads 14. The first conductor layer 10 is mainly made of copper. The first conductor layer 10 is formed of a seed layer 10a on the insulating layer 4 and an electroplating layer 10b on the seed layer 10a. The thickness of the seed layer 10a is less than 0.5 μm. The seed layer 10a is formed of a first layer 11a on the third surface 6 and a second layer 11b on the first layer 11a. The ratio of the thickness of the first layer 11a to the thickness of the second layer 11b (thickness of the first layer / thickness of the second layer) is 0.25 or more and 0.7 or less. The thickness of the second layer 11b is greater than the thickness of the first layer 11a. The first layer 11a is formed of an alloy (copper alloy) containing copper and a specific base metal. The specified base metal is a base metal other than copper. For example, the specified base metal is aluminum. The second layer 11b is made of copper. The electroplating layer 10b is made of copper. The first layer 11a is in contact with the insulating layer 4.

[0011] The copper content in the copper alloy forming the first layer 11a is greater than 90 at%. The copper content in the copper alloy of the first layer 11a is less than 99 at%. The copper content in the copper alloy is 98 at% or less. The copper content forming the second layer 11b is 99.9 at% or more. Preferably, the copper content in the second layer 11b is 99.95 at% or more.

[0012] The resin insulating layer 20 is formed on the third surface 6 of the insulating layer 4 and on the first conductor layer 10. The resin insulating layer 20 has a first surface 22 (top surface in the figure) and a second surface 24 (bottom surface in the figure) opposite to the first surface 22. The second surface 24 of the resin insulating layer 20 faces the first conductor layer 10. The resin insulating layer 20 has an opening 26 that exposes the pad 14. The diameter of the bottom of the opening 26 is 20 μm or more and 50 μm or less. The resin insulating layer 20 is formed of resin 80 and a large number of inorganic particles 90 dispersed within the resin 80. The resin 80 is an epoxy resin. Examples of resins are thermosetting resins and photocurable resins. The inorganic particles 90 are, for example, silica or alumina. The average particle size of the inorganic particles 90 is 0.5 μm or less. The amount of inorganic particles 90 in the resin insulating layer 20 is 75 wt% or more.

[0013] As shown in Figures 1 and 2, the inorganic particles 90 include first inorganic particles 91 partially embedded in the resin 80 and second inorganic particles 92 embedded within the resin 80. The first inorganic particles 91 and the second inorganic particles 92 are spherical in shape. As shown in Figure 2, the first inorganic particle 91 is formed of a first portion 91a protruding from the resin 80 and a second portion 91b embedded in the resin 80. The first surface 22 of the resin insulating layer 20 is formed of the upper surface of the resin 80 and the exposed surface of the first portion 91a exposed from the upper surface of the resin 80.

[0014] The ratio R (volume of the first part / volume of the first particle) of the volume of the first part 91a to the volume of the first inorganic particle 91 is greater than 0 and 0.4 or less. Preferably, the ratio R is 0.2 or less. More preferably, the ratio R is 0.1 or less. Most preferably, the ratio R is 0.05 or less. When the first part 91a protrudes from the resin 80, the first surface 22 of the resin insulating layer 20 has slight irregularities. However, the upper surface of the resin 80 is not roughened. Therefore, the first surface 22 has almost no depressions. The arithmetic mean roughness (Ra) of the first surface 22 is less than 0.08 μm. Preferably, the Ra of the first surface 22 is 0.05 μm or less. More preferably, the Ra of the first surface 22 is 0.03 μm or less.

[0015] As shown in FIGS. 1 and 3, the inorganic particles 90 further include third inorganic particles 93 that form the inner wall surface 27 of the opening 26. The shape of the third inorganic particles 93 is obtained by cutting a sphere with a plane. The shape of the third inorganic particles 93 is obtained by cutting the second inorganic particles 92 with a plane. The shape of the third inorganic particles 93 is different from the shape of the second inorganic particles 92. The third inorganic particles 93 have a flat portion 93a. The flat portion 93a forms the inner wall surface 27. The inner wall surface 27 is formed by the resin 80 and the flat portion 93a. The surfaces of the resin 80 that form the flat portion 93a and the inner wall surface 27 form substantially common surfaces. No irregularities are formed on the resin 80 that forms the inner wall surface 27. The surface of the resin 80 that forms the inner wall surface 27 is substantially smooth. No irregularities are formed on the exposed surface (the surface that forms the inner wall surface 27) of the flat portion 93a. The exposed surface of the flat portion 93a is smooth. The inner wall surface 27 is formed smoothly. The arithmetic mean roughness (Ra) of the inner wall surface 27 is 1.0 μm or less.

[0016] As shown in FIG. 1, the second conductor layer 30 is formed on the first surface 22 of the resin insulating layer 20. The second conductor layer 30 includes a first signal wiring 32, a second signal wiring 34, and a land 36. Although not shown in the figure, the second conductor layer 30 also includes conductor circuits other than the first signal wiring 32, the second signal wiring 34, and the land 36. The first signal wiring 32 and the second signal wiring 34 form a pair wiring. The first signal wiring 32 and the second signal wiring 34 are adjacent to each other. As shown in FIG. 2, the distance D1 between the first signal wiring 32 and the second signal wiring 34 is 1.5 μm or more and 10 μm or less. The distance D1 is preferably 1.5 μm or more and 8 μm or less.

[0017] The second conductor layer 30 is mainly formed of copper. The second conductor layer 30 is formed of a seed layer 30a on the first surface 22 and an electrolytic plating layer 30b on the seed layer 30a. The seed layer 30a is formed of a first layer 31a on the first surface 22 and a second layer 31b on the first layer 31a. The thickness of the seed layer 30a is less than 0.5 μm. The relationship between the thickness of the first layer 31a and the thickness of the second layer 31b is the same as the relationship between the thickness of the first layer 11a and the thickness of the second layer 11b. The first layer 31a and the second layer 31b form the second conductor layer 30, and the first layer 11a and the second layer 11b form the first conductor layer 10. The first layer 31a is formed of an alloy (copper alloy) containing copper and a specific base metal. The specific base metal is a base metal other than copper. The specific base metal is, for example, aluminum. The second layer 31b is formed of copper. The electrolytic plating layer 30b is formed of copper. The first layer 31a is in contact with the first surface 22.

[0018] The copper content in the copper alloy forming the first layer 31a is greater than 90 at%. The copper content in the copper alloy of the first layer 31a is less than 99 at%. The copper content in the copper alloy is 98 at% or less. The copper content of the copper forming the second layer 31b is 99.9 at% or more. It is preferable that the copper content in the second layer 31b is 99.95 at% or more.

[0019] The via conductor 40 is formed in the opening 26. The via conductor 40 connects the first conductor layer 10 and the second conductor layer 30. In FIG. 1, the via conductor 40 connects the pad 14 and the land 36. The via conductor 40 is formed of a seed layer 30a and an electrolytic plating layer 30b on the seed layer 30a. The seed layer 30a forming the via conductor 40 and the seed layer 30a forming the second conductor layer 30 are common. The first layer 31a is in contact with the inner wall surface 27.

[0020] Although not shown in the figure, the length of each side of the printed wiring board 2 is 50 mm or more. It is preferable that the length of each side is 100 mm or more. The length of each side is 250 mm or less.

[0021] [Manufacturing Method of Printed Wiring Board 2 of Embodiment] Figures 4A to 4G show the manufacturing method of the printed circuit board 2 according to the embodiment. Figures 4A to 4C, E, and 4G are cross-sectional views. Figures 4D and 4F are enlarged cross-sectional views. Figure 4A shows the insulating layer 4 and the first conductor layer 10 formed on the third surface 6 of the insulating layer 4. The first conductor layer 10 is formed by a semi-additive method. The first layer 11a and the second layer 11b are formed by sputtering. The first layer 11a and the second layer 11b are formed in a vacuum. The electroplated layer 10b is formed by electroplating.

[0022] As shown in Figure 4B, a resin insulating layer 20 and a protective film 50 are formed on the insulating layer 4 and the first conductor layer 10. The second surface 24 of the resin insulating layer 20 faces the third surface 6 of the insulating layer 4. The protective film 50 is formed on the first surface 22 of the resin insulating layer 20. The resin insulating layer 20 has resin 80 and inorganic particles 90 (second inorganic particles 92). The inorganic particles 90 are embedded in the resin 80.

[0023] The protective film 50 completely covers the first surface 22 of the resin insulating layer 20. An example of the protective film 50 is a film made of polyethylene terephthalate (PET). A release agent is formed between the protective film 50 and the resin insulating layer 20.

[0024] As shown in Figure 4C, a laser beam L is shone onto the protective film 50. The laser beam L penetrates both the protective film 50 and the resin insulating layer 20 simultaneously. An opening 26 for via conductors leading to the pad 14 of the first conductor layer 10 is formed. The laser beam L is, for example, a UV laser beam or a CO2 laser beam. The pad 14 is exposed by the opening 26. When the opening 26 is formed, the first surface 22 is covered with the protective film 50. Therefore, even if resin is scattered when the opening 26 is formed, adhesion of the resin to the first surface 22 is suppressed.

[0025] Figure 4D shows the inner wall surface 27b of the aperture 26 after laser irradiation. The inner wall surface 27b is formed of resin 80 and inorganic particles 90 protruding from the resin 80. To control the shape of the inner wall surface, the inner wall surface 27b is treated after laser irradiation. It is preferable to selectively remove the inorganic particles 90 protruding from the resin 80. This allows third inorganic particles 93 to be formed from the inorganic particles 90. For example, the inorganic particles 90 protruding from the resin 80 can be selectively removed by treating the inner wall surface 27b after laser irradiation with a chemical. Alternatively, the inorganic particles 90 protruding from the resin 80 can be selectively removed by treating the inner wall surface 27b after laser irradiation with plasma. Selective removal includes the etching rate of the inorganic particles 90 being greater than the etching rate of the resin 80. For example, the difference in etching rates between the two is 10 times or more. Alternatively, the difference in etching rates between the two is 50 times or more. Alternatively, the difference in etching rates between the two is 100 times or more. By processing the inner wall surface 27b after laser irradiation, a third inorganic particle 93 having a flat portion 93a (see Figure 3) is obtained. The shape of the inner wall surface 27 can be controlled by controlling the conditions for processing the inner wall surface 27b after laser irradiation. Examples of conditions include temperature, concentration, time, type of gas, and pressure. The etching rate of the inorganic particles 90 and the etching rate of the resin are controlled.

[0026] By irradiating the resin insulating layer 20 with laser light L, a portion of the second inorganic particles 92 embedded in the resin 80 forms the inner wall surface 27b after laser irradiation. The second inorganic particles 92 that form the inner wall surface 27b after laser irradiation are formed by a protruding portion P that protrudes from the resin 80 and a portion E that is embedded in the resin 80. The inner wall surface 27b after laser irradiation is processed. For example, the inner wall surface 27b is processed with a plasma of a gas containing tetrafluoride. The protruding portion P is selectively removed, and the inner wall surface 27 of the embodiment (Figures 1 and 3) is formed. Third inorganic particles 93 are formed from the second inorganic particles 92. By selectively removing the protruding portion P, third inorganic particles 93 having a flat portion 93a are formed. The flat portion 93a is a plane. When the spherical second inorganic particle 92 is cut by a plane, the shape of the third inorganic particle 93 is obtained. The inner wall surface 27 is formed by the flat portion 93a and the surface 80a of the resin 80. The exposed surface 93b of the flat portion 93a and the surface 80a of the resin 80 are located on substantially the same plane. For example, when a seed layer 30a is formed on the inner wall surface 27b by sputtering, the protruding portion P inhibits the growth of the sputtered film. For example, a continuous seed layer 30a cannot be formed on the inner wall surface 27b. Alternatively, the thickness of the seed layer 30a must be increased. Fine conductive circuits cannot be formed. In this embodiment, the protruding portion P is removed. The thickness of the seed layer 30a formed by sputtering can be reduced. Even if the thickness of the seed layer 30a formed by sputtering is thin, a continuous seed layer 30a can be obtained. The thickness of the seed layer 30a is 0.05 μm or more and less than 0.5 μm.

[0027] No irregularities are formed on the inner wall surface 27. The inner wall surface 27 is formed smoothly. The size of the irregularities is controlled by controlling the conditions for processing the inner wall surface 27b after laser irradiation.

[0028] The inside of the opening 26 is cleaned. By cleaning the inside of the opening 26, resin residue generated during the formation of the opening 26 is removed. The cleaning of the inside of the opening 26 is performed by plasma. That is, the cleaning is performed by a dry process. The cleaning includes desmearing. The first surface 22 of the resin insulating layer 20 is covered with a protective film 50 and is therefore not affected by the plasma. At this point, no irregularities are formed on the first surface 22 of the resin insulating layer 20. Inorganic particles 90 are not exposed on the first surface 22. The first surface 22 is not roughened.

[0029] If processing the inner wall surface 27b after laser irradiation includes cleaning the inside of the aperture 26, the cleaning of the inside of the aperture 26 can be omitted. If the inside of the aperture 26 is cleaned by processing the inner wall surface 27b with plasma after laser irradiation, then processing the inner wall surface 27b with plasma after laser irradiation also serves to clean the inside of the aperture 26 with plasma.

[0030] As shown in Figure 4E, the protective film 50 is removed from the resin insulating layer 20 after cleaning the inside of the opening 26. If the treatment of the inner wall surface 27b after laser irradiation includes cleaning the inside of the opening 26, the protective film 50 is removed from the resin insulating layer 20 after the treatment of the inner wall surface 27b after laser irradiation. When the inner wall surface 27b after laser irradiation is treated, the protective film 50 covers the first surface 22 of the resin insulating layer 20.

[0031] After the protective film 50 is removed, the first surface 22 of the resin insulating layer 20 is cleaned. The first surface 22 is dry-etched. Dry etching is performed by sputtering using argon gas (argon sputtering). Figures 4F(a) and 4F(b) schematically show the first surface 22 of the resin insulating layer 20 before and after dry etching. As shown in Figures 4F(a) and 4F(b), the resin 80 forming the resin insulating layer 20 is removed by dry etching by about 20 nm. For example, the adhesive used to bond the protective film 50 to the resin insulating layer 20 is removed. The resin 80 is selectively removed by dry etching. The thickness of the resin 80 is reduced. Some of the inorganic particles 90 (second inorganic particles 92) are partially exposed from the top surface of the resin 80 by dry etching. By exposing the second inorganic particles 92 embedded in the resin 80 from the top surface of the resin 80, first inorganic particles 91 are obtained. The first inorganic particles 91 are formed from the second inorganic particles 92. The shape of the first inorganic particle 91 and the shape of the second inorganic particle 92 are the same. Both are spherical in shape. As shown in Figure 4F(b), the first inorganic particle 91 is formed of a first portion 91a that protrudes from the resin 80 and a second portion 91b that is embedded in the resin 80. The first surface 22 of the resin insulating layer 20 is formed of the upper surface 80R of the resin 80 and the exposed surface 91aR of the first portion 91a that protrudes from the upper surface 80R of the resin 80. Dry etching exposes the exposed surface 91aR of the first portion 91a. The first surface 22 of the resin insulating layer 20 is not roughened. Therefore, almost no recesses are formed on the first surface 22.

[0032] The ratio R is calculated, for example, using the cross-sectional view of the first inorganic particle 91 shown in Figure 4F(b). Figure 4F(b) is obtained by cutting the resin insulating layer 20 with a plane perpendicular to the top surface 80R. The second conductor layer 30 is omitted in Figure 4F(b). The second conductor layer 30 is formed on the first inorganic particle 91 in Figure 4F(b). The exposed surface 91aR in Figure 4F(b) is covered with the second conductor layer 30. Using Figure 4F(b), the cross-sectional area 91aS of the first portion 91a can be determined. Similarly, the cross-sectional area 91S of the first inorganic particle 91 can be determined. For example, the ratio R is represented by the ratio of the cross-sectional area 91aS to the cross-sectional area 91S (cross-sectional area of ​​the first portion 91a 91aS / cross-sectional area of ​​the first inorganic particle 91 91S). For example, when the ratio R is evaluated, 50 first inorganic particles 91 are observed. Fifty first inorganic particles 91 satisfy ratio R.

[0033] As shown in Figure 4G, a seed layer 30a is formed on the first surface 22 of the resin insulating layer 20. The seed layer 30a is formed by sputtering. The formation of the seed layer 30a is carried out in a dry process. The first layer 31a is formed on the first surface 22 by sputtering. At the same time, the first layer 31a is formed by sputtering on the inner wall surface 27 exposed from the opening 26 and on the pad 14. There are almost no recesses formed on the first surface 22. Therefore, the first layer 31a on the first surface 22 is formed almost flat. Subsequently, the second layer 31b is formed on the first layer 31a by sputtering. The second layer 31b is formed almost flat. The first layer 31a and the second layer 31b are formed in a vacuum. The seed layer 30a is also formed on the upper surface of the pad 14 exposed from the opening 26 and on the inner wall surface 27 of the opening 26. The first layer 31a is formed of an alloy containing copper and a specific base metal (aluminum). The second layer 31b is formed of copper.

[0034] The first surface 22 has no recesses. The inner wall surface 27 is formed smoothly. Therefore, even if the sputtered film (first layer 31a, second layer 31b) is thin, a continuous seed layer 30a can be formed. As a result, fine wiring can be formed.

[0035] A plating resist (not shown) is formed on the seed layer 30a. The plating resist has openings for forming the first signal wiring 32, the second signal wiring 34, and lands 36 (Figure 1). If the first surface 22 has recesses, air caused by these recesses is easily trapped between the plating resist and the seed layer 30a. However, in this embodiment, the first surface 22 has almost no recesses. Therefore, the seed layer 30a on the first surface 22 is formed almost flat. The seed layer 30a has almost no recesses. Air is less likely to remain between the plating resist and the seed layer 30a. The contact area between the plating resist and the seed layer 30a is large. Even if the width of the plating resist for forming the space between the first signal wiring 32 and the second signal wiring 34 is 10 μm or less, the plating resist is less likely to peel off from the upper surface of the seed layer 30a. According to this embodiment, even if the width of the plating resist is 3 μm or more and 8 μm or less, the plating resist can be formed on the seed layer 30a. Even if the width of the plating resist is 6 μm or less, the plating resist is less likely to peel off from the seed layer 30a.

[0036] An electroplating layer 30b is formed on the seed layer 30a exposed from the plating resist. The electroplating layer 30b is made of copper. The electroplating layer 30b fills the opening 26. The seed layer 30a and the electroplating layer 30b on the first surface 22 form the first signal wiring 32, the second signal wiring 34, and the land 36. The second conductor layer 30 is formed. The seed layer 30a and the electroplating layer 30b in the opening 26 form a via conductor 40. The via conductor 40 connects the pad 14 and the land 36. The first signal wiring 32 and the second signal wiring 34 form a pair wiring.

[0037] The plating resist is removed. The seed layer 30a exposed from the electroplating layer 30b is removed. The seed layer 30a is removed by wet etching. The etching solution used for wet etching is an aqueous solution containing hydrogen peroxide and sulfuric acid. The first layer 31a and the second layer 31b are removed simultaneously by wet etching. The second conductor layer 30 and the via conductor 40 are formed simultaneously. A printed circuit board 2 of the embodiment (Figure 1) is obtained.

[0038] In the printed circuit board 2 of the embodiment (Figures 1 to 3), the first surface 22 of the resin insulating layer 20 is formed by the upper surface 80R of the resin 80 and the exposed surface 91aR of the first portion 91a exposed from the upper surface 80R of the resin 80. The first surface 22 does not have any recesses. Therefore, when a seed layer 30a is formed on the resin insulating layer 20 by sputtering, a continuous seed layer 30a can be formed even if the thickness of the sputtered film is thin. The seed layer 30a is formed thinly. When the seed layer 30a is removed, the amount of etching is small. Therefore, the amount of etching of the electroplated layer 30b is small. The second conductor layer 30 having the first signal wiring 32 and the second signal wiring 34 has the width as designed. Fine wiring is formed. A printed circuit board 2 with high quality is provided.

[0039] In the printed circuit board 2 of this embodiment, the inner wall surface 27 of the opening 26 is formed by the flat portion 93a of the third inorganic particles 93 and the resin 80. The flat portion 93a and the surface 80a of the resin 80 forming the inner wall surface 27 form a common surface. The inner wall surface 27 is formed smoothly. Therefore, a seed layer 30a of uniform thickness is formed on the inner wall surface 27 of the opening 26. The seed layer 30a is formed thinly (Figure 4G). When the seed layer 30a is removed, the amount of etching is small. Therefore, the amount of etching of the electroplating layer 30b is small. The second conductor layer 30 having the first signal wiring 32 and the second signal wiring 34 has the width as designed. Fine wiring is formed. A printed circuit board 2 with high quality is provided.

[0040] In the printed circuit board 2 of this embodiment, the first layer 31a and the second layer 31b of the seed layer 30a are formed by sputtering (Figure 4G). Since sputtering is performed in a vacuum, oxidation of the first layer 31a is unlikely to occur when the second layer 31b is formed. The first layer 31a and the second layer 31b adhere to each other well. The second layer 31b is unlikely to peel off from the first layer 31a. Even if the diameter of the opening 26 is small, the connection reliability between the via conductor 40 and the pad 14 is high. The connection resistance through the via conductor 40 does not increase easily. As shown in Figure 4(E), the diameter D of the via conductor 40 (diameter of the opening 26) is measured on the pad 14. The diameter D is 20 μm or more and 50 μm or less. Even if the length of each side of the printed circuit board 2 exceeds 50 mm, the connection resistance through the via conductor 40 does not increase easily. Even if the length of each side of the printed circuit board 2 exceeds 100 mm, the connection resistance does not increase easily over a long period of time. A high-quality printed circuit board 2 is provided.

[0041] [Another example of an embodiment 1] In another embodiment (1), the specific base metal is selected from titanium, nickel, chromium, tin, and calcium.

[0042] [Another example of an embodiment 2] In another embodiment 2, the first layers 11a and 31a of the seed layers 10a and 30a are formed of copper and a second element. The second element is selected from silicon, aluminum, titanium, nickel, chromium, carbon, oxygen, tin, and calcium. The first layers 11a and 31a are formed of a copper-containing alloy. The second layers 11b and 31b are formed of copper. The amount of copper forming the second layers 11b and 31b is 99.9 at% or more. 99.95 at% or more is preferred.

[0043] [Examples of modifications to the embodiment] Figure 5 shows a modified example of the embodiment. As shown in Figure 5, the modified printed circuit board 102 has a build-up layer 500 on the insulating layer 4. The build-up layer 500 has a plurality of conductor layers and a plurality of resin insulating layers. The conductor layers and resin insulating layers are laminated alternately. The build-up layer 500 has five conductor layers and four resin insulating layers. The five conductor layers include a first conductor layer 10, a second conductor layer 30, a third conductor layer 130, a fourth conductor layer 230, and a fifth conductor layer 330. The first conductor layer 10 and the second conductor layer 30 are the same as in the embodiment. The third conductor layer 130, the fourth conductor layer 230, and the fifth conductor layer 330 have a configuration common to the second conductor layer 30 (seed layer and electroplating layer). The third conductor layer 130, the fourth conductor layer 230, and the fifth conductor layer 330 are formed in the same way as the second conductor layer 30.

[0044] The four resin insulating layers include a first resin insulating layer 20, a second resin insulating layer 120 (inter-layer resin insulating layer), a third resin insulating layer (inter-layer resin insulating layer) 220, and a fourth resin insulating layer (inter-layer resin insulating layer) 320. The first resin insulating layer 20 is the same as the resin insulating layer 20 of the embodiment. The second resin insulating layer 120, the third resin insulating layer 220, and the fourth resin insulating layer 320 have a common structure (resin and inorganic particles) with the first resin insulating layer 20. The first resin insulating layer 20, the second resin insulating layer 120, the third resin insulating layer 220, and the fourth resin insulating layer 320 are formed in the same manner as the resin insulating layer 20 of the embodiment. The first resin insulating layer 20, the second resin insulating layer 120, the third resin insulating layer 220, and the fourth resin insulating layer 320 have openings 26, 126, 226, and 326.

[0045] The build-up layer 500 has four via conductors 40, 140, 240, and 340. Via conductor 40 is formed in an opening 26 and connects the first conductor layer 10 and the second conductor layer 30. Via conductor 140 is formed in an opening 126 and connects the second conductor layer 30 and the third conductor layer 130. Via conductor 240 is formed in an opening 226 and connects the third conductor layer 130 and the fourth conductor layer 230. Via conductor 240 is formed in an opening 226 and connects the third conductor layer 130 and the fourth conductor layer 230. Via conductor 340 is formed in an opening 326 and connects the fourth conductor layer 230 and the fifth conductor layer 330. The three via conductors 140, 240, and 340 are stacked directly above via conductor 40. The four via conductors 40, 140, 240, and 340 form a stacked via.

[0046] The modified printed circuit board 102 includes five conductor layers 10, 30, 130, 230, and 330, and four via conductors 40, 140, 240, and 340, forming a stacked via. During use of the printed circuit board 102, significant stress is applied to the connection between the lowest via conductor 40 and the first conductor layer 10 (pad 14). However, in the modified example, the connection reliability between the via conductor 40 and the first conductor layer 10 (pad 14) is high. The connection resistance through the via conductor 40 does not increase easily.

[0047] [Another example of modification] The build-up layer 500 has five or more conductive layers. Preferably, the build-up layer 500 has ten or more conductive layers. The number of conductive layers is 20 or less. [Explanation of Symbols]

[0048] 2: Printed circuit board 4: Insulating layer 10: First conductor layer 20: Resin insulating layer 22: 1st page 24:Second side 26 :Aperture 27: Interior wall surface 30: Second conductor layer 30a: Seed layer 31a: 1st layer 31b: 2nd layer 40: Via conductor 80: Resin 90: Inorganic particles 91: 1st inorganic particle 91a :1st part 91b :Second part 92:Second inorganic particle 93:Third inorganic particle

Claims

1. A resin insulating layer having a first surface and a second surface opposite to the first surface is formed on a first conductor layer having a conductor circuit, A protective film is formed on the first surface of the resin insulating layer, To form an opening for a via conductor that penetrates the resin insulating layer and reaches the first conductor layer, The opening is cleaned with plasma, After the cleaning, the protective film is removed from the resin insulating layer, A second conductive layer is formed on the first surface of the resin insulating layer, A method for manufacturing a printed circuit board, comprising forming via conductors connecting the first conductor layer and the second conductor layer in the opening, Forming the second conductor layer includes forming a seed layer on the first surface of the resin insulating layer, forming a plating resist on the seed layer, forming an electroplating layer on the seed layer exposed from the plating resist, removing the plating resist, and removing the seed layer exposed from the electroplating layer. Forming the seed layer involves sputtering a first layer made of an alloy containing copper and a specific base metal onto the first surface, and sputtering a second layer made of copper onto the first layer, wherein the specific base metal is a base metal other than copper.

2. A method for manufacturing a printed circuit board according to claim 1, wherein removing the seed layer includes removing the first layer and the second layer simultaneously.

3. A method for manufacturing a printed circuit board according to claim 2, wherein the removal of the seed layer includes removing the first layer and the second layer by wet etching, and the etching solution used for the wet etching is an aqueous solution containing hydrogen peroxide and sulfuric acid.

4. A method for manufacturing a printed circuit board according to claim 1, wherein the copper content in the alloy is greater than 90 at%.

5. A method for manufacturing a printed circuit board according to claim 1, wherein the specified base metal is aluminum.

6. A method for manufacturing a printed circuit board according to claim 1, wherein the copper content of the second layer is 99 at% or more.

7. A method for manufacturing a printed circuit board according to claim 1, wherein the resin insulating layer comprises a resin and inorganic particles, and further comprises selectively removing the resin after removing the protective film, wherein the inorganic particles comprises first inorganic particles partially embedded in the resin and second inorganic particles completely embedded in the resin, the first inorganic particles are formed of a first portion protruding from the resin and a second portion embedded in the resin, and the first surface after the selective removal is formed of the upper surface of the resin and the exposed surface of the first portion exposed from the upper surface.

8. A method for manufacturing a printed circuit board according to claim 7, wherein the ratio of the volume of the first portion to the volume of the first inorganic particles is greater than 0 and 0.4 or less.

9. A method for manufacturing a printed circuit board according to claim 7, wherein the arithmetic mean roughness (Ra) of the first surface after selective removal is less than 0.08 μm.

10. A method for manufacturing a printed circuit board according to claim 7, wherein the inorganic particles further include third inorganic particles that form the inner wall surface of the opening, the inner wall surface is formed by the third inorganic particles and the resin, the third inorganic particles have a flat portion, and the flat portion forms the inner wall surface.

11. A method for manufacturing a printed circuit board according to claim 10, wherein the arithmetic mean roughness (Ra) of the inner wall surface is 1.0 μm or less.

12. A method for manufacturing a printed circuit board according to claim 10, wherein the shape of the third inorganic particle is obtained by cutting a sphere with a plane.

13. A method for manufacturing a printed circuit board according to claim 12, wherein the shape of the third inorganic particle is obtained by cutting the second inorganic particle in a plane.

14. A method for manufacturing a printed circuit board according to claim 1, wherein the diameter of the bottom of the opening is 20 μm or more and 50 μm or less.

15. A method for manufacturing a printed circuit board according to claim 7, wherein the exposed surface of the first portion is exposed by selective removal.

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