Silicon wafer manufacturing method

Abstract

To reduce defects such as voids and BMDs even in a surface part and bulk part of a wafer.SOLUTION: A heat treatment process includes the steps of: introducing a wafer into a reaction chamber held at an initial temperature, and in an oxygen atmosphere, performing heat treatment at a rate of temperature rise of 1°C / min or more and 10°C / min or less to a first temperature lower than the maximum attained temperature; in an inert gas atmosphere, performing heat treatment at a rate of temperature rise of 1°C / min or more and 10°C / min or less from the first temperature to the maximum attained temperature; in the inert gas atmosphere, maintaining the maximum attained temperature for 5 minutes or more and 20 minutes or less; and in the oxygen atmosphere, maintaining the maximum attained temperature for 1 hour or more and 10 hours or less.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present invention relates to a method for manufacturing silicon wafers, and more particularly to a method for manufacturing silicon wafers that can improve device characteristics by reducing defects such as voids (sometimes called Crystal Originated Particles: COPs when detected on the surface) and BMDs (Balk Microdefects) in the surface layer and bulk portion of the silicon wafer. [Background technology]

[0002] Semiconductor devices are broadly classified into integrated circuits (ICs), which integrate multiple electronic components to form a single circuit, and discrete elements, which themselves are single electronic components (transistors, diodes, thyristors, etc.). In both cases, silicon wafers (hereinafter simply referred to as wafers) are primarily used as the substrate material. However, the device formation region differs significantly in that, in the case of ICs, it is limited to the surface layer of the substrate (for example, the depth region from the surface to a depth of 5 μm), whereas in the case of discrete elements, the entire thickness of the substrate is used. Therefore, when using silicon wafers for discrete components, it is necessary to reduce defects such as voids and BMDs not only in the surface layer of the wafer but also in the bulk layer.

[0003] As a method for reducing void defects, Patent Document 1 discloses a technique for producing silicon wafers free of grown-in defects across the entire radial direction of a single crystal by controlling the V / G value (V: pulling speed, G: average value of the temperature gradient within the crystal in the pulling axis direction in the temperature range from the silicon melt to 1300°C) when growing a silicon single crystal ingot using the Czochralski method (hereinafter also called the CZ method). However, the technology described in Patent Document 1 has the problem of reducing the efficiency of growing silicon single crystal ingots because it requires controlling the pulling speed to be low.

[0004] Furthermore, Patent Document 2 discloses a technique for eliminating void defects present in single-crystal silicon by performing an oxidation treatment on single-crystal silicon manufactured by the CZ method and then performing a heat treatment at a temperature of at least around 1300°C.

[0005] In addition, Patent Document 3 discloses a technique for eliminating grown-in defects to a depth of at least 10 μm from the surface by subjecting a silicon wafer cut from a nitrogen-doped silicon single crystal to a heat treatment at a temperature of 1000°C to 1350°C for 50 hours or less in a hydrogen and / or inert gas atmosphere to remove the inner wall oxide film of void defects, and then performing an oxidation heat treatment at a temperature range of 800°C to 1350°C for 50 hours or less to forcibly implant interstitial silicon atoms (hereinafter referred to as interstitial Si).

[0006] However, the technology described in Patent Document 2 has the problem that slip dislocations are likely to occur because the heat treatment is performed at a temperature of at least around 1300°C. Furthermore, the technology described in Patent Document 3 involves doping with nitrogen to reduce the size of COP and voids. However, nitrogen-doped wafers have a problem in that many nitrogen as-grown precipitation nuclei are formed within the crystal, and thermal donors are generated using these nitrogen nuclei, making the resistance value unstable.

[0007] In response to these challenges, the applicant has proposed in Patent Document 4 a method for eliminating voids present on the wafer surface and in the bulk by applying heat treatment to a silicon wafer cut from a nitrogen-non-doped silicon single crystal. Specifically, in the heat treatment process, the silicon wafer is placed in a reaction chamber maintained at 800°C or below, and the temperature is raised to a maximum attainable temperature of 1150°C to 1250°C in an inert gas atmosphere with an oxygen partial pressure of 1% to 8%. Then, the oxygen partial pressure in the inert gas atmosphere is reduced to 5% to 15%, and the wafer is held at the maximum attainable temperature for 30 minutes to 2 hours.

[0008] In other words, during the heat treatment process until the maximum temperature is reached, an inert gas is used to decompose and remove the oxide film on the inner walls of voids present on the wafer surface and in the bulk. In the subsequent heat treatment at the highest temperature, the surface of the silicon wafer is oxidized due to the increase in oxygen concentration in the atmosphere, and interstitial Si is supplied to the voids where the inner wall oxide film has been removed. This eliminates voids present in the wafer surface and bulk. [Prior art documents] [Patent Documents]

[0009] [Patent Document 1] Japanese Patent Application Publication No. 8-330316 [Patent Document 2] International Publication No. 2003 / 056621 Pamphlet [Patent Document 3] Japanese Patent Publication No. 2000-203999 [Patent Document 4] Japanese Patent Publication No. 2013-201303 [Overview of the project] [Problems that the invention aims to solve]

[0010] By the way, in the heat treatment step of the silicon wafer manufacturing method disclosed in Patent Document 1, the heat treatment is performed in an inert gas atmosphere predominantly inert gas until the maximum temperature reached is 1150°C or higher and 1250°C or lower. However, when a silicon wafer without an oxide film is subjected to heat treatment at temperatures exceeding 900°C in an inert gas atmosphere, for example, the silicon wafer surface undergoes active oxidation (etching by SiO generation), which negatively affects the surface properties of the silicon wafer.

[0011] Therefore, at the start of the heat treatment, it is desirable to form a thin oxide film on the silicon wafer surface by heat treatment in an oxygen atmosphere. However, if the oxide film on the wafer surface is too thick, the dissolution of the oxide film on the inner wall of the voids will be insufficient during the subsequent heat treatment in an inert gas atmosphere. Conversely, if the oxide film on the wafer surface is too thin, active oxidation of the wafer surface cannot be prevented during the subsequent heat treatment in an inert gas atmosphere.

[0012] The present invention has been made in view of the above circumstances, and aims to provide a method for manufacturing silicon wafers that can reduce defects such as voids and BMDs in both the surface and bulk portions of the wafer, and is suitable for discrete components. [Means for solving the problem]

[0013] To solve the aforementioned problems, the present invention provides a method for manufacturing a silicon wafer, comprising the steps of: growing a silicon single crystal ingot without nitrogen doping using the Czochralski method; cutting the silicon single crystal ingot to produce a disc-shaped wafer consisting of V-rich regions; planarizing the produced wafer; heat-treating the planarized wafer; and mirror-polishing at least one surface of the heat-treated wafer that will form a semiconductor device. The heat-treating step is characterized by including the steps of: placing the wafer in a reaction chamber maintained at an initial temperature and heat-treating it in an oxygen atmosphere at a heating rate of 1°C / min or more and 10°C / min or less to a first temperature lower than the maximum temperature reached; heat-treating it in an inert gas atmosphere at a heating rate of 1°C / min or more and 10°C / min or less to a first temperature lower than the maximum temperature reached; holding the wafer at the maximum temperature reached for 5 min or more and 20 min or less in an inert gas atmosphere; and holding the wafer at the maximum temperature reached for 1 h or more and 10 h or less in an oxygen atmosphere.

[0014] Furthermore, it is desirable that the maximum temperature reached is between 1150°C and 1250°C. Furthermore, the first temperature is preferably between 850°C and 950°C. Also, in the step of growing a silicon single crystal ingot with nitrogen undoping by the Chokralski method, the oxygen concentration in the grown silicon single crystal ingot is 5.0×10 17 atoms / cm 3 or less, which is desirable. Also, in the step of growing a silicon single crystal ingot with nitrogen undoping by the Chokralski method, the nitrogen concentration in the grown silicon single crystal ingot is 6.0×10 13 atoms / cm 3 or less, which is desirable. Also, after the step of putting the wafer into a reaction chamber maintained at an initial temperature and performing heat treatment in an oxygen atmosphere at a heating rate of 1°C / min or more and 10°C / min or less up to a first temperature lower than the maximum temperature reached, it is desirable to hold it in an inert gas atmosphere at the first temperature for 5 min or more and 20 min or less.

[0015] Thus, according to the present invention, in the heat treatment step, first, heat treatment is performed in an oxygen atmosphere at a heating rate of 1°C / min or more and 10°C / min or less up to a first temperature (desirably 900°C). Thereby, an oxide film is formed on the surface of the silicon wafer. Next, in an inert gas atmosphere, the temperature is raised at a heating rate of 1°C / min or more and 10°C / min or less from the first temperature to the maximum temperature reached (desirably 1150°C or more and 1250°C or less). Further, it is held in an inert gas atmosphere at the maximum temperature reached for 5 min or more and 20 min or less. Thereby, the inner wall oxide film of COP (void) in the wafer surface layer and the bulk layer is efficiently dissolved and removed from the wafer without the oxygen concentration in the wafer surface layer becoming saturated. Also, in this heat treatment in an inert gas atmosphere, active oxidation is prevented by the oxide film previously formed on the wafer surface. Subsequently, under an oxygen atmosphere, heat treatment is performed at the maximum temperature reached for 1 hour or more and 10 hours or less. As a result, the surface of the silicon wafer is further oxidized, and interstitial Si is supplied to the voids from which the inner wall oxide film has been removed. This can eliminate COPs (voids) present in the wafer surface layer and bulk.

Advantages of the Invention

[0016] According to the present invention, defects such as voids and BMDs can be reduced in both the surface layer and bulk of the wafer, and a method for manufacturing a silicon wafer suitable for discrete devices can be provided.

Brief Description of the Drawings

[0017] [Figure 1] It is a process flow diagram showing a method for manufacturing a silicon wafer according to an embodiment of the present invention. [Figure 2] It is a conceptual diagram schematically showing the relationship between the V / G value and the point defect distribution in the grown silicon single crystal ingot. [Figure 3] It is a conceptual diagram showing an example of the heat treatment sequence in the heat treatment process. [Figure 4] FIG. 4 is a graph showing the results of Test 1 of the examples. [Figure 5] FIG. 5 is a graph showing the results of Test 2 of the examples.

Modes for Carrying Out the Invention

[0018] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings and the like. FIG. 1 is a process flow diagram showing a method for manufacturing a silicon wafer according to an embodiment of the present invention. The method for manufacturing a silicon wafer according to the present embodiment includes, as shown in FIG. 1, a growth step (S101), a cutting step (S102), a planarization step (S103), a heat treatment step (S104), and a mirror polishing step (S105). [[ID= forty-one ]]

[0019] [[ID= forty-two ]] In the growth process (S101), the oxygen concentration in the V-rich region was 5 × 10⁻¹⁰ in nitrogen-non-doped form using the CZ method. 17 atoms / cm 3 The following silicon single crystal ingots will be grown. Specifically, using a well-known single-crystal pulling apparatus, a seed crystal is brought into contact with the surface of a silicon molten liquid in a nitrogen-non-doped state. While rotating the seed crystal and quartz crucible, the seed crystal is pulled up to form a neck portion and an expanded portion that expands to the desired diameter. Then, while maintaining the desired diameter, the V / G value (V: pulling speed, G: average value of the temperature gradient within the crystal in the pulling axis direction over a temperature range from the silicon melting point to 1300°C) is set to a predetermined value (for example, 0.25~0.35 mm) so that the central axis of the crystal becomes a V-rich region. 2 This is done by controlling the temperature ( / ℃·min) to form a straight cylinder section, then forming a reduced-diameter section that is smaller than the desired diameter, and finally separating the reduced-diameter section from the silicon melt.

[0020] In this invention, "nitrogen-free doping" refers to the practice of not intentionally doping silicon single crystal ingots with nitrogen (for example, by simultaneously loading silicon wafer pieces with a nitride film formed on them when loading polysilicon into a quartz crucible). Furthermore, the oxygen concentration of the silicon single crystal ingot being grown is adjusted by a well-known method, such as by adjusting the rotation speed of the quartz crucible, the furnace pressure, and the heater temperature.

[0021] Figure 2 is a conceptual diagram schematically showing the relationship between the V / G value and the point defect distribution in the grown silicon single crystal ingot. As shown in Figure 2, after forming the neck portion 2, if the pulling speed V of the silicon single crystal ingot 1 is gradually decreased from the diameter-expanding portion 3 to the diameter-reducing portion 4, the V / G value also decreases, and the defect distribution in the silicon single crystal ingot 1 changes accordingly. In this case, the G value hardly changes. When the pulling speed V value is large, i.e., when the V / G value is large, a V-rich region 5 is formed in which many atomic vacancies (COPs) are incorporated. Below the critical V / G value where this V-rich region 5 disappears, first an OSF ring region 6 is formed in which OSF is generated in a ring shape by oxidation heat treatment, and then a defect-free region 7 is formed in which there is little shortage or excess of atoms due to the balance between vacancies and interstitial silicon concentration. When the V / G value decreases further, an I-rich region 8 is formed in which many interstitial silicon are incorporated.

[0022] Thus, in the present invention, since a silicon single crystal ingot consisting of a straight body portion including a V-rich region is grown in the growth process (S101), the pulling speed V can be increased compared to growing a silicon single crystal ingot in which the straight body portion consists of a defect-free region. Therefore, a silicon single crystal ingot can be grown without reducing the growth efficiency. Furthermore, since silicon single crystal ingots are grown without nitrogen doping, the generation of nitrogen asgrown nuclei can be suppressed. Consequently, the generation of nitrogen-nucleated thermal donors can be suppressed.

[0023] Even when silicon single crystal ingots are grown using nitrogen doping, it is possible to diffuse the nitrogen from the surface layer of the wafer outward during the heat treatment process (S104) described later. However, even in this case, nitrogen in the bulk portion inside the wafer is not easily diffused outward, so nitrogen may remain in the bulk portion even after the heat treatment. Therefore, as nitrogen as-grown nuclei are more likely to form in the bulk portion, it is preferable to grow silicon single crystal ingots using nitrogen-free doping.

[0024] In the cutting process (S102), a known cutting device (such as a wire saw) is used to cut the silicon single crystal ingot to produce a disc-shaped wafer consisting of V-rich regions.

[0025] In the planarization step (S103), the prepared wafer is planarized by a well-known planarization treatment (lapping using free abrasive grains, grinding using fixed abrasive grains such as diamond, etching using an acidic solution (a solution of hydrofluoric acid (HF), nitric acid (HNO3), acetic acid (CH3COOH), and water (H2O) mixed in a certain ratio) or an alkaline solution (sodium hydroxide (NaOH) or potassium hydroxide (KOH) solution), polishing using an abrasive such as colloidal silica, etc.).

[0026] In the planarization step (S103), it is preferable to lap both sides of the wafer prepared by cutting the silicon single crystal ingot, etch both sides with an acidic solution, and then mirror polish at least one or both sides of the surface that will become the semiconductor device formation surface. Alternatively, a grinding process may be added to grind both sides of the wafer after the lapping process and before the etching process.

[0027] In the heat treatment process (S104), using a well-known heat treatment apparatus (such as a vertical heat treatment apparatus), the planarized wafer is placed in a reaction chamber maintained at an initial temperature of 800°C or lower, and the wafer is heat-treated in an oxygen atmosphere at a heating rate of 1°C / min or more and 10°C / min or less to a first temperature (for example, 900°C), the wafer is heat-treated in an inert gas atmosphere at a heating rate of 1°C / min or more and 10°C / min or less to a maximum temperature reached from the first temperature (for example, 1150°C or more and 1250°C or less), the wafer is held at the maximum temperature reached in an inert gas atmosphere for 5 minutes or more and 20 minutes or less, and the wafer is held at the maximum temperature reached in an oxygen atmosphere for 1 hour or more and 10 hours or less.

[0028] Figure 3 is a conceptual diagram showing an example of a heat treatment sequence in the heat treatment process (S104). The heat treatment process (S104) is carried out, for example, with a heat treatment sequence as shown in Figure 3. First, the flattened wafers are placed in a reaction chamber maintained at an initial temperature T0 (800°C or less) of a well-known vertical heat treatment apparatus, for example, by holding multiple wafers individually on a well-known vertical board. The wafers are then heat-treated in an oxygen atmosphere to a temperature T1 (900°C) at a heating rate of 1°C / min to 10°C / min. This forms an oxide film with a thickness of 3 nm to 10 nm on the surface of the silicon wafer. If the thickness of this oxide film is greater than 10 nm, there is a risk that the dissolution of the oxide film on the inner walls of the voids will be insufficient during the subsequent heat treatment in an inert gas atmosphere. On the other hand, if the oxide film on the wafer surface is less than 3 nm, there is a risk that active oxidation of the wafer surface cannot be prevented during the subsequent heat treatment in an inert gas atmosphere.

[0029] Next, the atmosphere inside the reaction chamber is changed to an inert gas atmosphere. It is desirable to maintain this inert gas atmosphere and temperature T1 for 5 minutes to 20 minutes. Next, the temperature is increased from temperature T1 to the maximum temperature T2 (1150°C to 1250°C) in an inert gas atmosphere at a heating rate of 1°C / min to 10°C / min. Then, the temperature is maintained at the maximum temperature T2 in an inert gas atmosphere for 5 minutes to 20 minutes. This allows the oxide film on the inner walls of COPs (voids) in the wafer surface layer and bulk layer to efficiently dissolve and be removed into the wafer without the oxygen concentration on the wafer surface reaching a saturation point. Furthermore, during heat treatment in this inert gas atmosphere, active oxidation is prevented by the oxide film that was previously formed on the wafer surface. In this heat treatment in an inert gas atmosphere, the wafer is held at the maximum temperature T2 for 5 to 20 minutes. However, if the holding time is shorter than 5 minutes, there is a risk that the oxide film on the inner walls of voids in the surface and bulk layers may not be completely removed. On the other hand, if the holding time is longer than 20 minutes, there is a risk of slippage occurring in the wafer.

[0030] Subsequently, the atmosphere in the reaction chamber is set to an oxygen atmosphere, and heat treatment is performed at a maximum temperature T2 (1150 °C or higher and 1250 °C or lower) for 1 h or longer and 10 h or shorter. As a result, the surface of the silicon wafer is oxidized, and interstitial Si is supplied to the voids from which the inner wall oxide film has been removed. Thereby, COPs (voids) present in the wafer surface layer and the bulk disappear. In this oxygen atmosphere, if the heat treatment time at the maximum temperature T2 is shorter than 1 h, there is a risk that the voids will not completely disappear. On the other hand, if the heat treatment time at the maximum temperature T2 is longer than 10 h, there is a risk that slips will occur in the wafer.

[0031] Further, when the oxygen concentration of the silicon single crystal ingot to be grown is more than 5×10 17 atoms / cm 3 since the oxygen concentration becomes high, it becomes difficult to dissolve the inner wall oxide film of the voids present in the surface layer portion and the bulk portion (particularly, the bulk portion) in the subsequent heat treatment step (S104). Also, it becomes difficult to dissolve the BMD nuclei generated during the growth of the silicon single crystal ingot in the surface layer portion and the bulk portion (particularly, the bulk portion) into the wafer. Therefore, it is not preferable because voids are likely to remain in the surface layer portion and the bulk portion (particularly, the bulk portion), and BMD is likely to be precipitated. From the viewpoints of ensuring the wafer strength (suppressing the generation of slip dislocations) in the subsequent heat treatment step (S104) and the heat treatment step during semiconductor device formation, etc., the lower limit of the oxygen concentration is preferably 2×10 17 atoms / cm 3 or more.

[0032] If the input temperature into the reaction chamber in the heat treatment step (S104) exceeds 800 °C, it is not preferable because slip dislocations are likely to occur in the wafer due to a rapid temperature change from room temperature (clean room: about 25 °C). From the viewpoint of productivity etc., the lower limit of the input temperature is preferably 300 °C or higher.

[0033] If the inert gas is nitrogen gas, a nitride film may form on the wafer surface after the heat treatment. This necessitates adding an etching process or other steps to remove the nitride film, which reduces productivity and is therefore undesirable. If the inert gas is hydrogen gas, it creates a mixed gas atmosphere of hydrogen and oxygen, which poses an explosion risk and is therefore undesirable.

[0034] If the maximum temperature reached is less than 1150°C, the low temperature makes it difficult to dissolve the inner wall oxide film of voids present in the surface layer and bulk layer (especially the bulk layer). Furthermore, it becomes difficult to dissolve BMD nuclei generated during silicon single crystal ingot growth in the surface layer and bulk layer (especially the bulk layer) into the wafer. Consequently, voids tend to remain in the surface layer and bulk layer (especially the bulk layer), and BMDs tend to precipitate, which is undesirable. If the maximum temperature reached exceeds 1250°C, the high temperature makes it easier for slip dislocations to occur during the heat treatment, which is undesirable.

[0035] The mirror polishing step (S105) involves using a well-known mirror polishing apparatus (including single-sided or double-sided polishing) to mirror polish at least the surface of the heat-treated wafer that will form a semiconductor device.

[0036] As mentioned above, in the heat treatment process (S104), the heat treatment is performed in an inert gas atmosphere with an oxygen partial pressure of 1% to 8% during the heating stage, and in an inert gas atmosphere with an oxygen partial pressure of 5% to 15% at the highest temperature reached. As a result, oxygen is more easily diffused inward into the wafer from the heating stage, making it particularly difficult for the inner wall oxide film of voids present in the surface layer to dissolve, and voids remain in the surface layer. Therefore, it is preferable to remove the surface layer in which the voids remain by mirror polishing at least the surface of the heat-treated wafer that will be the semiconductor device formation surface.

[0037] In the mirror polishing step (S105), it is preferable to remove 2 μm to 5 μm of the surface (polishing allowance of 2 μm to 5 μm). By using this polishing allowance, it is possible to remove the surface layer containing the voids in a productive manner while suppressing deterioration of the wafer's flatness during the mirror polishing process (S105).

[0038] The nitrogen concentration in the grown silicon single crystal ingot is 6.0 × 10⁻⁶ 13 atoms / cm 3 The following is preferable: By maintaining this nitrogen concentration, the occurrence of thermal donors can be reliably suppressed.

[0039] As described above, the silicon wafer manufacturing method according to the present invention can reduce defects such as voids and BMDs in the surface layer and bulk portion of the wafer. Therefore, silicon wafers manufactured according to the present invention can be suitably used, in particular, for discrete components. [Examples]

[0040] The present invention will be described in more detail below based on examples, but the present invention is not limited to the following examples.

[0041] (Test 1) (Example 1) Samples were prepared based on the process flow diagram shown in Figure 1. Specifically, by adjusting the rotation speed of the quartz crucible and the furnace pressure, the V / G value (V: pulling speed, G: average value of the temperature gradient within the crystal in the pulling axis direction over the temperature range from the silicon melting point to 1300°C) is controlled to 0.28~0.32 mm² / °C·min using the CZ method with nitrogen non-doping, resulting in an N-type crystal with a straight body consisting of a V-rich region, a crystal orientation (100), and an oxygen concentration of 5.0 × 10⁻⁶. 17 atoms / cm 3 After growing a silicon single crystal ingot, the straight section of the ingot is cut, and the nitrogen concentration in the V-rich region is 6.0 × 10⁻⁶. 13 / cm 3 A disc-shaped slice wafer with a diameter of 300 mm was obtained as follows. This oxygen concentration is the in-plane average concentration of the sliced ​​wafer measured using a Fourier transform infrared spectrophotometer (FTIR). The nitrogen concentration is estimated from the amount of nitride-coated wafer used, the nitrogen segregation coefficient, and the crystal solidification rate.

[0042] Next, the obtained slice wafers were subjected to lapping on both sides (front and back), followed by etching with an acidic solution (a solution of hydrofluoric acid (HF), nitric acid (HNO3), acetic acid (CH3COOH), and water (H2O) mixed in a specific ratio), and finally, both sides were polished to a mirror finish. Next, ten mirror-polished wafers were placed in a vertical boat made of SiC with an oxide film coated on its surface, and then placed into the reaction chamber of a well-known vertical heat treatment apparatus. The heat treatment was then performed according to the heat treatment sequence shown in Figure 3.

[0043] Other heat treatment conditions are as follows: T0: 600℃ T1: 900℃ T2: 1200℃ t1:10 minutes ·t2:50 minutes ·ΔTu1:4℃ / min ·ΔTu2:2℃ / min • ΔTd1: 1℃ / min ·ΔTd2:2℃ / min • ΔTd3: 4℃ / min

[0044] After heat treatment, the wafer was subjected to HF treatment to remove the oxide film from both sides, and then both sides of the wafer were polished again to a mirror finish (polishing allowance of 2 μm on the surface that would become the semiconductor device formation surface). The wafers, which had undergone the aforementioned heat treatment and mirror polishing, were polished to a depth of 6 μm from the surface that would become the semiconductor device formation surface. The number of LPDs (Light Point Defects) larger than 65 nm was measured using a KLA TENCOR Surfscan SP2 to evaluate the remaining state of void defects.

[0045] (Comparative Example 1) In Comparative Example 1, the atmosphere inside the reaction chamber was not changed from start to finish in the heat treatment sequence shown in Figure 3, and an inert gas (Ar) atmosphere was maintained. All other conditions were the same as in Example 1.

[0046] (Comparative Example 2) In Comparative Example 2, the atmosphere inside the reaction chamber was kept oxygen-based from start to finish in the heat treatment sequence shown in Figure 3. All other conditions were the same as in Example 1.

[0047] The results for Example 1 and Comparative Examples 1 and 2 are shown in the graph in Figure 4. The vertical axis of the graph in Figure 4 represents the number of LPDs (low-particle diameters) 65 nm or larger. As shown in the graph in Figure 4, almost no LPDs were observed in Example 1. Furthermore, when the observed LPDs were evaluated using a scanning electron microscope (SEM), they were all found to be attached particles.

[0048] Furthermore, in Comparative Example 1, which underwent heat treatment under an Ar gas atmosphere, an average of 29.7 LPDs were found. When the identified LPDs were evaluated using a scanning electron microscope (SEM), they were found to be voids where the inner wall oxide film had disappeared. Furthermore, in Comparative Example 2, which underwent heat treatment in an oxygen atmosphere, the average number of LPDs was 8.2. In addition, when the identified voids were evaluated using a scanning electron microscope (SEM), they were found to be SiOx defects of approximately 50 nm in size, which appear to have been formed by the shrinkage of the voids while retaining the inner wall oxide film.

[0049] (Exam 2) In Test 2, the preferred range of the heating rate ΔTu1 under an oxygen atmosphere was investigated in the heat treatment sequence shown in Figure 3. (Example 2) In Example 2, the wafer oxide film thickness was measured in the heat treatment sequence shown in Figure 3, with a heating rate ΔTu1 of 1°C / min under an oxygen atmosphere. (Example 3) In Example 3, the wafer oxide film thickness was measured in the heat treatment sequence shown in Figure 3, with a heating rate ΔTu1 of 5°C / min under an oxygen atmosphere. (Example 4) In Example 4, the wafer oxide film thickness was measured in the heat treatment sequence shown in Figure 3, with a heating rate ΔTu1 of 10°C / min under an oxygen atmosphere. (Comparative Example 3) In Comparative Example 3, the wafer oxide film thickness was measured in the heat treatment sequence shown in Figure 3, with a heating rate ΔTu1 of 0.5°C / min under an oxygen atmosphere. (Comparative Example 4) In Comparative Example 4, the wafer oxide film thickness was measured in the heat treatment sequence shown in Figure 3, with a heating rate ΔTu1 of 15°C / min under an oxygen atmosphere. (Comparative Example 5) In Comparative Example 5, the wafer oxide film thickness was measured in the heat treatment sequence shown in Figure 3, with a heating rate ΔTu1 of 20°C / min under an oxygen atmosphere.

[0050] The results for Examples 2, 3, and 4, and Comparative Examples 3, 4, and 5 are shown in the graph in Figure 5. In the graph in Figure 5, the vertical axis represents the oxide film thickness (nm). As shown in Figure 5, in Example 2 (ΔTu1: 1℃ / min), the average oxide film thickness of the wafer was 9.3 nm, in Example 3 (ΔTu1: 5℃ / min), the average oxide film thickness of the wafer was 5.1 nm, and in Example 4 (ΔTu1: 10℃ / min), the average oxide film thickness of the wafer was 3.4 nm. An oxide film with an appropriate thickness of 3 nm to 10 nm was formed to prevent active oxidation. On the other hand, in Comparative Example 3 (ΔTu1: 0.5℃ / min), the average oxide film thickness of the wafer was 14.8 nm, which was sufficient to prevent active oxidation, but there was a risk that it would affect the dissolution of the oxide film on the inner wall of the voids during subsequent heat treatment in an inert gas atmosphere. Furthermore, in Comparative Example 4 (ΔTu1: 15℃ / min), the average oxide film thickness of the wafer was 2.0 nm, and in Comparative Example 5 (ΔTu1: 20℃ / min), the average oxide film thickness of the wafer was 1.5 nm, indicating that a sufficient oxide film to prevent active oxidation was not formed. The results of this Test 2 confirmed that, in order to prevent active oxidation of the wafer and to form a suitable oxide film thickness during subsequent heat treatment in an inert gas atmosphere, it is desirable to set the heating rate (ΔTu1) in an oxygen atmosphere to between 1°C / min and 10°C / min.

[0051] (Exam 3) In Test 3, the preferred holding times for the first temperature (T1) and the second temperature (T2), which is the highest temperature reached, were investigated in the heat treatment sequence shown in Figure 3. As shown in Table 1, wafer voids and slip were evaluated using the holding times at the first temperature (T1) and the second temperature (T2) as conditions, with other conditions being the same as in Example 1. As in Example 1, the first temperature (T1) and the second temperature (T2) were set to 900°C and 1200°C, respectively.

[0052] [Table 1]

[0053] (Example 5) In Example 5, as shown in Table 1, the holding time at the first temperature (T1) was set to 5 minutes, and the holding time at the second temperature (T2) was set to 1 hour. (Example 6) In Example 6, as shown in Table 1, the holding time at the first temperature (T1) was set to 10 minutes, and the holding time at the second temperature (T2) was set to 2 hours. (Example 7) In Example 7, as shown in Table 1, the holding time at the first temperature (T1) was set to 20 minutes, and the holding time at the second temperature (T2) was set to 10 hours. (Comparative Example 6) In Comparative Example 6, as shown in Table 1, the holding time at the first temperature (T1) was 1 min The holding time at the second temperature (T2) was set to 0.5 hours. (Comparative Example 7) In Comparative Example 7, as shown in Table 1, the holding time at the first temperature (T1) was set to 30 minutes, and the holding time at the second temperature (T2) was set to 15 hours.

[0054] Table 1 shows the results for Examples 5, 6, and 7, and Comparative Examples 6 and 7. In Table 1, samples where voids or slips occurred are marked with ×, and samples where they did not occur are marked with ○. As shown in Table 1, no slips or voids occurred in the wafers in Examples 5, 6, and 7. On the other hand, as in Comparative Example 6, when the holding times for the first temperature (T1) and the second temperature (T2) were short (1 min and 0.5 h, respectively), slip did not occur, but voids remained in the surface and bulk layers. Furthermore, as in Comparative Example 7, when the holding times for the first temperature (T1) and the second temperature (T2) were increased (30 min and 15 h, respectively), the voids disappeared, but slippage occurred in the wafer. The results of Test 3 confirmed that, in order to eliminate voids in the surface and bulk while suppressing slippage, it is desirable to maintain the first temperature (T1) for 5 to 20 minutes in an inert gas atmosphere, and to maintain the second temperature (T2), which is the highest temperature reached, for 1 to 10 hours in an oxygen atmosphere.

[0055] Based on the results of the above embodiments, it was confirmed that the silicon wafer manufacturing method of the present invention can eliminate voids in the surface layer and bulk layer of the silicon wafer. [Explanation of Symbols]

[0056] 1. Silicon single crystal ingot 2. Neck section 3 Expanded diameter part 4 Reduced diameter part 5 V-rich region 6 Ring OSF region 7. Defect-free area 8. I-rich region

Claims

1. The process comprises: growing a silicon single crystal ingot without nitrogen doping using the Czochralski method; cutting the silicon single crystal ingot to produce a disc-shaped wafer consisting of a V-rich region; planarizing the produced wafer; heat-treating the planarized wafer; and mirror-polishing at least one surface of the heat-treated wafer that will form a semiconductor device. The aforementioned heat treatment step is The process involves placing the wafer into a reaction chamber maintained at an initial temperature and heat-treating it in an oxygen atmosphere at a heating rate of 1°C / min or more and 10°C / min or less to a first temperature lower than the maximum temperature reached. A step of performing heat treatment in an inert gas atmosphere at a heating rate of 1°C / min or more and 10°C / min or less from the first temperature to the maximum temperature reached, A process of maintaining the temperature at the highest attainable temperature for 5 min to 20 min in an inert gas atmosphere, A process of maintaining the temperature at the highest attainable temperature in an oxygen atmosphere for 1 hour to 10 hours, A method for manufacturing silicon wafers, characterized by including the following:

2. The method for manufacturing a silicon wafer according to claim 1, characterized in that the maximum temperature reached is 1150°C or higher and 1250°C or lower.

3. The method for manufacturing a silicon wafer according to claim 1, characterized in that the first temperature is 850°C or higher and 950°C or lower.

4. In the process of growing a silicon single crystal ingot without nitrogen doping using the Czochralski method described above, The oxygen concentration in the grown silicon single crystal ingot is 5.0 × 10⁻⁶ １７ atoms / cm ３ The method for manufacturing a silicon wafer according to claim 1, characterized in that it is as follows:

5. In the process of growing a silicon single crystal ingot without nitrogen doping using the Czochralski method described above, The nitrogen concentration in the grown silicon single crystal ingot was 6.0 × 10⁻⁶. １３ atoms / cm ３ The method for manufacturing a silicon wafer according to claim 1, characterized in that it is as follows:

6. The wafer is placed in a reaction chamber maintained at an initial temperature, and heat-treated in an oxygen atmosphere at a heating rate of 1°C / min to 10°C / min or less to a first temperature lower than the maximum temperature reached. A method for manufacturing a silicon wafer according to claim 1, characterized by holding the wafer in an inert gas atmosphere and at the first temperature for 5 min to 20 min.

Images