Semiconductor device and method for manufacturing a semiconductor device

Abstract

This semiconductor device comprises a first lead, a second lead, a third lead, a semiconductor element, a sealing resin, and a cover layer. The sealing resin has a bottom surface and an outer surface. A recess having an inner surface is formed on the bottom surface of the sealing resin. The second lead has a rear surface exposed from the bottom surface, and a side surface exposed from the outer surface. The cover layer contains a metal element and covers the rear surface and the side surface. The recess is located between the first lead and the second lead. The second lead and at least one of the first lead and the third lead have an inner end surface exposed from the inner surface of the recess.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device and a method for manufacturing the same.

Background Art

[0002] Patent Document 1 discloses an example of a semiconductor device. The semiconductor device includes a columnar conductor that conducts to a semiconductor element. The columnar conductor has a back surface exposed surface and a side surface exposed surface that are exposed from the encapsulating resin. Further, the semiconductor device includes an external electrode that covers the back surface exposed surface and the side surface exposed surface. When the semiconductor device has this configuration, when the semiconductor device is mounted on a wiring board, solder creeps up to the portion of the external electrode that covers the side surface exposed surface. Therefore, the bonding state of the semiconductor device to the wiring board can be easily visually confirmed.

[0003] In forming the external electrode of the semiconductor device disclosed in Patent Document 1, a step of exposing the side surface exposed surface of the columnar conductor from the encapsulating resin is required. Therefore, there is a problem that the manufacturing efficiency of the semiconductor device is reduced. Further, since the external electrode is formed by electroless plating, a relatively long time is required for the deposition of the metal layer that becomes the external electrode. This further causes a reduction in the manufacturing efficiency of the semiconductor device.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] In view of the above circumstances, one problem of the present disclosure is to provide a semiconductor device and a method for manufacturing the same in which a coating layer that covers the back surface and the side surface of a lead exposed from an encapsulating resin can be formed more efficiently. [Means for solving the problem]

[0006] A semiconductor device provided by a first aspect of this disclosure comprises: a first lead; a second lead located adjacent to the first lead in a direction perpendicular to the thickness direction of the first lead; a third lead located adjacent to the second lead in a direction perpendicular to the thickness direction; a first semiconductor element mounted on the first lead and conductive to the second lead; a sealing resin covering a portion of each of the first lead, the second lead, and the third lead, and the first semiconductor element; and a coating layer containing a metallic element. The sealing resin has a bottom surface facing the thickness direction and an outer surface connected to the bottom surface and facing outward from the sealing resin in a direction perpendicular to the thickness direction. A recess is formed in the sealing resin, recessed from the bottom surface, and the recess has an inner surface connected to the bottom surface and facing inward from the sealing resin in a direction perpendicular to the thickness direction. The second lead has a back surface exposed from the bottom surface and a side surface connected to the back surface and exposed from the outer surface. The coating layer covers the back surface and the side surface. The recess is located between the first lead and the second lead. The second lead and at least one of the first lead and the third lead have an inner end face exposed from the inner surface.

[0007] A method for manufacturing a semiconductor device provided by a second aspect of this disclosure comprises the steps of: mounting a semiconductor element on one of a plurality of leads, each having a back surface and a side surface connected to the back surface; and forming a sealing resin that covers a portion of each of the plurality of leads and the semiconductor element. In the step of forming the sealing resin, at least one of the back surface and side surface of the plurality of leads is exposed from the sealing resin. At least two of the plurality of leads are connected to each other by a connecting band having the same composition as the plurality of leads. The manufacturing method further comprises, after the step of forming the sealing resin, forming a coating layer containing a metallic element that covers the back surface and side surface exposed from the sealing resin by electroplating; and after the step of forming the coating layer, cutting the connecting band by removing a portion of the sealing resin from the side where the back surface is exposed. [Effects of the Invention]

[0008] According to the above configuration of this disclosure, it is possible to more efficiently form a coating layer that covers the back and sides of the lead exposed from the sealing resin.

[0009] Other features and advantages of this disclosure will become more apparent from the detailed description below, based on the accompanying drawings. [Brief explanation of the drawing]

[0010] [Figure 1] Figure 1 is a perspective view of a semiconductor device according to a first embodiment of the present disclosure. [Figure 2] Figure 2 is a plan view of the semiconductor device shown in Figure 1, with the sealing resin transparent. [Figure 3] Figure 3 is a bottom view of the semiconductor device shown in Figure 1. [Figure 4] Figure 4 is a right side view of the semiconductor device shown in Figure 1. [Figure 5] Figure 5 is a left side view of the semiconductor device shown in Figure 1. [Figure 6]FIG. 6 is a rear view of the semiconductor device shown in FIG. 1. [Figure 7] FIG. 7 is a cross-sectional view taken along line VII-VII of FIG. 2. [Figure 8] FIG. 8 is a cross-sectional view taken along line VIII-VIII of FIG. 2. [Figure 9] FIG. 9 is a cross-sectional view taken along line IX-IX of FIG. 2. [Figure 10] FIG. 10 is a partially enlarged view of FIG. 7. [Figure 11] FIG. 11 is a partially enlarged view of FIG. 9. [Figure 12] FIG. 12 is a plan view for explaining the manufacturing process of the semiconductor device shown in FIG. 1. [Figure 13] FIG. 13 is a plan view for explaining the manufacturing process of the semiconductor device shown in FIG. 1. [Figure 14] FIG. 14 is a cross-sectional view for explaining the manufacturing process of the semiconductor device shown in FIG. 1. [Figure 15] FIG. 15 is a plan view for explaining the manufacturing process of the semiconductor device shown in FIG. 1. [Figure 16] FIG. 16 is a cross-sectional view for explaining the manufacturing process of the semiconductor device shown in FIG. 1. [Figure 17] FIG. 17 is a bottom view for explaining the manufacturing process of the semiconductor device shown in FIG. 1. <000 extraordinari00083> [Figure 18] FIG. 18 is a partially enlarged cross-sectional view for explaining the manufacturing process of the semiconductor device shown in FIG. 1. [Figure 19] FIG. 19 is a partially enlarged cross-sectional view for explaining the manufacturing process of the semiconductor device shown in FIG. 1. [Figure 20] FIG. 20 is a plan view for explaining the manufacturing process of the semiconductor device shown in FIG. 1. [Figure 21] FIG. 21 is a partially enlarged cross-sectional view of the first modified example of the semiconductor device shown in FIG. 1. <000009 en00092>FIG. 22 is a partially enlarged cross-sectional view of the second modified example of the semiconductor device shown in FIG. 1. <000 extraordinari00093> [Figure 23] FIG. 23 is a partially enlarged cross-sectional view of the third modified example of the semiconductor device shown in FIG. 1. [Figure 24]FIG. 24 is a partially enlarged cross-sectional view for explaining the manufacturing process of the semiconductor device shown in FIG. 23. [Figure 25] FIG. 25 is a plan view of a semiconductor device according to a second embodiment of the present disclosure, with the encapsulating resin being transparent. [Figure 26] FIG. 26 is a bottom view of the semiconductor device shown in FIG. 25. [Figure 27] FIG. 27 is a right side view of the semiconductor device shown in FIG. 25. [Figure 28] FIG. 28 is a rear view of the semiconductor device shown in FIG. 25. [Figure 29] FIG. 29 is a cross-sectional view taken along line XXIX-XXIX of FIG. 25. [Figure 30] FIG. 30 is a partially enlarged view of FIG. 29. [Figure 31] FIG. 31 is a plan view for explaining the manufacturing process of the semiconductor device shown in FIG. 25. [Figure 32] FIG. 32 is a plan view for explaining the manufacturing process of the semiconductor device shown in FIG. 25. [Figure 33] FIG. 33 is a cross-sectional view for explaining the manufacturing process of the semiconductor device shown in FIG. 25. [Figure 34] FIG. 34 is a bottom view for explaining the manufacturing process of the semiconductor device shown in FIG. 25. [Figure 35] FIG. 35 is a cross-sectional view for explaining the manufacturing process of the semiconductor device shown in FIG. 25. [Figure 36] FIG. 36 is a bottom view for explaining the manufacturing process of the semiconductor device shown in FIG. 25. [Figure 37] FIG. 37 is a cross-sectional view for explaining the manufacturing process of the semiconductor device shown in FIG. 25. [Figure 38] FIG. 38 is a plan view of a semiconductor device according to a third embodiment of the present disclosure, with the encapsulating resin being transparent. [Figure 39] FIG. 39 is a bottom view of the semiconductor device shown in FIG. 38. [Figure 40] FIG. 40 is a cross-sectional view taken along line XL-XL of FIG. 38. [Figure 41] FIG. 41 is a cross-sectional view taken along line XLI-XLI of FIG. 38. [Figure 42] Figure 42 is a cross-sectional view along the line XLII-XLII in Figure 38. [Figure 43] Figure 43 is a magnified view of a portion of Figure 40. [Figure 44] Figure 44 is a plan view of a semiconductor device according to a fourth embodiment of the present disclosure, and shows a sealant resin. [Figure 45] Figure 45 is a bottom view of the semiconductor device shown in Figure 44. [Figure 46] Figure 46 is a bottom view of a semiconductor device according to a fifth embodiment of the present disclosure. [Figure 47] Figure 47 is a cross-sectional view of the semiconductor device shown in Figure 46. [Figure 48] Figure 48 is a cross-sectional view of the semiconductor device shown in Figure 46. [Figure 49] Figure 49 is a magnified view of a portion of Figure 48. [Modes for carrying out the invention]

[0011] The forms for implementing this disclosure will be described based on the attached drawings.

[0012] A semiconductor device A10 according to a first embodiment of this disclosure will be described based on Figures 1 to 11. The semiconductor device A10 is surface-mounted on a wiring board. The semiconductor device A10 comprises a plurality of leads 10, a plurality of semiconductor elements 20, a plurality of conductive members 30, a sealing resin 40, and a coating layer 50. Here, for ease of understanding, Figure 2 shows the sealing resin 40 as transparent and is indicated by dashed lines.

[0013] In describing the semiconductor device A10, for convenience, the thickness direction of multiple leads 10 (and by extension, any one lead 10) is referred to as the "thickness direction z". One direction perpendicular to the thickness direction z is referred to as the "first direction x". The direction perpendicular to both the thickness direction z and the first direction x is referred to as the "second direction y". The semiconductor device A10 is rectangular in shape when viewed in the thickness direction z.

[0014] As shown in Figure 2, the multiple leads 10 support multiple semiconductor elements 20 and form part of the conductive path between the wiring board on which the semiconductor device A10 is mounted and the multiple semiconductor elements 20. All of the multiple leads 10 consist of a common lead frame. Therefore, the composition of all of the multiple leads 10 is the same. The composition of the multiple leads 10 includes copper (Cu) (i.e., each lead 10 contains copper). The multiple leads 10 include a first lead 101, a second lead 102, a third lead 103, and a fourth lead 104.

[0015] As shown in Figure 2, the second lead 102 is located next to the first lead 101 in the first direction x. The third lead 103 is located next to the second lead 102 in the second direction y. The fourth lead 104 is located next to the third lead 103 in the first direction x, and also next to the first lead 101 in the second direction y.

[0016] As shown in Figures 2, 3, 7, and 9, the second lead 102 and the third lead 103 have a main surface 112, two back surfaces 122, two side surfaces 13, a first outer end surface 141, an inner end surface 15, an inner circumferential surface 16, a canopy portion 17, an outward projection 18, and an inward projection 19.

[0017] As shown in Figures 7 and 9, the main surface 112 faces in the thickness direction z. The main surface 112 is covered with the sealing resin 40. The two back surfaces 122 face away from the main surface 112 in the thickness direction z. The two main surfaces 112 are located apart from each other in the second direction y. The two back surfaces 122 are exposed from the sealing resin 40. As shown in Figures 3 and 7, the two side surfaces 13 are individually connected to the two back surfaces 122 and face in the first direction x. The two side surfaces 13 are exposed from the sealing resin 40.

[0018] As shown in Figures 2, 3, 6, and 9, the first outer end face 141 faces outward from the sealing resin 40 in the second direction y. The first outer end face 141 is exposed from the sealing resin 40. The area of ​​the first outer end face 141 is smaller than the area of ​​each of the two side surfaces 13. The first outer end face 141 is connected to the main surface 112 and is located away from the two back surfaces 122.

[0019] As shown in Figures 2, 3, and 11, the inner end face 15 faces inward into the sealing resin 40 in the second direction y. The inner end face 15 is exposed from the sealing resin 40. The area of ​​the inner end face 15 is smaller than the area of ​​each of the two side surfaces 13. The inner end face 15 connects to the main surface 112 and is located away from the two back surfaces 122 and the two side surfaces 13.

[0020] As shown in Figures 2, 3, 7, and 9, the inner circumferential surface 16 connects to two back surfaces 122 and faces in a direction perpendicular to the thickness direction z. The inner circumferential surface 16 is covered with sealing resin 40.

[0021] As shown in Figures 2, 3, 7, and 9, the eaves portion 17 protrudes from the inner circumferential surface 16 in a direction perpendicular to the thickness direction z. The eaves portion 17 includes the main surface 112. The eaves portion 17 has an overhanging surface 171 facing away from the main surface 112 in the thickness direction z. The overhanging surface 171 connects to the inner circumferential surface 16 and is located between the main surface 112 and the two back surfaces 122 in the thickness direction z. The eaves portion 17 is covered with sealing resin 40.

[0022] As shown in Figures 2, 3, and 9, the outward projection 18 protrudes outward from the eaves 17 in a second direction y toward the sealing resin 40. The outward projection 18 includes a main surface 112 and a first outward end surface 141. The lower surface of the outward projection 18, which faces the same side as the two back surfaces 122 in the thickness direction z, is flush with the overhang surface 171 of the eaves 17.

[0023] As shown in Figures 2, 3, and 11, the inward projection 19 protrudes inward from the eaves 17 in a second direction y into the sealing resin 40. The inward projection 19 includes a main surface 112 and an inward end surface 15. The lower surface of the inward projection 19, which faces the same side as the two back surfaces 122 in the thickness direction z, is flush with the overhang surface 171 of the eaves 17.

[0024] As shown in Figures 2, 3, 7, and 8, the first lead 101 and the fourth lead 104 have a mounting surface 111, a mounting surface 121, a first outer end surface 141, two second outer end surfaces 142, an inner end surface 15, an inner circumferential surface 16, a canopy portion 17, an outward projection 18, and an inward projection 19. The configuration of the inner end surface 15, inner circumferential surface 16, canopy portion 17, outward projection 18, and inward projection 19 is the same as that of the inner end surface 15, inner circumferential surface 16, canopy portion 17, outward projection 18, and inward projection 19 of the second lead 102 and the third lead 103, so a detailed explanation is omitted here.

[0025] As shown in Figure 7, the mounting surface 111 faces the same side as the main surfaces 112 of the second lead 102 and the third lead 103 in the thickness direction z. The mounting surface 111 is covered with encapsulating resin 40. One of the multiple semiconductor elements 20 is mounted on the mounting surface 111. The mounting surface 121 faces the opposite side from the mounting surface 111 in the thickness direction z. The mounting surface 121 is exposed from the encapsulating resin 40. As shown in Figure 3, the area of ​​the mounting surface 121 is smaller than the area of ​​each of the two back surfaces 122 of the second lead 102 and the third lead 103.

[0026] As shown in Figures 2, 3, 6, and 8, the first outer end faces 141 of the first lead 101 and the fourth lead 104 face outward from the encapsulating resin 40 in the second direction y. Therefore, the direction in which the first outer end face 141 faces is different from the direction in which the two side surfaces 13 of the second lead 102 and the third lead 103 face. The first outer end face 141 is exposed from the encapsulating resin 40. The area of ​​the first outer end face 141 is smaller than the area of ​​each of the two side surfaces 13. The first outer end face 141 is connected to the mounting surface 111 and located away from the mounting surface 121.

[0027] As shown in Figures 3 and 7, the two second outer end faces 142 connect to the mounting surface 121 and face in the first direction x. The two second outer end faces 142 face in the same direction as the two sides 13 of the second lead 102 and the third lead 103, and face opposite to the two sides 13. The two second outer end faces 142 are located apart from each other in the second direction y. The two second outer end faces 142 are exposed from the sealing resin 40. The area of ​​each of the two second outer end faces 142 is larger than the area of ​​the first outer end face 141 of the first lead 101 and the fourth lead 104.

[0028] As shown in Figures 2 and 8, the multiple semiconductor elements 20 are individually mounted on the mounting surface 111 of the first lead 101 and the mounting surface 111 of the fourth lead 104. In semiconductor device A10, the multiple semiconductor elements 20 are diodes.

[0029] As shown in Figure 10, the multiple semiconductor elements 20 have a first electrode 21 and a second electrode 22. The first electrode 21 is provided on the side facing the mounting surface 111 of the first lead 101. The first electrode 21 corresponds to the anode electrode.

[0030] As shown in Figure 42, the second electrode 22 is located on the opposite side of the first electrode 21 in the thickness direction z. The second electrode 22 faces either the mounting surface 111 of the first lead 101 or the mounting surface 111 of the fourth lead 104. The second electrode 22 corresponds to the cathode electrode.

[0031] As shown in Figures 2 and 8, the plurality of semiconductor elements 20 includes a first semiconductor element 201 and a second semiconductor element 202. The first semiconductor element 201 is mounted on the mounting surface 111 of the first lead 101. As shown in Figure 10, the second electrode 22 of the first semiconductor element 201 is bonded to the mounting surface 111 of the first lead 101 via a junction layer 29. The junction layer 29 is conductive. The junction layer 29 is, for example, solder. Alternatively, the junction layer 29 may be a sintered metal containing silver (Ag). As a result, the second electrode 22 of the first semiconductor element 201 is electrically connected to the first lead 101. The second electrode 22 of the second semiconductor element 202 is bonded to the mounting surface 111 of the fourth lead 104 via the junction layer 29. As a result, the second electrode 22 of the second semiconductor element 202 is electrically connected to the fourth lead 104.

[0032] The multiple conductive members 30 include two first members 31, as shown in Figure 2. One of the two first members 31 is bonded to the first electrode 21 of the first semiconductor element 201 and to the main surface 112 of the second lead 102 via a bonding layer 29. As a result, the first electrode 21 of the first semiconductor element 201 is electrically connected to the second lead 102. The other of the two first members 31 is bonded to the first electrode 21 of the second semiconductor element 202 and to the main surface 112 of the third lead 103 via a bonding layer 29. As a result, the first electrode 21 of the second semiconductor element 202 is electrically connected to the third lead 103. The two first members 31 are metal clips. The composition of the two first members 31 includes copper. Alternatively, the two first members 31 may be wires.

[0033] As shown in Figures 7 to 9, the sealing resin 40 covers a portion of each of the multiple leads 10, the multiple semiconductor elements 20, and the multiple conductive members 30. The sealing resin 40 has electrical insulating properties. The sealing resin 40 is made of a material including, for example, a black epoxy resin. As shown in Figures 4 and 5, the sealing resin 40 has a top surface 41, a bottom surface 42, an outer surface 43, and a recess 44.

[0034] As shown in Figures 7 to 9, the top surface 41 and the bottom surface 42 face opposite each other in the thickness direction z. Of these, the bottom surface 42 faces the same side as the two back surfaces 122 of the second lead 102 and the third lead 103 in the thickness direction z. The two back surfaces 122 and the mounting surface 121 of the first lead 101 and the fourth lead 104 are exposed from the bottom surface 42.

[0035] As shown in Figures 3 to 5, the outer surface 43 connects to the top surface 41 and the bottom surface 42 and faces outward toward the sealing resin 40 in a direction perpendicular to the thickness direction z. The outer surface 43 includes a pair of first surfaces 431 and a pair of second surfaces 432.

[0036] As shown in Figure 3, the pair of first surfaces 431 face opposite each other in the first direction x. As shown in Figures 4 and 7, two side surfaces 13 of the second lead 102 and the third lead 103 are exposed from one of the pair of first surfaces 431. As shown in Figures 5 and 7, two second outer end faces 142 of the first lead 101 and the fourth lead 104 are exposed from the other of the pair of first surfaces 431.

[0037] As shown in Figure 3, the pair of second surfaces 432 face opposite each other in the second direction y. As shown in Figures 1, 8, and 9, the first outer end face 141 of the first lead 101 and the first outer end face 141 of the second lead 102 are exposed from one of the pair of second surfaces 432. As shown in Figures 6, 8, and 9, the first outer end face 141 of the fourth lead 104 and the first outer end face 141 of the third lead 103 are exposed from the other of the pair of second surfaces 432.

[0038] As shown in Figures 3 to 5, the recess 44 is recessed from the bottom surface 42 in the thickness direction z. The recess 44 is a groove extending in a direction perpendicular to the thickness direction z. In the semiconductor device A10, the recess 44 extends in a first direction x. Both sides of the recess 44 in the first direction x are connected to a pair of first surfaces 431 of the outer surface 43. As a result, the bottom surface 42 is divided into two regions by the recess 44.

[0039] As shown in Figure 3, the fourth lead 104 is located next to the first lead 101, with the recess 44 in between. The third lead 103 is located next to the second lead 102, with the recess 44 in between. As shown in Figure 11, the recess 44 has an inner surface 441. The inner surface 441 connects to the bottom surface 42 and faces inward into the sealing resin 40 in a direction perpendicular to the thickness direction z. Furthermore, the inner surface 441 includes a pair of regions that are spaced apart from each other in a direction perpendicular to the thickness direction z and the direction in which the recess 44 extends (the second direction y in semiconductor device A10). The inner end faces 15 of the first lead 101 and the fourth lead 104, and the inner end faces 15 of the second lead 102 and the third lead 103 are exposed from this pair of regions.

[0040] As shown in Figure 11, the recess 44 has an intermediate surface 442. The intermediate surface 442 faces the same side as the bottom surface 42 in the thickness direction z and is connected to the inner surface 441. In the semiconductor device A10, in the thickness direction z, the intermediate surface 442 is located further from the bottom surface 42 than the main surfaces 112 of the second lead 102 and the third lead 103.

[0041] As shown in Figures 2, 3, and 7, the coating layer 50 covers the two back surfaces 122 and two side surfaces 13 of the second lead 102 and the third lead 103. Furthermore, the coating layer 50 covers the mounting surface 121 and two second outer end surfaces 142 of the first lead 101 and the fourth lead 104. The first outer end surface 141 and inner end surface 15 of the multiple leads 10 are not covered by the coating layer 50. The composition of the coating layer 50 includes a metallic element. This metallic element is, for example, tin (Sn). In addition, this metallic element may include at least one of nickel (Ni), palladium (Pd), and gold (Au). The metallic element included in the coating layer 50 is preferably an element that has properties that improve the wettability of the solder used when mounting the semiconductor device A10 to the wiring board.

[0042] Next, an example of a method for manufacturing the semiconductor device A10 will be described based on Figures 12 to 20. Here, the cross-sectional positions in Figures 14 and 16 are the same as those in Figure 7. The cross-sectional positions in Figures 18 and 19 are the same as those in Figure 11.

[0043] First, as shown in Figure 12, multiple semiconductor elements 20 are individually mounted on the mounting surfaces 111 of the first lead 101 and the fourth lead 104 of the multiple leads 10. The mounting surface 111 is located on the opposite side in the thickness direction z from the back surface 122 of the second lead 102 and the third lead 103 of the multiple leads 10. Subsequently, multiple conductive members 30 are individually joined to the first electrode 21 of the multiple semiconductor elements 20 and to the main surfaces 112 of the second lead 102 and the third lead 103.

[0044] As shown in Figure 12, the multiple leads 10 are connected to the frame 80 via tie bars 81. Furthermore, at least two of the multiple leads 10 are connected to each other by connecting bands 82. In semiconductor device A10, the first lead 101 and the fourth lead 104, and the second lead 102 and the third lead 103 are each connected to each other by connecting bands 82. The frame 80, tie bars 81, and connecting bands 82 are made of the same composition as the multiple leads 10. Therefore, the frame 80, tie bars 81, and connecting bands 82 are all conductive.

[0045] Next, as shown in Figures 13 and 14, a sealing resin 40 is formed to cover a portion of each of the multiple leads 10, the multiple semiconductor elements 20, and the multiple conductive members 30. The sealing resin 40 is formed by transfer molding. In this step, at least one of the back surface 122 and side surface 13 of the multiple leads 10 (second lead 102 and third lead 103) is exposed from the sealing resin 40. Furthermore, in this step, the mounting surface 121 of the first lead 101 and the fourth lead 104, and the two second outer end surfaces 142 are also exposed from the sealing resin 40.

[0046] Next, as shown in Figures 15 and 16, a coating layer 50 containing a metal element in its composition is formed by electroplating to cover the exposed back surface 122 and side surface 13 from the sealing resin 40. The coating layer 50 is, for example, a tin plating layer. In this step, the mounting surfaces 121 of the first lead 101 and the fourth lead 104, and the two second outer end faces 142 are also covered by the coating layer 50.

[0047] Next, as shown in Figure 17, the connecting band 82 is cut by removing a portion of the sealing resin 40 from the side where the back surface 122 is exposed in the thickness direction z. A cutting device such as a dicing blade or a laser is used to cut the connecting band 82. Figure 18 shows the state of the two leads 10 before cutting the connecting band 82. Figure 19 shows the state of the two leads 10 after cutting the connecting band 82. As shown in Figure 19, this process forms a recess 44 in the sealing resin 40, and the inner end faces 15 appear from the two leads 10 that were connected by the connecting band 82.

[0048] Finally, as shown in Figure 20, the tie bar 81 is cut to separate the multiple leads 10 from the frame 80. This step exposes the first outer end faces 141 from the multiple leads 10 that were connected by the tie bar 81. By going through the above steps, the semiconductor device A10 is obtained.

[0049] Next, semiconductor device A11, which is a first modified example of semiconductor device A10, will be described based on Figure 21. Here, the cross-sectional position in Figure 21 is the same as the cross-sectional position in Figure 11.

[0050] As shown in Figure 21, in semiconductor device A11, the configuration of the inner end faces 15 and inward protrusions 19 of the second lead 102 and the third lead 103 differs from that of semiconductor device A10. The lower surface of the inward protrusion 19, which faces the same side as the back surface 122 in the thickness direction z, is separated from the overhang surface 171 of the eaves portion 17 in the thickness direction z towards the side where the main surface 112 is located. The upper surface of the inward protrusion 19, which faces the same side as the main surface 112 in the thickness direction z, corresponds to the main surface 112. The inner end face 15 is connected to the main surface 112. As a result, the area of ​​the inner end face 15 is smaller than the area of ​​the inner end faces 15 of the second lead 102 and the third lead 103 in semiconductor device A10. The configuration of the inner end faces 15 and inward protrusions 19 of the first lead 101 and the fourth lead 104 is the same as this configuration.

[0051] Next, a second modified example of semiconductor device A10, semiconductor device A12, will be described based on Figure 22. Here, the cross-sectional position in Figure 22 is the same as the cross-sectional position in Figure 11.

[0052] As shown in Figure 22, in semiconductor device A12, the configuration of the inner end faces 15 and inward protrusions 19 of the second lead 102 and the third lead 103, and the configuration of the recesses 44 of the sealing resin 40 differ from those of semiconductor device A10. The upper surface of the inner end face 15, which faces the same side as the main surface 112 in the thickness direction z, is separated from the main surface 112 in the thickness direction z towards the side where the back surface 122 is located. The lower surface of the inward protrusion 19, which faces the same side as the back surface 122 in the thickness direction z, corresponds to the overhang surface 171 of the eaves portion 17. The inner end face 15 is connected to the overhang surface 171. As a result, the area of ​​the inner end face 15 is smaller than the area of ​​the inner end face 15 of the second lead 102 and the third lead 103 in semiconductor device A10. The configuration of the inner end faces 15 and inward protrusions 19 of the first lead 101 and the fourth lead 104 is the same as this configuration.

[0053] As shown in Figure 22, in the thickness direction z, the intermediate surface 442 of the recess 44 is located between the main surface 112 and the back surface 122. Therefore, the depth of the recess 44 is smaller than the depth of the recess 44 of the semiconductor device A10.

[0054] Next, a third modified example of semiconductor device A10, semiconductor device A13, will be described based on Figures 23 and 24. Here, the cross-sectional positions in Figures 23 and 24 are the same as those in Figure 11.

[0055] As shown in Figure 23, in semiconductor device A13, the configuration of the inner end faces 15 and inward protrusions 19 of the second lead 102 and the third lead 103 differs from that of semiconductor device A10. The lower surface of the inward protrusion 19, which faces the same side as the back surface 122 in the thickness direction z, is flush with the back surface 122. The lower surface of the inward protrusion 19 is covered by the coating layer 50. The upper surface of the inward protrusion 19, which faces the same side as the main surface 112 in the thickness direction z, corresponds to the main surface 112. The inner end face 15 is connected to the main surface 112.

[0056] Figure 24 shows the state of the semiconductor device A13 before the cutting of the connecting band 82 shown in Figure 17, which is part of the manufacturing process of the semiconductor device A13. The connecting band 82 is connected to the eaves portion 17 of the second lead 102 and the eaves portion 17 of the third lead 103. When cutting the connecting band 82, the semiconductor device A13 is obtained by leaving both ends of the connecting band 82 connected to the eaves portion 17. For this reason, the dimension of the long side (dimension in the thickness direction z) of the inner end face 15 is equal to the dimension of the long side of each of the two sides 13 of the second lead 102 and the two sides 13 of the third lead 103. Therefore, the area of ​​the inner end face 15 is larger than the area of ​​the inner end face 15 of each of the second lead 102 and the third lead 103 in the semiconductor device A10. However, the dimension of the short side of the inner end face 15 is smaller than the dimension of each of the short sides 13 of the two sides 13. Therefore, in semiconductor device A13, the area of ​​the inner end face 15 is smaller than the area of ​​each of the two side faces 13. The configuration of the inner end face 15 and the inward protrusion 19 of the first lead 101 and the fourth lead 104 is the same as this configuration.

[0057] Next, we will explain the effects and benefits of semiconductor device A10.

[0058] The semiconductor device A10 comprises a second lead 102 having a back surface 122 and a side surface 13 exposed from the sealing resin 40, and a coating layer 50 covering the back surface 122 and the side surface 13. The sealing resin 40 has an inner surface 441 and a recess 44 formed in the bottom surface 42. The second lead 102 and at least one of the first lead 101 and the third lead 103, which are located between the second lead 102 with the recess 44 in between, have an inner end surface 15 exposed from the inner surface 441.

[0059] Here, in the manufacturing process of the semiconductor device A10, in the step of forming the sealing resin 40 shown in Figures 13 and 14, the sealing resin 40 is formed such that the back surface 122 and side surface 13 of the second lead 102 are exposed from the sealing resin 40. Subsequently, in the step of forming the coating layer 50 shown in Figures 15 and 16, the coating layer 50 can be formed by electroplating. At this stage of the process, at least two leads 10, including the second lead 102, are connected by a connecting band 82 that has the same composition as the multiple leads 10, i.e., is conductive. With this configuration, even leads 10 that are not connected to the frame 80 by a tie bar 81 can be electrically connected to the frame 80. Subsequently, by going through the step of cutting the connecting band 82 shown in Figure 17, electrical insulation is provided between the two leads 10 connected by the connecting band 82. The inner end face 15 and recess 44 of the semiconductor device A10 are traces obtained by this process. Furthermore, by going through the process of cutting the tie bar 81 shown in Figure 20, all of the multiple leads 10 become electrically insulated from each other.

[0060] Therefore, in the semiconductor device A10, the coating layer 50 covering the back surface 122 and side surface 13 of the second lead 102 can be easily formed by electroplating. For this reason, in the semiconductor device A10, the step of exposing the side surface 13 from the sealing resin 40 after forming the sealing resin 40 is unnecessary. Furthermore, compared to the case where the coating layer 50 is formed by electroless plating, the formation efficiency of the coating layer 50 can be improved. As described above, according to the semiconductor device A10 and its manufacturing method, it is possible to form the coating layer 50 covering the back surface 122 and side surface 13 of the lead 10 (second lead 102) exposed from the sealing resin 40 more efficiently.

[0061] The recess 44 of the sealing resin 40 is a groove extending in a direction perpendicular to the thickness direction z. The inner surface 441 of the recess 44 includes a pair of regions that are spaced apart from each other in directions perpendicular to the thickness direction z and the direction in which the recess 44 extends. The recess 44 in this configuration is obtained by using a cutting device such as a dicing blade in the process of cutting the connecting band 82 shown in Figure 17 during the manufacturing process of the semiconductor device A10. By using such a cutting device, the connecting band 82 can be cut efficiently. Furthermore, when the bottom surface 42 of the sealing resin 40 is divided into multiple regions by the recess 44, the connecting band 82 can be cut smoothly without slowing down the cutting speed, thus suppressing a decrease in the manufacturing efficiency of the semiconductor device A10.

[0062] The inner end face 15 of the second lead 102 is located away from the side surface 13. This prevents defects from occurring in the coating layer 50 covering the side surface 13 during the manufacturing process of the semiconductor device A10, specifically in the step of cutting the connecting band 82 shown in Figure 17, due to the cutting of the connecting band 82.

[0063] The area of ​​the inner end face 15 of the second lead 102 is smaller than the area of ​​the side surface 13. This makes it possible to suppress the generation of metal burrs on the edge of the inner end face 15 during the cutting step of the connecting band 82 shown in Figure 17 in the manufacturing process of the semiconductor device A10. Furthermore, the inner end face 15 is located away from the back surface 122. This makes it possible to prevent a decrease in the bonding strength of the semiconductor device A10 to the wiring board caused by these metal burrs when mounting the semiconductor device A10 to the wiring board.

[0064] The inner end face 15 of the second lead 102 is connected to the main surface 112. In this configuration, it is desirable that the intermediate surface 442 of the recess 44 of the sealing resin 40 be located further away from the bottom surface 42 of the recess 44 than the main surface 112. This ensures that the connecting band 82 can be reliably cut in the step of cutting the connecting band 82 shown in Figure 17 during the manufacturing process of the semiconductor device A10.

[0065] The first lead 101 has a first outer end face 141 that is exposed from the outer surface 43 of the sealing resin 40 and faces a direction different from that of the side surface 13 of the second lead 102. The outer surface 43 is a trace obtained by the process of cutting the tie bar 81 shown in Figure 20 during the manufacturing process of the semiconductor device A10. This prevents defects from occurring in the coating layer 50 covering the side surface 13 due to the cutting of the tie bar 81 during this process.

[0066] The first outer end face 141 of the first lead 101 is located away from the mounting surface 121. In the manufacturing process of the semiconductor device A10, during the step of cutting the tie bar 81 shown in Figure 20, metal burrs are generated on the edge of the first outer end face 141. By adopting this configuration, when mounting the semiconductor device A10 to the wiring board, it is possible to prevent a decrease in the bonding strength of the semiconductor device A10 to the wiring board caused by these metal burrs.

[0067] The first lead 101 is connected to the mounting surface 121 and has a second outer end face 142 that is exposed from the outer surface 43 of the sealing resin 40. If the first lead 101 has at least the first outer end face 141, then in the manufacturing process of the semiconductor device A10, the coating layer 50 covering the mounting surface 121 and the second outer end face 142 can be easily formed by electroplating in the step of forming the coating layer 50 shown in Figures 15 and 16. As a result, when mounting the semiconductor device A10 to a wiring board, the bonding state to the wiring board can be easily confirmed visually not only for the second lead 102 but also for the first lead 101.

[0068] The area of ​​the mounting surface 121 of the first lead 101 is larger than the area of ​​the back surface 122 of the second lead 102. The first semiconductor element 201 is mounted on the first lead 101. This allows the heat generated from the first semiconductor element 201 to be dissipated to the outside more efficiently.

[0069] The semiconductor device A10 further includes a fourth lead 104 on which a second semiconductor element 202 is mounted. The recess 44 of the sealing resin 40 is also located between the first lead 101 and the fourth lead 104. The first lead 101 and the fourth lead 104 have inner end faces 15 that are exposed from the inner surface 441 of the recess 44. As a result, in the manufacturing process of the semiconductor device A10, in the step of forming the coating layer 50 shown in Figures 15 and 16, the coating layer 50 covering not only the first lead 101 but also the mounting surface 121 and the second outer end face 142 of the fourth lead 104 can be easily formed by electroplating.

[0070] In semiconductor devices A11 and A12, the inner end face 15 of the second lead 102 is smaller in area than the inner end face 15 of the second lead 102 in semiconductor device A10. This suppresses the generation of metal burrs on the edge of the inner end face 15 during the cutting of the connecting band 82 shown in Figure 17 in the manufacturing process of semiconductor device A10. Furthermore, in semiconductor device A12, the depth of the recess 44 in the sealing resin 40 is smaller than the depth of the recess 44 in semiconductor device A10. This reduces the volume of sealing resin 40 removed during the cutting of the connecting band 82 shown in Figure 17 in the manufacturing process of semiconductor device A10. This contributes to suppressing a decrease in the strength of the sealing resin 40.

[0071] A semiconductor device A20 according to a second embodiment of the present disclosure will be described based on Figures 25 to 30. In these figures, elements that are the same as or similar to those in the semiconductor device A10 described above are denoted by the same reference numerals, and redundant explanations are omitted. Here, for ease of understanding, Figure 25 shows the sealing resin 40 transparent and is indicated by dashed lines.

[0072] In semiconductor device A20, the configuration of the multiple leads 10 and the sealing resin 40 differs from that of semiconductor device A10 described above.

[0073] As shown in Figures 26 to 28, the pair of first surfaces 431 of the outer surface 43 of the sealing resin 40 have a first region 431A, a second region 431B, and a third region 431C. The first region 431A is connected to the top surface 41 of the sealing resin 40. The second region 431B is connected to the bottom surface 42 of the sealing resin 40 and is located further inward than the first region 431A. Two side surfaces 13 of the second region 431B of the pair of first surfaces 431 are exposed from one of the second regions 431B of the pair. Two second outer end faces 142 of the first lead 101 and the fourth lead 104 are exposed from the other second region 431B of the pair of first surfaces 431. The third region 431C is located between the top surface 41 and the bottom surface 42 in the thickness direction z, and is connected to the first region 431A and the second region 431B. The third region 431C faces the same side as the bottom surface 42 in the thickness direction z.

[0074] As shown in Figures 29 and 30, the coating layer 50 is located inward of the sealing resin 40 beyond the first region 431A of the pair of first surfaces 431 of the outer surface 43. As shown in Figure 26, in the thickness direction z, the third region 431C of the pair of first surfaces 431 overlaps with the coating layer 50. The third region 431C is located closer to the top surface 41 than the main surface 112 of the second lead 102 and the third lead 103 in the thickness direction z.

[0075] Next, an example of a method for manufacturing the semiconductor device A20 will be described based on Figures 31 to 37. Here, Figures 33, 35, and 37 have the same cross-sectional positions as those in Figure 29.

[0076] First, as shown in Figure 31, multiple semiconductor elements 20 are individually mounted on the mounting surfaces 111 of the first lead 101 and the fourth lead 104 of the multiple leads 10. Then, multiple conductive members 30 are individually joined to the first electrodes 21 of the multiple semiconductor elements 20 and to the main surfaces 112 of the second lead 102 and the third lead 103 of the multiple leads 10.

[0077] As shown in Figure 31, the frame 80 has a plurality of first frame portions 801 and a plurality of second frame portions 802. The plurality of first frame portions 801 extend along a first direction x and are located apart from each other in a second direction y. The plurality of second frame portions 802 extend along a second direction y and are located apart from each other in a first direction x. Both ends of each of the plurality of second frame portions 802 are connected to two first frame portions 801 that are adjacent to each other in the second direction y. The tie bar 81 is connected to the plurality of first frame portions 801. In the semiconductor device A20, each of the plurality of leads 10 is connected to one of two second frame portions 802 that are adjacent to each other in the first direction x.

[0078] Next, as shown in Figures 32 and 33, a sealing resin 40 is formed to cover a portion of each of the multiple leads 10, the multiple semiconductor elements 20, and the multiple conductive members 30. The sealing resin 40 is formed over the entire frame 80 by compression molding. In this step, the back surface 122 of at least one of the multiple leads 10 (second lead 102 and third lead 103) is exposed from the sealing resin 40. Furthermore, in this step, the mounting surfaces 121 of the first lead 101 and fourth lead 104 are also exposed from the sealing resin 40.

[0079] Next, as shown in Figures 34 and 35, the multiple second frame portions 802 are removed from the side where the back surface 122 is exposed in the thickness direction z. The removal of the multiple second frame portions 802 is performed by half-cut dicing. At this time, a portion of each of the multiple leads 10 located at the boundary with the multiple second frame portions 802 and a portion of the sealing resin 40 located at the boundary with the multiple second frame portions 802 are removed together. Through this process, multiple grooves 83 are formed in the sealing resin 40 that are recessed in the thickness direction z and extend along the second direction y. From two grooves 83 that are adjacent to each other in the first direction x, two side surfaces 13 of the second lead 102 and the third lead 103, and two second outer end faces 142 of the first lead 101 and the fourth lead 104, are exposed.

[0080] Next, as shown in Figures 36 and 37, a coating layer 50 is formed by electroplating to cover the exposed back surface 122 and side surface 13 from the sealing resin 40. In this step, the mounting surfaces 121 of the first lead 101 and the fourth lead 104, and the two second outer end surfaces 142 are also covered by the coating layer 50. Subsequently, the connecting band 82 is cut by removing a portion of the sealing resin 40 from the side where the back surface 122 is exposed in the thickness direction z. The method for cutting the connecting band 82 is the same as the cutting method in the manufacturing process of the semiconductor device A10 shown in Figures 17 to 19.

[0081] Finally, the multiple leads 10 are separated from the frame 80 by cutting the sealing resin 40 and tie bars 81 in a grid pattern along the first direction x and the second direction y. By going through the above steps, the semiconductor device A20 is obtained.

[0082] Next, we will explain the effects and benefits of semiconductor device A20.

[0083] The semiconductor device A20 comprises a second lead 102 having a back surface 122 and a side surface 13 exposed from the sealing resin 40, and a coating layer 50 covering the back surface 122 and the side surface 13. The sealing resin 40 has an inner surface 441 and a recess 44 formed in the bottom surface 42. The second lead 102 and at least one of the first lead 101 and the third lead 103, which are located between the second lead 102 and the recess 44 in between, each have an inner end surface 15 exposed from the inner surface 441. Therefore, with the semiconductor device A20, it is possible to more efficiently form the coating layer 50 that covers the back surface 122 and the side surface 13 of the lead 10 (second lead 102) exposed from the sealing resin 40. Furthermore, by having the same configuration as the semiconductor device A10, the semiconductor device A20 also achieves the effects of the said configuration.

[0084] In semiconductor device A20, the pair of first surfaces 431 of the outer surface 43 of the sealing resin 40 have a first region 431A, a second region 431B, and a third region 431C. This configuration is obtained by removing a plurality of second frame portions 802 after forming the sealing resin 40 during the manufacturing of semiconductor device A20. Until the plurality of second frame portions 802 are removed, each of the plurality of leads 10 is connected to one of the plurality of second frame portions 802. This allows the sealing resin 40 to be formed over the entire frame 80 by compression molding. Therefore, the formation of the sealing resin 40 is easier than in the case of semiconductor device A10.

[0085] A semiconductor device A30 according to a third embodiment of this disclosure will be described based on Figures 38 to 43. In these figures, elements that are the same as or similar to those in the semiconductor device A10 described above are denoted by the same reference numerals, and redundant explanations are omitted. Here, for ease of understanding, Figure 38 shows the sealing resin 40 being permeable. In Figure 38, the permeable sealing resin 40 is shown by dashed lines.

[0086] In semiconductor device A30, the configuration of the multiple leads 10, multiple semiconductor elements 20, multiple conductive members 30, and sealing resin 40 differs from the configuration of semiconductor device A10 described above.

[0087] As shown in Figures 38 and 39, the multiple leads 10 further include a fifth lead 105 and a sixth lead 106, in addition to the first lead 101, second lead 102, third lead 103, and fourth lead 104. The fifth lead 105 is located next to the second lead 102 in the second direction y and on the opposite side of the second lead 102 from the third lead 103 in the second direction y. The sixth lead 106 is located next to the third lead 103 in the second direction y and on the opposite side of the third lead 103 from the second lead 102 in the second direction y.

[0088] As shown in Figures 38, 39, and 41, the fifth lead 105 and the sixth lead 106 have a main surface 112, a back surface 122, a side surface 13, a first outer end surface 141, an inner circumferential surface 16, a canopy portion 17, and an outward projection 18.

[0089] As shown in Figures 38 and 39, the second lead 102 and the third lead 103 have a main surface 112, a back surface 122, a side surface 13, an inner end surface 15, an inner circumferential surface 16, a visor portion 17, and an inward projection 19. Furthermore, the inner end surface 15 of the second lead 102 includes a region facing inward into the sealing resin 40 in a first direction x and a region facing inward into the sealing resin 40 in a second direction y. Accordingly, the inward projection 19 of the second lead 102 includes a region projecting inward into the sealing resin 40 from the visor portion 17 in a first direction x and a region projecting inward into the sealing resin 40 from the visor portion 17 in a second direction y.

[0090] As shown in Figures 38 and 39, the first lead 101 has a mounting surface 111, a mounting surface 121, a first outer end surface 141, two second outer end surfaces 142, an inner end surface 15, an inner circumferential surface 16, a eaves portion 17, an outward projection 18, and an inward projection 19. The inner end surface 15 of the first lead 101 includes a region facing inward into the sealing resin 40 in a first direction x and a region facing inward into the sealing resin 40 in a second direction y. Accordingly, the inward projection 19 of the first lead 101 includes a region protruding inward into the sealing resin 40 from the eaves portion 17 in a first direction x and a region protruding inward into the sealing resin 40 from the eaves portion 17 in a second direction y. The configuration of the fourth lead 104 is the same as that of the fourth lead 104 of semiconductor device A10, so its description is omitted here.

[0091] In semiconductor device A30, the plurality of semiconductor elements 20 are n-channel type and vertically structured MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors). The plurality of semiconductor elements 20 include a compound semiconductor substrate. The main material of the compound semiconductor substrate is silicon carbide (SiC). Alternatively, silicon (Si) may be used as the main material of the compound semiconductor substrate. In addition, the plurality of semiconductor elements 20 may be other switching elements such as IGBTs (Insulated Gate Bipolar Transistors). In semiconductor device A30, the plurality of semiconductor elements 20 also include a first semiconductor element 201 and a second semiconductor element 202.

[0092] As shown in Figure 42, the multiple semiconductor elements 20 have a first electrode 21, a second electrode 22, and a gate electrode 23. The first electrode 21 is provided on the side facing the mounting surface 111 of the first lead 101. A current corresponding to the power converted by the semiconductor elements 20 flows through the first electrode 21. In other words, the first electrode 21 corresponds to the source electrode.

[0093] As shown in Figure 42, the second electrode 22 is located on the opposite side of the first electrode 21 in the thickness direction z. The second electrode 22 faces either the mounting surface 111 of the first lead 101 or the mounting surface 111 of the fourth lead 104. A current corresponding to the power before it is converted by the semiconductor element 20 flows through the second electrode 22. In other words, the second electrode 22 corresponds to the drain electrode.

[0094] As shown in Figure 42, the gate electrode 23 is located on the same side as the first electrode 21 in the thickness direction z, and is positioned away from the first electrode 21. A gate voltage is applied to the gate electrode 23 to drive the semiconductor element 20. As shown in Figure 38, the area of ​​the gate electrode 23 is smaller than the area of ​​the first electrode 21 when viewed in the thickness direction z.

[0095] As shown in Figure 38, the multiple conductive members 30 include two first members 31 and two second members 32. One of the two first members 31 is bonded to the first electrode 21 of the first semiconductor element 201 and to the main surface 112 of the fifth lead 105 via a bonding layer 29. As a result, the first electrode 21 of the first semiconductor element 201 is electrically connected to the fifth lead 105. The other of the two first members 31 is bonded to the first electrode 21 of the second semiconductor element 202 and to the main surface 112 of the sixth lead 106 via a bonding layer 29. As a result, the first electrode 21 of the second semiconductor element 202 is electrically connected to the sixth lead 106.

[0096] As shown in Figure 38, one of the two second members 32 is joined to the gate electrode 23 of the first semiconductor element 201 and the main surface 112 of the second lead 102. This allows the gate electrode 23 of the first semiconductor element 201 to conduct to the second lead 102. The other second member 32 is joined to the gate electrode 23 of the second semiconductor element 202 and the main surface 112 of the third lead 103. This allows the gate electrode 23 of the second semiconductor element 202 to conduct to the third lead 103. The two second members 32 are wires. The composition of the two second members 32 includes gold. Alternatively, the composition of the two second members 32 may include aluminum (Al) or copper.

[0097] As shown in Figure 38, when viewed in the thickness direction z, the multiple conductive members 30 are located away from the inner end faces 15 of the multiple leads 10 (first lead 101, second lead 102, and third lead 103).

[0098] The recesses 44 of the sealing resin 40 include a first groove 44A and a second groove 44B, as shown in Figures 39 to 41. The first groove 44A extends in a first direction x. Both sides of the first groove 44A in the first direction x connect to a pair of first surfaces 431 of the outer surface 43. The second groove 44B extends in a second direction y. Both sides of the second groove 44B in the second direction y connect to a pair of second surfaces 432 of the outer surface 43. The second groove 44B intersects with the first groove 44A. The bottom surface 42 of the sealing resin 40 is divided into four regions by the recesses 44.

[0099] As shown in Figure 39, the fourth lead 104 is located next to the first lead 101, with the first groove 44A in between. The third lead 103 is located next to the second lead 102, with the first groove 44A in between. From the inner surface 441 of the first groove 44A, the region of the inner end face 15 of the first lead 101 facing the second direction y, the inner end face 15 of the fourth lead 104, the region of the inner end face 15 of the second lead 102 facing the second direction y, and the inner end face 15 of the third lead 103 are exposed. As shown in Figures 39 and 43, the first lead 101 is located next to the second lead 102, with the second groove 44B in between. From the inner surface 441 of the second groove 44B, the region of the inner end face 15 of the first lead 101 facing the first direction x and the region of the second lead 102 facing the first direction x are exposed.

[0100] Next, we will explain the effects and benefits of semiconductor device A30.

[0101] The semiconductor device A30 comprises a second lead 102 having a back surface 122 and a side surface 13 exposed from the sealing resin 40, and a coating layer 50 covering the back surface 122 and the side surface 13. The sealing resin 40 has an inner surface 441 and a recess 44 formed in the bottom surface 42. The second lead 102 and at least one of the first lead 101 and the third lead 103, which are located between the second lead 102 and the recess 44 in between, each have an inner end surface 15 exposed from the inner surface 441. Therefore, with the semiconductor device A30, it is possible to more efficiently form the coating layer 50 that covers the back surface 122 and the side surface 13 of the lead 10 (second lead 102) exposed from the sealing resin 40. Furthermore, by having the same configuration as the semiconductor device A10, the semiconductor device A30 also achieves the effects of the said configuration.

[0102] In the semiconductor device A30, the recess 44 of the sealing resin 40 includes a first groove 44A extending in a first direction x and a second groove 44B extending in a second direction y. As a result, the inner end face 15 of the second lead 102 includes a region facing the first direction x and a region facing the second direction y. With this configuration, even if the second lead 102 and the third lead 103 do not have a first outer end face 141, a coating layer 50 covering the back surface 122 and side surface 13 of the second lead 102 and the third lead 103 can be easily formed by electroplating.

[0103] Viewed in the thickness direction z, the multiple conductive members 30 are located away from the inner end faces 15 of the multiple leads 10. This reduces the risk of the multiple conductive members 30 being cut along with the connecting band 82 during the cutting step of the connecting band 82 in the manufacturing process of the semiconductor device A30 (see Figure 17).

[0104] A semiconductor device A40 according to a fourth embodiment of the present disclosure will be described based on Figures 44 and 45. In these figures, elements that are the same as or similar to those in the semiconductor device A10 described above are denoted by the same reference numerals, and redundant explanations are omitted. Here, for ease of understanding, Figure 44 shows the sealing resin 40 being permeable. In Figure 44, the permeable sealing resin 40 is shown by dashed lines.

[0105] In semiconductor device A40, the configuration of the multiple leads 10, the multiple conductive members 30, and the sealing resin 40 differs from that of semiconductor device A10 described above. Furthermore, in semiconductor device A40, the semiconductor element 20 is composed of one first semiconductor element 201.

[0106] As shown in Figures 44 and 45, the multiple leads 10 include a first lead 101, a second lead 102, a third lead 103, and a fifth lead 105. Semiconductor device A40 does not include a fourth lead 104. The first lead 101 has a mounting surface 111, a mounting surface 121, two first outer end faces 141, four second outer end faces 142, an inner end face 15, an inner circumferential surface 16, a eaves portion 17, two outward protrusions 18, and an inward protrusion 19. The inner end face 15 of the first lead 101 faces inward into the sealing resin 40 in a first direction x. Accordingly, the inward protrusion 19 of the first lead 101 protrudes inward into the sealing resin 40 from the eaves portion 17 in the first direction x. The configuration of the first lead 101 is an integrated unit of the first lead 101 and the fourth lead 104 of semiconductor device A10.

[0107] As shown in Figures 44 and 45, the second lead 102 has a main surface 112, a back surface 122, a side surface 13, an inner end surface 15, an inner circumferential surface 16, a visor portion 17, and an inward projection portion 19. The inner end surface 15 of the second lead 102 faces the first direction x. Accordingly, the inward projection portion 19 of the second lead 102 protrudes from the visor portion 17 in the first direction x. The configuration of the third lead 103 is the same as that of the third lead 103 of semiconductor device A10, so its description is omitted here. Furthermore, the configuration of the fifth lead 105 is the same as that of the fifth lead 105 of semiconductor device A30, so its description is omitted here.

[0108] In semiconductor device A40, the first semiconductor element 201 (semiconductor element 20) is an n-channel type MOSFET with a vertical structure, similar to semiconductor device A30.

[0109] The multiple conductive members 30 include a first member 31, a second member 32, and a third member 33, as shown in Figure 44. The first member 31 is bonded to the first electrode 21 of the first semiconductor element 201 and to the main surface 112 of the third lead 103 via a bonding layer 29. As a result, the first electrode 21 of the first semiconductor element 201 is electrically connected to the third lead 103. The second member 32 is bonded to the gate electrode 23 of the first semiconductor element 201 and to the main surface 112 of the fifth lead 105. As a result, the gate electrode 23 of the first semiconductor element 201 is electrically connected to the fifth lead 105. The third member 33 is bonded to the first electrode 21 of the first semiconductor element 201 and to the main surface 112 of the second lead 102. As a result, the first electrode 21 of the first semiconductor element 201 is electrically connected to the second lead 102. The third member 33 is a wire. The composition of the third component 33 includes gold. In addition, the composition of the third component 33 may also include aluminum or copper.

[0110] The recess 44 of the sealing resin 40 is a groove extending in the second direction y, as shown in Figure 45. Both sides of the recess 44 in the second direction y are connected to a pair of second surfaces 432 of the outer surface 43. The first lead 101 is located next to the second lead 102, with the recess 44 in between. The inner end faces 15 of the first lead 101 and the inner end faces 15 of the second lead 102 are exposed from the inner surface 441 of the recess 44.

[0111] Next, we will explain the effects and benefits of semiconductor device A40.

[0112] The semiconductor device A40 comprises a second lead 102 having a back surface 122 and a side surface 13 exposed from the sealing resin 40, and a coating layer 50 covering the back surface 122 and the side surface 13. The sealing resin 40 has an inner surface 441 and a recess 44 formed in the bottom surface 42. The second lead 102 and at least one of the first lead 101 and the third lead 103, which are located between the second lead 102 and the recess 44 in between, each have an inner end surface 15 exposed from the inner surface 441. Therefore, with the semiconductor device A40, it is possible to more efficiently form the coating layer 50 that covers the back surface 122 and the side surface 13 of the lead 10 (second lead 102) exposed from the sealing resin 40. Furthermore, by having the same configuration as the semiconductor device A10, the semiconductor device A40 also achieves the effects of the said configuration.

[0113] In semiconductor device A40, the semiconductor element 20 is composed of one first semiconductor element 201. Therefore, this disclosure can be applied regardless of the number of semiconductor elements 20.

[0114] A semiconductor device A50 according to the fifth embodiment of this disclosure will be described based on Figures 46 to 49. In these figures, elements that are the same as or similar to those in the semiconductor device A10 described above are denoted by the same reference numerals, and redundant explanations are omitted. Here, in Figure 46, the sealing resin 40 is shown to be transparent for ease of understanding. In Figure 46, the transparent sealing resin 40 is shown by dashed lines. The cross-sectional position in Figure 47 is the same as the cross-sectional position in Figure 8 showing semiconductor device A10. The cross-sectional position in Figure 48 is the same as the cross-sectional position in Figure 9 showing semiconductor device A10.

[0115] The semiconductor device A50 differs from the aforementioned semiconductor device A10 in that it further includes an insulator 60.

[0116] As shown in Figures 46 to 49, the insulator 60 is filled into the recess 44 of the sealing resin 40. The insulator 60 is, for example, a resin used for underfill. Each of the inner end faces 15 of the multiple leads 10 is covered with the insulator 60. The insulator 60 is in contact with the intermediate surface 442 of the recess 44. However, the insulator 60 may be separated from the intermediate surface 442 if it is configured to cover two inner end faces 15 that face each other with the recess 44 in between.

[0117] The semiconductor device A50 comprises a second lead 102 having a back surface 122 and a side surface 13 exposed from the sealing resin 40, and a coating layer 50 covering the back surface 122 and the side surface 13. The sealing resin 40 has an inner surface 441 and a recess 44 formed in the bottom surface 42. The second lead 102 and at least one of the first lead 101 and the third lead 103, which are located between the second lead 102 and the recess 44 in between, each have an inner end surface 15 exposed from the inner surface 441. Therefore, with the semiconductor device A50, it is possible to more efficiently form the coating layer 50 that covers the back surface 122 and the side surface 13 of the lead 10 (second lead 102) exposed from the sealing resin 40. Furthermore, by having the same configuration as the semiconductor device A10, the semiconductor device A50 also achieves the effects of the said configuration.

[0118] The semiconductor device A50 further includes an insulator 60 filled in a recess 44 of the sealing resin 40. This prevents solder from adhering to the inner end faces 15 of two adjacent leads 10 with the recess 44 in between when the semiconductor device A50 is mounted on a wiring board. Therefore, a short circuit between two adjacent leads 10 with the recess 44 in between can be prevented.

[0119] This disclosure is not limited to the embodiments described above. The specific configuration of each part of this disclosure can be modified in various ways.

[0120] This disclosure includes embodiments described in the following appendix.

[0121] Note 1. First lead, A second lead located adjacent to the first lead in a direction perpendicular to the thickness direction of the first lead, A third lead located adjacent to the second lead in a direction perpendicular to the thickness direction, A first semiconductor element mounted on the first lead and electrically connected to the second lead, A sealing resin covering a portion of each of the first lead, the second lead, and the third lead, and the first semiconductor element, A coating layer containing a metal element, Equipped with, The sealing resin has a bottom surface facing the thickness direction and an outer surface connected to the bottom surface and facing outward in a direction perpendicular to the thickness direction. The sealing resin has a recess formed in the bottom surface, The recess has an inner surface that is connected to the bottom surface and faces inward towards the sealing resin in a direction perpendicular to the thickness direction, The second lead has a back surface exposed from the bottom surface and a side surface connected to the back surface and exposed from the outer surface, The covering layer covers the back surface and the side surface, The recess is located between the first lead and the second lead. A semiconductor device wherein the second lead and at least one of the first lead and the third lead have an inner end face exposed from the inner surface. Note 2. The recess is a groove extending in a direction perpendicular to the thickness direction, The inner surface includes a pair of regions that are spaced apart from each other in directions perpendicular to the thickness direction and the direction in which the recess extends, The semiconductor device according to Appendix 1, wherein the inner end faces are exposed from the pair of regions. Note 3. The semiconductor device described in Appendix 2, wherein the bottom surface is divided into multiple regions by the recess. Note 4. The recess includes a first groove and a second groove, The semiconductor device described in Appendix 3, wherein the second groove intersects the first groove. Note 5. The semiconductor device according to any one of appendices 1 to 4, wherein the inner end face of the second lead is located away from the side surface. Note 6. The semiconductor device according to Appendix 5, wherein the area of ​​the inner end face of the second lead is smaller than the area of ​​the side surface. Note 7. The semiconductor device according to Appendix 6, wherein the inner end face of the second lead is located away from the back surface. Note 8. The second lead has a main surface facing the opposite side from the back surface in the thickness direction, The semiconductor device according to Appendix 6 or 7, wherein the inner end face is connected to the main face. Note 9. The recess faces the same side as the bottom surface in the thickness direction and has an intermediate surface that connects to the inner surface, The semiconductor device according to Appendix 8, wherein, in the thickness direction, the intermediate surface is located further from the bottom surface than the main surface. Note 10. The first lead has a first outer end face exposed from the outer surface, A semiconductor device according to any one of the appendices 1 to 9, wherein the direction in which the first outer end face faces is different from the direction in which the side surface faces. Note 11. The first lead has a mounting surface exposed from the bottom surface, The semiconductor device according to Appendix 10, wherein the first outer end face is located away from the mounting surface. Note 12. The semiconductor device according to Appendix 11, wherein the area of ​​the mounting surface is larger than the area of ​​the back surface. Note 13. The first lead has a second outer end face that connects to the mounting surface and is exposed from the outer surface, The semiconductor device according to appendix 11 or 12, wherein the covering layer covers the mounting surface and the second outer end surface. Note 14. The direction in which the second outer end face faces is the same as the direction in which the side surface faces. The semiconductor device described in Appendix 13, wherein the second outer end face faces the opposite side from the side face. Note 15. The semiconductor device described in Appendix 14, wherein the area of ​​the second outer end face is larger than the area of ​​the first outer end face. Note 16. A fourth lead located adjacent to the first lead in a direction perpendicular to the thickness direction, The present invention further comprises a second semiconductor element mounted on the fourth lead and electrically connected to the third lead, The sealing resin covers a portion of the fourth lead and the second semiconductor element. The recess is also located between the first lead and the fourth lead. The semiconductor device according to any one of appendices 1 to 15, wherein the first lead and the fourth lead have the inward end faces. Note 17. A step of mounting a semiconductor element on one of a plurality of leads, each having a back surface and a side surface connected to the back surface, The process includes forming a sealing resin that covers a portion of each of the plurality of leads and the semiconductor element, In the step of forming the sealing resin, the back surface and side surface of at least one of the plurality of leads are exposed from the sealing resin. At least two of the aforementioned multiple leads are connected to each other by a connecting band having the same composition as the multiple leads. The process of forming the sealing resin is followed by the process of forming a coating layer containing a metal element that covers the back surface and side surfaces exposed from the sealing resin, by electroplating, A method for manufacturing a semiconductor device, further comprising the step of cutting the connecting band by removing a portion of the sealing resin from the side where the back surface is exposed, after the step of forming the coating layer. [Explanation of symbols]

[0122] A10, A20, A30: Semiconductor equipment 10: Lead 101: First lead 102: Second lead 103: 3rd lead 104: 4th lead 105: Fifth lead 106: Sixth lead 111: Mounting surface 112: Main surface 121: Mounting side 122: Back side 13: Side surface 141: First outer end surface 142: Second outer end surface 15: Inner end surface 16: Inner surface 17: Eave part 171: Overhanging surface 18: Outward convexity 19: Inward convex portion 20: Semiconductor element 201: First semiconductor element 202: Second semiconductor element 21: 1st electrode 22: 2nd electrode 23: Grid gate 29: Junction layer 30: Conductive member 31: First member 32: Second component 33: Third component 40: Sealing resin 41: Top surface 42: Bottom 43: Outer surface 431: 1st side 431A: 1st area 431B: 2nd area 431C: 3rd area 432: Second surface 44: Recess 441: Inner surface 442: Intermediate surface 50: Coating layer 60: Insulator 80: Frame 801: First frame section 802: Second frame section 81: Tiber 82: Connecting strip 83: Groove z: thickness direction x: first direction y: second direction

Claims

1. First lead, A second lead located adjacent to the first lead in a direction perpendicular to the thickness direction of the first lead, A third lead located adjacent to the second lead in a direction perpendicular to the thickness direction, A first semiconductor element mounted on the first lead and electrically connected to the second lead, A sealing resin covering a portion of each of the first lead, the second lead, and the third lead, and the first semiconductor element, A coating layer containing a metal element, The sealing resin has a bottom surface facing the thickness direction and an outer surface connected to the bottom surface and facing outward in a direction perpendicular to the thickness direction. The sealing resin has a recess formed in the bottom surface, The recess has an inner surface that is connected to the bottom surface and faces inward towards the sealing resin in a direction perpendicular to the thickness direction, The second lead has a back surface exposed from the bottom surface and a side surface connected to the back surface and exposed from the outer surface, The covering layer covers the back surface and the side surface, The recess is located between the first lead and the second lead. A semiconductor device wherein the second lead and at least one of the first lead and the third lead have an inner end face exposed from the inner surface.

2. The recess is a groove extending in a direction perpendicular to the thickness direction, The inner surface includes a pair of regions that are spaced apart from each other in directions perpendicular to the thickness direction and the direction in which the recess extends, The semiconductor device according to claim 1, wherein the inner end face is exposed from the pair of regions.

3. The semiconductor device according to claim 2, wherein the bottom surface is divided into a plurality of regions by the recess.

4. The recess includes a first groove and a second groove, The semiconductor device according to claim 3, wherein the second groove intersects the first groove.

5. The semiconductor device according to claim 1, wherein the inner end face of the second lead is located away from the side surface.

6. The semiconductor device according to claim 5, wherein the area of ​​the inner end face of the second lead is smaller than the area of ​​the side surface.

7. The semiconductor device according to claim 6, wherein the inner end face of the second lead is located away from the back surface.

8. The second lead has a main surface facing the opposite side from the back surface in the thickness direction, The semiconductor device according to claim 6, wherein the inner end face is connected to the main face.

9. The recess faces the same side as the bottom surface in the thickness direction and has an intermediate surface that connects to the inner surface, The semiconductor device according to claim 8, wherein, in the thickness direction, the intermediate surface is located further from the bottom surface than the main surface.

10. The first lead has a first outer end face exposed from the outer surface, The semiconductor device according to any one of claims 1 to 9, wherein the direction in which the first outer end face faces is different from the direction in which the side surface faces.

11. The first lead has a mounting surface exposed from the bottom surface, The semiconductor device according to claim 10, wherein the first outer end face is located away from the mounting surface.

12. The semiconductor device according to claim 11, wherein the area of ​​the mounting surface is larger than the area of ​​the back surface.

13. The first lead has a second outer end face that connects to the mounting surface and is exposed from the outer surface, The semiconductor device according to claim 11, wherein the covering layer covers the mounting surface and the second outer end surface.

14. The direction in which the second outer end face faces is the same as the direction in which the side surface faces. The semiconductor device according to claim 13, wherein the second outer end face faces the opposite side to the side face.

15. The semiconductor device according to claim 14, wherein the area of ​​the second outer end face is larger than the area of ​​the first outer end face.

16. A fourth lead located adjacent to the first lead in a direction perpendicular to the thickness direction, The present invention further comprises a second semiconductor element mounted on the fourth lead and electrically connected to the third lead, The sealing resin covers a portion of the fourth lead and the second semiconductor element. The recess is also located between the first lead and the fourth lead. The semiconductor device according to any one of claims 1 to 9, wherein the first lead and the fourth lead have the inward end faces.

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