An injection process to mitigate wafer warping introduced by the splitting process.
Implantation of cleavage and non-cleavage ions into crystalline substrates to form separation and relaxation layers addresses wafer warping, enabling efficient separation and cost reduction in semiconductor manufacturing.
Patent Information
- Authority / Receiving Office
- JP · JP
- Patent Type
- Patents
- Current Assignee / Owner
- II VI DELAWARE INC
- Filing Date
- 2025-01-10
- Publication Date
- 2026-07-01
AI Technical Summary
Wafer splitting from crystalline substrates like silicon carbide can cause warping, complicating subsequent process integration steps and increasing manufacturing costs.
Implantation of cleavage and non-cleavage ion species into the crystalline substrate from different surfaces to create a separation and relaxation layer, followed by thermal energy application to separate the wafer, mitigating warping through stress cancellation.
Reduces wafer warping significantly, allowing for efficient separation and subsequent processing, thereby reducing manufacturing costs and improving yield.
Smart Images
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Abstract
Description
[Technical Field]
[0001] Claim of priority
[0001] This patent application claims priority and benefit of U.S. Provisional Patent Application No. 63 / 620,479, filed on 12 January 2024, which is incorporated herein by reference in its entirety. [Background technology]
[0002]
[0002] Crystalline substrates, such as silicon carbide (SiC) substrates, can account for a large portion of the overall manufacturing cost of semiconductor devices. One option to reduce such costs is to split wafers from the crystalline substrate and manufacture semiconductor devices from the wafers split from the crystalline substrate. Further wafer splitting can be performed from the crystalline substrate, and even more semiconductor devices can be manufactured from such wafers. In this way, the costs associated with a single crystal substrate can be distributed across more semiconductor devices, thereby reducing the average manufacturing cost of semiconductor devices. While wafer splitting can potentially improve the device yield from a single substrate, wafer splitting can cause wafer warping (curvature of the surface). Such warping can further complicate subsequent process integration steps. [Overview of the Initiative]
[0003]
[0003] A process for mitigating the warping of a wafer separated from a crystalline substrate is illustrated and / or described in relation to at least one of the drawings and more fully described in the claims.
[0004]
[0004] Details of these and other advantages, aspects and novel features of the present disclosure, as well as of the exemplary embodiments thereof, will be better understood from the following description and drawings.
[0005] The various features and advantages of this disclosure can be more readily understood by referring to the following detailed description in conjunction with the attached drawings, in which similar reference numbers indicate similar structural elements. [Brief explanation of the drawing]
[0005] [Figure 1]
[0006] Figure 1 is a flowchart of a process for mitigating substrate warping according to various aspects of this disclosure. [Figure 2]
[0007] Figure 2 shows cross-sectional views of the substrate at various stages of the process shown in Figure 1. [Figure 3]
[0008] Figure 3 is a graph showing the relationship between ion species vacancies and depth for each injection energy and input amount. [Modes for carrying out the invention]
[0006]
[0009] The following discussion provides various examples of mitigating warping of substrates and / or wafers separated from such substrates. Such examples are non-limiting, and the appended claims should not be limited to the specific examples disclosed. In the following discussion, the terms “example” and “for example” are not limiting.
[0007]
[0010] The figures illustrate general configurations, and descriptions and details of well-known features and techniques may be omitted to avoid unnecessarily obscuring this disclosure. In addition, elements in the drawings are not necessarily drawn to scale. For example, the dimensions of some elements in the figures may be exaggerated compared to others to aid in a better understanding of the examples discussed in this disclosure. The same reference number in different figures indicates the same element.
[0008]
[0011] The term "and / or" means any one or more items in the list joined by "and / or". For example, "x and / or y" means any element of the three-element set {(x),(y),(x,y)}. Another example is "x,y and / or z" meaning any element of the seven-element set {(x),(y),(z),(x,y),(x,z),(y,z),(x,y,z)}.
[0009]
[0012] The terms “equipped,” “equipped,” “included,” and / or “contained” are “unrestricted” terms that specify the presence of the described feature but do not exclude the presence or addition of one or more other features.
[0010]
[0013] Terms such as “first,” “second,” etc., may be used in this specification to describe various elements, but these elements should not be limited by these terms. These terms are simply used to distinguish one element from another. Thus, for example, the first element discussed in this disclosure may be referred to as the second element without departing from the teachings of this disclosure.
[0011]
[0014] Unless otherwise specified, the term “combined” can be used to describe two elements that are in direct contact with each other, or two elements that are indirectly connected by one or more other elements. For example, when element A is combined with element B, element A can be in direct contact with element B, or it can be indirectly connected to element B by an intervening element C. Similarly, the terms “above” or “on top” can be used to describe two elements that are in direct contact with each other, or two elements that are indirectly connected by one or more other elements.
[0012]
[0015] Generally, aspects of this disclosure relate to processes for mitigating warpage of wafers or films separated from a crystalline substrate. In some embodiments, the process can implant cleavage ion species into the crystalline substrate from a first surface to a first depth. The implantation of cleavage ion species can cause warpage of the crystalline substrate and / or the attached wafer. To mitigate such warpage, the process can implant non-cleavage ion species into the crystalline substrate from a second surface to a second depth.
[0013]
[0016] Next, a process 100 for mitigating the warping of a wafer separated from a crystalline substrate is illustrated, with reference to Figures 1 and 2. Process 100 is illustrated and described below in relation to separating a silicon carbide (SiC) wafer or film from a silicon carbide substrate, but process 100 can be used to form crystalline wafers or films from crystalline substrate materials other than silicon carbide.
[0014]
[0017] In step 110, process 100 can prepare a silicon carbide substrate 10 for ion implantation. The silicon carbide substrate 10 may have a single-crystal structure defining a substrate top surface 12, a substrate bottom surface 14, and a substrate side surface 16 between the substrate top surface 12 and the substrate bottom surface 14. The single-crystal structure of the silicon carbide substrate 10 may represent one of many silicon carbide polymorphs, such as 3C-SiC, 4C-SiC, or 6H-SiC. Furthermore, the substrate top surface 12 may correspond to the Si plane of the silicon carbide substrate 10, and the substrate bottom surface 14 may correspond to the C plane of the silicon carbide substrate 10. In step 110, surface defects in the single-crystal structure of the silicon carbide substrate 10 can be removed by polishing the substrate top surface 12, for example, by pre-separating the wafer from the silicon carbide substrate 10.
[0015]
[0018] Despite such preparations, the substrate surface 12 may not be perfectly flat. Figure 2 shows four exemplary wafers (i.e., wafer 1, wafer 2, wafer 3, and wafer 4). The initial warp of wafer 1 is -1.1 μm (i.e., slightly concave), the initial warp of wafer 2 is -1.03 μm (i.e., slightly concave), the initial warp of wafer 3 is 5.188 μm (i.e., slightly convex), and the initial warp of wafer 4 is 0.07 μm (i.e., slightly convex).
[0016]
[0019] In step 120, process 100 can generate a separation layer 20 from the substrate bottom surface 14 at a desired depth D1. To this end, cleavage ions 22 can be implanted through the C-plane or the substrate bottom surface 14 to the desired depth D1 in the silicon carbide substrate 10. Such implantation may damage the crystal structure of the silicon carbide substrate 10 (e.g., create bonding vacancies in the crystal structure). Depending on the crystal material of the substrate, various cleavage ion species can be implanted. In particular, in the case of silicon carbide, hydrogen (H) ions can be used as cleavage ions 22. The depth to which such hydrogen (H) ions are implanted into the substrate bottom surface 14 depends on the implantation energy. See Figures 2 and 3. Furthermore, the amount of damage (e.g., vacancies created) may depend on the amount of hydrogen (H) ions implanted, i.e., the input amount.
[0017]
[0020] As shown in Figure 2, the hydrogen (H) ion concentration in the illustrated embodiment is 8e16 ions / cm³. 2 With this injection amount, an injection energy of 150 kiloelectron volts (keV) can be used for the injection. However, as mentioned above, the injection energy controls the injection depth, and the injection amount controls the amount of damage or vacancies introduced into the crystal structure. Therefore, the above values are merely illustrative. In other embodiments, these values can be adjusted based on the desired injection depth, the ion species to be injected, the crystal material to be injected, and so on.
[0018]
[0021] As shown in FIG. 3, the vacancies generated from the implanted ions are distributed over a range of depths rather than simply at a single depth. In particular, FIG. 3 shows hydrogen (H) ions implanted at a dose of 8e16 ions / cm 2 at an implantation energy of 150 keV. Due to such implantation of hydrogen (H) ions, the peak concentration implantation depth is approximately 6400 Å and the number of vacancies is approximately 1.6e22 / cm 3 .
[0019]
[0022] Furthermore, as shown in FIG. 2, due to the formation of the separation layer 20, the crystal structure of the silicon carbide substrate 10 is stressed and the upper surface 12 of the substrate may warp. In the example of FIG. 2, hydrogen (H) ions are implanted at a dose of 8e16 ions / cm 2 at an implantation energy of 150 keV, and each wafer 1, 2, 3, 4 may exhibit a warp exceeding -350 μm (i.e., significantly convex).
[0020]
[0023] At 130, the process 100 can form a relaxation layer 30 from the upper surface 12 of the substrate to a desired depth D2. For this purpose, non-split ions 32 can be implanted through the Si surface or the upper surface 12 of the substrate to a desired depth D2 of the silicon carbide substrate 10. Such implantation may damage the crystal structure of the silicon carbide substrate 10 (e.g., generate bonding vacancies in the crystal structure). Depending on the crystal material of the substrate, various non-split ion species can be implanted. In particular, in the case of silicon carbide, helium (He) ions can be used as the non-split ions 32. The depth at which such helium (He) ions are implanted into the upper surface 12 of the substrate depends on the implantation energy. See FIGS. 2 and 3. Furthermore, the amount of damage (e.g., the generated vacancies) can depend on the amount of helium (He) ions implanted, i.e., the dose.
[0021]
[0024] As shown in FIG. 2, the process 100 uses a dose of 6e15 ions / cm 2 at an implantation energy of 180 keV to implant helium (He) ions into wafer 1, and at an implantation energy of 180 keV and 1e16 ions / cm2 Using the input amount of 2 , helium (He) ions can be implanted into wafer 2. Further, process 100 uses an implantation energy of 280 keV and an input amount of 1e15 ions / cm 2 to implant helium (He) ions into wafer 3, and an implantation energy of 280 keV and an input amount of 6e15 ions / cm 2 to implant helium (He) ions into wafer 4. As described above, the implantation energy controls the depth of implantation, and the input amount controls the amount of damage or the amount of vacancies introduced into the crystal structure. Therefore, the above values are merely examples of a specific embodiment. Further, these values are selected at least in part based on the amount of warping counteracted by relaxation layer 30.
[0022]
[0025] As shown in FIG. 3, the vacancies generated from the implanted ions do not simply distribute at a single depth, but over a range of depths. In particular, FIG. 3 shows helium (He) ions implanted at an implantation energy of 180 keV and an input amount of 6e15 ions / cm 2 and helium (He) ions implanted at an implantation energy of 280 keV and an input amount of 6e15 ions / cm 2 . As shown, for the implantation at 180 keV, the peak concentration implantation depth is about 6400 Å and the number of vacancies is approximately 1.5e22 / cm 3 , and for the implantation at 280 keV, the peak concentration implantation depth is about 8400 Å and the number of vacancies is about 1.5e22 / cm 3 .
[0023]
[0026] Further, as shown in FIG. 2, the generation of relaxation layer 30 subjects the crystal structure of silicon carbide substrate 10 to stress and can cancel out the stress introduced by separation layer 20. In particular, the relaxation layer 30 generated above can reduce the warping of wafer 1 from more than -350 μm to -22.1 μm, the warping of wafer 2 from more than -350 μm to -66.59 μm, the warping of wafer 3 from more than -350 μm to -17.75 μm, and the warping of wafer 4 from more than -350 μm to -39.5 μm.
[0024]
[0027] After generating the relaxation layer 30, process 100 can separate the wafer 18 from the silicon carbide substrate 10 in step 140. To do this, process 100 applies thermal energy to the silicon carbide substrate 10 to coalesce the vacancies or bubbles in the separation layer 20, thereby separating the wafer 18 from the silicon carbide substrate 10. In particular, the amount of energy required to coalesce the vacancies in the separation layer 20 is far less than the amount of energy required to coalesce the vacancies in the relaxation layer 30. This energy difference is due to the ion species selected to generate the separation layer 20 and the relaxation layer 30. For example, in the above example, hydrogen (H) ions are considered to be the cleavage ion species for the silicon carbide substrate 10 because only a small amount of energy (e.g., 0.35 keV) is required to coalesce each bubble and separate the wafer 18 from the silicon carbide substrate 10. Conversely, helium (He) ions are considered non-cleaving ionic species for the silicon carbide substrate 10 because a large amount of energy (e.g., 2.40 keV) is required to coalesce each bubble. Due to this gap in the energy required to induce separation, process 100 can apply enough energy (e.g., heat) to the silicon carbide substrate 10 along the separation layer 20 to separate the wafer 18 from the silicon carbide substrate 10, but not enough to further separate it along the relaxation layer 30.
[0025]
[0028] In step 150, process 100 can output a silicon carbide wafer or film by finishing the separated wafer 18. In particular, process 100 can polish and / or etch the wafer 18 to remove any residue from the separation layer 20. Such polishing and / or etching can also remove and / or reduce defects introduced during the separation of the silicon carbide wafer 18 from the silicon carbide substrate 10.
[0026]
[0029] Furthermore, process 100 can be repeated on the same silicon carbide substrate. In this way, multiple silicon carbide wafers 18 can be obtained from a single silicon carbide substrate 10.
[0027]
[0030] This disclosure includes references to specific examples, but it will be understood by those skilled in the art that various modifications and substitutions can be made without departing from the scope of this disclosure. In addition, modifications can be made to the disclosed examples without departing from the scope of this disclosure. Therefore, this disclosure is not limited to the disclosed examples, and is intended to include all examples included in the appended claims.
Claims
1. A method for forming a wafer, The steps include providing a crystalline substrate including a first surface of the substrate and a second surface of the substrate opposite to the first surface of the substrate, The steps include generating a separation layer from the first surface of the substrate to a first depth, A step of generating a relaxation layer from the second surface of the substrate to a second depth, A step of separating the wafer from the crystal substrate along the separation layer. Includes, The step of generating the separation layer includes the step of implanting cleavage ions into the crystal substrate, The step of generating the relaxation layer includes the step of implanting non-cleaved ions into the crystal substrate, The cleaving ion is an ion that requires less energy than the non-cleaving ion to coalesce the vacancies or bubbles created in the substrate by the implantation of the ion. method.
2. The method according to Claim 1, wherein the cleaving ion is a hydrogen ion and the non-cleaving ion is a helium ion.
3. A method according to claim 1 or 2, The step of generating the separation layer involves bending the crystal substrate, The step of generating the relaxation layer reduces the warping of the crystal substrate. method.
4. A method according to claim 1 or 2, The step of generating the separation layer includes the step of implanting cleavage ions into the crystalline substrate through the first surface of the substrate, The step of generating the relaxation layer includes implanting non-cleaved ions into the crystalline substrate via the second surface of the substrate. method.
5. A method according to claim 1, wherein the step of generating the separation layer includes the step of implanting hydrogen ions into the crystal substrate.
6. A method according to claim 1, wherein the step of generating the relaxation layer includes the step of implanting helium ions into the crystal substrate.
7. A method according to claim 1 or 2, wherein the step of separating the wafer from the crystal substrate includes the step of applying a level of thermal energy sufficient to coalesce the voids in the separation layer.
8. A method according to claim 7, wherein the level of thermal energy is insufficient to coalesce the voids in the relaxation layer.
9. A method according to claim 1 or 2, comprising the step of removing the residue of the separation layer from the wafer.
10. A method according to claim 1 or 2, comprising the step of separating the wafer from the crystal substrate, and then reusing the crystal substrate to form another wafer.
11. A method for forming a silicon carbide wafer, The steps include providing a silicon carbide substrate including a Si surface and a C surface, The steps include: implanting cleavage ion species into the C-plane of the silicon carbide substrate to form a separation layer; The steps include: implanting non-cleaving ion species into the Si surface of the silicon carbide substrate to form a relaxation layer that cancels out the warping of the silicon carbide substrate; The steps include separating the silicon carbide wafer from the silicon carbide substrate along the separation layer, and A method comprising the above, wherein the cleaving ion species is an ion species that requires less energy than the non-cleaving ion species to coalesce the vacancies or bubbles generated in the substrate by the implantation of the ion species.
12. The method according to claim 11, wherein the cleaving ion species is a hydrogen ion and the non-cleaving ion species is a helium ion.
13. A method according to claim 11 or 12, wherein the step of implanting the cleavage ion species contributes to the warping of the silicon carbide substrate.
14. A method according to claim 11 or 12, The step of implanting the cleavage ion species involves forming the separation layer to a first depth from the C-plane of the silicon carbide substrate. The step of implanting the non-cleaving ion species involves forming the relaxation layer to a second depth from the Si surface of the silicon carbide substrate. method.
15. A method according to claim 11 or 12, wherein the step of implanting the non-cleaving ion species comprises forming the relaxation layer between the Si surface of the silicon carbide substrate and the separation layer.
16. A method according to claim 11, wherein the step of implanting the cleavage ion species includes the step of implanting hydrogen ions into the silicon carbide substrate.
17. A method according to claim 11, wherein the step of implanting a non-cleaving ion species includes the step of implanting helium ions into the silicon carbide substrate.
18. A method according to claim 11 or 12, wherein the step of separating the silicon carbide wafer from the silicon carbide substrate includes the step of applying energy at a level sufficient to coalesce the vacancies in the separation layer.
19. A method according to claim 18, wherein the level of energy is insufficient to coalesce the vacancies in the relaxation layer.
20. A method according to claim 11 or 12, comprising the step of removing the residue of the separation layer from the silicon carbide wafer.
21. A method according to claim 11 or 12, comprising the step of separating the silicon carbide wafer from the silicon carbide substrate, and then reusing the silicon carbide substrate to form another silicon carbide wafer.