Semiconductor device and method for manufacturing the same
The semiconductor device design addresses non-uniform temperature distribution by strategically arranging gates, sources, and through-holes, achieving improved temperature uniformity and output power in gallium nitride semiconductor devices.
Patent Information
- Authority / Receiving Office
- JP · JP
- Patent Type
- Patents
- Current Assignee / Owner
- DYNAX SEMICON
- Filing Date
- 2023-12-20
- Publication Date
- 2026-07-01
AI Technical Summary
Existing gallium nitride semiconductor devices face challenges in uniformly distributing temperature, leading to increased heat generation and reduced output power and reliability due to non-uniform temperature distribution and mutual heating effects between gates.
The semiconductor device design includes specific arrangements of gates, sources, and through-holes, with controlled temperature differences and thermal conductivity variations to ensure uniform temperature distribution, reducing mutual heating and improving high-frequency performance.
The solution achieves a more uniform temperature distribution, reducing heat loss and enhancing output power by balancing temperature differences between gates, thereby improving the device's high-frequency performance and reliability.
Smart Images
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Abstract
Description
Technical Field
[0001] Embodiments of the present invention relate to the technical field of semiconductors, and in particular, to semiconductor devices and manufacturing methods thereof.
Background Art
[0002] Gallium nitride (GaN) semiconductor devices have remarkable advantages such as a large bandgap, high electron mobility, high breakdown electric field strength, and high heat resistance. Compared with the first-generation silicon semiconductors and the second-generation gallium arsenide semiconductors, they are more suitable for the manufacture of high-temperature, high-pressure, high-frequency, and high-power electronic devices, and are expected to have a wide range of applications. They can be widely applied in the RF and microwave fields and the power electronics field, and are already being actively researched in the current semiconductor industry.
[0003] Currently, for 5G communication, the requirements for the bandwidth and operating frequency of semiconductor chips are increasing. The high electron mobility transistor of gallium nitride is a high electron mobility device formed by two-dimensional electron gas in the AlGaN / GaN heterojunction. Because of its excellent compatibility in the fields of high frequency, high voltage, and high power, it has attracted great attention in the 5G communication field.
[0004] In a gallium nitride high-frequency power amplifier, improving the power and high-frequency performance of the device has always been an issue pursued by gallium nitride high-frequency chips. However, in the design and use of semiconductor devices, there are various factors that affect the output power, high-frequency performance, and reliability of the device. For example, if the temperature distribution in the device is non-uniform, the heat generation of the device will increase and the reliability will decrease, and further, it will affect the output power and reliability of the device. Therefore, in the design process of semiconductor devices, how to evenly distribute the temperature of the semiconductor device has become a very important technology.
Summary of the Invention
Problems to be Solved by the Invention
[0005] In view of this, embodiments of the present invention provide a semiconductor device and a method for manufacturing the same, which can uniformly distribute the temperature of the semiconductor device, reduce the attenuation of the high-frequency performance of the device, and improve the output power. [Means for solving the problem]
[0006] In a first embodiment, the present invention provides a semiconductor device. This semiconductor device includes a substrate, an epitaxial structure located on one side of the substrate, and a plurality of gates located on one side of the epitaxial structure away from the substrate. The gates extend along a first direction. The plurality of gates are arranged along a second direction. The first and second directions intersect and are both parallel to the plane on which the substrate is located. The plurality of gates include a first gate and a second gate. Along the second direction, the first gate is located on one side of the second gate that is close to the edge of the semiconductor device. The maximum temperature of the first gate is T1, the maximum temperature of the second gate is T2, and (T2 - T1) / T1 ≤ 20%.
[0007] Selectively, the semiconductor device further includes a plurality of sources located on one side of the epitaxial structure away from the substrate. The sources extend along the first direction. The plurality of sources are arranged along the second direction.
[0008] The plurality of sources include a first source and a second source. Along the second direction, the first source is positioned adjacent to the first gate, the second source is positioned adjacent to the second gate, and the first source is located on one side of the second source closer to the edge of the semiconductor device. The semiconductor device further includes through holes penetrating the substrate and the epitaxial structure. The through holes include first type through holes and second type through holes. Along the thickness direction of the semiconductor device, the first source overlaps with the first type through holes, and the second source overlaps with the second type through holes. The first type through holes have a larger total opening area than the second type through holes.
[0009] Selectively, the first type of through-hole includes at least one first through-hole. The second type of through-hole includes at least one second through-hole. The first through-hole has a larger opening area than the second through-hole.
[0010] Selectively, along the second direction, the first through-hole is located on one side of either of the other through-holes, closer to the edge of the semiconductor device, and the second through-hole is located on one side of either of the other through-holes, closer to the center of the semiconductor device. The opening area of the through-holes gradually decreases along the direction from the first through-hole to the second through-hole.
[0011] Selectively, along the second direction, the first through-hole is located on one side of either of the other through-holes, closer to the edge of the semiconductor device, and the second through-hole is located on one side of either of the other through-holes, closer to the center of the semiconductor device. The opening area of the first through-hole is S1, and the opening area of the second through-hole is S2, and S2 <S1≦4*S2である。
[0012] Selectively, the first type of through hole includes at least two first through holes. The second type of through hole includes at least one second through hole. The number of first through holes is greater than the number of second through holes.
[0013] Selectively, along the second direction, the first through-hole is located on one side of either of the other through-holes, closer to the edge of the semiconductor device, and the second through-hole is located on one side of either of the other through-holes, closer to the center of the semiconductor device. The number of through-holes gradually decreases along the direction from the first through-hole to the second through-hole.
[0014] Selectively, along the second direction, the first through-hole is located on one side of either of the other through-holes, closer to the edge of the semiconductor device, and the second through-hole is located on one side of either of the other through-holes, closer to the center of the semiconductor device. The number of first through-holes of the first type is n1, the number of second through-holes of the second type is n2, and (n1-n2)≦5.
[0015] Selectively, the semiconductor device further includes a plurality of sources located on one side of the epitaxial structure away from the substrate. The sources extend along the first direction. The plurality of sources are arranged along the second direction. The plurality of sources include a first source and a second source. Along the second direction, the first source is located adjacent to the first gate, the second source is located adjacent to the second gate, and the first source is located on one side of the second source closer to the edge of the semiconductor device. The semiconductor device further includes through holes penetrating the substrate and the epitaxial structure. The through holes include a first type of through hole and a second type of through hole. Along the thickness direction of the semiconductor device, the first source overlaps with the first type of through hole, and the second source overlaps with the second type of through hole. Along the first direction, the center of the first type of through hole is located on one side of the center of the second type of through hole closer to the center of the semiconductor device.
[0016] Selectively, there is a gate spacing between two adjacent gates along the second direction. The plurality of gate spacings include a first gate spacing closer to the edge of the semiconductor device along the second direction, and a second gate spacing further away from the edge of the semiconductor device than the first gate spacing. Along the second direction, the first gate spacing is narrower than the second gate spacing.
[0017] Selectively, the second gate spacing is located on one side of any of the other gate spacings that is closer to the center of the semiconductor device, and the gate spacing gradually increases along the side from the first gate spacing toward the second gate spacing.
[0018] In a second embodiment, the present invention further provides a method for manufacturing a semiconductor device. The manufacturing method includes providing a substrate, forming an epitaxial structure on one side of the substrate, and forming a plurality of gates on one side of the epitaxial structure away from the substrate. The gates extend along a first direction. The plurality of gates are arranged along a second direction. The first and second directions intersect each other and are both parallel to the plane on which the substrate is located. The plurality of gates include a first gate and a second gate. Along the second direction, the first gate is located on one side of the second gate that is close to the edge of the semiconductor device. The maximum temperature of the first gate is T1, the maximum temperature of the second gate is T2, and (T2-T1) / T1 ≤ 20%.
[0019] In the semiconductor device according to an embodiment of the present invention, multiple gates are installed on one side away from the substrate of the epitaxial structure, and the first gate among the multiple gates is located on the side close to the edge of the semiconductor device of the second gate. The maximum temperature T1 of the first gate and the maximum temperature T2 of the second gate satisfy (T2 - T1) / T1 ≤ 20%, thereby ensuring a small temperature difference between the gates. This allows for a uniform temperature distribution of the semiconductor device, reducing attenuation of the high-frequency performance of the device and improving output power. [Brief explanation of the drawing]
[0020] [Figure 1] This is a schematic diagram of the structure of a semiconductor device according to an embodiment of the present invention. [Figure 2] This is a schematic cross-sectional diagram of the semiconductor device along the cross-sectional line A-A' in Figure 1. [Figure 3] This is a schematic cross-sectional diagram of the semiconductor device along the cross-sectional line B-B' in Figure 1. [Figure 4] This is a schematic diagram of the structure of another semiconductor device according to an embodiment of the present invention. [Figure 5] This is a schematic diagram of the structure of another semiconductor device according to an embodiment of the present invention. [Figure 6]It is a structural schematic diagram of another semiconductor device according to an embodiment of the present invention. [Figure 7] It is a structural schematic diagram of another semiconductor device according to an embodiment of the present invention. [Figure 8] It is a flowchart showing a method for manufacturing a semiconductor device according to an embodiment of the present invention.
Embodiments for Carrying Out the Invention
[0021] Hereinafter, the present invention will be described in more detail with reference to the drawings and embodiments. It should be understood that the specific embodiments described here are only for interpreting the present invention and are not limitations on the present invention. Also, for the convenience of explanation, only a part related to the present invention is shown in the drawings, and not all structures are shown.
[0022] FIG. 1 is a structural schematic diagram of a semiconductor device according to an embodiment of the present invention. As shown in FIG. 1, the semiconductor device includes a substrate 110, an epitaxial structure 120 located on one side of the substrate 110, and a plurality of gates 130 located on one side of the epitaxial structure 120 away from the substrate 110. The gates 130 extend along the first direction (the X direction shown in FIG. 1). The plurality of gates 130 are arranged along the second direction (the Y direction shown in FIG. 1). The first direction X and the second direction Y intersect and are both parallel to the plane where the substrate 110 is located. The plurality of gates 130 include a first gate 1301 and a second gate 1302. Along the second direction Y, the first gate 1301 is located on the side closer to the edge of the semiconductor device of the second gate 1302. The highest temperature of the first gate 1301 is T1, the highest temperature of the second gate 1302 is T2, and (T2 - T1) / T1 ≤ 20%.
[0023] Specifically, referring to Figure 1 again, the substrate 110 may be formed from one or more materials from among silicon, sapphire, silicon carbide, gallium arsenide, gallium nitride, diamond, or other materials suitable for the growth of gallium nitride. The epitaxial structure 120 is located on one side of the substrate 110 and may be formed from one or more materials from among III-V compound semiconductor materials, such as gallium arsenide, aluminum gallium arsenide, gallium nitride, aluminum gallium nitride, or indium gallium nitride.
[0024] Furthermore, among the multiple gates 130 located on one side of the epitaxial structure 120 away from the substrate 110, the first gate 1301 is located on the side closer to the edge of the semiconductor device than the second gate 1302. During operation of the semiconductor device, each gate 130 located in the active region self-heats, that is, each gate generates heat. In addition, the heat generated in each gate 130 diffuses to adjacent gates 130, that is, a mutual heating effect occurs between two adjacent gates 130. In other words, during normal operation of the semiconductor device, each gate 130 generates self-heat and mutual heating, and the temperature of each gate 130 is the sum of the temperatures generated by self-heating and mutual heating. Although the temperature difference between each gate 130 due to self-heating is small, the temperature of the first gate 1301 due to mutual heating decreases because the first gate 1301 is located on one side closer to the edge of the semiconductor device along the second direction Y, and the number of gates 130 adjacent to the first gate 1301 is small.
[0025] Specifically, by ensuring that the maximum temperature T1 of the first gate 1301 and the maximum temperature T2 of the second gate satisfy (T2 - T1) / T1 ≤ 20%, the temperature difference between the maximum temperature T1 of the first gate 1301 and the maximum temperature T2 of the second gate 1302, which are located on one side closer to the edge of the semiconductor device, can be reduced. This allows for a more uniform temperature distribution of the semiconductor device, reducing heat loss and improving the output power of the semiconductor device.
[0026] In the semiconductor device according to an embodiment of the present invention, multiple gates are installed on one side away from the substrate of the epitaxial structure, and the first gate among the multiple gates is located on the side close to the edge of the semiconductor device of the second gate. The maximum temperature T1 of the first gate 1301 and the maximum temperature T2 of the second gate satisfy (T2 - T1) / T1 ≤ 20%, thereby ensuring a small temperature difference between the gates. This allows for a uniform temperature distribution of the semiconductor device, reducing attenuation of high-frequency performance and improving output power.
[0027] Selectively referring to Figure 1 again, the maximum temperatures of any two adjacent gates 130 are approximately the same.
[0028] Specifically, by making the maximum temperatures of any two adjacent gates 130 approximate, it is possible to ensure a uniform temperature distribution in the semiconductor device and sufficiently reduce the attenuation of high-frequency performance.
[0029] Selectively, Figure 2 is a schematic cross-sectional view of the semiconductor device along the cross-sectional line A-A' in Figure 1. Referring to Figures 1 and 2, the semiconductor device further includes a plurality of sources 140 located on one side of the epitaxial structure 120 away from the substrate 110. The sources 140 extend along a first direction X. The plurality of sources 140 are arranged along a second direction Y. The plurality of sources 140 include a first source 1401 and a second source 1402. Along the second direction Y, the first source 1401 is located adjacent to the first gate 1301, the second source 1402 is located adjacent to the second gate 1302, and the first source 1401 is located on one side of the second source 1402 closer to the semiconductor edge. The semiconductor device further includes through holes 150 penetrating the substrate 110 and the epitaxial structure 120. The through-hole 150 includes a first-type through-hole 1501 and a second-type through-hole 1502. Along the thickness direction of the semiconductor device (the Z-direction shown in Figure 2), the first source 1401 overlaps with the first-type through-hole 1501, and the second source 1402 overlaps with the second-type through-hole 1502. The first-type through-hole 1501 has a larger total opening area than the second-type through-hole.
[0030] Specifically, the source 140 is connected to the back of the semiconductor device by a through-hole 150. For example, the through-hole 150 may penetrate the substrate 110 and the epitaxial structure 120, and be connected to the source 140 by a source signal input electrode D located on one side of the substrate 110 away from the epitaxial structure 120. In other words, the source 140 is electrically connected to the source signal input electrode D by the through-hole 150. For example, when the substrate 110 and the epitaxial structure 120 are formed in sequence, the source signal input electrode D can be electrically connected to the source 140 by drilling holes and filling the holes in the substrate 110 and the epitaxial structure 120 of each layer with a metal connecting material.
[0031] Furthermore, since the through-hole 150 penetrates both the substrate 110 and the epitaxial structure 120, and therefore the thermal conductivity of the through-hole 150 is lower than that of the substrate 110, the temperature of the through-hole 150 will be higher. Also, as the area of the through-hole 150 increases, the thermal conductivity decreases and the temperature becomes even higher.
[0032] Furthermore, the through-hole 150 includes a first-type through-hole 1501 and a second-type through-hole 1502. The first-type through-hole 1501 has a larger total opening area than the second-type through-hole 1502. That is, the product of the number of first-type through-holes 1501 and the area of one first-type through-hole 1501 is greater than the product of the number of second-type through-holes 1502 and the area of one second-type through-hole 1502. This balances the temperature between the first gate 1301 and the second gate 1302, meaning that the temperature at the first-type through-hole 1501 is higher than the temperature at the second-type through-hole 1502, thus offsetting the small mutual heat generation effect at the first gate 1301. This ensures a small temperature difference between the first gate 1301 and the second gate 1302, resulting in a uniform temperature distribution in the semiconductor device.
[0033] Selectively, Figure 3 is a schematic cross-sectional diagram of the semiconductor device along the cross-sectional line B-B' in Figure 1. Referring to Figures 1 to 3, the first type of through-hole 1501 includes at least one first through-hole 15011, and the second type of through-hole 1502 includes at least one second through-hole 15022. The opening area of the first through-hole 15011 is larger than the opening area of the second through-hole 15022.
[0034] Specifically, the opening area of the first through-hole 15011 is larger than the opening area of the second through-hole 15022. That is, because the opening area of the first through-hole 15011 is larger than that of the second through-hole 15022, the total opening area of the first type through-hole 1501, which consists of at least one first through-hole 15011, is large, ensuring that the heat dissipation of the first type through-hole 1501 is small and the temperature is high. This can offset the small mutual heat generation effect of the first gate 1301, allowing for a uniform temperature distribution of the semiconductor device, reducing attenuation of the device's high-frequency performance, and improving output power.
[0035] Selectively, Figure 4 is a schematic diagram of the structure of another semiconductor device according to an embodiment of the present invention. As shown in Figure 4, along the second direction Y, the first through-hole 15011 is located on one side closer to the edge of the semiconductor device than any of the other through-holes 150, and the second through-hole 15022 is located on one side closer to the center of the semiconductor device than any of the other through-holes 150. The opening area of the through-holes 150 gradually decreases along the direction from the first through-hole 15011 to the second through-hole 15022.
[0036] For example, the fact that the first through-hole 15011 may be located on one side closer to the edge of the semiconductor device can be understood as the first through-hole being located on both sides of the semiconductor device along the second direction Y, while being close to the edge of the semiconductor device. The fact that the second through-hole 15022 is located on one side closer to the center of the semiconductor device than any of the other through-holes 150 can be understood as the second through-hole 15022 covering the center of the semiconductor device, or the distance between the second through-hole 15022 and the center of the semiconductor device being shorter than
[0037] Specifically, the opening area of the through hole 150 gradually decreases along the direction from the first through hole 15011 to the second through hole 15022, that is, it gradually decreases from both sides of the second direction Y along the second direction Y towards the center of the semiconductor device. That is, since the opening area of the first through hole 15011 is larger than that of the second through hole 15022, less heat dissipation of the first through hole 15011 can be ensured, the mutual heating effect of the first gate 1301 can be offset, and the temperature difference between the first gate 1301 and the second gate 1302 can be ensured to be small. Thereby, the temperature of the semiconductor device can be evenly distributed, the attenuation of the high-frequency performance of the device can be reduced, and the output power can be improved.
[0038] Selectively, continuing to refer to FIG. 1, along the second direction Y, the first through hole 15011 is located on the side closer to the edge of the semiconductor device than any of the other through holes 150, and the second through hole 15022 is located on the side closer to the center of the semiconductor device than any of the other through holes 150. The opening area of the first through hole 15011 is S1, the opening area of the second through hole 15022 is S2, and S2 < S1 ≤ 4 * S2.
[0039] Specifically, by satisfying S2 < S1 ≤ 4 * S2 for the opening area S1 of the first through hole 15011 and the opening area S2 of the second through hole 15022, not only the heat dissipation of the first through hole 15011 is reduced, but it can also be avoided that the opening area of the first through hole 15011 is too large and affects the normal heat dissipation of the semiconductor device, and it can also be ensured that the formation of the through hole meets the process requirements.
[0040] Selectively, FIG. 5 is a structural schematic diagram of another semiconductor device according to an embodiment of the present invention. As shown in FIG. 5, the first type of through hole 1501 includes at least two first through holes 15011, and the second type of through hole 1502 includes at least one second through hole 15022. The number of the first through holes 15011 is larger than that of the second through holes 15022.
[0041] Specifically, the number of first through-holes 15011 is greater than the number of second through-holes 15022. By increasing the number of first through-holes 15011, the temperature difference between the first gate 1301 and the second gate 1302 can be balanced, ensuring that the temperature at the first through-holes 15011 is higher, offsetting the small amount of mutual heat generation at the first gate 1301. This allows for a uniform temperature distribution of the semiconductor device, reducing the attenuation of the device's high-frequency performance and improving output power.
[0042] Selectively, Figure 6 is a schematic diagram of the structure of another semiconductor device according to an embodiment of the present invention. As shown in Figure 6, along the second direction Y, the first through-hole 15011 is located on one side closer to the edge of the semiconductor device than any of the other through-holes 150, and the second through-hole 15022 is located on one side closer to the center of the semiconductor device than any of the other through-holes 150. The number of through-holes 150 gradually decreases along the direction from the first through-hole 15011 to the second through-hole 15022.
[0043] Specifically, the number of through-holes 150 gradually decreases along the direction from the first through-hole 15011 to the second through-hole 15022. By increasing the number of first through-holes 15011, the temperature at the first through-holes 15011 is increased, ensuring that the small amount of mutual heat generation at the first gate 1301 is offset. This allows for a uniform temperature distribution of the semiconductor device, reduces heat loss in the device, and simplifies the through-hole formation process.
[0044] Selectively referring to Figure 5, along the second direction Y, the first through-hole 15011 is located on one side closer to the edge of the semiconductor device than any of the other through-holes 150, and the second through-hole 15022 is located on one side closer to the center of the semiconductor device than any of the other through-holes 150. The quantity of the first through-hole 15011 among the first type of through-hole 1501 is n1, and the quantity of the second through-hole 15022 among the second type of through-hole 1502 is n2, where n1-n2≦5.
[0045] Specifically, by ensuring that the number of first through-holes 15011 (n1) and the number of second through-holes 15022 (n2) satisfy (n1-n2) ≤ 5, it is possible to secure a larger number of first through-holes 15011 compared to the number of second through-holes 15022. In other words, the temperature difference between the first gate 1301 and the second gate 1302 can be balanced. Furthermore, heat dissipation of the entire semiconductor device can be ensured, avoiding the impact of an excessive number of through-holes on the overall heat dissipation of the semiconductor device, and ensuring the normal operation of the semiconductor device. In addition, the through-hole formation process can be simplified, avoiding the increased difficulty of the semiconductor device process due to an excessive number of through-holes.
[0046] Selectively referring to Figure 1 again, the semiconductor device further includes a plurality of sources 140 located on one side of the epitaxial structure 120 away from the substrate 110. The sources 140 extend along a first direction X. The plurality of sources 140 are arranged along a second direction Y. The plurality of sources 140 include a first source 1401 and a second source 1402. Along the second direction Y, the first source 1401 is located adjacent to a first gate 1301, the second source 1402 is located adjacent to a second gate 1302, and the first source 1401 is located on one side of the second source 1402 closer to the edge of the semiconductor device. The semiconductor device further includes through holes 150 penetrating the substrate 110 and the epitaxial structure 120. The through holes 150 include a first type of through hole 1501 and a second type of through hole 1502. Along the thickness direction Z of the semiconductor device, the first source 1401 overlaps with the first type through hole 1501, and the second source 1402 overlaps with the second type through hole 1502. Along the first direction X, the center of the first type through hole 1501 is located on one side of the center of the second type through hole 1502, closer to the center of the semiconductor device.
[0047] Furthermore, during the operation of the semiconductor device, a significant amount of heat is generated towards the center of the semiconductor device in the first direction X, resulting in a high temperature. Specifically, by positioning the center of the first type through-hole 1501 closer to the center of the semiconductor device than the center of the second type through-hole 1502 along the first direction X, a high temperature can be maintained at the first through-hole 15011. This cancels out the small mutual heat generation effect of the first gate 1301, balances the temperature difference between the first gate 1301 and the second gate 1302, and reduces the attenuation of high-frequency performance.
[0048] Selectively referring to Figure 1 again, there is a gate spacing along the second direction Y between two adjacent gates 130. The multiple gate spacings include a first gate spacing d1 located closer to the edge of the semiconductor device along the second direction Y, and a second gate spacing d2 located on one side away from the edge of the semiconductor device relative to the first gate spacing d1. Along the second direction Y, the first gate spacing d1 is narrower than the second gate spacing d2.
[0049] Furthermore, the larger the gate spacing between two adjacent gates 130, the less thermal influence there is between them. Specifically, in the second direction Y, the first gate spacing d1 is narrower than the second gate spacing d2; that is, the first gate spacing d1 closer to the edge of the semiconductor device is narrower, resulting in greater thermal influence. To balance the thermal difference between the first gate 1301 and the second gate 1302, the temperature difference between the first gate 1301 and the second gate 1302 can be reduced by making the first gate spacing d1 narrower than the second gate spacing d2 along the second direction Y. This allows for a more uniform temperature distribution in the semiconductor device, reducing the attenuation of the device's high-frequency performance and improving output power.
[0050] Selectively, Figure 7 is a schematic diagram of the structure of another semiconductor device according to an embodiment of the present invention. As shown in Figure 7, the second gate spacing d2 is located on one side closer to the center of any other gate spacing semiconductor device. The gate spacing gradually increases along the side from the first gate spacing d1 toward the second gate spacing d2.
[0051] Specifically, referring continuously to FIG. 7, the gate pitch between the first gate 1301 and the second gate 1302 adjacent thereto is d1, the gate pitches between two adjacent second gates 1302 are d21 and d2, respectively, and d1 < d21 < d2. That is, the gate pitch gradually increases along the side toward the second gate pitch d2 from the first gate pitch d1, and the maximum gate pitch is at the central position of the semiconductor device, which is advantageous for reducing the mutual heat generation effect of the second gates 1302. Further, by gradually decreasing the gate pitch in the direction away from the central position of the semiconductor device from this central position, the difference in thermal interaction between the first gate 1301 and the second gate 1302 can be balanced, and the temperature at the center of the semiconductor device can be lowered. Thereby, the temperature of the semiconductor device can be uniformly distributed, and the heat loss of the device can be reduced.
[0052] Furthermore, the embodiment of the present invention improves the output power of a semiconductor device by adjusting the angle of the structural design of the semiconductor device. The semiconductor device may include, but is not limited to, high-power gallium nitride high-electron-mobility transistors (HEMTs) operating in high-voltage, high-current environments, silicon-on-insulator (SOI) transistors, gallium arsenide (GaAs)-based transistors, metal-oxide-semiconductor field-effect transistors (MOSFETs), metal-insulating semiconductor field-effect transistors (MISFETs), double heterojunction field-effect transistors (DHFETs), junction field-effect transistors (JFETs), metal-semiconductor field-effect transistors (MESFETs), metal-insulating semiconductor heterojunction field-effect transistors (MISHFETs), or other field-effect transistors.
[0053] Based on the same inventive concept, embodiments of the present invention further provide a method for manufacturing a semiconductor device. As shown in Figure 5, the method for manufacturing a semiconductor device according to embodiments of the present invention includes the following steps.
[0054] S101: Provides a circuit board.
[0055] For example, the substrate material may be Si, SiC, or sapphire, or other materials suitable for the growth of gallium nitride. The substrate manufacturing method may be atmospheric pressure chemical vapor deposition, sub-atmospheric pressure chemical vapor deposition, metal-organic compound chemical vapor deposition, reduced pressure chemical vapor deposition, high-density plasma chemical vapor deposition, ultra-high vacuum chemical vapor deposition, plasma-enhanced chemical vapor deposition, catalytic chemical vapor deposition, hybrid physicochemical vapor deposition, rapid thermochemical vapor deposition, vapor phase epitaxy, pulsed laser deposition, atomic layer epitaxy, molecular beam epitaxy, sputtering, or evaporation.
[0056] S102: Form an epitaxial structure on one side of the substrate.
[0057] For example, the epitaxial structure may be formed from one or more of the Group III and Group V nitrides, such as gallium nitride, aluminum gallium nitride, indium gallium nitride, aluminum nitride, and indium aluminum gallium nitride. Furthermore, a two-dimensional electron gas may be formed in the epitaxial structure. Methods for growing the epitaxial structure include, but are not limited to, organometallic chemical vapor deposition, hydrogen compound vapor phase epitaxial, molecular beam epitaxial, and liquid phase epitaxial. Specifically, a two-dimensional electron gas is formed in the epitaxial structure.
[0058] Selectively, the epitaxial structure may include a nucleation layer, a buffer layer, a channel layer, and a barrier layer.
[0059] For example, the nucleation layer material may be aluminum nitride. The nucleation layer is located between the substrate and the buffer layer and serves to bond the semiconductor material layer that needs to be grown next. The buffer layer is located on one side of the substrate. The buffer layer material may be gallium nitride. The buffer layer may contain iron atoms. This contributes to achieving high resistance performance of the buffer layer, ensuring the suppression of vertical leakage and improving the pinch-off performance of the semiconductor device.
[0060] For example, the channel layer is a group III nitride, e.g., Al x Ga 1-x N(0≦x<1) may also be the case where the energy at the interface between the channel layer and the barrier layer, i.e., the energy at the conductive band edge of the channel layer, is less than the energy at the conductive band edge of the barrier layer. For example, x=0 indicates that the channel layer is GaN. The channel layer may be other group III nitrides, e.g., InGaN, AlInGaN. The channel layer may be undoped or unintentionally doped. The channel layer may be a multilayer structure, e.g., a superlattice, or a combination of GaN or AlGaN.
[0061] For example, a barrier layer is formed on one side of the channel layer away from the substrate, and a heterojunction structure is formed between the barrier layer and the channel layer. The barrier layer may be AlN, AlInN, AlGaN, or AlInGaN. The barrier layer has sufficient thickness and a sufficiently high Al component to dope the interface between the channel layer and the barrier layer, thereby forming a significant carrier concentration. For example, the barrier layer may have a thickness of 20 nm and an Al dopant concentration of 25%.
[0062] For example, the channel layer may contain GaN and the barrier layer may contain AlGaN. That is, the material of the barrier layer may have a higher band gap than the material of the channel layer, and the channel layer may have a greater electron affinity than the barrier layer. Due to the band gap difference between the barrier layer and the channel layer, and the piezoelectric effect at the interface between the barrier layer and the channel layer, a two-dimensional electron gas is formed in the channel layer and the barrier layer.
[0063] Furthermore, the epitaxial structure may include a capping layer. The capping layer is located on the surface of the barrier layer, away from the substrate. The capping layer can reduce surface conditions, reduce surface leakage in subsequent semiconductor devices, and suppress current collapse. This can improve the performance and reliability of the epitaxial structure and the semiconductor device.
[0064] S103: Multiple gates are formed on one side of the epitaxial structure away from the substrate. The gates extend along a first direction. The multiple gates are arranged along a second direction. The first and second directions intersect each other and are both parallel to the plane on which the substrate is located. The multiple gates include a first gate and a second gate. Along the second direction, the first gate is located on one side of the second gate that is close to the edge of the semiconductor device. The maximum temperature of the first gate is T1, and the maximum temperature of the second gate is T2, where (T2-T1) / T1 ≤ 20%.
[0065] Specifically, referring to Figure 1, a plurality of gates 130 are formed on one side of the epitaxial structure 120 that is away from the substrate 110. Of the plurality of gates 130, the first gate 1301 is located on the side of the second gate 1302 that is close to the edge of the semiconductor device. Furthermore, during the operation of the semiconductor device, each gate 130 located in the active region self-heats, that is, each gate generates heat. The heat generated in each gate 130 diffuses to the adjacent gate 130, meaning that a mutual heating effect occurs between two adjacent gates 130. In other words, during the normal operation of the semiconductor device, each gate 130 self-heats and a mutual heating effect occurs, and the temperature of each gate 130 is the sum of the temperatures generated by self-heating and mutual heating. Although the temperature difference between each gate 130 generated by self-heating is small, the first gate 1301 is located on one side close to the edge of the semiconductor device along the second direction Y, and because there are few gates 130 adjacent to the first gate 1301, the temperature of the first gate 1301 decreases due to mutual heating.
[0066] Specifically, referring to Figure 1 again, by satisfying (T2 - T1) / T1 ≤ 20% between the maximum temperature T1 of the first gate 1301 and the maximum temperature T2 of the second gate, the temperature difference between the maximum temperature T1 of the first gate 1301 and the maximum temperature T2 of the second gate 1302, which are located on one side closer to the edge of the semiconductor device, can be reduced. This allows for a more uniform temperature distribution of the semiconductor device, reducing heat loss and improving the output power of the semiconductor device.
[0067] In the semiconductor device manufacturing method according to an embodiment of the present invention, multiple gates are formed on one side away from the substrate of the epitaxial structure, and the first gate among the multiple gates is located on the side close to the edge of the semiconductor device of the second gate. The maximum temperature T1 of the first gate 1301 and the maximum temperature T2 of the second gate satisfy (T2 - T1) / T1 ≤ 20%, thereby ensuring a small temperature difference between the gates. This allows for a uniform temperature distribution of the semiconductor device, reducing attenuation of high-frequency performance and improving output power.
[0068] It should be noted that the above are merely preferred embodiments and operational principles of the present invention. As those skilled in the art will understand, the present invention is not limited to the specific embodiments described herein, and those skilled in the art can make various obvious changes, adjustments, combinations, and substitutions without departing from the scope of protection of the present invention. Therefore, although the above embodiments have illustrated the present invention in more detail, the present invention is not limited to the above embodiments and can include many other equivalent embodiments without departing from the concept of the present invention, and the scope of protection of the present invention is determined by the appended claims.
Claims
1. A semiconductor device, circuit board and An epitaxial structure located on one side of the substrate, The epitaxial structure includes a plurality of gates located on one side away from the substrate, The gate extends along the first direction, The multiple gates are arranged along the second direction, The first direction and the second direction intersect and are both parallel to the plane on which the substrate is located. The plurality of gates include a first gate and a second gate, Along the second direction, the first gate is located on one side of the second gate that is close to the edge of the semiconductor device. The maximum temperature of the first gate is T1, the maximum temperature of the second gate is T2, and (T2 - T1) / T1 ≤ 20%. The epitaxial structure further includes a plurality of sources located on one side away from the substrate, The source extends along the first direction, Multiple sources are arranged along the second direction, The multiple sources include a first source and a second source, Along the second direction, the first source is installed adjacent to the first gate, the second source is installed adjacent to the second gate, and the first source is located on one side of the second source that is close to the edge of the semiconductor device. The substrate and the epitaxial structure further include through holes, The through-holes include a first type through-hole and a second type through-hole. Along the thickness direction of the semiconductor device, the first source overlaps with the first type of through hole, and the second source overlaps with the second type of through hole. A semiconductor device characterized in that, along the first direction, the center of the first type through hole is located on one side of the center of the second type through hole that is closer to the center of the semiconductor device.
2. The semiconductor device according to claim 1, characterized in that the first type of through hole has a larger total opening area than the second type of through hole.
3. The first type of through hole includes at least one first through hole, The second type of through hole includes at least one second through hole, The semiconductor device according to claim 2, characterized in that the first through-hole has a larger opening area than the second through-hole.
4. Along the second direction, the first through-hole is located on one side of either of the other through-holes that is closer to the edge of the semiconductor device, and the second through-hole is located on one side of either of the other through-holes that is closer to the center of the semiconductor device. The semiconductor device according to claim 3, characterized in that the opening area of the through-hole gradually decreases along the direction from the first through-hole to the second through-hole.
5. Along the second direction, the first through-hole is located on one side of either of the other through-holes that is closer to the edge of the semiconductor device, and the second through-hole is located on one side of either of the other through-holes that is closer to the center of the semiconductor device. The semiconductor device according to claim 3, characterized in that the opening area of the first through hole is S1, the opening area of the second through hole is S2, and S2 < S1 ≤ 4 * S2.
6. The first type of through hole includes at least two first through holes, The second type of through hole includes at least one second through hole, The semiconductor device according to claim 2, characterized in that the number of first through holes is greater than the number of second through holes.
7. Along the second direction, the first through-hole is located on one side of either of the other through-holes that is closer to the edge of the semiconductor device, and the second through-hole is located on one side of either of the other through-holes that is closer to the center of the semiconductor device. The semiconductor device according to claim 6, characterized in that the number of through holes gradually decreases along the direction from the first through hole to the second through hole.
8. Along the second direction, the first through-hole is located on one side of either of the other through-holes that is closer to the edge of the semiconductor device, and the second through-hole is located on one side of either of the other through-holes that is closer to the center of the semiconductor device. The semiconductor device according to claim 6, characterized in that the number of first through holes in the first type is n1, the number of second through holes in the second type is n2, and (n1 - n2) ≤ 5.
9. Between two adjacent gates, there is a gate gap along the second direction, The plurality of gate intervals include a first gate interval located near the edge of the semiconductor device along the second direction, and a second gate interval located on one side of the first gate interval away from the edge of the semiconductor device. The semiconductor device according to claim 1, characterized in that the first gate spacing is narrower than the second gate spacing along the second direction.
10. The second gate spacing is located on one side of any of the other gate spacings that is closer to the center of the semiconductor device. The semiconductor device according to claim 9, characterized in that the gate spacing gradually increases along the side from the first gate spacing toward the second gate spacing.
11. A method for manufacturing a semiconductor device according to any one of claims 1 to 10, To provide a substrate, To form an epitaxial structure on one side of the substrate, This includes forming a plurality of gates on one side of the epitaxial structure away from the substrate, The gate extends along the first direction, The multiple gates are arranged along the second direction, The first direction and the second direction intersect each other and are both parallel to the plane on which the substrate is located. The plurality of gates include a first gate and a second gate, Along the second direction, the first gate is located on one side of the second gate that is close to the edge of the semiconductor device. A method for manufacturing a semiconductor device, characterized in that the maximum temperature of the first gate is T1, the maximum temperature of the second gate is T2, and (T2 - T1) / T1 ≤ 20%.