Indication device

Abstract

This invention provides a semiconductor device that shifts low-level signals using a small number of transistors. [Solution] The first terminal is electrically connected to the first wiring, and the second terminal is electrically connected to the second wiring. A first transistor is electrically connected, and the first terminal is electrically connected to the third wiring. The second terminal is electrically connected to the second wiring of the second transistor, and the first terminal is connected to the fourth The wiring is electrically connected, and the second terminal is electrically connected to the gate of the second transistor. The third transistor is connected to the fifth wire at the first terminal, and the second terminal is connected to the fifth terminal. The gate of the third transistor is electrically connected, and the gate is electrically connected to the sixth wiring. The fourth transistor is connected to the third wiring at its first terminal, and the second terminal is connected to the third terminal. It has a first transistor gate and a first switch that is electrically connected to it.

Description

Technical Field

[0001] One aspect of the present invention relates to a semiconductor device, a display device, and the like.

Background Art

[0002] In recent years, the development of a shift register circuit composed of transistors of the same polarity has been actively promoted (see Patent Document 1). The shift register circuit of Patent Document 1 is composed of N-channel transistors. Then, when the clock signal becomes high level, by outputting the clock signal, high-level signals are sequentially output. However, since the shift register circuit of Patent Document 1 outputs a clock signal, it cannot sequentially output low-level signals.

[0003] <0,000,030><00000,31>

Prior Art Documents

Patent Documents

[0005]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0006] <000005,1> In a shift register circuit composed of the above, it is required to sequentially output high-level signals. It is being done.

[0006] Therefore, one aspect of the present invention is composed of an N-channel transistor and low-level signal One objective is to provide a circuit for sequentially outputting the following. Another aspect of the present invention is It consists of P-channel transistors and is a circuit for sequentially outputting high-level signals. One of the objectives is to provide [this]. Another aspect of the present invention aims to reduce the circuit size. One of the challenges is to reduce power consumption. Another aspect of the present invention aims to reduce power consumption. . [Means for solving the problem]

[0007] One aspect of the present invention is that one of the source and drain is electrically connected to a first wiring, and the source And the other side of the drain is electrically connected to the second wiring of the first transistor, and the source and One of the source and drain is electrically connected to the third wiring, and the other of the source and drain is connected to the second A second transistor electrically connected to the wiring, and one of the source and drain of the fourth wiring The wire is electrically connected, with the source and drain of the other being connected to the gate of the second transistor. A third transistor is directly connected, and one of its sources and drains is electrically connected to the fifth wiring. It is connected, and the source and the other drain are electrically connected to the gate of the third transistor. The gate of the fourth transistor is electrically connected to the sixth wiring, and the first terminal is connected to the third The wiring is electrically connected, and the second terminal is electrically connected to the gate of the first transistor. A semiconductor device having a first switch.

[0008] Note that in one aspect of the present invention, the first terminal is electrically connected to the first wiring, and the second terminal may have a second switch in which the second terminal is electrically connected to the gate of the first transistor .

[0009] Note that in one aspect of the present invention, the first terminal is electrically connected to the third wiring, and the second terminal may have a third switch in which the second terminal is electrically connected to the gate of the second transistor .

[0010] Note that in one aspect of the present invention, the first to fourth transistors may include an oxide semiconductor in the channel formation region . [Advantages of the Invention]

[0011] One aspect of the present invention can provide a circuit composed of N-channel transistors for sequentially outputting low-level signals. Further, one aspect of the present invention can provide a circuit composed of P-channel transistors for sequentially outputting high-level signals. Further, one aspect of the present invention can reduce the circuit scale. Further, one aspect of the present invention can reduce power consumption . Further, one aspect of the present invention can provide a circuit composed of P-channel transistors for sequentially outputting high-level signals . Further, one aspect of the present invention can reduce the circuit scale. Further, one aspect of the present invention can reduce power consumption . . Further, one aspect of the present invention can reduce power consumption [Brief Description of the Drawings]

[0012] [Figure 1] A diagram for explaining the basic circuit according to the present invention [Figure 2] A diagram for explaining the sequential circuit according to the present invention [Figure 3] A diagram for explaining the shift register circuit according to the present invention [Figure 4] A diagram for explaining the shift register circuit according to the present invention [Figure 5] A diagram for explaining the sequential circuit according to the present invention [Figure 6] A diagram for explaining the sequential circuit according to the present invention [Figure 7] A diagram illustrating a sequential circuit according to the present invention. [Figure 8] A diagram illustrating a sequential circuit according to the present invention. [Figure 9] A diagram illustrating a sequential circuit according to the present invention. [Figure 10] A diagram illustrating the basic circuit and sequential circuit according to the present invention. [Figure 11] A diagram illustrating the basic circuit according to the present invention. [Figure 12] A diagram illustrating the display device according to the present invention. [Figure 13] A diagram illustrating the display device according to the present invention. [Figure 14] A diagram illustrating the transistor according to the present invention. [Figure 15] A diagram illustrating the electronic device according to the present invention. [Modes for carrying out the invention]

[0013] Hereinafter, embodiments of the present invention will be described with reference to the drawings. However, the configuration of the present invention is It can be implemented in many different ways, and does not deviate from the spirit and scope of the present invention. It will be easily understood by those skilled in the art that its form and details can be changed in various ways without any modifications. Therefore, this embodiment should not be interpreted as being limited to its contents. In the configuration of the present invention, reference numerals indicating the same object are common across different drawings.

[0014] Furthermore, the size, layer thickness, signal waveform, or The area may be exaggerated in its representation for clarity. Therefore, it may not necessarily reflect the actual scale. Not limited to [specific type / method].

[0015] Furthermore, the terms 1st, 2nd, 3rd, through Nth (where N is a natural number) used in this specification are defined as follows: This is added to avoid confusion regarding the constituent elements and does not mean that the number is limited. do.

[0016] (Embodiment 1) In this embodiment, a basic circuit, a sequential circuit, and a shift register circuit according to one aspect of the present invention are described. Let me explain the road.

[0017] First, the basic circuit of this embodiment (also referred to as a semiconductor device or drive circuit) will be described.

[0018] Figure 1(A) is a circuit diagram of the basic circuit of this embodiment. The basic circuit of Figure 1(A) is a tra It has transistors 101 to 105.

[0019] In one embodiment of the present invention, the polarity of the transistor may be N-channel or P-channel. A Nell-type transistor is also acceptable. However, transistors 101 through 105 must have the same polarity. It is preferable that this is the case. In this embodiment, transistors 101 to 105 Let's explain this assuming it's an N-channel type.

[0020] In one embodiment of the present invention, the transistor is a channel formation region made of silicon or Transistors containing semiconductors such as germanium can be used. As a starter, the channel formation region includes a semiconductor such as an oxide semiconductor or a nitride semiconductor. A transistor can be used. The semiconductors mentioned above can be amorphous, microcrystalline, polycrystalline, or It has a region that is a single crystal.

[0021] In one embodiment of the present invention, the transistor is a thin-film transistor (TFT). It can be used. Furthermore, as a transistor, a semiconductor substrate or SOI substrate can be used. The resulting transistors are MOS-type transistors, junction-type transistors, or bipolar transistors, etc. You can use it.

[0022] Next, we will explain the connection relationships of the basic circuit in Figure 1(A).

[0023] The first terminal of transistor 101 (also known as the source or drain) is in contact with wiring 11. The second terminal of transistor 101 (also known as the source and drain) is connected to the wiring. It is connected to 12. The first terminal of transistor 102 is connected to wiring 13, and the transistor The second terminal of transistor 102 is connected to wire 12, and the gate of transistor 102 is connected to wire 14. The first terminal of transistor 103 is connected to the wiring 15, and transistor 10 The second terminal of 3 is connected to wire 14. The first terminal of transistor 104 is connected to wire 13. The second terminal of transistor 104 is connected to the gate of transistor 101, The gate of transistor 104 is connected to wire 14. The first terminal of transistor 105 It is connected to wiring 17, and the second terminal of transistor 105 is connected to the gate of transistor 103. The gate of transistor 105 is connected to wire 16.

[0024] Furthermore, the connection point between the gate of transistor 103 and the second terminal of transistor 105 is... This is denoted as N1. Also, the gate of transistor 101 and the second terminal of transistor 104 The connection point is indicated as node N2.

[0025] In this specification, "connection" refers to an electrical connection, including current, voltage, potential, This corresponds to a state in which signals or electric charges can be supplied or transmitted. Therefore, "connected" means In addition to being directly connected, for example, wiring, conductive films, resistors, diodes, transistors This category also includes situations where connections are made indirectly through elements such as switches and other components. nothing.

[0026] Next, the signals or potentials of wiring 11 to 17 will be described.

[0027] The potential VDD is supplied to wiring 11. The signal OUTA is output from wiring 12. The potential VSS is supplied to 13. The signal OUTB is output from wiring 14. Wiring 15 Signal CK1 is input to this. Signal CK2 is input to wiring 16. Signal CK2 is input to wiring 17. SP is entered.

[0028] Note that the potentials VDD and VSS are constant. Also, the potential VDD is greater than the potential VSS. It has a higher potential.

[0029] Note that signals OUTA, OUTB, CK1, CK2, and SP are high-level signals. It is a digital signal having both a low and a low level.

[0030] Note that the signals or potentials of wiring 11 to 17 are not limited to those described above. Wiring 11 It is sufficient that a signal or potential is supplied to raise the potential of wiring 12. 3 contains a signal or potential, etc., for lowering the potential of wiring 12, and / or a transistor. It is sufficient that a signal or potential is supplied to turn off 101. A signal or potential such as a signal to raise the potential of line 14 turns on transistor 102. A signal or potential, etc., for turning on transistor 104, and / or a signal or potential for turning on transistor 104 It is sufficient that a potential or similar input is provided. Wiring 16 controls the on or off state of transistor 105. All that's needed is a signal to control it. Connect the transistor 103 to wire 17. It is sufficient if a signal or potential is input for that purpose.

[0031] In this specification, etc., a wire into which a signal is input may be referred to as a signal line. The wiring to which it is supplied can also be called a power line.

[0032] In one embodiment of the present invention, the wiring has the function of transmitting signals or electric potential, etc. Wiring 15 has the function of transmitting signal CK1.

[0033] Next, we will explain the operation of the basic circuit shown in Figure 1(A).

[0034] Figure 1(B) is a timing chart to explain the operation of the basic circuit shown in Figure 1(A). The timing chart in Figure 1(B) shows signals CK1, CK2, SP, and node N1. The potential VN1, the potential VN2 at node N2, and signals OUTA and OUTB are shown.

[0035] For convenience, the high-level potentials of signals SP, CK1, and CK2 are referred to as potential VDD. The low-level potential is described as potential VSS.

[0036] For convenience, the initial value of the potential VN1 at node N1 is set to potential VSS, and the initial value of the potential VN2 at node N2 is set to potential VN2 The initial value is explained as a potential that exceeds the sum of the potential VDD and the threshold voltage of transistor 101. ru.

[0037] For convenience, we will explain this by dividing it into two periods: Period T1 and Period T2.

[0038] During period T1, signal SP becomes high level, signal CK1 becomes low level, and signal CK Level 2 becomes high-level.

[0039] When transistor 105 is turned on, the signal SP from wiring 17 is supplied to node N1. During period T1, the signal SP is at a high level, so the potential of node N1 rises. The potential of N1 is from the gate potential of transistor 105 (e.g., potential VDD) to the transistor When the potential rises to the level obtained by subtracting the threshold voltage of transistor 105, transistor 105 turns off. Then, node N1 enters a floating state.

[0040] When transistor 103 is turned on, signal CK1 is supplied to wiring 14. Period T1 Therefore, since signal CK1 is at a low level, the potential of wiring 14 becomes potential VSS. In other words, The signal OUTB becomes low level.

[0041] When transistor 104 is turned off, node N2 becomes floating. Therefore, node The potential of N2 is maintained at a potential that exceeds the sum of the potential VDD and the threshold voltage of transistor 101. ru.

[0042] When transistor 101 turns on and transistor 102 turns off, the wiring 11 The potential VDD is supplied to wiring 12. Therefore, the potential of wiring 12 becomes the potential VDD. As a result, the signal OUTA becomes high level.

[0043] During period T2, signal SP becomes low level, signal CK1 becomes high level, and signal CK 2 becomes the low level.

[0044] When transistor 105 is turned off, node N1 becomes floating.

[0045] When transistor 103 is turned on, the signal CK1 from wiring 15 is supplied to wiring 14. During period T2, the signal CK1 is at a high level, causing the potential of wiring 14 to rise. Node N1 is in a floating state, and transistor 103 is connected to node N1 and wiring 14. The potential difference between them is maintained. Therefore, as the potential of wiring 14 rises, the potential of node N1 rises. The potential of node N1 rises. The potential of the first terminal of transistor 103 (for example, potential V) If the potential exceeds the sum of the threshold voltage of DD and transistor 103, then the potential of wiring 14 will The potential becomes VDD. In other words, the signal OUTB becomes high level.

[0046] When transistor 104 is turned on, the potential VSS of wiring 13 is supplied to node N2. Therefore, the potential at node N2 becomes potential VSS.

[0047] When transistor 101 turns off and transistor 102 turns on, the wiring 13 The potential VSS is supplied to the wiring 12. Therefore, the potential of the wiring 12 becomes the potential VSS. As a result, the signal OUTA becomes low level.

[0048] As described above, signal OUTA becomes high level during period T1, and low during period T2. It becomes a low level. Also, signal OUTB becomes a low level during period T1, and during period T2 To reach a high level in that area.

[0049] Next, we will explain sequential circuits using the basic circuit shown in Figure 1(A).

[0050] Figure 2(A) is a circuit diagram of the sequential circuit of this embodiment. The sequential circuit in Figure 2(A) is a tra It has transistors 101 to 107.

[0051] Note that transistors 106 and 107 have the same polarity as transistor 101. It is preferable that transistors 106 and 107 are N Let's explain it assuming it's a channel type.

[0052] Note that transistor 106 in the sequential circuit of Figure 2(A) does not need to be provided. The transistor 107 in the sequential circuit of ) does not need to be provided.

[0053] Next, we will explain the connection relationships of the sequential circuit in Figure 2(A).

[0054] The connection relationships between transistors 101 through 105 are the same as in the basic circuit shown in Figure 1(A). Therefore, the explanation will be omitted. The first terminal of transistor 106 is connected to wiring 13. The second terminal of transistor 106 is connected to wire 14, and the gate of transistor 106 It is connected to node N2. The first terminal of transistor 107 is connected to wiring 11, The second terminal of transistor 107 is connected to node N2, and the gate of transistor 107 is It is connected to wiring 16.

[0055] Next, we will explain the operation of the sequential circuit shown in Figure 2(A).

[0056] Figure 2(B) is a timing chart illustrating the operation of the sequential circuit in Figure 2(A). The timing chart in Figure 2(B) shows signals CK1, CK2, SP, and node N1. The potential VN1, the potential VN2 at node N2, and signals OUTA and OUTB are shown.

[0057] For convenience, the high-level potentials of signals SP, CK1, and CK2 are referred to as potential VDD. The low-level potential is described as potential VSS.

[0058] For convenience, the initial value of the potential VN1 at node N1 is set to potential VSS, and the initial value of the potential VN2 at node N2 is set to potential VN2 The initial value is explained as a potential that exceeds the sum of the potential VDD and the threshold voltage of transistor 101. ru.

[0059] For convenience, the explanation will be divided into periods T1, T2, T3, and T4.

[0060] During period T1, signal SP becomes high level, signal CK1 becomes low level, and signal CK Level 2 becomes high-level.

[0061] When transistor 105 is turned on, the signal SP from wiring 17 is supplied to node N1. During period T1, the signal SP is at a high level, so the potential of node N1 rises. The potential of N1 is from the gate potential of transistor 105 (e.g., potential VDD) to the transistor When the potential rises to the level obtained by subtracting the threshold voltage of transistor 105, transistor 105 turns off. Then, node N1 enters a floating state.

[0062] When transistor 103 turns on, and then transistor 106 turns on, the wiring 15 Signal CK1 and the potential VSS of wiring 13 are supplied to wiring 14. During period T1, signal CK1 Because it is low level, the potential of wiring 14 becomes potential VSS. In other words, signal OUTB is It will become low level.

[0063] When transistor 107 turns off, and then transistor 104 turns off, node N2 It becomes a floating state. Therefore, the potential of node N2 is equal to the potential of the first terminal of transistor 101. (For example, potential VDD) is maintained at a potential that exceeds the sum of the threshold voltage of transistor 101. .

[0064] Furthermore, if the initial value of the potential VN2 of node N2 is the potential VSS, then transistor 107 is As a result, the potential VDD of wiring 11 is supplied to node N2.

[0065] When transistor 101 turns on and transistor 102 turns off, the wiring 11 The potential VDD is supplied to wiring 12. Therefore, the potential of wiring 12 becomes the potential VDD. As a result, the signal OUTA becomes high level.

[0066] During period T2, signal SP becomes low level, signal CK1 becomes high level, and signal CK 2 becomes the low level.

[0067] Because transistor 105 is turned off, node N1 becomes floating.

[0068] When transistor 103 turns on and transistor 106 turns off, the wiring 15 Signal CK1 is supplied to wiring 14. During period T2, signal CK1 is at a high level, The potential of wiring 14 rises. At this time, node N1 is in a floating state, and the transistor Between the gate of 103 and the second terminal of transistor 103, there is a connection between node N1 and wiring 14. The potential difference is maintained. Therefore, as the potential of wiring 14 rises, the potential of node N1 also rises. It rises. The potential of node N1 is equal to the potential of the first terminal of transistor 103 (e.g., potential VD). If the potential rises to a level exceeding the sum of D) and the threshold voltage of transistor 103, the power of wiring 14 The voltage becomes VDD. In other words, the signal OUTB becomes high level.

[0069] When transistor 107 turns off and transistor 104 turns on, the wiring 13 The potential VSS is supplied to node N2. Therefore, the potential of node N2 becomes the potential VSS.

[0070] When transistor 101 turns off and transistor 102 turns on, the wiring 13 The potential VSS is supplied to the wiring 12. Therefore, the potential of the wiring 12 becomes the potential VSS. As a result, the signal OUTA becomes low level.

[0071] During period T3, signal SP becomes low level, signal CK1 becomes low level, and signal CK Level 2 becomes high-level.

[0072] When transistor 105 is turned on, the signal SP from wiring 17 is supplied to node N1. During period T3, since signal SP is at a low level, the potential of node N1 becomes potential VSS. .

[0073] When transistor 103 turns off and transistor 106 turns on, the wiring 13 The potential VSS is supplied to wiring 14. Therefore, the potential of wiring 14 becomes the potential VSS. As a result, the OUTB signal becomes low level.

[0074] When transistor 107 turns on and transistor 104 turns off, the wiring 11 The potential VDD is supplied to node N2. Therefore, the potential of node N2 rises. Node N The potential of 2 is from the gate potential of transistor 107 (e.g., potential VDD) to transistor 1 When the potential rises to the level obtained by subtracting the threshold voltage of 07, transistor 107 turns off. Therefore, Node N2 becomes floating.

[0075] When transistor 101 turns on and transistor 102 turns off, the wiring 11 The potential VDD is supplied to the wiring 12. Therefore, the potential of wiring 12 rises. At this time, The N2 is in a floating state, and the gate of transistor 101 and the second of transistor 101 A potential difference is maintained between node N2 and wiring 12 at the terminal. Therefore, wiring 1 As the potential of node 2 increases, the potential of node N2 also increases. The potential of the first terminal of transistor 101 (e.g., potential VDD) and the threshold voltage of transistor 101 If the potential rises beyond the sum, the potential of wiring 12 becomes potential VDD. In other words, signal OU The TAs will become highly skilled.

[0076] During period T4, signal SP becomes low level, signal CK1 becomes high level, and signal CK 2 becomes the low level.

[0077] When transistor 105 is turned off, node N1 becomes floating. Therefore, node The potential of N1 is maintained at the potential during period T3.

[0078] When transistor 103 turns off and transistor 106 turns on, the wiring 13 The potential VSS is supplied to wiring 14. Therefore, the potential of wiring 14 becomes the potential VSS. As a result, the OUTB signal becomes low level.

[0079] When transistor 107 turns off, and then transistor 104 turns off, node N2 The atom becomes suspended. Therefore, the potential of node N2 is maintained at the potential during period T3.

[0080] When transistor 101 turns on and transistor 102 turns off, the wiring 11 The potential VDD is supplied to wiring 12. Therefore, the potential of wiring 12 becomes the potential VDD. As a result, the signal OUTA becomes high level.

[0081] As described above, signal OUTA becomes low level during period T2, and during periods T1 and T2. It becomes high level in period T4. Also, signal OUTB is high in period T2. It becomes an i-level, and then a low level during periods T1, T3, and T4.

[0082] Next, we will explain the shift register circuit using the sequential circuit shown in Figure 2(A).

[0083] Figure 3 is a circuit diagram of the shift register circuit of this embodiment. Shift register circuit of Figure 3 It has N (where N is a natural number) sequential circuits 100 (also called N stages). However, Figure 3 shows , sequential circuits of the first to third stages (sequential circuit 100[1], sequential circuit 100[2], sequential circuit Only road 100[3] is shown.

[0084] Note that each of the N sequential circuits 100 is the sequential circuit shown in Figure 2(A).

[0085] Next, we will explain the connection relationships of the shift register circuit shown in Figure 3.

[0086] The shift register circuit in Figure 3 consists of N wires 21, N wires 22, 23, 24, It is connected to wiring 25, wiring 26, and wiring 27.

[0087] Specifically, the i (where i is any one from 2 to N) stage sequential circuit 100 (sequential circuit 100[ In the configuration indicated by [i], the second terminal of transistor 101 is connected to the wiring 21[i]. The gate of transistor 102 is connected to wiring 22[i]. The terminal of transistor 105 Terminal 1 is connected to wire 22[i-1]. The first terminal of transistor 101 is connected to wire 2 It is connected to 3. The first terminal of transistor 102 is connected to wiring 24. Transistor The first terminal of transistor 103 is connected to one of the wires 25 and 26. Transistor 107 The gate is connected to the other end of wiring 25 and wiring 26.

[0088] In other words, in sequential circuit 100[i], wiring 21[i] corresponds to wiring 12. Line 22[i] corresponds to wiring 14. Wiring 23 corresponds to wiring 11. Wiring 24 corresponds to wiring 1 Corresponds to 3. One of wires 25 and 26 corresponds to wire 15. Wire 25 and wire 2 The other side of 6 corresponds to wiring 16. Wiring 22[i-1] corresponds to wiring 17.

[0089] In addition, in sequential circuit 100[i-1] or sequential circuit 100[i+1], the transistor The first terminal of transistor 103 is connected to the other end of wire 25 and wire 26. Transistor 107 The gate of transistor 103 is connected to one of the wires 25 and 26. The connection destinations of terminal 1 and the gate of transistor 107 are as follows: They are replaced.

[0090] In the sequential circuit 100[1], the first terminal of transistor 105 is connected to wiring 27. The connection point differs from that of the i-th stage sequential circuit 100.

[0091] Next, the signals or potentials of wiring 21 to 27 will be explained.

[0092] Signal SOUTA is output from wiring 21. Signal SOUTB is output from wiring 22. Wiring 23 is supplied with potential VDD. Wiring 24 is supplied with potential VSS. Signal SCK1 is input to wire 25. Signal SCK2 is input to wire 26. Wiring 27 The signal SSP is input to it.

[0093] Note that signal SOUTA corresponds to signal OUTA, and signal SOUTB corresponds to signal OUTB. Signal SCK1 corresponds to either signal CK1 or signal CK2. Signal SCK2 corresponds to signal CK1. Alternatively, it corresponds to signal CK2. Signal SSP corresponds to signal SP.

[0094] Next, we will explain the operation of the shift register circuit shown in Figure 3.

[0095] Figure 4 is a timing chart illustrating the operation of the shift register circuit shown in Figure 3. The timing chart in Figure 4 shows signals SSP, SCK1, SCK2, and SOUT. A[1] to signal SOUTA[3], signal SOUTA[N-1], signal SOUTA[N] , signal SOUTB[1] to signal SOUTB[3], signal SOUTB[N-1], signal S This indicates OUTB[N].

[0096] When the signal SOUTB[i-1] becomes high level, the sequential circuit 100[i] is activated during period T1. The operation is performed. Therefore, the signal SOUTA[i] becomes high level, and the signal SOUTB[ i] becomes a low level.

[0097] Subsequently, when signals SCK1 and SCK2 are reversed, the sequential circuit 100[i] enters period T2 The operation in this case is performed. Therefore, the signal SOUTA[i] becomes low level, and the signal SOUT B[i] becomes high level.

[0098] Subsequently, until signal SOUTB[i-1] becomes high again, signal SCK1 and signal Each time SCK2 inverts, the sequential circuit 100[i] operates in period T3 and in period T4. The action of pressing and repeating. Therefore, the signal SOUTA[i] becomes high level, and the signal SOU TB[i] becomes low level.

[0099] Furthermore, the sequential circuit 100[1] operates during period T1 when the signal SSP is at a high level. This is where it differs from sequential circuit 100[i].

[0100] As described above, signals SOUTA[1] to SOUTA[N] are high-frequency signals. After becoming a bell, it gradually goes to a low level. Also, signal SOUTB[1] or signal SOU TB[N] becomes high-level sequentially after the SSP signal becomes high-level.

[0101] Next, the functions of transistors 101 through 107 will be described.

[0102] Each of transistors 101 through 107 has a first terminal to which it is connected and a second terminal to which it is connected. It has a function to control the continuity or non-continuity with the destination of the child. It has the function of supplying a voltage or potential to the connection destination of the second terminal. For example, transistor 10 2 has the function of controlling the continuity or non-continuity between wiring 13 and wiring 12. Also, the potential VSS It has the function of supplying power to wiring 12.

[0103] Furthermore, transistors 101 and 103 are connected to the gate destination and the second terminal. It has the function of maintaining the potential difference between it and the preceding point. For example, transistor 101 is connected to node N2 and It has the function of maintaining the potential difference with respect to the wiring 12.

[0104] Furthermore, transistors 105 and 107 have a connection destination for the first terminal and a second terminal. After making the connection point conductive, the connection point of the first terminal and the connection point of the second terminal are made non-conductive. It has the function of supplying the signal or potential of the connection point of the first terminal to the connection point of the second terminal. After that, it has the function of stopping the supply of signals or potentials to the connected terminal of the first terminal. For example, After making the wiring 17 and node N1 conductive, the transistor 105 then connects the wiring 17 and node N1 It has the function of making the two non-conductive. Also, after supplying signal SP to node N1, signal SP It has the function of stopping the supply.

[0105] Furthermore, transistor 101 supplies a signal or potential to raise the potential to the wiring 12. It has the function of lowering the potential of the wiring 12. Transistor 102 provides a signal or potential to lower the potential of the wiring 12. It has the function of supplying the following. Transistor 103 is a signal to raise the potential of the wiring 14. It has the function of supplying voltage or potential, etc. Transistor 104 is connected to node N2 Transistor 105 has the function of supplying a signal or potential, etc., to turn off 101. This function supplies a signal or potential, etc., to node N1 to turn on transistor 103. It has. Transistor 106 supplies a signal or potential, etc., to the wiring 14 to lower the potential. It has the function of turning on transistor 101 at node N2. It has the function of supplying signals or potentials for that purpose.

[0106] In one aspect of the present invention, the transistor is connected to the first terminal and the second terminal. Alternatively, it may be replaced with a switch that has a function to control non-conductivity. The first transistor The terminal corresponds to the first terminal of the switch, and the second terminal of the transistor corresponds to the second terminal of the switch. Additionally, the transistor's gate corresponds to the switch's control terminal, if necessary.

[0107] Next, the W / L (W: channel width, L: channel width) of transistors 101 to 107 Let's explain the length of the channel.

[0108] The W / L of transistor 101 is equal to the W / L of transistors 102 through 107. It is preferable that the ratio is also large. Also, the W / L of transistor 102 is the same as that of transistor 104. It is preferable that it is greater than W / L. Also, the W / L of transistor 103 is It is preferable that the W / L of transistor 105 is greater than that of transistor 105. Also, the W / L of transistor 104 is It is preferable that the W / L ratio is greater than that of the 106.

[0109] By the way, transistors 101 to 107 are P-channel type transistors When using a t-type circuit, supply potential VSS to wiring 11 and potential VDD to wiring 13. It is preferable to do so. It is also preferable to invert signals CK1, CK2, and SP. So, signals OUTA and OUTB are also inverted. Also, transistor 101 When using a P-channel type transistor as transistor 107, the above explanation applies. In the Ming Dynasty, you simply need to replace "ascending" with "descending" and "descending" with "ascending".

[0110] Next, regarding the effects of the basic circuit, sequential circuit, and shift register circuit of this embodiment, I will explain.

[0111] In a circuit composed of N-channel transistors, a low-level signal is shifted. It is possible to do so. Also, in a circuit composed of P-channel transistors, Hi-Re The bell signal can be shifted.

[0112] Furthermore, it is possible to generate signals such as signal OUTA and signal SOUTA with a small number of transistors. It is possible.

[0113] Furthermore, the period during which both transistor 107 and transistor 104 are turned on is eliminated. Therefore, the current between wiring 11 and wiring 13 can be reduced. This allows for a reduction in power consumption.

[0114] Furthermore, the period during which both transistor 101 and transistor 102 are turned on is eliminated. Therefore, the current between wiring 11 and wiring 13 can be reduced. This allows for a reduction in power consumption.

[0115] Furthermore, during the period when signal CK1 is at a high level, transistor 103 and transistor This eliminates the period during which both terminals 106 are turned on, between wiring 15 and wiring 13. This reduces the current generated. Therefore, it is possible to reduce power consumption.

[0116] Furthermore, during period T3, transistor 105 turns on, which is a low level signal. SP can be supplied to node N1. Therefore, the potential of node N1 can be set to potential VSS. It can be made easier to maintain and malfunctions can be prevented.

[0117] Furthermore, during period T3, transistor 107 turns on, causing the potential VDD to change to the node It can supply power to N2. Therefore, it makes it easier to maintain a high potential at node N2. This allows for the prevention of malfunctions.

[0118] Furthermore, during periods T3 and T4, when transistor 106 is turned on, wiring 1 A potential of 3, VSS, can be supplied to the wiring 14. Therefore, the potential of the wiring 14 is VSS. This makes it easier to maintain the S setting and prevents malfunctions.

[0119] This embodiment can be implemented in appropriate combination with other embodiments, etc.

[0120] (Embodiment 2) In this embodiment, the basic circuit, sequential circuit, and shift register circuit differ from those in Embodiment 1. The circuits will be described. However, parts common to Embodiment 1 will be indicated by the same reference numerals. I will omit the explanation.

[0121] In this embodiment, the diagram of the sequential circuit in Figure 2(A) has been modified and is used to represent the actual implementation. The basic circuits, sequential circuits, and shift register circuits will be explained. However, The configuration described in this embodiment includes not only the sequential circuit in Figure 2(A), but also the configuration described in Embodiment 1. It can also be applied to other basic circuits, sequential circuits, and shift register circuits.

[0122] The basic circuit, sequential circuit, and shift register circuit of this embodiment are described in Embodiment 1. It produces a similar effect to the beading effect.

[0123] First, we will explain the connection relationship of transistor 105, which differs from that of Embodiment 1.

[0124] The first terminal of transistor 105 is connected to wires 11, 12, 16, 17 or node Connect to N2, and connect the second terminal of transistor 105 to node N1, and transistor 1 You may also connect gate 05 to wiring 17.

[0125] Figure 5(A) shows the first terminal of transistor 105 connected to wiring 17, and transistor 10 Connect the second terminal of 5 to node N1, and connect the gate of transistor 105 to wire 17. This is a circuit diagram of a sequential circuit.

[0126] Next, we will describe a different connection relationship for transistor 107 compared to Embodiment 1.

[0127] Connect the first terminal of transistor 107 to the wire 16, and the second terminal of transistor 107 Alternatively, you may connect it to node N2 and connect the gate of transistor 107 to wiring 16. The first terminal of transistor 107 is connected to the wiring 11, and the second terminal of transistor 107 is connected to the wiring 11. Alternatively, the child node may be connected to node N2, and the gate of transistor 107 may be connected to wiring 11.

[0128] Figure 5(B) shows the first terminal of transistor 107 connected to wiring 16, and transistor 10 Connect the second terminal of 7 to node N2, and connect the gate of transistor 107 to wire 16. This is a circuit diagram of a sequential circuit.

[0129] Next, we will describe a different connection relationship for transistor 104 compared to Embodiment 1.

[0130] Connect the first terminal of transistor 104 to the wiring 13, and the second terminal of transistor 104 Connect this to node N2, and connect the gate of transistor 104 to node N1 or wiring 17. That's fine.

[0131] Figure 6(A) shows the first terminal of transistor 104 connected to wiring 13, and transistor 10 Connect the second terminal of 4 to node N2, and connect the gate of transistor 104 to node N1. This is a circuit diagram of the sequential circuit.

[0132] Next, we will describe a different connection relationship for transistor 102 compared to Embodiment 1.

[0133] Connect the first terminal of transistor 102 to the wiring 13, and the second terminal of transistor 102 Connect this to wiring 12, and connect the gate of transistor 102 to node N1 or wiring 17. That's good too.

[0134] Figure 6(B) shows the first terminal of transistor 102 connected to wiring 13, and transistor 10 Connect the second terminal of 2 to wiring 12, and connect the gate of transistor 102 to node N1. This is a circuit diagram of a sequential circuit.

[0135] Next, we will describe a different connection relationship for transistor 106 compared to Embodiment 1.

[0136] Connect the first terminal of transistor 106 to the wiring 13, and the second terminal of transistor 106 Alternatively, you can connect this to wiring 14 and connect the gate of transistor 106 to wiring 16. This allows the time that transistor 106 is ON to be shortened, and also reduces the duration T3. In this configuration, the potential VSS of wiring 13 can be supplied to wiring 14, so the potential of wiring 14 It can be maintained stably.

[0137] Figure 7(A) shows the first terminal of transistor 106 connected to wiring 13, and transistor 10 The second terminal of 6 was connected to wire 14, and the gate of transistor 106 was connected to wire 16. This is a circuit diagram of a sequential circuit.

[0138] Next, transistor 201, transistor 202, transistor 203 and transistor I will now explain the configuration that includes 204.

[0139] Figure 7(B) shows transistors 201, 202, 203 and This is a circuit diagram of a sequential circuit with transistor 204. The first terminal of transistor 201 is The second terminal of transistor 201 is connected to node N1, and the transistor The gate of transistor 201 is connected to wire 31. The first terminal of transistor 202 is connected to wire 1 The second terminal of transistor 202 is connected to node N2, and the transistor The gate of transistor 202 is connected to wire 31. The first terminal of transistor 203 is connected to wire 11. The second terminal of transistor 203 is connected to wire 12, and transistor 203 The gate of the transistor is connected to wire 31. The first terminal of transistor 204 is connected to wire 13. The second terminal of transistor 204 is connected to wire 14, and the gate of transistor 204 The wire is connected to wiring 31.

[0140] Signal RE is input to wiring 31. Signal RE is a digital signal with high and low levels. This is a digital signal. However, the wiring 31 has connections to transistors 201 through 204. It is sufficient that a signal is input to control whether the circuit is open or closed.

[0141] In sequential circuit 100[i], wiring 31 corresponds to wiring 22[i+1]. And, wiring 31 is like wiring 22[i+2] or wiring 22[i+3], wiring 22[i+n] This can also be represented as (where n is a natural number).

[0142] When the signal RE becomes high level, transistors 201 through 204 turn on. Transistors 201 and 204 turn on, and the potential V of wiring 13 is increased. SS is supplied to node N1 and wiring 14. Therefore, the potential of node N1 and wiring 14 is The potential becomes VSS. Also, transistors 202 and 203 turn on. Then, the potential VDD of wiring 11 is supplied to node N2 and wiring 12. Therefore, node N2 And the potential of wiring 12 becomes higher than the potential VDD or the potential VSS.

[0143] On the other hand, when the signal RE becomes low level, transistors 201 to 204 are It becomes F.

[0144] Let's explain an example of the timing of signal RE. Wiring 31 corresponds to wiring 22[i+1]. If so, signal RE corresponds to signal OUTB[i+1]. Therefore, signal RE is It becomes high after interval T2 (for example, period T3 immediately following period T2), and otherwise During this period, the level becomes low. Therefore, after period T2, the sequential circuit can be initialized. ru.

[0145] Furthermore, one, two, or three transistors selected from transistors 201 to 204 It is also acceptable to provide only transistors.

[0146] Next, transistors 205, 206, 207 and I will now explain the configuration that includes 208.

[0147] Figure 8(A) shows transistors 205, 206, 207 and This is a circuit diagram of a sequential circuit with transistor 208. Transistors 205 and beyond are also shown. The connection of 208 is such that the gate is connected to wiring 32, which is the same as transistor 201. It is different from transistor 204.

[0148] Furthermore, in all or at least two of the N sequential circuits 100, the transistor 205 The gates of transistor 208 are connected to the same destination.

[0149] Signal INI is input to wiring 32. Signal INI has a high level and a low level. It is a digital signal. However, the wiring 32 has transistors 205 to 208 It is sufficient that a signal is input to control whether the circuit is conductive or non-conductive.

[0150] When signal INI becomes high level, transistors 205 through 208 turn on. As transistors 205 and 208 turn on, the wiring 13 The potential VSS is supplied to node N1 and wiring 14. Therefore, node N1 and wiring 14 The potential becomes potential VSS. Also, transistors 206 and 207 are turned on. As a result, the potential VDD of wiring 11 is supplied to node N2 and wiring 12. Therefore, The potential of node N2 and wiring 12 becomes higher than the potential VDD or potential VSS.

[0151] On the other hand, when the signal INI becomes low, transistors 205 through 208 It turns off.

[0152] Let me explain an example of the timing of the signal INI. During the period when the signal SSP is at a high level... Before that, the signal INI becomes high level. Therefore, the first stage sequential circuit 100 is in period T1 Before performing the operation in the above, each sequential circuit 100 can be initialized. Therefore, malfunction This can help prevent it.

[0153] Note that this occurs after signal OUTB[N] has reached a high level, and also when signal SSP is at a high level. It is preferable that the signal INI becomes high level before this happens. Also, after power-on And, before the signal SSP becomes high level, the signal INI becomes high level. That's good too.

[0154] Alternatively, the first terminal of transistor 207 may be connected to wiring 13.

[0155] The gates of transistors 205 through 208 may also be connected to wiring 27. In other words, the signal SSP may be used as the signal INI.

[0156] Furthermore, one, two, or three transistors selected from transistors 205 to 208 It is also acceptable to provide only transistors.

[0157] Next, we will describe a configuration that includes transistors 209 and 210.

[0158] Figure 8(B) is a circuit diagram of a sequential circuit with transistors 209 and 210. Yes. The first terminal of transistor 209 is connected to wire 13, and the second terminal of transistor 209 Terminal 2 is connected to wire 14, and the gate of transistor 209 is connected to wire 16. The first terminal of transistor 210 is connected to the wiring 11, and the second terminal of transistor 210 The child is connected to wire 12, and the gate of transistor 210 is connected to wire 16.

[0159] When signal CK2 reaches a high level, transistors 209 and 210 turn on. When transistor 209 is turned on, the potential VSS of wiring 13 is supplied to wiring 14. When transistor 210 is turned on, the potential VDD of wiring 11 is supplied to wiring 12. .

[0160] On the other hand, when the signal CK2 becomes low level, the transistors 209 and 210 turn off.

[0161] The signal CK2 becomes high level in the periods T1 and T3, and becomes low level in the periods T2 and T4. Therefore, in the periods T1 and T3, the potential V SS of the wiring 13 is supplied to the wiring 14, and the potential VDD of the wiring 11 is supplied to the wiring 12. In particular, when the signal CK2 becomes high level in the period T3, the potential VSS of the wiring 13 is periodically supplied to the wiring 1 4, and the potential VDD of the wiring 11 is periodically supplied to the wiring 12. Therefore , it becomes easier to maintain the potentials of the wiring 14 and the wiring 12.

[0162] Note that only one of the transistors 209 and 210 may be provided.

[0163] Next, a configuration provided with the transistors 211 and 212 will be described.

[0164] FIG. 9(A) is a circuit diagram of a sequential circuit provided with the transistors 211 and 212 There is. The first terminal of the transistor 211 is connected to the wiring 17, and the second terminal of the transistor 211 is connected to the first terminal of the transistor 105, and the gate of the transistor 211 is connected to the wiring 33. The first terminal of the transistor 212 is connected to the wiring 31, and the trans The second terminal of the transistor 212 is connected to the first terminal of the transistor 105, and the transistor The gate of 212 is connected to the wiring 34.

[0165] Note that in all or at least two of the N sequential circuits 100, the transistor 211's The gate connections are common, and the gate connection of transistor 212 is also common.

[0166] Signal SC1 is input to wiring 33. Signal SC1 has a high level and a low level. It is a digital signal. However, wiring 33 controls the continuity or non-continuity of transistor 211. It is sufficient that a signal or potential is input for this purpose. Also, signal SC2 is input to wiring 34. It is powered. Signal SC2 is a digital signal with high and low levels. However, The wiring 34 contains signals or potentials for controlling the conduction or non-conductivity of transistor 212. It's fine as long as it's entered.

[0167] When signal SC1 becomes high level and signal SC2 becomes low level, transistor 211 When it turns on, transistor 212 turns off. When transistor 211 turns on, The signal SP from wiring 17 is supplied to the first terminal of transistor 105.

[0168] On the other hand, when signal SC1 becomes low level and signal SC2 becomes high level, the transistor Transistor 211 turns off, and transistor 212 turns on. Transistor 212 turns on. Then, the signal RE from wiring 31 is supplied to the first terminal of transistor 105.

[0169] An example of the timing of signals SC1 and SC2 will be explained. If the shift direction is from sequential circuit 100[1] to sequential circuit 100[N], Signal SC1 becomes high level, and signal SC2 becomes low level. Also, the shift register rotation If the path shift direction is from sequential circuit 100[N] to sequential circuit 100[1], Signal SC1 becomes low level, and signal SC2 becomes high level.

[0170] Next, we will describe a configuration that includes transistors 213 and 214.

[0171] Figure 9(B) is a circuit diagram of a sequential circuit with transistors 213 and 214. Yes. The first terminal of transistor 213 is connected to the second terminal of transistor 105. The second terminal of transistor 213 is connected to the gate of transistor 103, and the transistor The gate of transistor 213 is connected to wiring 11. The first terminal of transistor 214 is connected to the transistor The second terminal of transistor 107 is connected to the second terminal of transistor 214, and the second terminal of transistor 1 The gate of transistor 214 is connected to wire 11, and the gate of transistor 214 is connected to wire 11.

[0172] By having transistor 213, the gate potential of transistor 103 rises. This prevents excessive wear and tear. Therefore, it is possible to suppress the degradation of transistor 103 or the breakdown of dielectric strength. This can help prevent damage and other problems.

[0173] Furthermore, by having transistor 214, the gate potential of transistor 101 is raised. This prevents the temperature from rising too high. Therefore, it suppresses the degradation of transistor 101 or This can help prevent dielectric breakdown, etc. It also reduces the Vgs of transistor 106. This allows for the suppression of the degradation of transistor 106.

[0174] Note that the gate of transistor 213 is connected to wires 12, 16, 17, and transistor 10 It may also be connected to the gate of 1, etc. Furthermore, the first terminal of transistor 213 may be connected to wiring 17. Furthermore, even if the second terminal of transistor 213 is connected to the first terminal of transistor 105 Okay.

[0175] Note that the gate of transistor 214 may be connected to wiring 12, wiring 16, etc. Also, the first terminal of transistor 214 may be connected to wiring 11, and the second terminal of transistor 214 may be connected to the first terminal of transistor 107.

[0176] Note that the gate of transistor 106 may be connected to the second terminal of transistor 104. .

[0177] Note that only one of transistor 213 and transistor 214 may be provided.

[0178] Next, a configuration in which a part of the transistor is replaced with a switch will be described.

[0179] FIG. 10(A) is a circuit diagram of a sequential circuit using switches as transistors 104, transistor 106, and transistor 107. Switches 104S, 106S, and 107S respectively correspond to transistors 104, 106, and transistor 107. Also, the first terminal of switch 104S is connected to wiring 13, and the second terminal of the switch 104S is connected to the gate of transistor 101. The first terminal of switch 106S is connected to wiring 13, and the second terminal of switch 106S is connected to wiring 14. The first terminal of switch 107S is connected to wiring 11, and the second terminal of switch 107S is connected to the gate of transistor 101.

[0180] During period T1, switch 104S turns off, switch 106S turns on, and s witch 107S turns on. Also, during period T2, switch 104S turns on Switch 106S turns off, and switch 107S turns off. Also, during period T3... Then, switch 104S turns off, switch 106S turns on, and switch 107 S is turned on. Also, during period T4, switch 104S is turned off, and switch 1 Switch 06S turns on, and switch 107S turns off.

[0181] Note that switch 104S may be turned on during period T1. Also, switch 106 S may be turned off during either period T3 or period T4. Also, switch 107S This may be turned on during period T4.

[0182] Figure 10(B) shows a basic circuit using switch 104S as transistor 104. This is a circuit diagram. Figure 11(A) shows the basic circuit of Figure 10(B) with a switch 106S added. This is a circuit diagram of the basic digit circuit. Also, Figure 11(B) shows the basic circuit of Figure 10(B) with a switch. This is a circuit diagram of the basic circuit with the Chi 107S installed.

[0183] Next, the functions of transistors 201 through 214 will be described.

[0184] Each of transistors 201 through 214 has a first terminal to which it is connected and a second terminal It has a function to control the conductivity or non-conductivity between the terminal and the destination to which it is connected. It has the function of supplying a signal or potential, etc., to the connection destination of the second terminal. For example, transistor 2 01 has the function of controlling the conductivity or non-conduction between wiring 13 and node N1. Also, potential V It has the function of supplying SS to node N1.

[0185] Furthermore, transistors 213 and 214 have a connection destination for the first terminal and a second terminal. After making the connection point conductive, the connection point of the first terminal and the connection point of the second terminal are made non-conductive. It has the function of supplying the signal or potential of the connection point of the first terminal to the connection point of the second terminal. After that, it has the function of stopping the supply of signals or potentials to the connected terminal of the first terminal. For example, Transistor 213 is connected to the second terminal of transistor 105 and the gate of transistor 103. After making it conductive, the second terminal of transistor 105 and the gate of transistor 103 are connected. It has the function of making it non-conductive. Also, the potential of the second terminal of transistor 105 is set at node N1 After supplying power, it has the function of stopping the supply of potential to the second terminal of transistor 105.

[0186] By the way, transistors 201 through 214 have the same pole as transistor 101. It is preferable that it be female.

[0187] Furthermore, the W / L of transistor 101 is the W / of transistors 201 to 214 It is preferable that it be larger than L.

[0188] This embodiment can be implemented in appropriate combination with other embodiments, etc.

[0189] (Embodiment 3) This embodiment describes a display device according to one aspect of the present invention.

[0190] Figure 12(A) is a circuit diagram of the display device of this embodiment. The display device in Figure 12(A) is Pixel unit 300, gate driver 301, gate driver 302, source driver 3 03 and has. The pixel section 300 has a plurality of pixels 310. These are transistor 311, transistor 312, display element 313, and circuit 32. It has 0 and . Note that the gate driver 302 is the same as in Embodiment 1 and Embodiment 2. A shift register circuit can be used.

[0191] In one embodiment of the present invention, the display element is a liquid crystal element (also called a liquid crystal display element). A light-emitting element (also called a light-emitting display element) can be used. The light-emitting element is powered by current or electricity. This category includes elements whose brightness is controlled by pressure, specifically inorganic EL (Ele). This includes (CTR Luminescence) elements, organic EL elements, etc. Also, electronic elements Display media where the contrast changes due to electrical effects, such as ink, can also be used.

[0192] Next, we will explain the connection relationships of the display device shown in Figure 12(A).

[0193] Gate driver 301 is connected to N wires 41. Gate driver 302 is connected to N wires It is connected to line 42. The source driver 303 is connected to M (M is a natural number) wires 43. Note that Figure 12(A) shows the i-th wire 41 out of N wires 41 (wire 41[i] (as shown), the i-th wire 42 out of N wires 42 (shown as wire 42[i]), M wires Of the lines 43, the jth (where j is one of 1 to M) wire 43 (indicated as wire 43[j]) To show.

[0194] Among multiple pixels 310, the pixel 310 belonging to the i-th row and j-th column (referred to as pixel 310[i,j]) The wire (su) is connected to wiring 41[i], wiring 42[i], wiring 43[j], and wiring 44.

[0195] In pixel 310[i, j], the first terminal of transistor 311 is connected to wiring 44. The gate of transistor 311 is connected to circuit 320. The first of transistor 312 The terminal is connected to the second terminal of transistor 311, and the second terminal of transistor 312 is The gate of transistor 312 is connected to wiring 42[i], and is connected to display element 313. Circuit 320 is also connected to wiring 43[j] and wiring 41[i].

[0196] Furthermore, voltage is input to wiring 44. Wiring 44 supplies the current that flows to the display element 313. It has the function of [doing something].

[0197] The gate driver 302 is the shift register circuit of Embodiment 1 and Embodiment 2. When using this, N wires 42 correspond to N wires 21. For example, wire 42[i] Corresponds to wiring 21[i].

[0198] Next, we will explain the operation of the display device shown in Figure 12(A).

[0199] The gate driver 301 sequentially outputs high-level signals to N wires 41. Driver 302 sequentially outputs low-level signals to N wires 42. Source driver 3 03 outputs the video signal to the M wire 43.

[0200] For example, in pixel 310[i, j], the gate driver 301 outputs a high-level signal via wiring 4 When output to 1[i], the video signal on wire 43[j] is written. This video signal is This is the video signal output by source driver 303 to wiring 43[j]. Subsequently, pixel 31 0[i, j] is where the gate driver 301 outputs a high-level signal to wiring 41[i] again. The video signal is held until the specified time, and a display corresponding to the video signal is performed.

[0201] Specifically, when the gate driver 301 outputs a high-level signal to wiring 41[i], The video signal is input to circuit 320. Circuit 320 uses transistor 311 to process the video signal. The corrected video signal is then transmitted after applying corrections based on the threshold voltage and / or mobility. The gate is supplied to transistor 311. Then, transistor 311 receives the corrected video signal. It becomes possible to supply current according to the number. However, if the video signal is received by circuit 320 The period during which the input is received, the period during which circuit 320 applies correction to the video signal, and / or circuit 32 During the initialization period before the video signal is input to 0, the current in transistor 311 is The values ​​are often incorrect. If this current is supplied to the display element, the grayscale will be distorted. This can cause blurring or blackening. Therefore, during the period mentioned above, gated Driver 302 outputs a low-level signal to wiring 42[i], which causes the transistor Turn off 312.

[0202] The gate driver 302 is the shift register circuit of Embodiment 1 and Embodiment 2. When using this, the gate driver 302 outputs signals to wiring 42[1] to wiring 42[N]. The numbers correspond to signals SOUTA[1] through SOUTA[N]. For example, gate dry The signal that b302 outputs to wiring 42[i] corresponds to signal SOUTA[i].

[0203] As shown in Figure 12(B), the connection point between transistor 311 and transistor 312 You can swap the positions.

[0204] The shift register circuits of Embodiment 1 and Embodiment 2 are used as the gate driver 302. By doing so, the gate driver 302 is made a transistor with the same polarity as the pixel transistor. This makes it possible to configure not only the gate driver 301, but also the gate driver 302 can be formed on the same substrate as the pixel section 300.

[0205] This embodiment can be implemented in appropriate combination with other embodiments.

[0206] (Embodiment 4) In this embodiment, the cross-sectional configuration of the pixels and driving circuit of a display device according to one aspect of the present invention is described below. Let's explain using an EL display device as an example.

[0207] Figure 13 is a cross-sectional view of the display device of this embodiment, showing the pixels 840 and the drive circuit 841. A view drawing is shown.

[0208] Pixel 840 comprises a light-emitting element 832 and a transistor that has the function of supplying current to the light-emitting element 832. It has a zista 831. The pixel 840 has a light-emitting element 832 and a transistor 831. In addition, a transistor that controls the input of the image signal to pixel 840, and / or the image signal It may have various semiconductor elements, such as capacitive elements that maintain the potential.

[0209] The drive circuit 841 includes transistor 830 and holds the gate voltage of transistor 830. It has a capacitive element 833 for this purpose. The drive circuit 841 is of Embodiment 1 or Embodiment 2. It covers basic circuits, sequential circuits, and shift register circuits, etc. Specifically, it covers transistor 8 30 corresponds to transistor 101, etc. Note that the drive circuit 841 corresponds to transistor 83 In addition to the 0 and capacitance element 833, it has various semiconductor elements such as transistors and capacitance elements. It's fine if you do that.

[0210] Transistor 831 has a conductive film that functions as a gate on a substrate 800 having an insulating surface. 816, the gate insulating film 802 on the conductive film 816, and at a position overlapping with the conductive film 816 A semiconductor film 817 located on the gate insulating film 802, and a source terminal or drain terminal It functions and has conductive films 815 and 818 located on the semiconductor film 817. The film 816 also functions as a scan line.

[0211] The transistor 830 has a conductive film that functions as a gate on a substrate 800 having an insulating surface. 812, the gate insulating film 802 on the conductive film 812, and at a position overlapping with the conductive film 812 A semiconductor film 813 located on the gate insulating film 802, and a source terminal or drain terminal It functions and has conductive films 814 and 819 located on the semiconductor film 813.

[0212] Capacitive element 833 is provided on a substrate 800 having an insulating surface, with a conductive film 812 and on the conductive film 812 The gate insulating film 802 and the conductive film 812 overlap at a position on the gate insulating film 802 It has a conductive film 819 placed on top.

[0213] On conductive films 814, 815, 818, and 819, there is an insulating film 820 and an insulating film The edge films 821 are arranged to be stacked in order. And on the insulating film 821, A conductive film 822 that functions as an electrode is provided. The conductive film 822 is an insulating film 820 and an insulating film The conductive film 818 is connected via a contact hole 823 formed in the edge film 821. ru.

[0214] An insulating film 824 having an opening that exposes a portion of the conductive film 822 is placed on the insulating film 821. It is provided. On a part of the conductive film 822 and on the insulating film 824, there is an EL layer 825 and a cathode and A conductive film 826 that functions as a conductive film is provided in a layered manner. The region where the EL layer 825 and the conductive film 826 overlap corresponds to the light-emitting element 832.

[0215] In one embodiment of the present invention, the transistor is amorphous, microcrystalline, polycrystalline, or single-crystal. A semiconductor such as silicon or germanium may be used in the semiconductor film, or acid Wide-bandgap semiconductors such as monoxide semiconductors may be used in the semiconductor film.

[0216] The semiconductor film of the transistor is made of amorphous, microcrystalline, polycrystalline, or single-crystal silicon or gelatin. When semiconductors such as luminium are used, one impurity element that imparts conductivity to the semiconductor is used. It is added to the film to form an impurity region that functions as a source or drain terminal. Example For example, by adding phosphorus or arsenic to the semiconductor film, an impurity region having n-type conductivity can be obtained. A region can be formed. Also, for example, by adding boron to the above semiconductor film, p A conductive impurity region of the type can be formed.

[0217] Furthermore, when an oxide semiconductor is used for the semiconductor film of a transistor, the dopant is the above-mentioned semiconductor. By adding to a conductive film, an impurity region is formed that functions as a source terminal or drain terminal. This is also acceptable. Dopant addition can be performed using ion implantation. Dopants are, for example, Noble gases such as helium, argon, and xenon, as well as nitrogen, phosphorus, arsenic, and antimony. Group 15 elements can be used. For example, if nitrogen is used as a dopant, The concentration of nitrogen atoms in the pure material region is 5 × 10⁻⁶ 19 / cm3 The above 1 x 10 22 / cm 3 Below It is desirable to have one.

[0218] Furthermore, silicon semiconductors are produced using vapor phase growth methods such as plasma CVD or sputtering. Amorphous silicon produced by the annealing method, amorphous silicon subjected to treatments such as laser annealing Hydrogen ions and other substances are implanted into polycrystalline silicon and single-crystal silicon wafers to form a crystallized surface layer. Single-crystal silicon from which a portion has been peeled off can be used.

[0219] Furthermore, the oxide semiconductor contains at least indium (In) or zinc (Zn). It is preferable to include In and Zn. Furthermore, using the oxide semiconductor As a stabilizer to reduce variations in the electrical characteristics of transistors, In addition, it is preferable to have gallium (Ga). Also, tin (S) as a stabilizer is preferable. It is preferable to have n). Also, it is preferable to have hafnium (Hf) as a stabilizer. It is preferable that the stabilizer be made of aluminum (Al). It's nice.

[0220] Also, other stabilizers include lanthanides such as lanthanum (La) and cerium ( Ce, praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), hol Mium (Ho), Erbium (Er), Thulium (Tm), Ytterbium (Yb), Lu It may contain one or more types of tecium (Lu).

[0221] For example, oxide semiconductors include indium oxide, tin oxide, zinc oxide, and In-Zn-based oxides. Substances, Sn-Zn oxides, Al-Zn oxides, Zn-Mg oxides, Sn-Mg oxides Materials, In-Mg oxides, In-Ga oxides, In-Ga-Zn oxides (IGZO and (Also written as), In-Al-Zn oxide, In-Sn-Zn oxide, Sn-Ga-Z n-based oxides, Al-Ga-Zn-based oxides, Sn-Al-Zn-based oxides, In-Hf-Zn In-La-Zn oxides, In-Ce-Zn oxides, In-Pr-Zn oxides Oxides, In-Nd-Zn oxides, In-Sm-Zn oxides, In-Eu-Zn acids In-Gd-Zn oxides, In-Tb-Zn oxides, In-Dy-Zn oxides Materials, In-Ho-Zn oxides, In-Er-Zn oxides, In-Tm-Zn oxides In-Yb-Zn oxides, In-Lu-Zn ​​oxides, In-Sn-Ga-Zn oxides In-Hf-Ga-Zn oxides, In-Al-Ga-Zn oxides, In-Sn -Al-Zn oxides, In-Sn-Hf-Zn oxides, In-Hf-Al-Zn acids A silicon oxide can be used. Furthermore, the oxide semiconductor may contain silicon.

[0222] For example, an In-Ga-Zn oxide is an oxide containing In, Ga, and Zn. This is about taste, and the ratio of In, Ga, and Zn is not important. Also, metal elements other than In, Ga, and Zn are not considered. It may contain. In-Ga-Zn oxides have sufficiently high resistance in the absence of an electric field and are off-electric. Because it can reduce the current sufficiently and also has high mobility, it is used in transistors. It is suitable as a semiconductor material.

[0223] For example, In:Ga:Zn = 1:1:1 (= 1 / 3:1 / 3:1 / 3) or In:G In-Ga-Zn system oxidation with atomic ratio a:Zn=2:2:1 (=2 / 5:2 / 5:1 / 5) Oxides with a similar composition to the substance can be used. Alternatively, In:Sn:Zn=1: 1:1(=1 / 3:1 / 3:1 / 3), In:Sn:Zn=2:1:3(=1 / 3:1 / 6:1 / 2) or In:Sn:Zn=2:1:5 (=1 / 4:1 / 8:5 / 8) It is advisable to use In-Sn-Zn oxides with a specific ratio or oxides with a similar composition.

[0224] For example, high mobility can be obtained relatively easily with In-Sn-Zn oxides. However, Furthermore, even with In-Ga-Zn oxides, mobility can be increased by reducing the bulk defect density. It is possible to do so.

[0225] Furthermore, impurities such as water or hydrogen, which act as electron donors, are reduced, and acid Purified oxide semiconductors (purified Oxi) are achieved by reducing elemental defects. A de Semiconductor is an i-type (intrinsic semiconductor) or very close to an i-type. Therefore, transistors using the above-mentioned oxide semiconductor have the characteristic of having a remarkably low off-current. It has the following characteristics. Furthermore, the band gap of the oxide semiconductor is 2 eV or more, preferably 2.5 eV. More preferably, the voltage is 3 eV or higher. The concentration of impurities such as water or hydrogen is sufficiently reduced. Furthermore, by reducing oxygen deficiency, a highly purified oxide semiconductor film is used. This allows the transistor's off-current to be reduced.

[0226] Specifically, transistors using highly purified oxide semiconductors as semiconductor films have a low off-current. This can be proven through various experiments. For example, if the channel width is 1 × 10⁻⁶ 6 micrometers Even with an element with a channel length of 10 μm, the voltage between the source terminal and the drain terminal (drain voltage) When the voltage is in the range of 1V to 10V, the off-current is measured by a semiconductor parameter analyzer. Below the limit, i.e., 1 × 10⁻⁶ -13 It is possible to obtain the characteristic of being A or less. In this case, The off-current density, which corresponds to the value obtained by dividing the f-current by the transistor's channel width, is 100 Hz. It can be seen that it is less than / μm. Also, by connecting the capacitive element and the transistor, the capacitive element Using a circuit that controls the charge flowing into or out of a capacitive element with the transistor, Current density was measured. In this measurement, the above transistor was subjected to highly purified oxide semiconductor By using a conductive film as the channel formation region, the change in the amount of charge per unit time of the capacitive element is used to determine the channel The off-current density of the transistor was measured. The results showed the source terminal and drain of the transistor. When the voltage across the terminals is 3V, an even lower off-current density of several tens of yA / μm can be obtained. It was found that a highly purified oxide semiconductor film was used in the channel formation region. The off-current of the transistor is significantly different compared to transistors using crystalline silicon. It's very low.

[0227] In this specification, off-current refers to the current in an n-channel transistor. With the input terminal at a higher potential than the source terminal and gate, the potential of the source terminal is When the gate potential is 0 or less when used as a reference, between the source terminal and the drain terminal It refers to the current that flows. Also, in a p-channel transistor, the off-current and This is when the drain terminal is at a lower potential than the source terminal and gate, and the source terminal When the gate potential is greater than or equal to the potential of the source terminal and drain terminal, It refers to the electric current flowing between the particles.

[0228] For example, oxide semiconductor films include In (indium), Ga (gallium), and Zn ( It can be formed by sputtering using a target containing zinc. When depositing a Zn-based oxide semiconductor film by sputtering, preferably, the atomic ratio is In :Ga:Zn=1:1:1, 4:2:3, 3:1:2, 1:1:2, 2:1:3, or A target of an In-Ga-Zn oxide system, represented by the ratio 3:1:4, is used. To deposit an oxide semiconductor film using an In-Ga-Zn-based oxide target having the following properties. This makes it easier for polycrystalline or CAAC (described later) to form. Also, In, Ga, and Zn The filling rate of the target including is 90% to 100%, preferably 95% to 100%. It is complete. By using a target with a high packing density, the deposited oxide semiconductor film is dense. It forms a membrane.

[0229] Furthermore, when using an In-Zn-based oxide material as the oxide semiconductor film, the target to be used The composition, in terms of atomic ratio, is In:Zn = 50:1 to 1:2 (which translates to In2O in terms of mole ratio). 3:ZnO = 25:1 to 1:4), preferably In:Zn = 20:1 to 1:1 (molar ratio) Converted to this ratio, In2O3:ZnO = 10:1 to 1:2), and more preferably In:Zn = 1.5:1 to 15:1 (converted to a mole ratio of In2O3:ZnO = 3:4 to 15:2) For example, the target used to form an oxide semiconductor film which is an In-Zn-based oxide is When the atomic ratio is In:Zn:O=X:Y:Z, assume Z>1.5X+Y. Ratio of Zn By keeping it within the above range, it is possible to improve mobility.

[0230] Specifically, the oxide semiconductor film is processed by holding the substrate in a processing chamber that is kept under reduced pressure, and then processing... While removing residual moisture in the laboratory, sputtered gas from which hydrogen and moisture have been removed is introduced, and the above-mentioned It can be formed using a film-forming agent. During film formation, the substrate temperature should be between 100°C and 600°C. Alternatively, the temperature may be between 200°C and 400°C. By depositing the film while heating the substrate... This allows for a reduction in the impurity concentration contained in the deposited oxide semiconductor film. Damage caused by tarring is reduced. To remove residual moisture in the processing chamber, an adsorption type It is preferable to use a vacuum pump. For example, a cryopump, ion pump, or titanium pump. It is preferable to use a breech pump. Furthermore, a turbopump is preferred as the exhaust means. A cold trap may be added to the system. The deposition chamber is evacuated using a cryopump. Then, for example, hydrogen atoms, water (H2O) and other compounds containing hydrogen atoms (more preferably carbon Because compounds containing elementary atoms are also exhausted, the oxide semiconductor film deposited in the processing chamber contains The concentration of impurities can be reduced.

[0231] Furthermore, in oxide semiconductor films formed by sputtering, etc., there may be water or hydrogen as an impurity. It may contain a large amount of (hydroxyl groups). Water or hydrogen forms donor levels. Because it is easily oxidized, it is an impurity for oxide semiconductors. Therefore, in one aspect of the present invention, To reduce impurities such as water or hydrogen in a semiconductor film (dehydration or dehydrogenation) For oxide semiconductor films, under reduced pressure, under an inert gas atmosphere such as nitrogen or a rare gas, acid Under a gas atmosphere or in ultra-dry air (CRDS (cavity ring-down laser spectroscopy) The moisture content measured using a dew point meter of the ) type is 20 ppm or less (equivalent to a dew point of -55°C). The heat treatment is performed in an atmosphere (preferably 1 ppm or less, preferably 10 ppb or less of air) To administer.

[0232] By applying heat treatment to the oxide semiconductor film, water or hydrogen is removed from the oxide semiconductor film. This is possible. Specifically, a substrate at 250°C to 750°C, preferably 400°C or higher. The heat treatment should be performed at a temperature below the strain point. For example, 500°C for 3 minutes to 6 minutes. It should be done to a certain extent. If the RTA method is used for heat treatment, dehydration or dehydrogenation can be performed in a short time. Therefore, processing can be performed even at temperatures exceeding the strain point of the glass substrate.

[0233] Furthermore, the above heat treatment causes oxygen to be removed from the oxide semiconductor film, and oxygen remains in the oxide semiconductor film. Defects may be formed. Therefore, in one aspect of the present invention, the g An insulating film containing oxygen is used as the insulating film, such as a galvanic insulating film. After forming the film, heat treatment is applied to supply oxygen from the insulating film to the oxide semiconductor film. This configuration reduces the oxygen vacancies that serve as donors and is contained in the oxide semiconductor film. The oxide semiconductor can satisfy the stoichiometric composition. As a result, the oxide semiconductor film This makes it possible to bring it closer to type i, reducing variations in the electrical characteristics of transistors due to oxygen deficiency. This can reduce the noise and improve electrical characteristics.

[0234] Furthermore, the heat treatment to supply oxygen to the oxide semiconductor film is performed using nitrogen, ultra-dry air, or dilute air. In a gaseous atmosphere (such as argon or helium), preferably at a temperature of 200°C to 400°C. The following steps should be performed at a temperature (for example, between 250°C and 350°C). The gas used should have a water content of 20 ppm. The following is preferably 1 ppm or less, and more preferably 10 ppb or less.

[0235] Oxide semiconductor films can be single crystals, polycrystalline (also called polycrystals), or amorphous. To act in a certain manner.

[0236] Preferably, the oxide semiconductor film is CAAC-OS(C Axis Aligned Cr The film is a ystalline oxide semiconductor film.

[0237] Furthermore, the crystalline portion is often small enough to fit within a cube with sides less than 100 nm in size. Also, a transmission electron microscope (TEM) In the image observed using an icroscope, the amorphous and crystalline parts contained in the CAAC-OS film are visible. The boundary between the crystal and the crystalline parts is not clear. Also, CAAC-O No clear grain boundaries (also called grain boundaries) can be observed in the S film. Therefore, C The AAC-OS film suppresses the decrease in electron mobility caused by grain boundaries.

[0238] The crystalline portion contained in the CAAC-OS film has a c-axis that is the normal vector to the surface on which the CAAC-OS film is formed. Aligned in a direction parallel to the normal vector of the plane or surface, and triangular when viewed from a direction perpendicular to the ab plane. Having a shape or hexagonal atomic arrangement, the metal atoms are layered or when viewed from a direction perpendicular to the c-axis. Metal atoms and oxygen atoms are arranged in layers. Furthermore, between different crystalline regions, the a-axis is... The orientation of the b-axis may be different. In this specification, when simply referred to as vertical, 8 The range of 5° to 95° is also included. Furthermore, when simply describing something as parallel, -5 This will include the range of 5° to 5°.

[0239] Furthermore, the distribution of crystalline regions in the CAAC-OS film does not need to be uniform. For example, CAA In the formation process of a C-OS film, when crystal growth is performed from the surface side of the oxide semiconductor film, the shape The proportion of crystalline material may be higher near the surface compared to near the surface of the material. Also, CA By adding impurities to the AC-OS film, the crystalline region in the impurity-added area becomes amorphous. It can also become qualitative.

[0240] The c-axis of the crystalline portion contained in the CAAC-OS film is the normal vector to the surface on which the CAAC-OS film is formed. Because it aligns in a direction parallel to the normal vector of the surface or the material, the shape of the CAAC-OS film (formed Depending on the cross-sectional shape of the surface or face, they may face in different directions. Oh, the direction of the c-axis of the crystalline portion is the normal vector to the surface on which the CAAC-OS film was formed. The direction is parallel to the normal vector of the crystalline or surface. The crystalline portion is formed by deposition, and It is formed by performing crystallization treatments such as heat treatment after film formation.

[0241] Transistors using CAAC-OS film exhibit changes in electrical properties due to irradiation with visible light and ultraviolet light. Its value is small. Therefore, this transistor is highly reliable.

[0242] Furthermore, some of the oxygen constituting the oxide semiconductor film may be replaced with nitrogen.

[0243] Next, an example of a specific configuration of a transistor according to one aspect of the present invention will be described.

[0244] The transistor shown in Figure 14(A) is a bottom-gate type with a channel etch structure.

[0245] The transistor shown in Figure 14(A) has a gate electrode 16 formed on an insulating surface. 02, gate insulating film 1603 on gate electrode 1602, and on gate insulating film 1603 The semiconductor film 1604 overlaps with the gate electrode 1602, and is formed on the semiconductor film 1604. It has conductive films 1605 and 1606. Furthermore, the transistor has a semiconductor film 1604, conductive film 1605 and insulating film 1607 formed on conductive film 1606, its structure It may be included as a component.

[0246] Furthermore, the transistor shown in Figure 14(A) is in an insulating position where it overlaps with the semiconductor film 1604. The device may further have a back gate electrode formed on the edge film 1607.

[0247] The transistor shown in Figure 14(B) is a bottom-gate type with a channel protection structure.

[0248] The transistor shown in Figure 14(B) has a gate electrode 1612 formed on an insulating surface, and A gate insulating film 1613 on the gate electrode 1612, and a gate insulating film 1613 on the gate A semiconductor film 1614 overlapping the electrode 1612, and a chain formed on the semiconductor film 1614. Nell protective film 1618, conductive film 1615 and conductive film 161 formed on semiconductor film 1614 It has 6. Furthermore, the transistor has a channel protection film 1618, a conductive film 1615 and An insulating film 1617 formed on the conductive film 1616 may also be included as a component.

[0249] Furthermore, the transistor shown in Figure 14(B) is in an insulating position where it overlaps with the semiconductor film 1614. The device may further have a back gate electrode formed on the edge film 1617.

[0250] By providing the channel protection film 1618, the channel formation region of the semiconductor film 1614 and In subsequent processes, the film formed by plasma or etching agent during etching of certain parts This prevents damage such as wear and tear. Therefore, it improves the reliability of transistors. It is possible.

[0251] The transistor shown in Figure 14(C) is a bottom-gate type with a bottom-contact structure.

[0252] The transistor shown in Figure 14(C) has a gate electrode 1622 formed on an insulating surface, and A gate insulating film 1623 on the gate electrode 1622, and a conductive film 162 on the gate insulating film 1623 5. The conductive film 1626 and the gate electrode 1622 overlap on the gate insulating film 1623. Furthermore, it has a conductive film 1625 and a semiconductor film 1624 formed on the conductive film 1626. Furthermore, the transistor has conductive film 1625, conductive film 1626, and semiconductor film 162 The insulating film 1627 formed on 4 may also be included as a component.

[0253] Furthermore, the transistor shown in Figure 14(C) is in an insulating position where it overlaps with the semiconductor film 1624. The device may further have a back gate electrode formed on the edge film 1627.

[0254] The transistor shown in Figure 14(D) is a top-gate type with a bottom-contact structure.

[0255] The transistor shown in Figure 14(D) has conductive film 1645 and conductive film 1 formed on the insulating surface. 646, an insulating surface and conductive film 1645, and a semiconductor film 164 formed on the conductive film 1646. 4 and gate insulation formed on semiconductor film 1644, conductive film 1645 and conductive film 1646 The film 1643 and the gate that overlaps with the semiconductor film 1644 on the gate insulating film 1643. It has an electrode 1642. Furthermore, the transistor is formed on the gate electrode 1642 An insulating film 1647 may be included as a component.

[0256] The transistors of this embodiment are used in the basic circuits, sequential circuits, and of Embodiment 1 and Embodiment 2. Transistors constituting a shift register circuit, and components of the display device of Embodiment 3 It can be used in transistors. In particular, transistors using oxide semiconductors have high mobility. The voltage is high and the off-current is low. Therefore, the basic circuits and sequential circuits of Embodiment 1 and Embodiment 2 are high. The path and shift register circuit, as well as the display device of Embodiment 3, can be operated at high speed. It is possible to reduce the amount of charge leaking from each node.

[0257] This embodiment can be implemented in appropriate combination with other embodiments.

[0258] (Embodiment 5) A basic circuit, sequential circuit, shift register circuit, and display device according to one aspect of the present invention are shown in the table. Image playback device equipped with display devices, personal computers, and recording media (typically DVDs): Playback of recording media such as Digital Versatile Discs and display of their images. It can be used in a device having a display capable of doing so. In addition, in one aspect of the present invention Electrical equipment that can use the following basic circuits, sequential circuits, shift register circuits, and display devices. As sub-devices, these include mobile phones, game consoles (including portable models), personal digital assistants, e-readers, and video cameras. Digital still cameras, goggle-type displays (head-mounted displays), Navigation systems, audio playback devices (car audio, digital audio players) - etc.), photocopiers, fax machines, printers, multifunction printers, ATMs Examples include ATMs and vending machines. Specific examples of these electronic devices are shown in Figure 15.

[0259] Figure 15(A) shows a portable game console, comprising a casing 5001, casing 5002, display unit 5003, Display unit 5004, microphone 5005, speaker 5006, operation keys 5007, stand It has illustrations such as Illustra 5008. Note that the portable game console shown in Figure 15(A) has two displays. It has a section 5003 and a display section 5004, but the number of display sections a portable game console has is This is not limited to this.

[0260] Figure 15(B) shows a display device, which includes a housing 5201, a display unit 5202, a support base 5203, etc. The display devices include those for personal computers, TV broadcast reception, and advertising displays. This includes all information display devices.

[0261] Figure 15(C) shows a notebook personal computer, consisting of a casing 5401 and a display unit 5402. It includes a keyboard 5403, a pointing device 5404, and the like.

[0262] Figure 15(D) shows a portable information terminal, consisting of a first housing 5601, a second housing 5602, and a first display unit. It includes 5603, a second display unit 5604, a connection unit 5605, an operation key 5606, etc. Table 1 The display unit 5603 is provided in the first housing 5601, and the second display unit 5604 is provided in the second housing 56 It is located at 02. And the first housing 5601 and the second housing 5602 are connected at the connection part 56 They are connected by 05, and the angle between the first housing 5601 and the second housing 5602 is the connection part It is made movable by 5605. The video switching in the first display unit 5603 is connected Switching according to the angle between the first housing 5601 and the second housing 5602 in section 5605 It can also be configured in a way that allows for this.

[0263] Figure 15(E) is a mobile phone, consisting of a housing 5801, a display unit 5802, an audio input unit 5803, It has an audio output unit 5804, an operation key 5805, a light receiving unit 5806, etc. By converting the received light into an electrical signal, external images can be captured.

[0264] This embodiment can be implemented in appropriate combination with other embodiments. [Explanation of Symbols]

[0265] 11 Wiring 12 Wiring 13 Wiring 14 Wiring 15 Wiring 16 Wiring 17 Wiring 21 Wiring 22 Wiring 23 Wiring 24 Wiring 25 Wiring 26 Wiring 27 Wiring 31 Wiring 32 Wiring 33 Wiring 34 Wiring 41 Wiring 42 Wiring 43 Wiring 44 Wiring 100 sequential circuits 101 Transistors 102 transistors 103 Transistors 104 transistors 104S Switch 105 transistors 106 transistors 106S Switch 107 transistors 107S Switch 201 Transistors 202 transistors 203 Transistors 204 transistors 205 transistors 206 transistors 207 transistors 208 transistors 209 transistors 210 transistors 211 transistors 212 transistors 213 transistors 214 transistors 300 pixel section 301 Gate Driver 302 Gate Driver 303 Source Driver 310 pixels 311 transistors 312 transistors 313 Display element 320 circuits 800 circuit boards 802 Gate Insulator 812 Conductive film 813 Semiconductor film 814 Conductive film 815 Conductive film 816 Conductive film 817 Semiconductor film 818 Conductive film 819 Conductive film 820 Insulating film 821 Insulating film 822 Conductive film 823 Contact Hole 824 Insulating film 825 EL layer 826 Conductive film 830 transistors 831 Transistors 832 Light-emitting element 833 Capacitive element 840 pixels 841 Drive Circuit 1602 Gate Shuttle 1603 Gate Insulator 1604 Semiconductor film 1605 Conductive film 1606 Conductive film 1607 Insulating film 1612 Shuttle gate 1613 Gate insulating film 1614 Semiconductor film 1615 Conductive film 1616 Conductive film 1617 Insulating film 1618 Channel protective film 1622 Gate 1623 Gate insulating film 1624 Semiconductor film 1625 Conductive film 1626 Conductive film 1627 Insulating film 1642 Shutdown gate 1643 Gate insulating film 1644 Semiconductor film 1645 Conductive film 1646 Conductive film 1647 Insulating film 5001 enclosure 5002 enclosure 5003 Display section 5004 Display section 5005 Microphone 5006 Speaker 5007 Operation Keys 5008 Stylus 5201 enclosure 5202 Display section 5203 Support stand 5401 enclosure 5402 Display section 5403 Keyboard 5404 Pointing device 5601 enclosure 5602 enclosure 5603 Display section 5604 Display section 5605 Connection part 5606 Operation Keys 5801 enclosure 5802 Display section 5803 Voice Input Section 5804 Audio output section 5805 Operation Keys 5806 Light receiving section CK1 signal CK2 signal N1 node N2 node SC1 signal SC2 signal SCK1 signal SCK2 signal T1 period T2 period T3 period T4 period VN1 potential VN2 Potential VDD potential VSS potential SP signal SSP signal OUTA signal OUTB signal SOUTA signal SOUTB signal RE signal INI signal

Claims

1. Having a gate driver, The gate driver comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, and a ninth transistor. The source or drain of the first transistor is electrically connected to the source or drain of the second transistor. Either the source or the drain of the first transistor is electrically connected to the first wiring. The source or drain of the first transistor, the other of which is electrically connected to the first power line, The source or drain of the second transistor, the other of which is electrically connected to the second power line, Either the source or the drain of the third transistor is electrically connected to the gate of the first transistor. The gate of the third transistor is electrically connected to the first power line. Either the source or drain of the fourth transistor is electrically connected to either the source or drain of the fifth transistor. The source or drain of the fourth transistor is electrically connected to the other source or drain of the third transistor. The gate of the fourth transistor is electrically connected to the second wiring, The source or drain of the fifth transistor, the other of which is electrically connected to the second power line, The source or drain of the sixth transistor is electrically connected to the source or drain of the seventh transistor. Either the source or the drain of the sixth transistor is electrically connected to the gate of the second transistor. The source or drain of the sixth transistor, the other of which is electrically connected to the second power line, The gate of the sixth transistor is electrically connected to the gate of the first transistor. The source or drain of the seventh transistor, the other of which is electrically connected to the third wiring, Either the source or drain of the eighth transistor is electrically connected to the gate of the seventh transistor. The gate of the eighth transistor is electrically connected to the first power line. The source or drain of the ninth transistor is electrically connected to the other source or drain of the eighth transistor. The gate of the ninth transistor is electrically connected to the second wiring. The first clock signal is input to the second wiring. A display device to which the second clock signal is input is connected to the third wiring.

2. Having a gate driver, The gate driver comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, and a ninth transistor. The source or drain of the first transistor is electrically connected to the source or drain of the second transistor. Either the source or the drain of the first transistor is electrically connected to the first wiring. The source or drain of the first transistor, the other of which is electrically connected to the first power line, The source or drain of the second transistor, the other of which is electrically connected to the second power line, Either the source or the drain of the third transistor is electrically connected to the gate of the first transistor. The gate of the third transistor is electrically connected to the first power line. Either the source or drain of the fourth transistor is electrically connected to either the source or drain of the fifth transistor. The source or drain of the fourth transistor is electrically connected to the other source or drain of the third transistor. The gate of the fourth transistor is electrically connected to the second wiring, The source or drain of the fifth transistor, the other of which is electrically connected to the second power line, The source or drain of the sixth transistor is electrically connected to the source or drain of the seventh transistor. Either the source or the drain of the sixth transistor is electrically connected to the gate of the second transistor. The source or drain of the sixth transistor, the other of which is electrically connected to the second power line, The gate of the sixth transistor is electrically connected to the gate of the first transistor. The source or drain of the seventh transistor, the other of which is electrically connected to the third wiring, Either the source or drain of the eighth transistor is electrically connected to the gate of the seventh transistor. The gate of the eighth transistor is electrically connected to the first power line. The source or drain of the ninth transistor is electrically connected to the other source or drain of the eighth transistor. The gate of the ninth transistor is electrically connected to the second wiring. The first clock signal is input to the second wiring. The third wiring is connected to the second clock signal. The W / L (W is the channel width, L is the channel length) of the first transistor is greater than the W / L of the third transistor. The W / L of the first transistor is greater than the W / L of the fourth transistor. The W / L of the first transistor is greater than the W / L of the fifth transistor. The W / L of the first transistor is greater than the W / L of the sixth transistor. The W / L of the first transistor is greater than the W / L of the seventh transistor. The W / L of the first transistor is greater than the W / L of the eighth transistor. The W / L of the first transistor is greater than the W / L of the ninth transistor. A display device in which the W / L of the second transistor is greater than the W / L of the fifth transistor.

3. comprising a gate driver and a pixel, The gate driver comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, and a ninth transistor. The source or drain of the first transistor is electrically connected to the source or drain of the second transistor. Either the source or the drain of the first transistor is electrically connected to the first wiring. The source or drain of the first transistor, the other of which is electrically connected to the first power line, The source or drain of the second transistor, the other of which is electrically connected to the second power line, Either the source or the drain of the third transistor is electrically connected to the gate of the first transistor. The gate of the third transistor is electrically connected to the first power line. Either the source or drain of the fourth transistor is electrically connected to either the source or drain of the fifth transistor. The source or drain of the fourth transistor is electrically connected to the other source or drain of the third transistor. The gate of the fourth transistor is electrically connected to the second wiring, The source or drain of the fifth transistor, the other of which is electrically connected to the second power line, The source or drain of the sixth transistor is electrically connected to the source or drain of the seventh transistor. Either the source or the drain of the sixth transistor is electrically connected to the gate of the second transistor. The source or drain of the sixth transistor, the other of which is electrically connected to the second power line, The gate of the sixth transistor is electrically connected to the gate of the first transistor. The source or drain of the seventh transistor, the other of which is electrically connected to the third wiring, Either the source or drain of the eighth transistor is electrically connected to the gate of the seventh transistor. The gate of the eighth transistor is electrically connected to the first power line. The source or drain of the ninth transistor is electrically connected to the other source or drain of the eighth transistor. The gate of the ninth transistor is electrically connected to the second wiring. The first clock signal is input to the second wiring. The third wiring is connected to the second clock signal. The pixel comprises a tenth transistor, an eleventh transistor, and a light-emitting element. The source or drain of the 10th transistor is electrically connected to the source or drain of the 11th transistor. The source or drain of the 11th transistor is electrically connected to the light-emitting element. The gate of the eleventh transistor is electrically connected to the first wiring in the display device.

4. comprising a gate driver and a pixel, The gate driver comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, and a ninth transistor. The source or drain of the first transistor is electrically connected to the source or drain of the second transistor. Either the source or the drain of the first transistor is electrically connected to the first wiring. The source or drain of the first transistor, the other of which is electrically connected to the first power line, The source or drain of the second transistor, the other of which is electrically connected to the second power line, Either the source or the drain of the third transistor is electrically connected to the gate of the first transistor. The gate of the third transistor is electrically connected to the first power line. Either the source or drain of the fourth transistor is electrically connected to either the source or drain of the fifth transistor. The source or drain of the fourth transistor is electrically connected to the other source or drain of the third transistor. The gate of the fourth transistor is electrically connected to the second wiring, The source or drain of the fifth transistor, the other of which is electrically connected to the second power line, The source or drain of the sixth transistor is electrically connected to the source or drain of the seventh transistor. Either the source or the drain of the sixth transistor is electrically connected to the gate of the second transistor. The source or drain of the sixth transistor, the other of which is electrically connected to the second power line, The gate of the sixth transistor is electrically connected to the gate of the first transistor. The source or drain of the seventh transistor, the other of which is electrically connected to the third wiring, Either the source or drain of the eighth transistor is electrically connected to the gate of the seventh transistor. The gate of the eighth transistor is electrically connected to the first power line. The source or drain of the ninth transistor is electrically connected to the other source or drain of the eighth transistor. The gate of the ninth transistor is electrically connected to the second wiring. The first clock signal is input to the second wiring. The third wiring is connected to the second clock signal. The W / L (W is the channel width, L is the channel length) of the first transistor is greater than the W / L of the third transistor. The W / L of the first transistor is greater than the W / L of the fourth transistor. The W / L of the first transistor is greater than the W / L of the fifth transistor. The W / L of the first transistor is greater than the W / L of the sixth transistor. The W / L of the first transistor is greater than the W / L of the seventh transistor. The W / L of the first transistor is greater than the W / L of the eighth transistor. The W / L of the first transistor is greater than the W / L of the ninth transistor. The W / L of the second transistor is greater than the W / L of the fifth transistor. The pixel comprises a tenth transistor, an eleventh transistor, and a light-emitting element. The source or drain of the 10th transistor is electrically connected to the source or drain of the 11th transistor. The source or drain of the 11th transistor is electrically connected to the light-emitting element. The gate of the eleventh transistor is electrically connected to the first wiring in the display device.

5. Having a gate driver, The gate driver comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, and a switch. The source or drain of the first transistor is electrically connected to the source or drain of the second transistor. Either the source or the drain of the first transistor is electrically connected to the first wiring. The source or drain of the first transistor, the other of which is electrically connected to the first power line, The source or drain of the second transistor, the other of which is electrically connected to the second power line, Either the source or the drain of the third transistor is electrically connected to the gate of the first transistor. The gate of the third transistor is electrically connected to the first power line. Either the source or the drain of the fourth transistor is electrically connected to the first terminal of the switch. The source or drain of the fourth transistor is electrically connected to the other source or drain of the third transistor. The gate of the fourth transistor is electrically connected to the second wiring, The second terminal of the switch is electrically connected to the second power line. The source or drain of the fifth transistor is electrically connected to the source or drain of the sixth transistor. Either the source or the drain of the fifth transistor is electrically connected to the gate of the second transistor. The source or drain of the fifth transistor, the other of which is electrically connected to the second power line, The gate of the fifth transistor is electrically connected to the gate of the first transistor. The source or drain of the sixth transistor, the other of which is electrically connected to the third wiring, Either the source or drain of the seventh transistor is electrically connected to the gate of the sixth transistor. The gate of the seventh transistor is electrically connected to the first power line. The source or drain of the eighth transistor is electrically connected to the other source or drain of the seventh transistor. The gate of the eighth transistor is electrically connected to the second wiring. The first clock signal is input to the second wiring. A display device to which the second clock signal is input is connected to the third wiring.

6. Having a gate driver, The gate driver comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, and a switch. The source or drain of the first transistor is electrically connected to the source or drain of the second transistor. Either the source or the drain of the first transistor is electrically connected to the first wiring. The source or drain of the first transistor, the other of which is electrically connected to the first power line, The source or drain of the second transistor, the other of which is electrically connected to the second power line, Either the source or the drain of the third transistor is electrically connected to the gate of the first transistor. The gate of the third transistor is electrically connected to the first power line. Either the source or the drain of the fourth transistor is electrically connected to the first terminal of the switch. The source or drain of the fourth transistor is electrically connected to the other source or drain of the third transistor. The gate of the fourth transistor is electrically connected to the second wiring, The second terminal of the switch is electrically connected to the second power line. The source or drain of the fifth transistor is electrically connected to the source or drain of the sixth transistor. Either the source or the drain of the fifth transistor is electrically connected to the gate of the second transistor. The source or drain of the fifth transistor, the other of which is electrically connected to the second power line, The gate of the fifth transistor is electrically connected to the gate of the first transistor. The source or drain of the sixth transistor, the other of which is electrically connected to the third wiring, Either the source or drain of the seventh transistor is electrically connected to the gate of the sixth transistor. The gate of the seventh transistor is electrically connected to the first power line. The source or drain of the eighth transistor is electrically connected to the other source or drain of the seventh transistor. The gate of the eighth transistor is electrically connected to the second wiring. The first clock signal is input to the second wiring. The third wiring is connected to the second clock signal. The W / L (W is the channel width, L is the channel length) of the first transistor is greater than the W / L of the third transistor. The W / L of the first transistor is greater than the W / L of the fourth transistor. The W / L of the first transistor is greater than the W / L of the fifth transistor. The W / L of the first transistor is greater than the W / L of the sixth transistor. The W / L of the first transistor is greater than the W / L of the seventh transistor. A display device in which the W / L of the first transistor is greater than the W / L of the eighth transistor.

7. comprising a gate driver and a pixel, The gate driver comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, and a switch. The source or drain of the first transistor is electrically connected to the source or drain of the second transistor. Either the source or the drain of the first transistor is electrically connected to the first wiring. The source or drain of the first transistor, the other of which is electrically connected to the first power line, The source or drain of the second transistor, the other of which is electrically connected to the second power line, Either the source or the drain of the third transistor is electrically connected to the gate of the first transistor. The gate of the third transistor is electrically connected to the first power line. Either the source or the drain of the fourth transistor is electrically connected to the first terminal of the switch. The source or drain of the fourth transistor is electrically connected to the other source or drain of the third transistor. The gate of the fourth transistor is electrically connected to the second wiring, The second terminal of the switch is electrically connected to the second power line. The source or drain of the fifth transistor is electrically connected to the source or drain of the sixth transistor. Either the source or the drain of the fifth transistor is electrically connected to the gate of the second transistor. The source or drain of the fifth transistor, the other of which is electrically connected to the second power line, The gate of the fifth transistor is electrically connected to the gate of the first transistor. The source or drain of the sixth transistor, the other of which is electrically connected to the third wiring, Either the source or drain of the seventh transistor is electrically connected to the gate of the sixth transistor. The gate of the seventh transistor is electrically connected to the first power line. The source or drain of the eighth transistor is electrically connected to the other source or drain of the seventh transistor. The gate of the eighth transistor is electrically connected to the second wiring. The first clock signal is input to the second wiring. The third wiring is connected to the second clock signal. The pixel comprises a ninth transistor, a tenth transistor, and a light-emitting element. The source or drain of the ninth transistor is electrically connected to the source or drain of the tenth transistor. The source or drain of the 10th transistor is electrically connected to the light-emitting element. The gate of the tenth transistor is electrically connected to the first wiring in the display device.

8. comprising a gate driver and a pixel, The gate driver comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, and a switch. The source or drain of the first transistor is electrically connected to the source or drain of the second transistor. Either the source or the drain of the first transistor is electrically connected to the first wiring. The source or drain of the first transistor, the other of which is electrically connected to the first power line, The source or drain of the second transistor, the other of which is electrically connected to the second power line, Either the source or the drain of the third transistor is electrically connected to the gate of the first transistor. The gate of the third transistor is electrically connected to the first power line. Either the source or the drain of the fourth transistor is electrically connected to the first terminal of the switch. The source or drain of the fourth transistor is electrically connected to the other source or drain of the third transistor. The gate of the fourth transistor is electrically connected to the second wiring, The second terminal of the switch is electrically connected to the second power line. The source or drain of the fifth transistor is electrically connected to the source or drain of the sixth transistor. Either the source or the drain of the fifth transistor is electrically connected to the gate of the second transistor. The source or drain of the fifth transistor, the other of which is electrically connected to the second power line, The gate of the fifth transistor is electrically connected to the gate of the first transistor. The source or drain of the sixth transistor, the other of which is electrically connected to the third wiring, Either the source or drain of the seventh transistor is electrically connected to the gate of the sixth transistor. The gate of the seventh transistor is electrically connected to the first power line. The source or drain of the eighth transistor is electrically connected to the other source or drain of the seventh transistor. The gate of the eighth transistor is electrically connected to the second wiring. The first clock signal is input to the second wiring. The third wiring is connected to the second clock signal. The W / L (W is the channel width, L is the channel length) of the first transistor is greater than the W / L of the third transistor. The W / L of the first transistor is greater than the W / L of the fourth transistor. The W / L of the first transistor is greater than the W / L of the fifth transistor. The W / L of the first transistor is greater than the W / L of the sixth transistor. The W / L of the first transistor is greater than the W / L of the seventh transistor. The W / L of the first transistor is greater than the W / L of the eighth transistor. The pixel comprises a ninth transistor, a tenth transistor, and a light-emitting element. The source or drain of the ninth transistor is electrically connected to the source or drain of the tenth transistor. The source or drain of the 10th transistor is electrically connected to the light-emitting element. The gate of the tenth transistor is electrically connected to the first wiring in the display device.

9. Having a gate driver, The gate driver comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, and a ninth transistor. The source or drain of the first transistor is electrically connected to the source or drain of the second transistor. Either the source or the drain of the first transistor is electrically connected to the first wiring. The source or drain of the first transistor, the other of which is electrically connected to the first power line, The source or drain of the second transistor, the other of which is electrically connected to the second power line, Either the source or the drain of the third transistor is electrically connected to the gate of the first transistor. The gate of the third transistor is electrically connected to the first power line. Either the source or drain of the fourth transistor is electrically connected to either the source or drain of the fifth transistor. The source or drain of the fourth transistor is electrically connected to the other source or drain of the third transistor. The gate of the fourth transistor is electrically connected to the second wiring, The source or drain of the fifth transistor, the other of which is electrically connected to the second power line, The source or drain of the sixth transistor is electrically connected to the source or drain of the seventh transistor. Either the source or the drain of the sixth transistor is electrically connected to the gate of the second transistor. The source or drain of the sixth transistor, the other of which is electrically connected to the second power line, The gate of the sixth transistor is electrically connected to the gate of the first transistor. The source or drain of the seventh transistor, the other of which is electrically connected to the third wiring, Either the source or drain of the eighth transistor is electrically connected to the gate of the seventh transistor. The gate of the eighth transistor is input to the same potential as the first power line. The source or drain of the ninth transistor is electrically connected to the other source or drain of the eighth transistor. The gate of the ninth transistor is electrically connected to the second wiring. The first clock signal is input to the second wiring. A display device to which the second clock signal is input is connected to the third wiring.

10. Having a gate driver, The gate driver comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, and a ninth transistor. The source or drain of the first transistor is electrically connected to the source or drain of the second transistor. Either the source or the drain of the first transistor is electrically connected to the first wiring. The source or drain of the first transistor, the other of which is electrically connected to the first power line, The source or drain of the second transistor, the other of which is electrically connected to the second power line, Either the source or the drain of the third transistor is electrically connected to the gate of the first transistor. The gate of the third transistor is electrically connected to the first power line. Either the source or drain of the fourth transistor is electrically connected to either the source or drain of the fifth transistor. The source or drain of the fourth transistor is electrically connected to the other source or drain of the third transistor. The gate of the fourth transistor is electrically connected to the second wiring, The source or drain of the fifth transistor, the other of which is electrically connected to the second power line, The source or drain of the sixth transistor is electrically connected to the source or drain of the seventh transistor. Either the source or the drain of the sixth transistor is electrically connected to the gate of the second transistor. The source or drain of the sixth transistor, the other of which is electrically connected to the second power line, The gate of the sixth transistor is electrically connected to the gate of the first transistor. The source or drain of the seventh transistor, the other of which is electrically connected to the third wiring, Either the source or drain of the eighth transistor is electrically connected to the gate of the seventh transistor. The gate of the eighth transistor is input to the same potential as the first power line. The source or drain of the ninth transistor is electrically connected to the other source or drain of the eighth transistor. The gate of the ninth transistor is electrically connected to the second wiring. The first clock signal is input to the second wiring. The third wiring is connected to the second clock signal. The W / L (W is the channel width, L is the channel length) of the first transistor is greater than the W / L of the third transistor. The W / L of the first transistor is greater than the W / L of the fourth transistor. The W / L of the first transistor is greater than the W / L of the fifth transistor. The W / L of the first transistor is greater than the W / L of the sixth transistor. The W / L of the first transistor is greater than the W / L of the seventh transistor. The W / L of the first transistor is greater than the W / L of the eighth transistor. The W / L of the first transistor is greater than the W / L of the ninth transistor. A display device in which the W / L of the second transistor is greater than the W / L of the fifth transistor.

11. comprising a gate driver and a pixel, The gate driver comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, and a ninth transistor. The source or drain of the first transistor is electrically connected to the source or drain of the second transistor. Either the source or the drain of the first transistor is electrically connected to the first wiring. The source or drain of the first transistor, the other of which is electrically connected to the first power line, The source or drain of the second transistor, the other of which is electrically connected to the second power line, Either the source or the drain of the third transistor is electrically connected to the gate of the first transistor. The gate of the third transistor is electrically connected to the first power line. Either the source or drain of the fourth transistor is electrically connected to either the source or drain of the fifth transistor. The source or drain of the fourth transistor is electrically connected to the other source or drain of the third transistor. The gate of the fourth transistor is electrically connected to the second wiring, The source or drain of the fifth transistor, the other of which is electrically connected to the second power line, The source or drain of the sixth transistor is electrically connected to the source or drain of the seventh transistor. Either the source or the drain of the sixth transistor is electrically connected to the gate of the second transistor. The source or drain of the sixth transistor, the other of which is electrically connected to the second power line, The gate of the sixth transistor is electrically connected to the gate of the first transistor. The source or drain of the seventh transistor, the other of which is electrically connected to the third wiring, Either the source or drain of the eighth transistor is electrically connected to the gate of the seventh transistor. The gate of the eighth transistor is input to the same potential as the first power line. The source or drain of the ninth transistor is electrically connected to the other source or drain of the eighth transistor. The gate of the ninth transistor is electrically connected to the second wiring. The first clock signal is input to the second wiring. The third wiring is connected to the second clock signal. The pixel comprises a tenth transistor, an eleventh transistor, and a light-emitting element. The source or drain of the 10th transistor is electrically connected to the source or drain of the 11th transistor. The source or drain of the 11th transistor is electrically connected to the light-emitting element. The gate of the eleventh transistor is electrically connected to the first wiring in the display device.

12. comprising a gate driver and a pixel, The gate driver comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, and a ninth transistor. The source or drain of the first transistor is electrically connected to the source or drain of the second transistor. Either the source or the drain of the first transistor is electrically connected to the first wiring. The source or drain of the first transistor, the other of which is electrically connected to the first power line, The source or drain of the second transistor, the other of which is electrically connected to the second power line, Either the source or the drain of the third transistor is electrically connected to the gate of the first transistor. The gate of the third transistor is electrically connected to the first power line. Either the source or drain of the fourth transistor is electrically connected to either the source or drain of the fifth transistor. The source or drain of the fourth transistor is electrically connected to the other source or drain of the third transistor. The gate of the fourth transistor is electrically connected to the second wiring, The source or drain of the fifth transistor, the other of which is electrically connected to the second power line, The source or drain of the sixth transistor is electrically connected to the source or drain of the seventh transistor. Either the source or the drain of the sixth transistor is electrically connected to the gate of the second transistor. The source or drain of the sixth transistor, the other of which is electrically connected to the second power line, The gate of the sixth transistor is electrically connected to the gate of the first transistor. The source or drain of the seventh transistor, the other of which is electrically connected to the third wiring, Either the source or drain of the eighth transistor is electrically connected to the gate of the seventh transistor. The gate of the eighth transistor is input to the same potential as the first power line. The source or drain of the ninth transistor is electrically connected to the other source or drain of the eighth transistor. The gate of the ninth transistor is electrically connected to the second wiring. The first clock signal is input to the second wiring. The third wiring is connected to the second clock signal. The W / L (W is the channel width, L is the channel length) of the first transistor is greater than the W / L of the third transistor. The W / L of the first transistor is greater than the W / L of the fourth transistor. The W / L of the first transistor is greater than the W / L of the fifth transistor. The W / L of the first transistor is greater than the W / L of the sixth transistor. The W / L of the first transistor is greater than the W / L of the seventh transistor. The W / L of the first transistor is greater than the W / L of the eighth transistor. The W / L of the first transistor is greater than the W / L of the ninth transistor. The W / L of the second transistor is greater than the W / L of the fifth transistor. The pixel comprises a tenth transistor, an eleventh transistor, and a light-emitting element. The source or drain of the 10th transistor is electrically connected to the source or drain of the 11th transistor. The source or drain of the 11th transistor is electrically connected to the light-emitting element. The gate of the eleventh transistor is electrically connected to the first wiring in the display device.

13. Having a gate driver, The gate driver comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, and a switch. The source or drain of the first transistor is electrically connected to the source or drain of the second transistor. Either the source or the drain of the first transistor is electrically connected to the first wiring. The source or drain of the first transistor, the other of which is electrically connected to the first power line, The source or drain of the second transistor, the other of which is electrically connected to the second power line, Either the source or the drain of the third transistor is electrically connected to the gate of the first transistor. The gate of the third transistor is electrically connected to the first power line. Either the source or the drain of the fourth transistor is electrically connected to the first terminal of the switch. The source or drain of the fourth transistor is electrically connected to the other source or drain of the third transistor. The gate of the fourth transistor is electrically connected to the second wiring, The second terminal of the switch is electrically connected to the second power line. The source or drain of the fifth transistor is electrically connected to the source or drain of the sixth transistor. Either the source or the drain of the fifth transistor is electrically connected to the gate of the second transistor. The source or drain of the fifth transistor, the other of which is electrically connected to the second power line, The gate of the fifth transistor is electrically connected to the gate of the first transistor. The source or drain of the sixth transistor, the other of which is electrically connected to the third wiring, Either the source or drain of the seventh transistor is electrically connected to the gate of the sixth transistor. The gate of the seventh transistor is input to the same potential as the first power supply line. The source or drain of the eighth transistor is electrically connected to the other source or drain of the seventh transistor. The gate of the eighth transistor is electrically connected to the second wiring. The first clock signal is input to the second wiring. A display device to which the second clock signal is input is connected to the third wiring.

14. Having a gate driver, The gate driver comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, and a switch. The source or drain of the first transistor is electrically connected to the source or drain of the second transistor. Either the source or the drain of the first transistor is electrically connected to the first wiring. The source or drain of the first transistor, the other of which is electrically connected to the first power line, The source or drain of the second transistor, the other of which is electrically connected to the second power line, Either the source or the drain of the third transistor is electrically connected to the gate of the first transistor. The gate of the third transistor is electrically connected to the first power line. Either the source or the drain of the fourth transistor is electrically connected to the first terminal of the switch. The source or drain of the fourth transistor is electrically connected to the other source or drain of the third transistor. The gate of the fourth transistor is electrically connected to the second wiring, The second terminal of the switch is electrically connected to the second power line. The source or drain of the fifth transistor is electrically connected to the source or drain of the sixth transistor. Either the source or the drain of the fifth transistor is electrically connected to the gate of the second transistor. The source or drain of the fifth transistor, the other of which is electrically connected to the second power line, The gate of the fifth transistor is electrically connected to the gate of the first transistor. The source or drain of the sixth transistor, the other of which is electrically connected to the third wiring, Either the source or drain of the seventh transistor is electrically connected to the gate of the sixth transistor. The gate of the seventh transistor is input to the same potential as the first power supply line. The source or drain of the eighth transistor is electrically connected to the other source or drain of the seventh transistor. The gate of the eighth transistor is electrically connected to the second wiring. The first clock signal is input to the second wiring. The third wiring is connected to the second clock signal. The W / L (W is the channel width, L is the channel length) of the first transistor is greater than the W / L of the third transistor. The W / L of the first transistor is greater than the W / L of the fourth transistor. The W / L of the first transistor is greater than the W / L of the fifth transistor. The W / L of the first transistor is greater than the W / L of the sixth transistor. The W / L of the first transistor is greater than the W / L of the seventh transistor. A display device in which the W / L of the first transistor is greater than the W / L of the eighth transistor.

15. comprising a gate driver and a pixel, The gate driver comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, and a switch. The source or drain of the first transistor is electrically connected to the source or drain of the second transistor. Either the source or the drain of the first transistor is electrically connected to the first wiring. The source or drain of the first transistor, the other of which is electrically connected to the first power line, The source or drain of the second transistor, the other of which is electrically connected to the second power line, Either the source or the drain of the third transistor is electrically connected to the gate of the first transistor. The gate of the third transistor is electrically connected to the first power line. Either the source or the drain of the fourth transistor is electrically connected to the first terminal of the switch. The source or drain of the fourth transistor is electrically connected to the other source or drain of the third transistor. The gate of the fourth transistor is electrically connected to the second wiring, The second terminal of the switch is electrically connected to the second power line. The source or drain of the fifth transistor is electrically connected to the source or drain of the sixth transistor. Either the source or the drain of the fifth transistor is electrically connected to the gate of the second transistor. The source or drain of the fifth transistor, the other of which is electrically connected to the second power line, The gate of the fifth transistor is electrically connected to the gate of the first transistor. The source or drain of the sixth transistor, the other of which is electrically connected to the third wiring, Either the source or drain of the seventh transistor is electrically connected to the gate of the sixth transistor. The gate of the seventh transistor is input to the same potential as the first power supply line. The source or drain of the eighth transistor is electrically connected to the other source or drain of the seventh transistor. The gate of the eighth transistor is electrically connected to the second wiring. The first clock signal is input to the second wiring. The third wiring is connected to the second clock signal. The pixel comprises a ninth transistor, a tenth transistor, and a light-emitting element. The source or drain of the ninth transistor is electrically connected to the source or drain of the tenth transistor. The source or drain of the 10th transistor is electrically connected to the light-emitting element. The gate of the tenth transistor is electrically connected to the first wiring in the display device.

16. comprising a gate driver and a pixel, The gate driver comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, and a switch. The source or drain of the first transistor is electrically connected to the source or drain of the second transistor. Either the source or the drain of the first transistor is electrically connected to the first wiring. The source or drain of the first transistor, the other of which is electrically connected to the first power line, The source or drain of the second transistor, the other of which is electrically connected to the second power line, Either the source or the drain of the third transistor is electrically connected to the gate of the first transistor. The gate of the third transistor is electrically connected to the first power line. Either the source or the drain of the fourth transistor is electrically connected to the first terminal of the switch. The source or drain of the fourth transistor is electrically connected to the other source or drain of the third transistor. The gate of the fourth transistor is electrically connected to the second wiring, The second terminal of the switch is electrically connected to the second power line. The source or drain of the fifth transistor is electrically connected to the source or drain of the sixth transistor. Either the source or the drain of the fifth transistor is electrically connected to the gate of the second transistor. The source or drain of the fifth transistor, the other of which is electrically connected to the second power line, The gate of the fifth transistor is electrically connected to the gate of the first transistor. The source or drain of the sixth transistor, the other of which is electrically connected to the third wiring, Either the source or drain of the seventh transistor is electrically connected to the gate of the sixth transistor. The gate of the seventh transistor is input to the same potential as the first power supply line. The source or drain of the eighth transistor is electrically connected to the other source or drain of the seventh transistor. The gate of the eighth transistor is electrically connected to the second wiring. The first clock signal is input to the second wiring. The third wiring is connected to the second clock signal. The W / L (W is the channel width, L is the channel length) of the first transistor is greater than the W / L of the third transistor. The W / L of the first transistor is greater than the W / L of the fourth transistor. The W / L of the first transistor is greater than the W / L of the fifth transistor. The W / L of the first transistor is greater than the W / L of the sixth transistor. The W / L of the first transistor is greater than the W / L of the seventh transistor. The W / L of the first transistor is greater than the W / L of the eighth transistor. The pixel comprises a ninth transistor, a tenth transistor, and a light-emitting element. The source or drain of the ninth transistor is electrically connected to the source or drain of the tenth transistor. The source or drain of the 10th transistor is electrically connected to the light-emitting element. The gate of the tenth transistor is electrically connected to the first wiring in the display device.

17. In any one of Claim 1, Claim 2, Claim 9, or Claim 10, The first to ninth transistors are N-channel type transistors in the display device.

18. In any one of Claim 3, Claim 4, Claim 11, or Claim 12, The first to eleventh transistors are N-channel type transistors in a display device.

19. In any one of Claim 5, Claim 6, Claim 13, or Claim 14, The first to eighth transistors are N-channel type transistors in the display device.

20. In any one of Claim 7, Claim 8, Claim 15, or Claim 16, The first to tenth transistors are N-channel type transistors in a display device.

21. In any one of Claims 1 to 20, A display device in which the potential of the first power line is higher than the potential of the second power line.

22. In any one of Claim 1, Claim 2, Claim 9, or Claim 10, The first to ninth transistors are P-channel type transistors in the display device.

23. In any one of Claim 3, Claim 4, Claim 11, or Claim 12, The first to eleventh transistors are P-channel type transistors in a display device.

24. In any one of Claim 5, Claim 6, Claim 13, or Claim 14, The first to eighth transistors are P-channel type transistors in the display device.

25. In any one of Claim 7, Claim 8, Claim 15, or Claim 16, The first to tenth transistors are P-channel type transistors in a display device.

26. In any one of claims 1 to 16 or claims 22 to 25, A display device in which the potential of the second power line is higher than the potential of the first power line.

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