Solid-state image sensor and imaging device
The CMOS-type image sensor optimizes signal-to-noise ratio by using a specific layer configuration and impurity concentration to enhance image quality in stacked photoelectric conversion and charge multiplication layers.
Patent Information
- Authority / Receiving Office
- JP · JP
- Patent Type
- Patents
- Current Assignee / Owner
- NIPPON HOSO KYOKAI
- Filing Date
- 2022-02-18
- Publication Date
- 2026-07-02
Smart Images
Figure 0007883860000002 
Figure 0007883860000003 
Figure 0007883860000004
Abstract
Description
[Technical Field]
[0001] The present invention relates to a solid-state image sensor and an imaging device, and more specifically, to a solid-state image sensor and an imaging device capable of capturing high-quality images, comprising a photoelectric conversion layer and charge multiplier stacked type photoelectric conversion unit. [Background technology]
[0002] Conventionally, in solid-state image sensors, such as CMOS image sensors, pixel reset noise has been suppressed by combining a 4-transistor type pixel with an analog CDS (see Non-Patent Document 1 below) to enable the capture of high-quality images with low noise, and technological development for improving image quality has been advanced.
[0003] Furthermore, the miniaturization of pixel size has led to a reduction in the area of the photoelectric conversion unit that converts light into electrical signals, which has resulted in decreased sensitivity. To improve sensitivity, structures with stacked photoelectric conversion films that have excellent charge multiplication properties are attracting attention, and research and development are underway (see Non-Patent Document 2 below). In such solid-state image sensors with stacked photoelectric conversion layers and charge multiplication layers that have both photoelectric conversion and charge multiplication functions, there is a known type in which each unit pixel is of the 3-transistor type (see Patent Document 1 below).
[0004] A conventional 3-transistor pixel with a photoelectric conversion layer and charge multiplier stacked structure will be described using its band diagram. For convenience, the band diagram shown in Figure 6, which is used in the embodiment, will be used for this explanation. Figure 6 shows the photoelectric conversion layer and charge multiplication layer 305, the n-type stray diffusion capacitance (FD) 313, and the P-type substrate 301. The photoelectric conversion layer and charge multiplication layer 305 is configured to use the holes from the electron-hole pairs generated by photoelectric conversion as mobile carriers within the film (see Patent Document 2 below). It is known that with this configuration, charge multiplication by avalanche occurs in the photoelectric conversion layer and charge multiplication layer 305 (see Non-Patent Document 2 below). [Prior art documents]
Patent Document
[0005]
Patent Document 1
Patent Document 2
Non-Patent Document
[0006]
Non-Patent Document 1
Non-Patent Document 2
Summary of the Invention
Problems to be Solved by the Invention
[0007] In the case of the pixel according to the above-described conventional technology, it is required to improve the signal-to-noise ratio of the output of the image sensor. For this purpose, it is important to improve the signal-to-noise ratio under the generation conditions of the avalanche multiplication effect of the photoelectric conversion layer and charge multiplication layer.
[0008] The present invention has been made in view of the above circumstances, and aims to provide a solid-state image sensor and imaging device that can improve the signal-to-noise ratio under conditions for avalanche multiplication in each pixel of a 3-transistor type stacked photoelectric conversion layer and charge multiplication layer. [Means for solving the problem]
[0009] The present invention relates to ru koto The body image sensor is, A CMOS-type solid-state image sensor equipped with photoelectric conversion means consisting of a laminate including a photoelectric conversion layer and a charge multiplier layer arranged on a pixel circuit, The photoelectric conversion means is equipped with a stray diffusion capacitor that converts the signal charge generated into a signal voltage, The suspended diffusion capacity is configured to be placed in a well provided on the substrate. The floating diffusion capacitance is made of an n-type semiconductor, the well is made of a p-type semiconductor, the conductivity type of the substrate is either n-type or p-type, and the pixel electrode is connected to the floating diffusion capacitance. The photoelectric conversion means comprises an electron injection blocking layer, a photoelectric conversion layer and charge multiplication layer, a hole injection blocking layer, and a film electrode, each layer stacked in this order on the pixel electrode. The film electrode is configured to apply a positive voltage to the reset voltage applied to the pixel electrode, and to use the holes among the electron-hole pairs generated by photoelectric conversion as the traveling carriers of the photoelectric conversion means. The impurity concentration of the aforementioned photoelectric conversion layer and charge multiplier layer is set to 1 × 10 16 cm -3 It is configured as follows: 、 The voltage applied to the photoelectric conversion layer and charge multiplication layer is set based on the voltage at which the current density saturates during light irradiation, and is set to a voltage at which the signal current becomes 10 times the current density at which the current density saturates. It is characterized by the following.
[0010] Also, The impurity concentration of the aforementioned photoelectric conversion layer and charge multiplier layer is 1 × 10⁻¹⁶ 16 cm -3 The following values represent impurity concentrations of 1 × 10⁻⁶. 16 cm -3 It is preferable that the characteristic is that the signal current to dark current shot noise ratio decreases when it exceeds a certain value.
[0011] In addition, it is preferable that the pixel circuit includes three transistors: a reset transistor disposed between the floating diffusion capacitance and a reset power supply, a source follower amplifier transistor having a gate electrode connected to the floating diffusion capacitance, and a selection transistor having a gate electrode to which a drive waveform for selecting a pixel is input.
[0012] In addition, the imaging device of the present invention is characterized by including the solid-state imaging device according to any one of the above, and means for outputting the image information obtained by this solid-state imaging device.
Effects of the Invention
[0013] In the solid-state imaging device and the imaging device using the same according to the present invention, the conductivity type of the floating diffusion capacitance is n-type, the conductivity type of the well is p-type, the conductivity type of the substrate is composed of n-type or p-type, and the impurity concentration of the photoelectric conversion layer and charge multiplication layer is 1×10 ru koto cm 16 cm -3 or less, and is configured such that holes among the electron-hole pairs generated by photoelectric conversion in the photoelectric conversion layer and charge multiplication layer are used as traveling carriers, and a positive voltage is applied to the film electrode with reference to the pixel electrode.
[0015] In the solid-state imaging device and the imaging device using the same according to the above ta solid a voltage necessary for generating avalanche multiplication is applied to the film electrode, and since the photoelectric conversion layer and charge multiplication layer is depleted, carriers have moved and are absent. There is a space charge with a fixed position in the photoelectric conversion layer and charge multiplication layer, and since the impurity concentration is 1×10 16 cm -3 or less and is low, the amount of charge of the space charge is small. Therefore, the change in the electric field strength in the film is poor, and the slope of the band diagram is almost uniform. Among the electron-hole pairs generated by photoelectric conversion , positive holes ,eachIt moves as a traveling carrier within the film. Using the current value at which the amount of carriers generated by photoelectric conversion saturates as the reference value, the signal current value and dark current value are derived at the voltage value at which the signal current value becomes 10 times the reference value due to avalanche multiplication, and the value of the signal current to dark current shot noise is calculated, and the impurity concentration of the photoelectric conversion layer and charge multiplication layer is 1 × 10⁻⁶ 16 cm -3 By setting the value to the following low level, the ratio of signal current to dark current shot noise can be improved.
[0016] Therefore, the impurity concentration of the photoelectric conversion layer and charge multiplication layer should be 1 × 10⁻⁶ 16 cm -3 By setting the parameters as follows, the signal-to-noise ratio of the image sensor output can be improved. [Brief explanation of the drawing]
[0017] [Figure 1] This figure schematically shows the configuration of a solid-state image sensor according to an embodiment of the present invention. [Figure 2] This is a circuit diagram showing the equivalent circuit of a 3-transistor type pixel circuit in a solid-state image sensor equipped with a photoelectric conversion layer and charge multiplication layer according to the embodiment. [Figure 3] This shows a time chart of the signals input to the pixel circuit when a signal readout is performed in the solid-state image sensor according to the embodiment. [Figure 4] This is a schematic diagram showing the energy bands at timings (a), (b), (c), and (d) of the signal time chart shown in Figure 3, in the solid-state image sensor according to the embodiment. [Figure 5] This is a schematic cross-sectional view of the pixel portion of a solid-state image sensor according to an embodiment. [Figure 6] Figure 5 shows the band diagram in the AA' line cross-section, illustrating the state at the time of reset. [Figure 7] Figure 6 shows the relationship between the potential and depth from the surface when a voltage is applied in the photoelectric conversion layer and charge multiplier layer of the solid-state image sensor according to the embodiment shown, comparing the cases when the impurity concentration of the photoelectric conversion layer and charge multiplier layer is changed. [Figure 8] Figure 7 shows the relationship between the potential and depth from the surface when a voltage is applied in the photoelectric conversion layer and charge multiplier layer of the solid-state image sensor of the embodiment shown, and the relationship between the electric field strength and depth from the surface, superimposed on this figure. [Figure 9] This figure shows, superimposed on the relationship between the potential and depth from the surface when a voltage is applied in the photoelectric conversion layer and charge multiplication layer of the solid-state image sensor shown in the embodiment of Figure 7, and the relationship between the carrier generation rate and depth from the surface when incident light is irradiated. [Figure 10] Figure 7 shows the relationship between applied voltage and current density in the photoelectric conversion layer and charge multiplication layer of the solid-state image sensor according to the embodiment shown. [Figure 11] Figure 10 shows the relationship between applied voltage and current density in the photoelectric conversion layer and charge multiplication layer of the solid-state image sensor of the embodiment shown, where the signal current ratio to dark current shot noise is calculated from the signal current value and dark current value at a voltage value where the signal current becomes 10 times the saturation current, and this is shown in relation to the impurity concentration. [Figure 12] Figure 11 is a diagram summarizing the relevant numerical values regarding the relationship between impurity concentration and the ratio of signal current to dark current shot noise. [Modes for carrying out the invention]
[0018] Hereinafter, a solid-state image sensor and an imaging device using the same, according to embodiments of the present invention, will be described with reference to the drawings. In this embodiment, an example is shown in which the carriers of the photoelectric conversion film (referred to as "photoelectric conversion means" in the claims) are holes, the floating diffusion capacitance is of type n, the well is of type p, and the substrate is of type p (it can also be of type n). In this embodiment, the photoelectric conversion film (320: see Figure 5) consists of a laminate formed by stacking multiple layers, including a photoelectric conversion layer and a charge multiplication layer (305: see Figure 5). Furthermore, the same effect can be achieved even when the solid-state image sensor of this embodiment uses electrons as the carriers of the photoelectric conversion film, has a p-type stray diffusion capacitance, has an n-type well, and has a p-type or n-type substrate.
[0019] (Embodiment) Figure 1 shows the pixel array 101 of the unit pixels that form the basis of the solid-state image sensor in this embodiment, and specifically, it is a system configuration diagram of a CMOS type solid-state image sensor 100. The CMOS type solid-state image sensor 100 has a pixel array 101 in which unit pixels 102 including photoelectric conversion elements are arranged in a two-dimensional array and connected to pixel drive wiring 103 and vertical signal lines 104. The peripheral circuits consist of a column-parallel signal processing circuit 105, an output circuit 106, a timing control circuit 107, a horizontal scanning circuit 108, and a vertical scanning circuit 109. The column-parallel signal processing circuit 105 is configured to include an analog-to-digital converter (ADC).
[0020] Here, the reason why the column-parallel signal processing circuit 105 and the horizontal scanning circuit 108 are arranged at the top and bottom of Figure 1 is that, compared to when they are arranged on one side, it is possible to arrange one column-parallel signal processing circuit per column of unit pixels while doubling the layout width of the column-parallel signal processing circuit 105 to the width of the unit pixel.
[0021] The imaging device according to the embodiment of the present invention includes, for example, a solid-state image sensor 100 as shown in Figure 1, and further includes a signal output unit that outputs signals from, for example, an output circuit 106 to the outside either as is or converted into a desired signal format. It is an imaging device in a broad sense that includes, for example, cameras and sensors.
[0022] Figure 2 shows the equivalent circuit diagram of a unit pixel 102 used in the solid-state image sensor according to this embodiment. The equivalent circuit of the unit pixel 102 according to this embodiment shown in Figure 2 is an nMOS3 transistor type unit pixel 102 circuit configuration in which the pixel circuit that reads the signal charge from the photoelectric conversion film (PL) 220 consists of an n-type stray diffusion capacitance (FD) 213, a reset transistor (RT) 214, a source follower amplifier transistor (SF) 215, a selection transistor (SL) 216, a pixel output (OUT) 217, a source follower amplifier transistor power supply (SFVDD) 222, and a reset transistor power supply (RTVDD) 223.
[0023] As shown in Figure 2, the lower electrode of the photoelectric conversion film (PL) 220 is connected to an n-type stray diffusion capacitor (FD) 213 through a via (VIA) 227. A reset transistor (RT) 214 for resetting the n-type stray diffusion capacitor (FD) 213 is connected between the n-type stray diffusion capacitor (FD) 213 and the reset transistor power supply (RTVDD) 223. The n-type stray diffusion capacitor (FD) 213 is connected to the gate electrode of a source follower amplifier transistor (SF) 215. The source follower amplifier transistor (SF) 215 and a selection transistor (SL) 216 are connected between the source follower amplifier transistor power supply (SFVDD) 222 and the pixel output (OUT) 217. Figure 2 shows a pixel circuit of a unit pixel 102 using an nMOS3 transistor type, but a circuit configuration with an additional feedback reset function may also be used.
[0024] Figure 3 shows the time chart of the input signals in the pixel circuit of the unit pixel 102 according to this embodiment. Specifically, it shows the time chart of the input signals of the selection transistor (SL) 216 and the n-type stray diffusion capacitance reset transistor (RT) 214. Furthermore, the symbols (1), (2), (n), etc., after these labels indicate which row of the pixel array 101 in Figure 1 it represents. The figure also shows a time chart of the sampling timing of the analog-to-digital converter (ADC). Finally, it describes the calculations used to reduce reset noise in the digital correlated double sampling circuit (DCDS). Figure 4 shows schematic diagrams of the energy bands at each timing (a), (b), (c), and (d) in Figure 3.
[0025] The timing in (a) in Figures 3 and 4 indicates that charge accumulation is occurring. A positive voltage is applied to the upper electrode (film electrode) of the photoelectric conversion film (PL) 220, with the voltage of the reset transistor power supply (RTVDD) 223 as the reference. Signal charge holes are generated in the photoelectric conversion film (PL) 220, and these signal charge holes move from the photoelectric conversion film (PL) 220 through the VIA 227 to the n-type stray diffusion capacitance (FD) 213. Signal charge holes accumulate in the n-type stray diffusion capacitance (FD) 213, and the potential increases.
[0026] At timing (b), the selection transistor (SL) 216 is turned on to select the pixel, the signal charge stored in the n-type stray diffusion capacitor (FD) 213 is read out, and the analog value is converted to a digital value in the analog-to-digital converter (ADC). At timing (c), the reset transistor (RT) 214 is turned on, and the n-type stray diffusion capacitance (FD) 213 is reset to the voltage value of the reset transistor power supply (RTVDD) 223. At timing (d), the reset transistor (RT) 214 is turned off. Also, the reset noise mixed into the n-type stray diffusion capacitance (FD) 213 is read out and converted from an analog value to a digital value in the analog-to-digital converter (ADC).
[0027] In Figure 3, after the reset of unit pixel 102 in the first row of frame M-1, the value of the reset noise is read out. The time until the first row of frame M is read out constitutes one accumulation time. Subsequently, unit pixel 102 is selected, and the signal with the superimposed reset noise is converted from analog to digital and read out. Since the reset noise is the same in the value obtained by converting the signal with the superimposed reset noise in the first row of frame M to analog to digital and in the value obtained by converting the reset noise in the first row of frame M-1 to analog to digital, the reset noise can be canceled out by digital correlation double sampling processing outside the sensor, and only the signal can be separated and extracted (see Japanese Patent Application Publication No. 2015-167343).
[0028] Figure 5 shows a schematic cross-sectional view of the pixel structure of the solid-state image sensor according to this embodiment. This solid-state image sensor is formed by stacking photoelectric conversion films 320 on a pixel circuit. The photoelectric conversion film 320 has a structure in which an electron injection blocking layer (thickness, for example, 20 nm) 307, a photoelectric conversion layer and charge multiplication layer (thickness, for example, 300 nm) 305, a hole injection blocking layer (thickness, for example, 20 nm) 304, and a film electrode (thickness, for example, 30 nm) 306 made of an ITO layer are stacked in this order. Furthermore, the pixel circuit is constructed by forming a p-type well 302 on a p-type substrate 301 and forming an n-type MOS transistor section within the p-type well 302. The pixel electrode 303 is electrically connected to an n-type stray diffusion capacitor 313. The gate electrode of a reset transistor 314 is connected between the n-type stray diffusion capacitor 313 and a reset transistor power supply 323. In addition, an insulating layer 309 is provided between the p-type substrate 301 and the pixel electrode 303.
[0029] Figure 6 is a band diagram of the AA' line cross-section in Figure 5, showing the state at the time of reset. The band diagram in Figure 6 is a relative potential diagram showing the state inside the pixel, and for the hole injection blocking layer 304, the photoelectric conversion layer and charge multiplication layer 305, the electron injection blocking layer 307, and the n-type stray diffusion capacitance 313 and the p-type substrate 301 (silicon semiconductor material), the lower edge of the conduction band and the upper edge of the valence band are shown. Furthermore, the potential between the pixel electrode 303 and the n-type stray diffusion capacitance 313 is 2.3V, which is the reset voltage when the n-type stray diffusion capacitance 313 is reset. The potential of the film electrode (ITO layer) 306 is 15.3V, and +13.0V is applied based on the reset voltage of the pixel electrode 303, with the mobile carriers within the film being holes.
[0030] By placing a hole injection blocking layer 304 between the film electrode 306 and the photoelectric conversion layer / charge multiplication layer 305, the injection of holes from the film electrode 306 into the photoelectric conversion layer / charge multiplication layer 305 is prevented. By placing an electron injection blocking layer 307 between the pixel electrode 303 and the photoelectric conversion layer / charge multiplication layer 305, the injection of electrons from the pixel electrode 303 into the photoelectric conversion layer / charge multiplication layer 305 is prevented. By placing an n-type floating diffusion capacitance 313 between the pixel electrode 303 and the p-type substrate 301, the movement of electrons from the pixel electrode 303 to the p-type substrate 301 is prevented.
[0031] The following describes a method for improving the ratio of signal current to dark current shot noise in this embodiment. The configuration of this embodiment will be explained using Figure 7. In a structure in which the electron injection blocking layer 307, the photoelectric conversion layer and charge multiplication layer 305, the hole injection blocking layer 304, and the film electrode 306 are stacked on the pixel electrode 303 in this order, this is a schematic band diagram when a voltage of 15V is applied to the film electrode 306.
[0032] This shows the case where the impurity concentration of the photoelectric conversion layer and charge multiplication layer 305 is varied in three ways. 15 cm -3 The slope of the band diagram in is almost uniform within the photoelectric conversion layer / charge multiplication layer 305, and the impurity concentration is 1 × 10⁻⁶ 16 cm -3 The slope of the band diagram in is 1 × 10 15 cm -3 The band diagram is almost the same as in [previous example], but the impurity concentration is 1 × 10⁻⁶. 17 cm -3 The slope of the band diagram in this region is non-uniform within the photoelectric conversion layer and charge multiplication layer 305, and as shown in Figure 7, it has an upward convex shape.
[0033] In other words, the impurity is 1 × 10 17 cm -3In this case, the potential is not proportional to the depth from the surface. In the range of 50 nm to 200 nm from the surface, the change in potential in response to the change in depth from the surface is large (the slope of the band diagram is large), while conversely, in the range of 200 nm to 350 nm from the surface, the change in potential in response to the change in depth from the surface is small (the slope of the band diagram is small). For simplicity, when identifying the graphs in the figures, the impurity is described as 1 × 10⁻⁶. N cm -3 In that case, 1ENcm -3 This shall be written as follows (the same applies in Figures 8-10 and 12).
[0034] Figure 8 shows a graph illustrating the relationship between electric field strength and depth from the surface in the band diagram shown in Figure 7. For easier understanding, the band diagram from Figure 7 is also reproduced in Figure 8. The slope of the band diagram shown in Figure 7 represents the magnitude of the electric field strength. Therefore, the impurity concentration is 1 × 10 15 cm -3 The electric field strength in this region is almost uniform in the depth direction within the photoelectric conversion layer and charge multiplication layer 305. Furthermore, the impurity concentration is 1 × 10⁻⁶. 16 cm -3 The change in electric field strength in this case is when the impurity concentration is 1 × 10 15 cm -3 This is roughly the same as the change in electric field strength in [location]. On the other hand, the impurity concentration is 1 × 10 17 cm -3 The electric field strength in the photoelectric conversion layer and charge multiplication layer 305 is non-uniform in the depth direction, with the electric field strength being high in the range of 50 nm to 200 nm from the surface and decreasing in the range of 200 nm to 350 nm from the surface.
[0035] In Figure 9, the intensity is 2.5 μW / cm². 2The curve of the electron-hole pair generation rate by photoelectric conversion when light with a wavelength of 550 nm is incident from the hole injection blocking layer 304 side is superimposed on the band diagram in Figure 7. Note that the hole injection blocking layer 304 does not absorb light with a wavelength of 550 nm because it has a large band gap. The photoelectric conversion layer and charge multiplication layer 305 absorbs the light, and electron-hole pairs represented by the following equation (1) are generated.
number
[0036] On the other hand, in the dark, no electron-hole pairs are generated as shown in equation (1) above. Instead, electrons and holes are generated and recombined in the Shockley-Read-Hall model, and this becomes the dark current. The impurity concentration is 1 × 10 15 cm -3 In this case, since the electric field strength is almost uniform in the depth direction within the photoelectric conversion layer and charge multiplication layer 305, the generation of dark current is uniform. Also, the impurity concentration is 1 × 10⁻⁶ 16 cm -3 Even in this case, the impurity concentration is 1 × 10 15 cm -3 Similar to the previous case, the electric field strength is approximately uniform in the depth direction within the photoelectric conversion layer and charge multiplication layer 305, so the generation of dark current is generally uniform. In contrast, the impurity concentration is 1 × 10 17 cm -3 In this case, the electric field strength is high in the shallow depth region, leading to a large amount of dark current generation, and the avalanche effect causes a rapid increase in dark current. Therefore, when the impurity concentration is 1 × 10⁻⁶ 17 cm -3 In this case, the impurity concentration is 1 × 10 15 cm -3 or 1 x 10 16 cm -3 The dark current increases significantly compared to the previous case.
[0037] Figure 10 shows the relationship between current density and applied voltage when light is irradiated to generate electron-hole pairs as shown in Figure 9, and when it is dark. Here, the unit of current density is the number of elementary charge particles generated per pixel and per frame, assuming a pixel area of 3.2 μm square and a frame frequency of 60 Hz. As shown in Figure 10, the current density saturates when the applied voltage is low. Using this saturated current density as a reference, the signal current value and dark current value at a voltage value when the signal current value increases tenfold are derived.
[0038] Figure 11 shows the relationship between the signal current to dark current shot noise ratio, calculated using equation (2) below from the signal current and dark current values derived in Figure 10, and the impurity concentration. The ratio of signal current to dark current shot noise = signal current / √(dark current) ……(2) In Figure 11, the ratio of signal current to dark current shot noise is expressed in arbitrary units (au). As shown in Figure 11, the impurity concentration is 1 × 10⁻⁶ 16 cm -3 In the vicinity, the ratio of signal current to dark current shot noise changes significantly. In other words, the impurity concentration is 1 × 10 16 cm -3 If the following conditions are met, the change in the ratio of signal current to dark current shot noise is small, but the impurity concentration is 1 × 10⁻⁶ 16 cm -3 Beyond a certain point, the ratio of signal current to dark current shot noise decreases sharply in proportion to the increase in impurity concentration.
[0039] Figure 12 shows the impurity concentration as 1 × 10⁻⁶. 15 cm -3 , 1 x 10 16 cm -3 , 1 x 10 17 cm -3 The following values are shown for each of the following cases: the saturation current value at 1V, the signal current value at 10 times the saturation current value, the voltage value at which the signal current value becomes 10 times the saturation current value, the dark current value at the voltage value at which it becomes 10 times the saturation current value, and the ratio of signal current to dark current shot noise. As shown in Figures 11 and 12, a lower impurity concentration results in a better signal current to dark current shot noise ratio, but an impurity concentration of 1 × 10⁻⁶ 16 cm -3 If the following conditions are met, the signal current versus dark current shot noise does not change significantly. Therefore, the impurity concentration is 1 × 10⁻⁶. 16 cm -3 By setting the parameters as follows, the signal-to-noise ratio of the image sensor output can be improved to a good value.
[0040] Various embodiments can be adopted for the solid-state image sensor and imaging device according to the present invention, in place of the above embodiments. For example, the photoelectric conversion film of the solid-state image sensor in the above-described embodiment is configured by stacking the electron injection blocking layer, the photoelectric conversion layer and charge multiplication layer, the hole injection blocking layer, and the film electrode in this order, but other layers may be inserted between these layers. For example, an independent electron transport layer or hole transport layer may be separately inserted between the above layers. Also, the photoelectric conversion layer and charge multiplication layer may be separated into two layers: the photoelectric conversion layer and the charge multiplication layer. Also, another electron injection blocking layer or hole injection blocking layer may be separately inserted. Furthermore, the electron injection blocking layer and the hole injection blocking layer may be made of different materials from the photoelectric conversion layer and charge multiplication layer, or they may be made of the same material with different doping impurities. Furthermore, the photoelectric conversion film of the solid-state image sensor in the above embodiment may have wavelength selectivity by absorbing light of a specific wavelength. [Explanation of symbols]
[0041] 100 CMOS type solid-state image sensor 101-pixel array 10² unit pixels 103 Pixel drive wiring 104 Vertical signal line 105-row parallel signal processing circuit 106 Output Circuit 107 Timing control circuit 108 Horizontal scanning circuit 109 Vertical scanning circuit 213, 313 n-type suspended diffusion capacity (FD) 214, 314 Reset transistor (RT) 215 Source Follower Amplifier Transistor (SF) 216 Selective Transistor (SL) 217 pixel output (OUT) 220, 320 Photoelectric conversion film (PL) 222 Source Follower Amplifier Transistor Power Supply (SFVDD) 223, 323 Reset transistor power supply (RTVDD) 227 VIA 301 p type substrate 302 p-type well 303 Pixel Electrodes 304 Hole injection blockage layer 305 Photoelectric conversion layer and charge multiplication layer 306 Membrane electrode 307 Electron injection blocking layer 309 Insulating layer DCDS Digital Correlated Dual Sampling Circuit
Claims
1. A CMOS-type solid-state image sensor equipped with photoelectric conversion means consisting of a laminate including a photoelectric conversion layer and a charge multiplier layer arranged on a pixel circuit, The photoelectric conversion means is equipped with a stray diffusion capacitor that converts the signal charge generated into a signal voltage, The suspended diffusion capacity is configured to be placed in a well provided on the substrate. The floating diffusion capacitance is made of an n-type semiconductor, the well is made of a p-type semiconductor, the conductivity type of the substrate is either n-type or p-type, and the pixel electrode is connected to the floating diffusion capacitance. The photoelectric conversion means comprises an electron injection blocking layer, a photoelectric conversion layer and charge multiplication layer, a hole injection blocking layer, and a film electrode, each layer stacked in this order on the pixel electrode. The film electrode is configured to apply a positive voltage to the reset voltage applied to the pixel electrode, and to use the holes among the electron-hole pairs generated by photoelectric conversion as the traveling carriers of the photoelectric conversion means. The impurity concentration of the aforementioned photoelectric conversion layer and charge multiplier layer is set to 1 × 10 １６ cm －３ It is configured as follows: The voltage applied to the photoelectric conversion layer and charge multiplication layer is set based on the voltage at which the current density saturates during light irradiation, and is characterized in that the voltage is such that the signal current becomes 10 times the current density at which the current density saturates.
2. The solid-state image sensor according to Claim 1, characterized in that the value of 1 × 10¹⁶ cm⁻³ or less for the impurity concentration of the photoelectric conversion layer and charge multiplier layer is based on the characteristic that the signal current to dark current shot noise ratio decreases when the impurity concentration exceeds 1 × 10¹⁶ cm⁻³.
3. The solid-state image sensor according to claim 1 or 2, characterized in that the pixel circuit comprises three transistors: a reset transistor disposed between the stray diffusion capacitance and the reset power supply; a source follower amplifier transistor having a gate electrode connected to the stray diffusion capacitance; and a selection transistor having a gate electrode to which a drive waveform for selecting a pixel is input.
4. An imaging device comprising a solid-state image sensor as described in any one of claims 1 to 3, and comprising means for outputting image information obtained by the solid-state image sensor.