Power supply device

Abstract

To provide a power supply device that can suppress inrush current.SOLUTION: A power supply device 1 according to the present disclosure includes: a switched capacitor circuit 2 having capacitive elements Cin2 to Cin2 (connection point: node N1) and switching elements Q1 to Q4; a step-down chopper circuit 3 having the switching element Q1 (shared with the switched capacitor circuit 2), a capacitive element Co, an inductive element Lo, and a resistive element Ro; and an inrush current suppression circuit 4 having a capacitive element Cfly and an inductive element Lr. The switched capacitor circuit 2 is connected between input nodes Nin1 and Nin2, the step-down chopper circuit 3 is connected between the shared switching element Q1 and a load, and the inrush current suppression circuit 4 is connected between a node N2 and a node N3. The operation timing of the switching element Q2 is shifted before the operation timing of the switching element Q4.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present disclosure relates to a power supply device.

Background Art

[0002] A power supply device may be configured using a switched capacitor circuit (see, for example, Patent Document 1). In this power supply device, a plurality of sets of switching elements and capacitors are provided in the switched capacitor circuit. In the switched capacitor circuit, the voltages of a plurality of capacitors are equalized by alternately turning on even-numbered switching elements and odd-numbered switching elements.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In a power supply device, when even-numbered switching elements and odd-numbered switching elements alternately turn on in a switched capacitor circuit, a large inrush current may transiently occur in the capacitor. When a large inrush current occurs, elements such as switching elements are likely to deteriorate.

[0005] The present disclosure provides a power supply device capable of suppressing an inrush current.

Means for Solving the Problems

[0006] The power supply device according to this disclosure includes a first capacitive element, a second capacitive element, a first switching element, a second switching element, a third switching element, a fourth switching element, a third capacitive element, a first inductive element, and a second inductive element. The first capacitive element is electrically connected between a first input node and a first node. The second capacitive element is electrically connected between a second input node and a first node. The first switching element is electrically connected between a first input node and a second node. The second switching element is electrically connected between a first node and a second node. The third switching element is electrically connected between a first node and a third node. The fourth switching element is electrically connected between a second input node and a third node. The third capacitive element is electrically connected between a second node and a third node. The first inductive element is, One end Second node It is connected to the other end First output node to The second inductive element is electrically connected in series with the third capacitive element between the second and third nodes. The operating timing of the second switching element is shifted to precede the operating timing of the fourth switching element. [Effects of the Invention]

[0007] The power supply device described herein can suppress inrush current. [Brief explanation of the drawing]

[0008] [Figure 1] A circuit diagram showing the configuration of the power supply device according to the embodiment. [Figure 2] Waveform diagram showing the operation of the power supply device in the embodiment. [Figure 3] Waveform diagram showing the operation of the power supply device in the embodiment. [Figure 4] Waveform diagrams illustrating the operation of multiple modes in the embodiment. [Figure 5] A circuit diagram illustrating the operation of multiple modes in an embodiment. [Figure 6]A circuit diagram showing the configuration of a power supply device according to a modified embodiment. [Modes for carrying out the invention]

[0009] (Embodiment) The power supply according to this embodiment is configured by connecting a step-down chopper circuit to a switched-capacitor circuit, and an inrush current suppression circuit is further added. The inrush current suppression circuit is a circuit for suppressing the inrush current in the switched-capacitor circuit. For example, the power supply may be configured as shown in Figure 1. Figure 1 is a circuit diagram showing the configuration of the power supply according to this embodiment. Power supply 1 is electrically connected between an external power supply Vin and a load circuit LD. Power supply 1 is connected to power supply Vin via input nodes Nin1 and Nin2, and to load circuit LD via output nodes Nout1 and Nout2. Input node Nin1 is connected to ground potential and the positive side of power supply Vin. Input node Nin1 is connected to the negative side of power supply Vin. That is, power supply 1 is a power supply that operates with a negative power supply voltage Vin. Power supply 1 receives the power supply voltage Vin from power supply Vin and generates a power supply voltage Vout for the load circuit LD according to the power supply voltage Vin. Power supply 1 supplies the power supply voltage Vout to the load circuit LD. Power supply unit 1 includes a switched-capacitor circuit 2, a buck chopper circuit 3, and an inrush current suppression circuit 4. The switched-capacitor circuit 2 is electrically connected between input nodes Nin1, Nin2 and the buck chopper circuit 3. The buck chopper circuit 3 is electrically connected between the switched-capacitor circuit 2 and output nodes Nout1, Nout2. The inrush current suppression circuit 4 is electrically connected to the switched-capacitor circuit 2 and the buck chopper circuit 3, respectively. The switched-capacitor circuit 2 is a circuit that can boost, buck, and reverse the polarity of a voltage without using magnetic components. The switched-capacitor circuit 2 is provided with multiple sets of switching elements and capacitors. The switched-capacitor circuit 2 includes a capacitive element Cin1, a capacitive element Cin2, a switching element Q1 (an example of a first switching element), a switching element Q2 (an example of a second switching element), a switching element Q3 (an example of a third switching element), and a switching element Q4 (an example of a fourth switching element). Capacitive element Cin1 and switching elements Q1 and Q2 correspond to each other and form one set. Capacitive element Cin2 and switching elements Q3 and Q4 correspond to each other and form one set.Capacitor element Cin1 is electrically connected between input node Nin1 and node N1. One end of capacitor element Cin1 is connected to input node Nin1 and the other end is connected to node N1. Capacitor element Cin2 is electrically connected between input node Nin2 and node N1. One end of capacitor element Cin2 is connected to input node Nin2 and the other end is connected to node N1.

[0010] Switching element Q1 is electrically connected between input node Nin1 and node N2. Switching element Q1 includes, for example, a transistor NM1 and a diode D1. Transistor NM1 is, for example, an NMOS transistor, with its gate connected to an external control circuit CTR, its source connected to node N2, and its drain connected to input node Nin1 and output node Nout1. Diode D1 is, for example, a parasitic diode of an NMOS transistor, with its cathode connected to input node Nin1 and its anode connected to node N2. Switching element Q2 is electrically connected between node N1 and node N2. Switching element Q2 includes, for example, a transistor NM2 and a diode D2. Transistor NM2 is, for example, an NMOS transistor, with its gate connected to an external control circuit CTR, its source connected to node N1, and its drain connected to node N2. Diode D2 is, for example, a parasitic diode of an NMOS transistor, with its cathode connected to node N2 and its anode connected to node N1. Switching element Q3 is electrically connected between node N1 and node N3. Switching element Q3 includes, for example, a transistor NM3 and a diode D3. Transistor NM3 is, for example, an NMOS transistor, with its gate connected to an external control circuit CTR, its source connected to node N3, and its drain connected to node N1. Diode D3 is, for example, a parasitic diode of an NMOS transistor, with its cathode connected to node N1 and its anode connected to node N3. Switching element Q4 is electrically connected between input node Nin2 and node N3. Switching element Q4 includes, for example, a transistor NM4 and a diode D4. Transistor NM4 is, for example, an NMOS transistor, with its gate connected to an external control circuit CTR, its source connected to input node Nin2, and its drain connected to node N3. Diode D4 is, for example, a parasitic diode of an NMOS transistor, with its cathode connected to node N3 and its anode connected to input node Nin2.

[0011] The switched-capacitor circuit 2 does not have the function of regulating the magnitude of the power supply voltage Vout that should be output from the power supply unit 1. Therefore, a buck chopper circuit 3 is connected after the switched-capacitor circuit 2. The buck chopper circuit 3 can regulate the magnitude of the power supply voltage Vout according to the switching duty cycle (i.e., the ratio of on / off time). The buck chopper circuit 3 has a switching element Q1, a capacitive element Co, an inductive element Lo, and a resistive element Ro. The buck chopper circuit 3 shares the switching element Q1 with the switched-capacitor circuit 2. The capacitive element Co is electrically connected between output node Nout1 and output node Nout2. One end of the capacitive element Co is connected to output node Nout1 and the other end is connected to output node Nout2. The inductive element Lo is electrically connected between node N2 and output node Nout2. One end of the inductive element Lo is connected to node N2 and the other end is connected to output node Nout2. The resistive element Ro is electrically connected between output node Nout1 and output node Nout2. Resistor Ro has one end connected to output node Nout1 and the other end connected to output node Nout2. Since the switched-capacitor circuit 2 is a circuit that includes multiple sets of switching elements and capacitors (Q1, Q2, Cin1), (Q3, Q4, Cin2), excessive inrush current may flow and increase switching losses under high load and high voltage. Therefore, the inrush current suppression circuit 4 is electrically connected to the switched-capacitor circuit 2. The inrush current suppression circuit 4 can suppress inrush current by delaying the phase of the current using resonance.

[0012] The inrush current suppression circuit 4 includes a capacitive element Cfly and an inductive element Lr. The resonant frequency of the loop including the capacitive element Cin1, the capacitive element Cfly, and the inductive element Lr is lower than the switching frequencies of the switching elements Q1, Q2, Q3, and Q4. This allows the phase of the current flowing through the loop including the capacitive element Cin1, the capacitive element Cfly, and the inductive element Lr to be delayed during switching. The resonant frequency of the loop including the capacitive element Cin2, the capacitive element Cfly, and the inductive element Lr is lower than the switching frequencies of the switching elements Q1, Q2, Q3, and Q4. This allows the phase of the current flowing through the loop including the capacitive element Cin2, the capacitive element Cfly, and the inductive element Lr to be delayed during switching. Note that the resonant frequencies of the loop including the capacitive element Cin1, the capacitive element Cfly, and the inductive element Lr and the resonant frequencies of the loop including the capacitive element Cin2, the capacitive element Cfly, and the inductive element Lr may be the same or different. The capacitive element Cfly is electrically connected between nodes N2 and N3. One end of the capacitive element Cfly is connected to node N2, and the other end is connected to node N3. The capacitive element Cfly is also called a floating capacitor because it can become floating during switching. The inductive element Lr is electrically connected in series with the capacitive element Cfly between nodes N2 and N3. The inductive element Lr may be electrically connected between node N2 and the capacitive element Cfly, or between the capacitive element Cfly and node N3. In Figure 1, one end of the inductive element Lr is connected to node N2, and the other end is connected to the capacitive element Cfly. In the inrush current suppression circuit 4, by inserting the inductive element Lr in series with the capacitive element Cfly, a resonant current can be generated in the loop including the inrush current suppression circuit 4. By designing the resonant frequency at this time to be lower than the switching frequency, soft switching operation is possible when the switching elements (Q1, Q3, Q4) are turned on, and switching losses can be reduced. Therefore, highly efficient circuit operation can be achieved.

[0013] Soft switching refers to a switching operation in which the trajectory of the switching element on the voltage-current characteristic plane during the switching process moves within a triangular region (a region that can be considered to have a gradual change) connecting the point of maximum voltage, the point of maximum current, and the origin. If the entire trajectory of the switching element remains within the triangular region during on / off switching, soft switching is successful; if it deviates even slightly outside the region, soft switching fails and hard switching occurs. For example, when a switching element is turned off, if the current flowing through the switching element decreases to 0A before the voltage across the switching element rises and transitions to a predetermined voltage value, the operation will be within the region of the triangle described above, resulting in soft-switch operation. In other words, if the transition time of the voltage across the switching element is longer than the transition time of the current flowing through the switching element, soft-switch operation occurs. However, even if the current flowing through the switching element decreases to 0A before the voltage across the switching element rises and transitions to a predetermined voltage value during the turn-off of the switching element, if the voltage across the switching element overshoots beyond the predetermined voltage value due to the generation of a surge voltage, hard switching operation will occur. On the other hand, when a switching element is turned off, if the voltage across the switching element rises and transitions to a predetermined voltage value, but the current flowing through the switching element does not decrease to 0A, then the operation will be outside the region of the triangle described above, resulting in hard-switch operation. In other words, if the transition time of the voltage across the switching element is shorter than the transition time of the current flowing through the switching element, hard-switch operation occurs. Furthermore, when a switching element is turned off, if the time it takes for the voltage across the switching element to rise and transition to a predetermined voltage value is approximately equal to the time it takes for the current flowing through the switching element to decrease and transition to 0A, then the behavior meets the boundary conditions for a soft-hard switch. When a switching element is turned on, if the voltage across the switching element drops to 0V, but the current flowing through the switching element is still rising, the switching element will operate within the triangular region described above, resulting in soft-switch operation. On the other hand, when the current flowing through the switching element is completed before the voltage across the switching element decreases and transitions to 0 V when the switching element is turned on, it operates outside the above triangular region, resulting in hard switching operation. Also, when the time for the voltage across the switching element to decrease and transition to 0 V is substantially equal to the time until the increase in the current flowing through the switching element is completed when the switching element is turned on, it is an operation at the boundary condition of soft-hard switching.

[0014] Here, when the switching elements Q1 and Q3 are simultaneously turned on and off, and the switching elements Q2 and Q4 are simultaneously turned on and off, the peak current when the switching element Q2 is turned on and off may increase. Therefore, in the power supply device 1, the timing of turning on and off the switching element Q2 is shifted earlier than the timing of turning on and off the switching element Q4. As a result, the current balance when the switching elements Q2 and Q4 are turned on and off can be adjusted, and the losses of the switching elements Q2 and Q4 can be equalized, so that the long life of the components can be achieved.

[0015] For example, power supply unit 1 may operate as shown in Figures 2 and 3. Figures 2 and 3 are waveform diagrams showing the operation of power supply unit 1, respectively. Figure 2 shows the results of a simulation of the operation of switching elements Q1 and Q2, and Figure 3 shows the results of a simulation of switching elements Q3 and Q4. The simulations in both Figures 2 and 3 were performed under the following conditions: Input voltage from power supply Vin is Vin = 1500V. Capacitance value of capacitive element Cin1 is Cin1 = 12μF. Capacitance value of capacitive element Cin2 is Cin2 = 12μF. Capacitance value of capacitive element Cin3 is Cin3 = 12μF. Inductance value of inductive element Lr is Lr = 500nH. Inductance value of inductive element Lo is Lo = 100μH. Capacitance value of capacitive element Co is Co = 12μF. Resistance value of resistive element Ro is Ro = 16.66Ω. Switching frequency is 100kHz. The duty cycle is (on-period of switching element Q2) / (switching period) = 50%. The interval (dead time) between the on-period of switching element Q1 and the on-period of switching element Q2 is 120 ns. Switching elements Q1 and Q3 are switched on and off simultaneously. The on / off timing of switching element Q2 is 20 ns earlier than the on / off timing of switching element Q4. Under these conditions, the resonant frequency of the loop including capacitive elements Cin1 and Cfly and inductive element Lr is 91.9 kHz, which is less than the switching frequency of 100 kHz. The resonant frequency of the loop including capacitive elements Cin2 and Cfly and inductive element Lr is 91.9 kHz, which is less than the switching frequency of 100 kHz. As described above, the on / off timing of switching element Q2 is shifted earlier than the on / off timing of switching element Q4, but the range of this shift is shorter than the dead time (120 ns in the above example).

[0016] Waveform diagrams obtained by expanding the portions enclosed by the dashed lines in FIGS. 2(a) to 2(c) in the time direction are shown in FIGS. 2(d) to 2(f). Waveform diagrams obtained by expanding the portions enclosed by the chain double-dashed lines in FIGS. 2(a) to 2(c) in the time direction are shown in FIGS. 2(g) to 2(i). In FIGS. 2(a), 2(d), and 2(g), the gate signal of the switching element Q1 is shown by a solid line, and the gate signal of the switching element Q2 is shown by a dotted line. In FIGS. 2(b), 2(e), and 2(h), the voltage across the switching element Q1 is shown by a solid line, and the current flowing through the switching element Q1 is shown by a dotted line. In FIGS. 2(c), 2(f), and 2(i), the voltage across the switching element Q2 is shown by a solid line, and the current flowing through the switching element Q2 is shown by a dotted line. As shown in FIG. 2(a), the switching element Q1 is turned on at timing t1, turned off at timing t2, turned on at timing t5, and turned off at timing t6. The switching element Q2 is turned on at timing t3a, turned off at timing t4a, and turned on at timing t7a. The periods from t2 to t3a, from t4a to t5, and from t6 to t7a are dead times during which both the switching element Q1 and the switching element Q2 are in the off state, respectively. As shown in FIGS. 2(a) and 2(d), when the switching element Q1 is turned off at timing t2, as shown in FIGS. 2(b) and 2(e), the negative current flowing through the switching element Q1 gradually changes to zero. That is, as shown by the dotted line in FIG. 2(e), in the switching element Q1, when it is turned off, current flows through the diode D1 and the current changes gradually with respect to the voltage change of the gate signal, resulting in a soft switching operation. As shown in FIGS. 2(a) and 2(g), when the switching element Q1 is turned on at timing t5, as shown in FIGS. 2(b) and 2(h), a substantially constant negative current flows through the switching element Q1. That is, as shown by the dotted line in FIG. 2(h), in the switching element Q1, when it is turned on, current flows through the diode D1 and the current changes gradually with respect to the voltage change of the gate signal, resulting in a soft switching operation.

[0017] As shown in Figures 2(a) and 2(d), when the switching element Q2 is turned on at timing t3a, the switching element Q4 is turned off, as shown in Figures 2(c) and 2(f). Therefore, the current flowing through the switching element Q2 changes in the same way as the gate signal and becomes a positive current. In other words, as shown in Figures 2(d) and 2(f), the transition time of the voltage across switching element Q2 and the transition time of the current flowing through switching element Q2 are approximately equal, resulting in the operation of a soft-hard switch boundary condition. Note that timing t3a is shifted to before the timing t3 (see Figures 3(d) to 3(f)) when switching element Q4 is turned on. As shown in Figures 2(a) and 2(g), when the switching element Q2 is turned off at timing t4a, as shown in Figures 2(c) and 2(i), the positive current flowing through the switching element Q2 changes more gradually than the gate signal and becomes zero. Furthermore, by utilizing the resonant characteristics of the loop including the inrush current suppression circuit 4, a portion of the current flowing through the switching element Q2 during switching flows through the loop including the inrush current suppression circuit 4. Therefore, the current flowing through the switching element Q2 is reduced more gradually compared to when the inrush current suppression circuit 4 is not provided. In other words, as shown in Figures 2(g) and 2(i), the transition time of the voltage across the switching element Q2 and the transition time of the current flowing through the switching element Q2 are approximately equal, resulting in the operation of a soft-hard switch boundary condition. Note that timing t4a is shifted to precede the timing t4 (see Figures 3(g) to 3(i)) at which the switching element Q4 is turned off.

[0018] Figures 3(d) to 3(f) show waveforms of the areas enclosed by dashed lines in Figures 3(a) to 3(c) magnified in the time direction. Figures 3(g) to 3(i) show waveforms of the areas enclosed by double-dotted lines in Figures 3(a) to 3(c) magnified in the time direction. In Figures 3(a), 3(d), and 3(g), the gate signal of switching element Q3 is shown by a solid line, and the gate signal of switching element Q4 is shown by a dotted line. In Figures 3(b), 3(e), and 3(h), the voltage across switching element Q3 is shown by a solid line, and the current flowing through switching element Q3 is shown by a dotted line. In Figures 3(c), 3(f), and 3(i), the voltage across switching element Q4 is shown by a solid line, and the current flowing through switching element Q4 is shown by a dotted line. As shown in Figure 3(a), switching element Q3 is turned on at timing t1, turned off at timing t2, turned on at timing t5, and turned off at timing t6. Switching element Q4 is turned on at timing t3, turned off at timing t4, and turned on at timing t7. The periods from t2 to t3, t4 to t5, and t6 to t7 are dead times in which both switching elements Q3 and Q4 are in the off state. As shown in Figures 3(a) and 3(d), when the switching element Q3 is turned off at timing t2, as shown in Figures 3(b) and 3(e), a portion of the current flowing through the switching element Q3 flows into the loop including the inrush current suppression circuit 4. That is, as shown enclosed by the dotted line in Figure 3(e), the voltage in the switching element Q3 changes slowly due to resonance when it is turned off, resulting in soft-switch operation. As shown in Figures 3(a) and 3(g), when the switching element Q3 is turned on at timing t5, a nearly constant negative current flows through the switching element Q3, as shown in Figures 3(b) and 3(h). That is, as shown enclosed by the dotted line in Figure 3(h), when the switching element Q3 is turned on, current flows through the diode D3, and the current changes slowly in response to the voltage change of the gate signal, resulting in soft-switch operation. As shown in Figures 3(a) and 3(d), when switching element Q4 is turned on at timing t3, as shown in Figures 3(c) and 3(f), switching element Q2 is turned on at the preceding timing t3a, so current flows through the parasitic diode D4 of switching element Q4, and the current changes gradually in response to the voltage change of the gate signal. This results in soft-switch operation. As shown in Figures 3(a) and 3(g), when the switching element Q4 is turned off at timing t4, the positive current flowing through the switching element Q4 changes to zero, similar to the gate signal, as shown in Figures 3(c) and 3(i). In other words, as shown in Figures 3(g) and 3(i), the transition time of the voltage across switching element Q4 and the transition time of the current flowing through switching element Q4 are approximately equal, resulting in the operation of a soft-hard switch boundary condition. However, because switching element Q2 is turned off at the preceding timing t4a, the current when switching element Q4 is turned off at timing t4 increases.

[0019] Next, the temporal changes in the current path in power supply unit 1 will be explained using Figures 4 and 5. The temporal changes in the current path can be classified into several modes. Figure 4 is a waveform diagram showing the operation in several modes. Figures 4(a), 4(b), 4(c), 4(d), and 4(e) show the temporal changes in the current flowing through the capacitive element Cfly, switching element Q1, switching element Q2, switching element Q3, and switching element Q4, respectively. Figure 5 is a circuit diagram showing the operation in several modes. During the period t11 to t12 shown in Figure 4, mode (6) operation occurs. During the period t12 to t13, mode (1) operation occurs. During the period t13 to t14, mode (1)' operation occurs. During the period t14 to t15, mode (2) operation occurs. During the period t15 to t16, mode (3) operation occurs. During the period t16 to t17, mode (4) operation occurs. During the period from timing t17 to t18, mode (5) operation is performed. During the period from timing t18 to t19, mode (6) operation is performed. In Figures 2 and 3, timing t3a corresponds to timing t11, timing t3 corresponds to timing t12, timing t4a corresponds to timing t14, timing t4 corresponds to timing t15, timing t7a corresponds to timing t18, and timing t7 corresponds to timing t19.

[0020] At timing t11, the switching element Q2 turns on and a current equal to the parasitic capacitance Coss begins to flow. However, since the transition time of the voltage across the switching element Q2 and the transition time of the current flowing through the switching element Q2 are approximately equal, the behavior conforms to the boundary conditions of a soft-hard switch. In other words, in mode (6) operation, as shown in Figure 5(a), switching element Q2 turns on first, so the voltage Vds across switching element Q2 changes from 750V to 0V (see timing t3a in Figure 2(f)), and the voltage Vds across switching element Q3 changes from 0V to 750V (see timing t3 in Figure 3(e)), so the voltage Vds across switching element Q4 becomes 0V (see timing t3 in Figure 3(f)) and current begins to flow through diode D4. When switching element Q4 turns on at timing t12, switching element Q2 is already turned on at the preceding timing t11, so current flows through the diode D4 of switching element Q4, and the current changes gradually in response to the voltage change of the gate signal. This results in soft-switch operation. That is, in mode (1), as shown in Figure 5(b), switching element Q2 remains in the ON state, and switching element Q4 turns on with a delay equal to the shift. At this time, current flows through the diode D4 side of switching element Q4, and the voltage Vds across switching element Q4 is 0V, so its turn-on is a soft-switch operation. A current flows through switching element Q2 that is the sum of the current from capacitive element Cin1 → capacitive element Co and resistive element Ro → inductive element Lo and the resonant current from capacitive element Cin2 → capacitive element Cfly → inductive element Lr. At timing t13, both switching elements Q2 and Q4 are kept in the ON state. That is, in mode (1)', as shown in Figure 5(c), the resonant current from the capacitive element Cin2 → inductive element Lr → capacitive element Cfly flows through the transistor NM4 side of switching element Q4. When switching element Q2 turns off at timing t14, switching element Q4 is on, so the current from when switching element Q2 is off flows into the resonant loop including the inrush current suppression circuit 4 and is gradually reduced, resulting in soft-switch operation. That is, in mode (2), as shown in Figure 5(d), switching element Q2 turns off first, and the current from capacitive element Cin1 to capacitive element Co and resistive element Ro to inductive element Lo flows to the switching element Q4 side. As a result, the current flowing through switching element Q4 increases. On the other hand, when switching element Q2 turns off, the voltage across it Vds rises from 0V to 750V, which corresponds to the voltage of capacitive element Cin1 (see timing t4a in Figure 2(i)). Therefore, the diode D1 of switching element Q1 turns on. When switching element Q2 is off, the operation is in the boundary condition of a soft-hard switch as described above. Subsequently, switching element Q4 turns off at a slightly delayed timing t15. At this time, because switching element Q2 has already turned off, the current flowing through switching element Q4 is greater than at timing t14 when it turns off. On the other hand, when switching element Q4 turns off, the voltage across it Vds rises from 0V to 750V, which corresponds to the voltage of capacitive element Cin2 (see timing t4 in Figure 3(i)). As a result, diode D3 of switching element Q3 turns on. Note that when switching element Q4 is off, the operation follows the boundary conditions of a soft / hard switch as described above. When the dead time ends in this state, switching elements Q1 and Q3 turn on, and the system transitions to mode (3). In mode (3), as shown by the dashed arrow in Figure 5(e), a resonant current flows through the path from capacitive element Cin1 → switching element Q1 → inductive element Lr → capacitive element Cfly → diode D3 → capacitive element Cin1. Current flows through the diodes D1 and D3 on the switching elements Q1 and Q3, and the voltage Vds across both of them is 0V. At this time, the resonant frequency of the loop of capacitive element Cin1, inductive element Lr, and capacitive element Cfly is lower than the switching frequency of switching elements Q1 to Q4. As described above, the ON operation of switching elements Q1 and Q3 is a soft-switch operation. At timing t16, due to the resonance of the capacitive element Cin1, the capacitive element Cfly, and the inductive element Lr, the dashed-dotted line current begins to flow in the reverse direction. That is, in mode (4), the sum of the current in the path from capacitive element Cin1 → switching element Q3 → capacitive element Cfly → inductive element Lr → diode D1 shown as a dotted line in Figure 5(e) and the current in the path from capacitive element Co and resistive element Ro → inductive element Lo → diode D1 shown as a solid line in Figure 5(e) flows through the diode D1 of the switching element Q1. At timing t17, switching elements Q1 and Q3 turn off, but the resonant operation of the loop of capacitive element Cin1, inductive element Lr, and capacitive element Cfly results in soft-switch operation. That is, in mode (5), as shown in Figure 5(f), switching elements Q1 and Q3 turn off. Since the current from switching element Q1 flows directly through the diode D1 side, its off operation becomes a soft-switch operation. On the switching element Q3 side, after turning off, resonance occurs between the output capacitance of Q3 (several hundred pF), capacitive element Cin1, capacitive element Cfly, and inductive element Lr, and the voltage Vds across switching element Q3 becomes a half-wave waveform during the dead time (120 nsec), the voltage rises and then drops to 0, and current begins to flow through the diode D3 side. In other words, all switching elements Q1 to Q4 are turned off, and current flows through diodes D1 and D3 when switching elements Q1 and Q3 are turned off. As a result, 750V is applied across the series connection of the inductive element Lr and the capacitive element Cfly, and the cross-voltage Vds of switching element Q2 also becomes 750V. At timing t18, the switching element Q2 turns on and the parasitic capacitance Coss begins to flow, resulting in the operation of a soft-hard switch boundary condition. That is, mode (6) operation occurs again, but the transition time of the voltage across the switching element Q2 and the transition time of the current flowing through the switching element Q2 become approximately equal, resulting in the operation of a soft-hard switch boundary condition.

[0021] For example, when switching elements Q2 and Q4 are turned on simultaneously, a rapid current change occurs due to the charge accumulated in the parasitic capacitance Coss between the source and drain of both elements, causing both of their on-operations to be hard-switched. On the other hand, if the ON timing of switching element Q2 is shifted to be earlier than the ON timing of switching element Q4, the current change due to parasitic capacitance Coss is suppressed by the OFF state of switching element Q4. As a result, the ON operation of switching element Q2 is relaxed to the boundary condition operation of a soft-hard switch, and the ON operation of switching element Q4 is relaxed to a soft-switch operation. Furthermore, when switching elements Q2 and Q4 are turned off simultaneously, a current flows in proportion to the ratio of the parasitic capacitances Coss of switching elements Q2 and Q4, and the off-operations of both elements become the boundary conditions for a soft-hard switch. On the other hand, if the off-timing of switching element Q2 is shifted to be earlier than the off-timing of switching element Q4, the current from when switching element Q2 is turned off can be supplied to switching element Q4, thereby reducing the off-loss of switching element Q2. This allows the off-operation of switching element Q2 to be mitigated to the boundary conditions for a soft-hard switch, while the off-operation of switching element Q4 is maintained to the boundary conditions for a soft-hard switch.

[0022] As described above, in this embodiment, the power supply unit 1 has an inrush current suppression circuit 4 in addition to the switched-capacitor circuit 2 and the buck chopper circuit 3. The inrush current suppression circuit 4 is connected between the switched-capacitor circuit 2 and the buck chopper circuit 3 and includes a series connection of a capacitive element Cfly and an inductive element Lr. This allows the inrush current suppression circuit 4 to transiently form a resonant circuit with the switched-capacitor circuit 2. Furthermore, the operating timing of the switching element Q2 is shifted to precede the operating timing of the switching element Q4. This makes it possible to homogenize the losses between the switching elements Q2 and Q4, thereby extending the lifespan of the components. Therefore, a highly efficient circuit can be realized that suppresses inrush current and reduces switch stress while utilizing the advantages of a switched capacitor, namely the mitigation of the voltage applied to the element and soft switching using resonance. In addition, by utilizing resonance for the switch of the buck chopper, which would normally be a hard switch operation, conduction loss and switching loss can be suppressed, thereby maintaining regulation while also reducing stress on semiconductor components. This makes it easier to miniaturize the entire power supply unit 1 by keeping component costs down and reducing losses.

[0023] The power supply unit 1i may be configured to receive a positive power supply voltage Vin, as shown in Figure 6. Figure 6 is a circuit diagram showing the configuration of a power supply unit according to a modified embodiment. Power supply unit 1i is a power supply unit that operates with a positive power supply voltage Vin, with input node Nin2 connected to ground potential instead of input node Nin1. It has a circuit configuration symmetrical to power supply unit 1 (see Figure 1). Power supply unit 1i has a buck chopper circuit 3i and an inrush current suppression circuit 4i instead of the buck chopper circuit 3 and inrush current suppression circuit 4 (see Figure 1). The buck chopper circuit 3i has a switching element Q4 (an example of a first switching element) instead of the switching element Q1 in the configuration example of Figure 1. The buck chopper circuit 3i shares the switching element Q4 with the switched capacitor circuit 2. The buck chopper circuit 3i has a circuit configuration symmetrical to the buck chopper circuit 3. The inductive element Lo is electrically connected between node N2i and output node Nout1. The inductive element Lo has one end connected to node N2i and the other end connected to output node Nout1. The inrush current suppression circuit 4i has a circuit configuration symmetric to that of the inrush current suppression circuit 4. The capacitive element Cfly is electrically connected between node N2i and node N3i. The capacitive element Cfly has one end connected to node N2i and the other end connected to node N3i. Node N2i is connected to one end of the inductive element Lo, one end of the capacitive element Cfly, the source of switching element Q3 (an example of a second switching element), and the drain of switching element Q4. Node N3i is connected to the source of switching element Q1 (an example of a fourth switching element) and the drain of switching element Q2 (an example of a third switching element). With this configuration, the inrush current suppression circuit 4i can transiently form a resonant circuit with the switched-capacitor circuit 2. For example, by setting the resonant frequency of the transiently formed resonant circuit lower than the switching frequency of the switching element in the switched-capacitor circuit 2, and by using resonance to delay the phase of the current, inrush current during switching operation can be suppressed. [Explanation of symbols]

[0024] 1,1i power supply 2. Switched Capacitor Circuit 3.3i Step-Down Chopper Circuit 4,4i Inrush current suppression circuit

Claims

1. A first capacitive element electrically connected between a first input node and a first node, A second capacitive element electrically connected between the second input node and the first node, A first switching element electrically connected between the first input node and the second node, A second switching element electrically connected between the first node and the second node, A third switching element electrically connected between the first node and the third node, A fourth switching element electrically connected between the second input node and the third node, A third capacitive element electrically connected between the second node and the third node, A first inductive element having one end connected to the second node and the other end connected to the first output node, A second inductive element electrically connected in series with the third capacitive element between the second node and the third node, Equipped with, The operating timing of the second switching element is shifted to precede the operating timing of the fourth switching element. power supply.

2. The fourth switching element is turned off at the first timing, The second switching element is turned off at a second timing that precedes the first timing. The power supply device according to claim 1.

3. The fourth switching element turns on at the third timing, The second switching element turns on at a fourth timing, which is before the third timing. The power supply device according to claim 1 or 2.

4. During a first period, the first switching element and the third switching element are kept in the ON state; during a second period beginning after the end of the first period, the second switching element is kept in the ON state; and during a third period beginning between the start and end of the second period and ending after the end of the second period, the fourth switching element is kept in the ON state. The power supply device according to claim 1.

5. The resonant frequency of the loop including the first capacitive element, the third capacitive element, and the second inductive element is lower than the switching frequencies of the first switching element, the second switching element, the third switching element, and the fourth switching element. The resonant frequency of the loop including the second capacitive element, the third capacitive element, and the second inductive element is lower than the switching frequencies of the first switching element, the second switching element, the third switching element, and the fourth switching element. A power supply device according to any one of claims 1 to 4.

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