Semiconductor equipment

Abstract

To provide a novel semiconductor device.SOLUTION: A flip-flop, a first memory circuit, and a second memory circuit are provided. The flip-flop is formed on a substrate. The first memory circuit is formed in a first die on the substrate. The second memory circuit is formed in a second die on the first die. The flip-flop is electrically connected to each of the first memory circuit and the second memory circuit. The flip-flop has a function of keeping first data corresponding to a task in operation. The first memory circuit has a function of keeping the first data in accordance with switching of the task. The second memory circuit has a function of keeping the first data when the first memory circuit keeps second data in accordance with the switching of the task.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] One aspect of the present invention relates to a semiconductor device.

[0002] Furthermore, one aspect of the present invention is not limited to the above-mentioned technical field. The technical field of one aspect of the invention disclosed herein relates to a product, a method, a driving method, or a manufacturing method. Alternatively, one aspect of the present invention relates to a process, a machine, a manufacture, or a composition of matter. More specifically, examples of the technical fields of one aspect of the present invention disclosed herein include semiconductor devices, display devices, light-emitting devices, energy storage devices, optical devices, imaging devices, illumination devices, computing devices, control devices, memory devices, input devices, output devices, input / output devices, signal processing devices, computers, electronic devices, methods for driving them, or methods for manufacturing them. [Background technology]

[0003] In recent years, the development of semiconductor devices has progressed, and for example, LSIs (Large Scale Integrations), CPUs (Central Processing Units), and memory are mainly used in semiconductor devices. A CPU is an assembly of semiconductor elements (for example, transistors or diodes) that have integrated circuits (ICs) formed by processing semiconductor wafers and creating chips with electrodes that serve as connection terminals. For example, IC chips such as LSIs, CPUs, or memory are mounted on circuit boards, such as printed circuit boards, and used as components in various electronic devices.

[0004] Furthermore, the technology of constructing transistors using semiconductor thin films formed on substrates with insulating surfaces is attracting attention. These transistors are widely applied in electronic devices such as integrated circuits and image display devices (also simply referred to as display devices). While silicon-based semiconductor materials are widely known as semiconductor thin films applicable to transistors, oxide semiconductors are attracting attention as other materials.

[0005] Furthermore, transistors using oxide semiconductors are known to have extremely low leakage current in the non-conductive state. For example, Patent Document 1 discloses a low-power CPU that takes advantage of the low leakage current characteristic of transistors using oxide semiconductors. Also, for example, Patent Document 2 discloses a memory device that can retain its contents for a long period of time by taking advantage of the low leakage current characteristic of transistors using oxide semiconductors.

[0006] Furthermore, in recent years, with the miniaturization and weight reduction of electronic devices, there has been a growing demand for even higher density integrated circuits. There is also a need to improve the productivity of semiconductor devices, including integrated circuits. For example, Patent Document 3 and Non-Patent Document 1 disclose a technology for increasing the density of integrated circuits by stacking a first transistor using an oxide semiconductor film and a second transistor using an oxide semiconductor film to provide multiple superimposed memory cells. [Prior art documents] [Patent Documents]

[0007] [Patent Document 1] Japanese Patent Publication No. 2012-257187 [Patent Document 2] Japanese Patent Publication No. 2011-151383 [Patent Document 3] International Publication No. 2021 / 053473 [Non-patent literature]

[0008] [Non-Patent Document 1] M.Oota et.al, “3D-Stacked CAAC-In-Ga-Zn Oxide FETs with Gate Length of 72nm”, IEDM Tech. Dig., 2019, pp.50-53 [Overview of the Initiative] [Problems that the invention aims to solve]

[0009] For example, in a semiconductor device such as a CPU, a series of processes (tasks) can be executed by sequentially executing processes according to program data. When the semiconductor device executes a plurality of tasks, each task can be divided into small processing units, and by sequentially executing the processing units of each task, it can be made to appear as if a plurality of tasks are being executed simultaneously. In order to execute such processing, a plurality of register banks (sets of general-purpose registers) are prepared that can hold the state (also referred to as context) of the semiconductor device when executing each task. The semiconductor device can execute a plurality of tasks by sequentially switching the register banks corresponding to each task. That is, when switching tasks, the semiconductor device saves (also referred to as saving, storing, or backing up) the context of the task being executed in the corresponding register bank, interrupts the processing, and then restores (also referred to as restoring, loading, or recovering) the context of the next task to be executed from the corresponding register bank and resumes the processing. Therefore, the semiconductor device can improve the operating speed by shortening the time required for context save and restore, and can improve the arithmetic performance.

[0010] One aspect of the present invention has as one of its problems to provide a semiconductor device with an improved operating speed. Or, one of its problems is to provide a semiconductor device with reduced power consumption. Or, one of its problems is to provide a semiconductor device with improved arithmetic performance. Or, one of its problems is to provide a novel semiconductor device.

[0011] Note that the above-listed problems do not prevent the existence of other problems. Note that one aspect of the present invention does not need to solve all of the above-listed problems. Note that other problems other than the above-listed problems will naturally become clear from the descriptions in the specification, drawings, or claims, etc., and it is possible to extract other problems other than the above-listed problems from the descriptions in the specification, drawings, or claims, etc.

Means for Solving the Problem

[0012] (1) One aspect of the present invention includes a flip-flop, a first memory circuit, and a second memory circuit. The flip-flop is formed on a substrate. The first memory circuit is formed on a first die on the substrate. The second memory circuit is formed on a second die on the first die. The flip-flop is electrically connected to each of the first memory circuit and the second memory circuit. The flip-flop has a function of holding first data corresponding to a task being executed. The first memory circuit has a function of holding the first data as the task is switched. The second memory circuit has a function of holding the first data when second data is held in the first memory circuit as the task is switched. It is a semiconductor device.

[0013] (2) Also, in the above (1), the substrate includes a first electrode. The first die includes a second electrode formed on one surface side of the first die and a third electrode formed on the other surface side of the first die. The second die includes a fourth electrode. The first electrode may be joined to the second electrode, and the third electrode may be joined to the fourth electrode.

[0014] (3) Also, in the above (1) or (2), the first die includes a first transistor, and the second die includes a second transistor. The first transistor has a function of making the connection between the flip-flop and the first memory circuit non-conductive when no data is held in each of the first memory circuit and the second memory circuit. The second transistor has a function of making the connection between the flip-flop and the second memory circuit non-conductive when no data is held in the second memory circuit.

[0015] (4) Also, in the above (3), the first transistor and the second transistor may be transistors including an oxide semiconductor in a channel formation region.

Advantages of the Invention

[0016] One aspect of the present invention can provide a semiconductor device with improved operating speed, or a semiconductor device with reduced power consumption, or a semiconductor device with improved computing performance, or a novel semiconductor device.

[0017] Furthermore, the effects listed above do not preclude the existence of other effects. Moreover, one embodiment of the present invention does not need to possess all of the effects listed above. Other effects not listed above will naturally become apparent from the description in the specification, drawings, or claims, and it is possible to extract other effects not listed above from the description in the specification, drawings, or claims. [Brief explanation of the drawing]

[0018] [Figure 1] Figure 1 is a diagram illustrating an example of a semiconductor device configuration. [Figure 2] Figure 2(A) is a diagram illustrating an example of the configuration of a semiconductor device. Figure 2(B) is a circuit diagram illustrating an example of the configuration of a semiconductor device. [Figure 3] Figure 3 is a flowchart illustrating an example of the operation of a semiconductor device. [Figure 4] Figure 4 is a flowchart illustrating an example of the operation of a semiconductor device. [Figure 5] Figure 5 is a flowchart illustrating an example of the operation of a semiconductor device. [Figure 6] Figures 6(A) through 6(D) are flowcharts illustrating examples of the operation of semiconductor devices. [Figure 7] Figures 7(A) through 7(D) are flowcharts illustrating examples of semiconductor device operation. [Figure 8] Figure 8 illustrates an example of the operation of a semiconductor device. [Figure 9] Figure 9 is a circuit diagram illustrating an example of a semiconductor device configuration. [Figure 10]Figure 10 is a timing chart illustrating an example of semiconductor device operation. [Figure 11] Figures 11(A) through 11(D) illustrate examples of the operation of a semiconductor device. [Figure 12] Figures 12(A) to 12(D) illustrate examples of the operation of a semiconductor device. [Figure 13] Figure 13 is a circuit diagram illustrating an example of a semiconductor device configuration. [Figure 14] Figure 14 is a timing chart illustrating an example of semiconductor device operation. [Figure 15] Figure 15(A) is a diagram illustrating an example of the configuration of a semiconductor device. Figure 15(B) is a circuit diagram illustrating an example of the configuration of a semiconductor device. [Figure 16] Figure 16 is a flowchart illustrating an example of the operation of a semiconductor device. [Figure 17] Figure 17 is a flowchart illustrating an example of the operation of a semiconductor device. [Figure 18] Figures 18(A) to 18(C) are flowcharts illustrating examples of the operation of a semiconductor device. [Figure 19] Figure 19 illustrates an example of the operation of a semiconductor device. [Figure 20] Figure 20 is a circuit diagram illustrating an example of a semiconductor device configuration. [Figure 21] Figure 21 is a timing chart illustrating an example of semiconductor device operation. [Figure 22] Figures 22(A) to 22(D) illustrate examples of the operation of a semiconductor device. [Figure 23] Figures 23(A) to 23(D) illustrate examples of the operation of a semiconductor device. [Figure 24] Figure 24 illustrates an example of a semiconductor device configuration. [Figure 25] Figures 25(A) to 25(C) illustrate examples of semiconductor device configurations. [Figure 26] Figure 26 illustrates an example of a semiconductor device configuration. [Figure 27]Figure 27 is a diagram illustrating an example of the memory unit configuration. [Figure 28] Figure 28(A) is a diagram illustrating an example of the memory layer configuration. Figure 28(B) is a diagram illustrating the equivalent circuit of the memory layer. [Figure 29] Figure 29 is a diagram illustrating an example of the memory unit configuration. [Figure 30] Figure 30(A) is a diagram illustrating an example of the memory layer configuration. Figure 30(B) is a diagram illustrating the equivalent circuit of the memory layer. [Figure 31] Figures 31(A) and 31(B) show examples of electronic components. [Figure 32] Figures 32(A) and 32(B) show examples of electronic devices. Figures 32(C) through 32(E) show examples of large-scale computers. [Figure 33] Figure 33 shows an example of space equipment. [Figure 34] Figure 34 shows an example of a storage system applicable to a data center. [Modes for carrying out the invention]

[0019] In this specification, a semiconductor device is a device that utilizes semiconductor properties, such as a circuit containing semiconductor elements (e.g., transistors or diodes), or a device having such a circuit. It also refers to any device that can function by utilizing semiconductor properties. For example, integrated circuits containing semiconductor elements, chips equipped with integrated circuits, electronic components with chips housed in a package, or electronic devices on which electronic components are mounted are examples of semiconductor devices. Furthermore, for example, display devices, light-emitting devices, energy storage devices, optical devices, imaging devices, illumination devices, computing devices, control devices, memory devices, input devices, output devices, input / output devices, signal processing devices, computers, or electronic devices are themselves semiconductor devices and may also contain semiconductor devices.

[0020] The embodiments will be described below with reference to the drawings. However, the embodiments can be implemented in many different ways. Therefore, it will be easily understood by those skilled in the art that their form and details can be changed in various ways without departing from the spirit and scope. Accordingly, the present invention is not to be construed as being limited to the contents described in the embodiments.

[0021] Furthermore, in this specification, the configurations shown in each embodiment can be appropriately combined with the configurations shown in other embodiments to form one aspect of the present invention. Also, if multiple configurations are shown in one embodiment, these configurations can be appropriately combined to form one aspect of the present invention.

[0022] In addition, in drawings illustrating embodiments of the invention, the same reference numerals may be used across different drawings for identical or functionally similar parts, thereby omitting repeated explanations. Furthermore, in drawings, if similar functions are indicated, for example, hatching patterns may be the same and no reference numerals may be assigned. Also, in order to facilitate understanding, some components may be omitted in drawings, such as perspective views or top views (also called "plan views"). Furthermore, some hidden lines may be omitted in drawings. Also, some hatching patterns may be omitted in drawings.

[0023] Furthermore, in drawings, size, layer thickness, or area may be exaggerated for clarity. Therefore, drawings are not limited to, for example, their size or aspect ratio. Also, drawings are schematic representations of ideal examples and are not limited to, for example, the shapes or values ​​shown in the drawings. For example, in actual manufacturing processes, layers or resist masks may be unintentionally reduced due to processes such as etching, but these may not be reflected in the drawings for ease of understanding. Similarly, in actual circuit operation, variations in voltage or current may occur due to, for example, noise or timing discrepancies, but these may not be reflected in the drawings for ease of understanding.

[0024] Furthermore, in this specification and the drawings, the components of the present invention may be classified by function and shown as independent elements. However, it is difficult to separate the components by function, and there are cases where multiple functions are involved in one element, or where one function is involved across multiple elements. Therefore, the elements shown in this specification and the drawings are not limited to their descriptions and may be appropriately rephrased depending on the situation.

[0025] Furthermore, in this specification and drawings, when the same reference numeral is used for multiple elements, and especially when it is necessary to distinguish them, the reference numeral may be accompanied by an identifying numeral such as "A", "b", "_1", "[n]", or "[m,n]".

[0026] In this specification, the "conducting state" or "on state" of a transistor refers to a state in which the source and drain of the transistor can be considered to be electrically short-circuited, or a state in which current can flow between the source and drain. For example, in an n-channel transistor, a state in which the voltage between the gate and source is higher than the threshold voltage, or in a p-channel transistor, a state in which the voltage between the gate and source is lower than the threshold voltage, may be referred to as the "conducting state" or "on state." Furthermore, the "non-conducting state," "blocked state," or "off state" of a transistor refers to a state in which the source and drain of the transistor can be considered to be electrically blocked. For example, in an n-channel transistor, a state in which the voltage between the gate and source is lower than the threshold voltage, or in a p-channel transistor, a state in which the voltage between the gate and source is higher than the threshold voltage, may be referred to as the "non-conducting state," "blocked state," or "off state."

[0027] Furthermore, in this specification, unless otherwise specified, the "off-current" of a transistor refers to the current flowing between the source and drain (also called the drain current) when the transistor is in the off state. In this specification, the drain current and the current flowing between the gate and source or drain (also called the gate leakage current) when the transistor is in the off state may be referred to as the leakage current.

[0028] (Embodiment 1) A semiconductor device according to one aspect of the present invention will be described with reference to the drawings. The semiconductor device according to one aspect of the present invention may be suitably used, for example, as part of a central processing unit (CPU).

[0029] Figure 1 is a block diagram illustrating an example configuration of a semiconductor device 100 according to one aspect of the present invention.

[0030] The semiconductor device 100 shown in Figure 1 comprises a state control unit 101 and a CPU core 102. The CPU core 102 comprises a register unit 103 and an arithmetic unit 104. The register unit 103 comprises a plurality of register banks 105. The register banks 105 comprise a plurality of general-purpose registers 106. The general-purpose registers 106 comprise a plurality of registers 110.

[0031] The semiconductor device 100 can perform a series of processes (tasks) by sequentially executing processes according to program data. The semiconductor device 100 can perform multiple tasks.

[0032] The state control unit 101 has the function of outputting control signals for switching between multiple tasks in response to signals such as interrupt signals input from outside the semiconductor device 100, or sleep signals generated by the CPU core 102. For example, when switching between multiple tasks, it has the function of generating a signal to control the operation of a register 110 in the CPU core 102 and supplying it to the register 110.

[0033] The state control unit 101 may also have a function to output signals for controlling the power gating of the CPU core 102, for example.

[0034] The CPU core 102 has the function of performing calculations in the arithmetic unit 104 according to the program data held in the register unit 103. The CPU core 102 is sometimes referred to as a processor core. The semiconductor device 100 may be configured to have one CPU core 102 (single core), or it may be configured to have two or more CPU cores (for example, a dual-core or many-core multi-core).

[0035] The register section 103 includes a register bank 105, which contains, for example, pipeline registers and register files. The register section 103 has the function of temporarily holding program data for performing calculations in the arithmetic unit 104, data used in the calculations, and data obtained by the calculations.

[0036] The arithmetic unit 104 has the function of performing various arithmetic operations, such as basic arithmetic operations and logical operations, according to the program data held in the register unit 103. The arithmetic unit 104 is sometimes referred to as an ALU (Arithmetic logic unit). In addition to the register unit 103 and the arithmetic unit 104, the CPU core 102 may also include, for example, a program counter or a control circuit.

[0037] Register bank 105 is provided for each of the multiple tasks that are executed by processing according to the program data. The multiple general-purpose registers 106 within register bank 105 each have the function of holding program data for performing arithmetic processing, data used in arithmetic processing, or data obtained by arithmetic processing when executing each task. Register 110 within general-purpose register 106 corresponds to a memory circuit that has the function of holding data.

[0038] In other words, the state (also called the context) of the semiconductor device 100 when each task is executed is maintained in each of the register banks 105 provided for each task.

[0039] The semiconductor device 100 is controlled by a state control unit 101 to switch to the register bank 105 corresponding to each task when switching between multiple tasks. In other words, when switching tasks, the semiconductor device 100 is controlled by the state control unit 101 to save (store, or back up) the context of the currently executing task to the corresponding register bank 105, interrupt processing, and then restore (recover, load, or recover) the context of the next task to be executed from the corresponding register bank 105 before resuming processing. By executing multiple tasks while switching between register banks 105 in this way, it is not necessary to exchange data for executing each task with memory provided outside the semiconductor device 100 (for example, cache memory or main memory). Therefore, the operating speed of the semiconductor device 100 can be improved. In other words, the computational performance of the semiconductor device 100 can be improved.

[0040] <Configuration example A> Various configurations can be used as the register 110 according to one aspect of the present invention.

[0041] Figure 2(A) is a schematic diagram illustrating an example configuration of a semiconductor device 110A according to one aspect of the present invention. The semiconductor device 110A is an example of a configuration that can be suitably used in the register 110 described above.

[0042] As shown in Figure 2(A), the semiconductor device 110A includes a substrate 171. The substrate 171 is, for example, a substrate containing silicon. Alternatively, the substrate 171 may be a substrate containing a compound semiconductor such as silicon carbide or gallium nitride.

[0043] In Figure 2(A), the Z-direction is defined to make the positional relationship of each element constituting the semiconductor device 110A easier to understand. In Figure 2(A), the Z-direction is defined as being perpendicular or approximately perpendicular to the surface of the substrate 171. In this embodiment, approximately perpendicular means that the angle between the two elements in question is between 85 degrees and 95 degrees. In this embodiment, the Z-direction is sometimes referred to as the perpendicular direction for ease of understanding.

[0044] Dies 180[1] to 180[k] (where k is an integer of 2 or more) are arranged vertically on the substrate 171. Each of the dies 180[1] to 180[k] is, for example, a silicon die.

[0045] In this specification, a die refers to a chip piece obtained in the semiconductor chip manufacturing process by forming a circuit pattern on, for example, a disc-shaped substrate (also called a wafer) and then cutting it into cubes. Examples of semiconductor materials that can be used for dies include silicon, silicon carbide, or gallium nitride. For example, a die obtained from a silicon substrate (also called a silicon wafer) is sometimes called a silicon die.

[0046] Each of the substrate 171 and the die 180[1] to die 180[k] is a region on which a Si transistor (a transistor containing silicon in its channel formation region) or a circuit containing a Si transistor is provided.

[0047] A scan flip-flop 120 is formed on one side of the substrate 171.

[0048] Furthermore, each of the memory circuits 131[1] to 131[k] is formed on one side of each die 180[1] to 180[k] in a one-to-one correspondence. The memory circuits 131[1] to 131[k] form the data holding circuit 130A.

[0049] Electrodes 173 are formed on one side of each of the substrate 171 and the die 180[1] to die 180[k]. Electrodes 174 are formed on the other side of each of the die 180[1] to die 180[k]. In each of the dies 180[1] to die 180[k], a plug 175 is formed through the die to electrically connect the electrode 173 and the electrode 174. The plug 175 is, for example, a through-silicon via (TSV).

[0050] The substrate 171 and the die 180[1] are electrically connected to each other by the joining of electrodes 173 formed on one side of each substrate 171 and die 180[1]. In other words, the scan flip-flop 120 and the memory circuit 131[1] are electrically connected to each other by the joining of electrodes 173 formed on one side of each substrate 171 and die 180[1]. Furthermore, each die 180[1] through die 180[k] is electrically connected to each other by the joining of electrodes 174 formed on the other side of each die 180[1] through die 180[k-1] and electrodes 173 formed on one side of each die 180[2] through die 180[k]. In other words, the electrodes 174 formed on the other side of each die 180[1] to die 180[k-1] and the electrodes 173 formed on one side of each die 180[2] to die 180[k] are joined together, thereby electrically connecting each of the memory circuits 131[1] to memory circuits 131[k]. For example, the electrodes 174 formed on the other side of die 180[1] and the electrodes 173 formed on one side of die 180[2] are joined together, thereby electrically connecting memory circuit 131[1] and memory circuit 131[2].

[0051] It is preferable to use the same conductive material for both electrode 173 and electrode 174. As the conductive material for electrode 173 and electrode 174, for example, a metal film containing an element selected from aluminum, chromium, copper, tantalum, tin, zinc, gold, silver, platinum, titanium, molybdenum, and tungsten, or a metal nitride film composed of the above elements (for example, a titanium nitride film, a molybdenum nitride film, or a tungsten nitride film) can be used. In particular, it is preferable to use copper as the conductive material for electrode 173 and electrode 174. This allows the application of Cu-Cu direct bonding technology (a technology that achieves electrical conductivity by connecting copper (Cu) electrodes together). Microbump bonding technology, in which microbumps are formed between electrode 173 and electrode 174, may also be applied.

[0052] Furthermore, for example, in die 180[k], the electrodes 174 and plug 175 may not be formed.

[0053] Furthermore, for example, each of the memory circuits 131[1] to 131[k] may be formed on the other side of each die 180[1] to die 180[k] in a one-to-one correspondence.

[0054] Furthermore, for example, in Figure 2(A), one side of the substrate 171 and one side of each of the dies 180[1] to 180[k] are arranged to face each other, but this is not limited to this arrangement. For example, one side of the substrate 171 and at least one other side of each of the dies 180[1] to 180[k] may be arranged to face each other. In this case, each of the dies 180[1] to 180[k] may be electrically connected to each other, for example, by joining electrodes 173 together or electrodes 174 together. Also, for example, electrodes 173 and plugs 175 may not be formed on die 180[k].

[0055] Furthermore, a state control unit 101 and an arithmetic unit 104, etc., of the semiconductor device 100 may be formed on one side of the substrate 171. Alternatively, a memory, etc., which is provided outside the semiconductor device 100, may be formed on one side of the substrate 171.

[0056] Figure 2(B) is a circuit diagram illustrating an example configuration of the semiconductor device 110A.

[0057] As shown in Figure 2(B), the semiconductor device 110A includes a scan flip-flop 120 and a data holding circuit 130A. The scan flip-flop 120 includes a selector 121 and a flip-flop 122. The data holding circuit 130A includes memory circuits 131[1] to 131[k]. The semiconductor device 110A also includes a transistor 123. The transistor 123 is formed, for example, on one side of the substrate 171.

[0058] Various signals (signals BK[1] to BK[k], RE[1] to RE[k], signal SE, signal CLK, and signal BK[0]) that control the operation of the semiconductor device 110A are supplied to the semiconductor device 110A. These various signals can be generated by the state control unit 101 described above.

[0059] In this specification, for example, each signal is assumed to be at either a high level or a low level potential, and the high level is assumed to be at a higher potential than the low level. For example, it is preferable that the potential difference between the high level and the low level is greater than the threshold voltage of the transistor to which each signal is supplied. Note that the high level and the low level may differ for each signal.

[0060] In this specification, high levels may be represented as "H" or "High," and low levels as "L" or "Low." Furthermore, setting a signal to a high level may be expressed as "set the signal to "H"" or "set the signal to "H"," and setting a signal to a low level may be expressed as "set the signal to "L"" or "set the signal to "L."

[0061] Each of signals BK[1] through BK[k] controls the saving (also called saving, storing, or backing up) of data held in flip-flop 122 within scan flip-flop 120. The data saved is then written to and held in one of the memory circuits 131[1] through 131[k] within the data holding circuit 130A.

[0062] Each of signals RE[1] through RE[k] is a circuit that controls the restoration (also called recovery, loading, or restoration) of data held in any one of the memory circuits 131[1] through 131[k] within the data holding circuit 130A. Upon data restoration, the data held in any one of the memory circuits 131[1] through 131[k] is written back to the flip-flop 122 within the scan flip-flop 120 and then held there.

[0063] Signal SE is a switching signal used to select the output of selector 121.

[0064] The signal CLK is the clock signal used to operate flip-flop 122.

[0065] The semiconductor device 110A, in synchronization with the signal CLK, stores and holds data input from terminal D or terminal SD in the flip-flop 122 within the scan flip-flop 120, and outputs it from terminal Q. The data held in flip-flop 122 is saved from terminal Q to one of the memory circuits 131[1] to 131[k] within the data holding circuit 130A, under the control of signals BK[1] to BK[k]. The data held in one of the memory circuits 131[1] to 131[k] is restored from terminal SD to flip-flop 122 under the control of signals RE[1] to RE[k].

[0066] Selector 121 has the function of transmitting the signal from terminal D or terminal SD to flip-flop 122 by controlling signal SE. Terminal D is a terminal to which data input from outside semiconductor device 110A is received. Terminal SD is a terminal to which data input from data holding circuit 130A or data input from terminal SD_IN is received. Terminal SD_IN is a terminal to which scan test data is received. Data input from terminal SD_IN is supplied to terminal SD via transistor 123, whose conduction or non-conduction state is controlled by signal BK[0].

[0067] Flip-flop 122 can use flip-flops available in a standard circuit library. For example, flip-flop 122 can use a positive edge-triggered D flip-flop. Flip-flop 122 can hold one data point by incorporating a circuit such as an inverter loop. Flip-flop 122 holds the data at input terminal Df in synchronization with the signal CLK, and outputs the held data from output terminal Qf to terminal Q.

[0068] The data retention circuit 130A can maintain the state of the scan flip-flop 120 for each task, which occurs when switching between multiple tasks, in a one-to-one correspondence with each of the memory circuits 131[1] to 131[k]. When saving data, the data retention circuit 130A selects one of the memory circuits 131[1] to 131[k] by controlling signals BK[1] to BK[k]. Similarly, when restoring data, the data retention circuit 130A selects one of the memory circuits 131[1] to 131[k] by controlling signals RE[1] to RE[k].

[0069] Various circuit configurations can be used for the memory circuits 131[1] to 131[k] provided in the data holding circuit 130A. Each of the memory circuits 131[1] to 131[k] can hold one piece of data by including a circuit such as an inverter loop. Specific examples of the configurations of the memory circuits 131[1] to 131[k] will be described later.

[0070] Furthermore, when switching tasks, the semiconductor device 100 can store the task ID of each task in a memory circuit (such as a register) provided in the state control unit 101. This allows the state control unit 101 to know which of the memory circuits 131[1] to 131[k] holds the state of the scan flip-flop 120 corresponding to each task.

[0071] Furthermore, if the number of memory circuits 131[1] to 131[k] provided in the data retention circuit 130A becomes insufficient for the number of tasks, data saving and restoration will be performed, for example, to memory provided outside the semiconductor device 100. The memory provided outside may be, for example, main memory (also called primary memory) or cache memory (also called buffer memory).

[0072] DRAM (Dynamic Random Access Memory) is commonly used as the main memory. Alternatively, DOSRAM (registered trademark) may be used instead of DRAM. DOSRAM is an abbreviation for Dynamic Oxide Semiconductor Random Access Memory. Like DRAM, DOSRAM consists of one transistor and one capacitor, but by using an OS transistor (a transistor containing an oxide semiconductor in the channel formation region) with extremely low off-current, data can be stored for long periods. Therefore, DOSRAM can significantly reduce the refresh cycle compared to DRAM. For example, the refresh cycle of DRAM is less than a millisecond, but the refresh cycle of DOSRAM can be as short as one hour to one year. Furthermore, DOSRAM can be arranged on multiple layers on a substrate 171, for example. Due to these features, DOSRAM can operate at higher speeds and reduce access energy (energy consumed by writing or reading data) compared to DRAM. Specific examples of DOSRAM configurations will be described later.

[0073] Cache memory generally uses SRAM (Static Random Access Memory). Alternatively, NOSRAM (registered trademark) may be used instead of SRAM. NOSRAM is an abbreviation for Nonvolatile Oxide Semiconductor Random Access Memory. NOSRAM is a non-volatile memory that stores data by retaining charge for a long period of time, taking advantage of the characteristics of OS transistors, which have extremely low off-current. NOSRAM also has the features of having no limit on the number of rewrites in principle and being able to write multi-level data. Furthermore, NOSRAM can be easily integrated because, for example, layers can be provided on a substrate 171 and the components can be freely arranged on those layers. Specific examples of NOSRAM configurations will be described later.

[0074] <Example of operation A> In one aspect of the present invention, the semiconductor device 110A is controlled by a state control unit 101 to save the state of the scan flip-flop 120 for each task that occurs when switching between multiple tasks. The state is saved in the memory circuits 131[1] to 131[k] in order from the one closest to the scan flip-flop 120. For example, if data is already held in memory circuit 131[1], the data is then held in memory circuit 131[2] when the task is switched. Similarly, if data is already held in memory circuits 131[1] to 131[k-1], the data is then held in memory circuit 131[k] when the task is switched. Among the memory circuits 131[1] to 131[k], the one closer to the scan flip-flop 120 has a shorter signal delay time due to the parasitic resistance and capacitance of the wiring, thus reducing the time required for saving or restoring. Therefore, the operating speed of the semiconductor device 110A can be improved.

[0075] Figures 3, 4, 5, 6(A) to 6(D), and 7(A) to 7(D) are flowcharts illustrating an example of the operation of the semiconductor device 110A.

[0076] The following example of operation of the semiconductor device 110A will describe, as an example, the case in which the data retention circuit 130A within the semiconductor device 110A has three memory circuits 131. That is, the case in which the data retention circuit 130A is composed of memory circuits 131[1] to 131[3] will be described. The following description can also be appropriately considered when the data retention circuit 130A has two memory circuits 131, or four or more memory circuits 131.

[0077] Each of the memory circuits 131[1] to 131[3] can be configured to have write access enabled or disabled. By configuring the write access status, the semiconductor device 110A is controlled by the state control unit 101 to save data to the writable memory circuits among the memory circuits 131[1] to 131[3], and not to save data to the unwritable memory circuits. The write access status information for each of the memory circuits 131[1] to 131[3] is stored, for example, in a storage circuit (e.g., a register) provided in the state control unit 101.

[0078] Data saving is performed according to the flowchart shown in Figure 3. The flowchart shown in Figure 3 will be explained below with reference to Figures 5 and 6(A) through 6(D).

[0079] First, process A1 is performed (step S101 in Figure 3).

[0080] In process A1, each of the memory circuits 131[1] to 131[3] is set to have write permission (step S131 in Figure 5).

[0081] Next, it is determined whether a task switch has occurred (step S103 in Figure 3).

[0082] When a task switch occurs, the state of scan flip-flop 120 corresponding to the currently running task is saved first.

[0083] First, it is determined whether or not the memory circuit 131[1] has write permission (step S104 in Figure 3).

[0084] If the memory circuit 131[1] is writable, process A31 is performed (step S105 in Figure 3).

[0085] If the memory circuit 131[1] is unwritable, it is determined whether the memory circuit 131[2] has write permissions (step S106 in Figure 3).

[0086] If the memory circuit 131[2] is writable, process A32 is performed (step S107 in Figure 3).

[0087] If the memory circuit 131[2] is unwritable, it is determined whether the memory circuit 131[3] has write permissions (step S108 in Figure 3).

[0088] If the memory circuit 131[3] is writable, process A33 is performed (step S109 in Figure 3).

[0089] If the memory circuit 131[3] is unwritable, process A4 is performed (step S110 in Figure 3).

[0090] In process A31, the state of the scan flip-flop 120 corresponding to the currently executing task is saved to the memory circuit 131[1] (step S1512 in Figure 6(A)), and the memory circuit 131[1] is set to unwritable (step S1513 in Figure 6(A)).

[0091] In process A32, the state of the scan flip-flop 120 corresponding to the currently executing task is saved to the memory circuit 131[2] (step S1522 in Figure 6(B)), and the memory circuit 131[2] is set to unwritable (step S1523 in Figure 6(B)).

[0092] In process A33, the state of the scan flip-flop 120 corresponding to the currently running task is saved to the memory circuit 131[3] (step S1532 in Figure 6(C)), and the memory circuit 131[3] is set to unwritable (step S1533 in Figure 6(C)).

[0093] In process A4, the state of the scan flip-flop 120 corresponding to the task currently being executed is backed up in memory (EXMEM) located outside the semiconductor device 100 (step S161 in Figure 6(D)).

[0094] In each of processes A31, A32, A33, and A4, the state of the scan flip-flop 120 corresponding to the currently executing task is saved or backed up, after which the task is suspended. At this time, the task ID of the suspended task is stored, for example, in a memory circuit (e.g., a register) provided in the state control unit 101.

[0095] After process A31, A32, A33, or A4 is completed and the task is interrupted, the state of scan flip-flop 120 corresponding to the task to be resumed is restored.

[0096] Data restoration is performed according to the flowchart shown in Figure 4. The flowchart shown in Figure 4 will be explained below with reference to Figures 7(A) to 7(D).

[0097] First, it is determined whether the state of the scan flip-flop 120 corresponding to the task to be resumed is held in memory circuit 131[1] or memory circuit 131[3] (step S121 in Figure 4). For example, this is determined by querying the task ID of the task for which resumption has been requested and the task ID held in a memory circuit (e.g., a register) provided in the state control unit 101.

[0098] If the state of the scan flip-flop 120 corresponding to the task to be resumed is held in the memory circuit 131[1], then process A51 is performed (step S122 in Figure 4).

[0099] If the state of the scan flip-flop 120 corresponding to the task to be resumed is held in the memory circuit 131[2], then process A52 is performed (step S123 in Figure 4).

[0100] If the state of the scan flip-flop 120 corresponding to the task to be resumed is held in the memory circuit 131[3], process A53 is performed (step S124 in Figure 4).

[0101] If the state of the scan flip-flop 120 corresponding to the task to be resumed is not held in any of the memory circuits 131[1] to 131[3], but is stored in memory (EXMEM) located outside the semiconductor device 100, then process A6 is performed (step S125 in Figure 4).

[0102] In process A51, the state of the scan flip-flop 120 corresponding to the task to be resumed is restored from the memory circuit 131[1] (step S1711 in Figure 7(A)), and the memory circuit 131[1] is set to writable (step S1712 in Figure 7(A)).

[0103] In process A52, the state of the scan flip-flop 120 corresponding to the task to be resumed is restored from the memory circuit 131[2] (step S1721 in Figure 7(B)), and the memory circuit 131[2] is set to writable (step S1722 in Figure 7(B)).

[0104] In process A53, the state of the scan flip-flop 120 corresponding to the task to be resumed is restored from the memory circuit 131[3] (step S1731 in Figure 7(C)), and the memory circuit 131[3] is set to writable (step S1732 in Figure 7(C)).

[0105] In process A6, the state of the scan flip-flop 120 corresponding to the task to be resumed is restored from memory (EXMEM) located outside the semiconductor device 100 (step S181 in Figure 7(D)).

[0106] After process A51, process A52, process A53, or process A6 is completed and the task is restarted, the process returns to determining whether a task switch occurred (step S103 in Figure 3).

[0107] Figure 8 illustrates an example of the operation of the semiconductor device 110A in conjunction with task switching.

[0108] Figure 8 illustrates how three tasks, Task 1, Task 2, and Task 3, are executed sequentially, switching between them at each of the times T1 through T6. The dashed arrows indicate how, when a task switches, the data for executing each of Task 1 through Task 3 is saved from the scan flip-flop 120 to memory circuits 131[1] through 131[3], and how it is restored from memory circuits 131[1] through 131[3] back into the scan flip-flop 120. The figure also illustrates how the write permission status (writable or unwritable) of each of the memory circuits 131[1] through 131[3] switches when a task switches.

[0109] Assume that Task 1 is being executed immediately before time T1. Also assume that the write permissions for each of the memory circuits 131[1] to 131[3] are set to "write permission granted".

[0110] At time T1, task 1 is interrupted and task 2 is started. That is, while task 1 is running, the data in the scan flip-flop 120 is saved to the memory circuit 131[1], and the system is switched to a state where task 2 can be executed. Here, as an example, let's assume that the data for executing task 2 is not held in any of the memory circuits 131[1] or 131[3], and is written from external memory to the scan flip-flop 120. After the saving to the memory circuit 131[1] is complete, the write permission for the memory circuit 131[1] is set to no write permission.

[0111] At time T2, Task 2 is interrupted and Task 1 is resumed. That is, while Task 2 is running, the data in the scan flip-flop 120 is saved to the memory circuit 131[2], and the data in the memory circuit 131[1] is restored to the scan flip-flop 120, thereby switching Task 1 to an executable state. As a result, Task 1 resumes from the point where it was interrupted at time T1. After the saving to the memory circuit 131[2] is complete, the write permission for the memory circuit 131[2] is set to no write permission. After the restoration from the memory circuit 131[1] is complete, the write permission for the memory circuit 131[1] is set to write permission enabled.

[0112] At time T3, task 1 is interrupted and task 3 is started. That is, while task 1 is running, the data in the scan flip-flop 120 is saved to the memory circuit 131[1], and the system is switched to a state where task 3 can be executed. Here, as an example, let's assume that the data for executing task 3 is not held in either the memory circuit 131[1] or the memory circuit 131[3], and is written from external memory to the scan flip-flop 120. After the saving to the memory circuit 131[1] is complete, the write permission for the memory circuit 131[1] is set to no write permission.

[0113] At time T4, task 3 is interrupted and task 2 is resumed. That is, while task 3 is running, the data in scan flip-flop 120 is saved to memory circuit 131[3], and the data in memory circuit 131[2] is restored to scan flip-flop 120, thereby switching to a state where task 2 can be executed. As a result, task 2 resumes from the point where it was interrupted at time T2. After the saving to memory circuit 131[3] is complete, the write permission for memory circuit 131[3] is set to no write permission. Also, after the restoration from memory circuit 131[2] is complete, the write permission for memory circuit 131[2] is set to write permission enabled.

[0114] At time T5, Task 2 is completed and Task 3 is resumed. That is, with Task 2 completed, the data from memory circuit 131[3] is restored to scan flip-flop 120, switching the system to a state where Task 3 can be executed. As a result, Task 3 resumes from where it was interrupted at time T4. After the restoration from memory circuit 131[3] is complete, the write permission for memory circuit 131[3] is set to write permission enabled.

[0115] At time T6, task 3 is interrupted and task 1 is resumed. That is, while task 3 is running, the data in scan flip-flop 120 is saved to memory circuit 131[2], and the data in memory circuit 131[1] is restored to scan flip-flop 120, thereby switching to a state where task 1 can be executed. As a result, task 1 resumes from the point where it was interrupted at time T3. After the saving to memory circuit 131[2] is complete, the write permission for memory circuit 131[2] is set to no write permission. After the restoration from memory circuit 131[1] is complete, the write permission for memory circuit 131[1] is set to write permission enabled.

[0116] By operating the semiconductor device 110A as described above, a task can be resumed from the point in time when it was interrupted by a task switch. Furthermore, by operating the semiconductor device 110A as described above, when saving data for executing a task in conjunction with a task switch, the data can be stored in memory circuits 131[1] to 131[3] in order from the one closest to the scan flip-flop 120. In the semiconductor device 110A, the signal delay time due to parasitic resistance and capacitance of the wiring is shorter in any of the memory circuits 131[1] to 131[k] that is closer to the scan flip-flop 120. Therefore, by operating the semiconductor device 110A as described above, the time required for saving or restoring can be reduced. Thus, the operating speed of the semiconductor device 110A can be improved.

[0117] [Configuration Example Aa] As described above, various circuit configurations can be used as the memory circuits 131[1] to 131[k] provided in the data holding circuit 130A.

[0118] Figure 9 is a circuit diagram illustrating an example configuration of a semiconductor device 110Aa that includes a data retention circuit 130Aa.

[0119] The data retention circuit 130Aa includes memory circuits 131a[1] to 131a[k].

[0120] Each of signals BK[1] to BK[k] and each of signals RE[1] to RE[k] are supplied to each of memory circuits 131a[1] to 131a[k] in a one-to-one correspondence.

[0121] In this embodiment, etc., the contents common to each of the memory circuits 131a[1] to 131a[k] may be described as memory circuit 131a. In that case, each of the signals BK[1] to BK[k] may be described as signal BK, and each of the signals RE[1] to RE[k] may be described as signal RE.

[0122] As shown in Figure 9, the memory circuit 131a is connected to terminals Q and SD. In the memory circuit 131a, the terminal (wiring) connected to terminal Q is an input terminal, and the terminal (wiring) connected to terminal SD is an output terminal. In other words, in the semiconductor device 110Aa, the output terminal Qf of the flip-flop 122 is electrically connected to the input terminal of the memory circuit 131a, and the input terminal Df of the flip-flop 122 is electrically connected to the output terminal of the memory circuit 131a via the selector 121.

[0123] The memory circuit 131a includes inverter 13a, inverter 13b, clocked inverter 132, inverter 133, clocked inverter 134, and inverter 135.

[0124] Note that inverters 13a, 13b, 133, and 135 can each be replaced with inverters provided in the standard circuit library. Similarly, clocked inverters 132 and 134 can each be replaced with clocked inverters provided in the standard circuit library.

[0125] In the memory circuit 131a, the input terminal of the clocked inverter 132 is electrically connected to terminal Q. The output terminal of the clocked inverter 132 is electrically connected to the input terminal of inverter 13a, the output terminal of inverter 13b, and the input terminal of clocked inverter 134. The output terminal of inverter 13a is electrically connected to the input terminal of inverter 13b. The output terminal of clocked inverter 134 is connected to terminal SD.

[0126] In other words, the input terminal of the clocked inverter 132 is the input terminal of the memory circuit 131a, and the output terminal of the clocked inverter 134 is the output terminal of the memory circuit 131a.

[0127] In addition, in each of the memory circuits 131a[1] to 131a[k], the node to which the output terminal of inverter 13a and the input terminal of inverter 13b are electrically connected may be described as node SN[1] to node SN[k]. Furthermore, when describing content common to each of the memory circuits 131a[1] to 131a[k], each of node SN[1] to node SN[k] may be described as node SN.

[0128] The memory circuit 131a can hold one piece of data at node SN through an inverter loop formed by inverters 13a and 13b.

[0129] Signal BK is supplied to one of the control terminals of the clocked inverter 132, and also supplied to the other control terminal of the clocked inverter 132 via inverter 133. Signal BK is a signal for saving the data held by the flip-flop 122 to the memory circuit 131a.

[0130] The clocked inverter 132 becomes an inverter or a non-conducting state depending on the signal BK. For example, the clocked inverter 132 becomes an inverter when the signal BK = "H", or becomes a non-conducting state when the signal BK = "L".

[0131] Signal RE is supplied to one of the control terminals of the clocked inverter 134, and also supplied to the other control terminal of the clocked inverter 134 via inverter 135. Signal RE is a signal for restoring the data held in the memory circuit 131a to the flip-flop 122.

[0132] The clocked inverter 134 becomes an inverter or a non-conducting state depending on the signal RE. For example, the clocked inverter 134 becomes an inverter when the signal RE = "H", or becomes a non-conducting state when the signal RE = "L".

[0133] Selector 121 selects and outputs the signal from either terminal SD or terminal D according to the signal SE. For example, by setting signal SE = "H", selector 121 selects and outputs the signal from terminal SD, or by setting signal SE = "L", selects and outputs the signal from terminal D.

[0134] The memory circuit 131a can write data held by the flip-flop 122 to node SN by setting the signal BK = "H". Furthermore, the memory circuit 131a can write data held by node SN back to the flip-flop 122 by setting the signal RE = "H" and the signal SE = "H".

[0135] The data holding circuit 130Aa can save the data held by the flip-flop 122 to one of the memory circuits 131a[1] to 131a[k] by setting one of the signals BK[1] to BK[k] to "H". For example, by setting signal BK[1] = "H", the data held by the flip-flop 122 can be written to node SN[1] of memory circuit 131a[1]. Similarly, for example, by setting signal BK[k] = "H", the data held by the flip-flop 122 can be written to node SN[k] of memory circuit 131a[k].

[0136] The data holding circuit 130Aa can restore data held in any one of the memory circuits 131a[1] to 131a[k] to the flip-flop 122 by setting any one of the signals RE[1] to RE[k] to "H". For example, by setting signal RE[1] = "H" and signal SE = "H", data held in node SN[1] of memory circuit 131a[1] can be written back to the flip-flop 122. Similarly, for example, by setting signal RE[k] = "H" and signal SE = "H", data held in node SN[k] of memory circuit 131a[k] can be written back to the flip-flop 122.

[0137] [Example of operation Aa] The operation of the data retention circuit 130Aa will be explained.

[0138] Figure 10 is a timing chart illustrating an example of the operation of a semiconductor device 110Aa equipped with a data retention circuit 130Aa. As an example, the case where the data retention circuit 130Aa within the semiconductor device 110Aa has three memory circuits 131a is described.

[0139] Figure 10 illustrates the state (high level or low level) of each signal, CLK, BK[1] to BK[3], RE[1] to RE[3], and SE, during each of the periods T11 to T18. It also illustrates the state of the data (any one of data D1 to D7) assigned to each of terminals Q, D, SD, and nodes SN[1] to SN[3]. Furthermore, it illustrates the write permission state (writable or unwritable) of each of the memory circuits 131a[1] to 131a[3].

[0140] During each of the periods T11 through T18, the flip-flop 122 stores the data at the input terminal Df and outputs it from the output terminal Qf, synchronized with the timing (rising edge) when the signal CLK switches from "L" to "H".

[0141] Figures 11(A) to 11(D) and 12(A) to 12(D) are schematic diagrams illustrating the state of the semiconductor device 110Aa during each period of the timing chart shown in Figure 10.

[0142] Figures 11(A) to 11(D) and Figures 12(A) to 12(D) each illustrate the state of the semiconductor device 110Aa during the period before the rising edge of signal CLK (indicated by the sign "-1" for each period) and the state of the semiconductor device 110Aa during the period after the rising edge of signal CLK (indicated by the sign "-2" for each period) for each period T11 to T18.

[0143] During period T11, the signals BK[1] through BK[3], RE[1] through RE[3], and SE are all assumed to be "L". Furthermore, the write permissions for memory circuits 131a[1] through 131a[3] are assumed to be granted. In the following explanation, unless otherwise specified, the state of each signal and each memory circuit regarding write permissions is assumed to be maintained as it was in the previous period.

[0144] Synchronized with the rising edge of signal CLK, data D1, which is input to terminal D, is stored in scan flip-flop 120 and output to terminal Q (period T11-2 in Figure 11(A)).

[0145] During period T12, the write permissions for memory circuits 131a[1] through 131a[3] are initially set to "write permission granted". Additionally, the data D1 stored in the scan flip-flop 120 is output to terminal Q. By setting the signal BK[1] to "H", the data D1 output to terminal Q is stored in node SN[1] of memory circuit 131a[1] (period T12-1 in Figure 11(B)). Subsequently, by setting the signal BK[1] to "L", the data D1 stored in node SN[1] is retained. Furthermore, the write permission for memory circuit 131a[1] is set to "write permission denied".

[0146] Next, synchronized with the rising edge of signal CLK, data D2, which is input to terminal D, is stored in scan flip-flop 120 and output to terminal Q (period T12-2 in Figure 11(B)).

[0147] During period T13, first, the write permissions for memory circuits 131a[2] and 131a[3] are set to "write permission granted," while the write permission for memory circuit 131a[1] is set to "write permission denied." Also, the data D2 stored in scan flip-flop 120 is output to terminal Q. Here, by setting signal BK[2] = "H," the data D2 output to terminal Q is stored in node SN[2] of memory circuit 131a[2] (period T13-1 in Figure 11(C)). Subsequently, by setting signal BK[2] = "L," the data D2 stored in node SN[2] is retained. Also, the write permission for memory circuit 131a[2] is set to "write permission denied."

[0148] Next, by setting signal RE[1]=“H”, data D1 stored in node SN[1] of memory circuit 131a[1] is supplied to terminal SD. Data D3 is supplied to terminal D, but by setting signal SE=“H”, terminal SD is selected. At this point, synchronized with the rising edge of signal CLK, data D1 supplied to terminal SD is stored in scan flip-flop 120 and output to terminal Q (period T13-2 in Figure 11(C)). After that, signal RE[1]=“L”, and signal SE=“L”. Also, the write permission of memory circuit 131a[1] is set to write permission enabled.

[0149] During period T14, first, the write permissions for memory circuits 131a[1] and 131a[3] are granted, while the write permission for memory circuit 131a[2] is denied. Also, the data D1 stored in the scan flip-flop 120 is output to terminal Q (period T14-1 in Figure 11(D)).

[0150] Next, synchronized with the rising edge of signal CLK, data D4, which is supplied to terminal D, is stored in scan flip-flop 120 and output to terminal Q (period T14-2 in Figure 11(D)).

[0151] During period T15, first, the write permissions for memory circuits 131a[1] and 131a[3] are set to "write permission granted," while the write permission for memory circuit 131a[2] is set to "write permission denied." Also, the data D4 stored in scan flip-flop 120 is output to terminal Q. Here, by setting signal BK[1] = "H," the data D4 output to terminal Q is stored in node SN[1] of memory circuit 131a[1] (period T15-1 in Figure 12(A)). Subsequently, by setting signal BK[1] = "L," the data D4 stored in node SN[1] is retained. Also, the write permission for memory circuit 131a[1] is set to "write permission denied."

[0152] Next, synchronized with the rising edge of signal CLK, data D5, which is input to terminal D, is stored in scan flip-flop 120 and output to terminal Q (period T15-2 in Figure 12(A)).

[0153] During period T16, first, the write privilege for memory circuit 131a[3] is granted, while the write privileges for memory circuits 131a[1] and 131a[2] are denied. Also, the data D5 stored in scan flip-flop 120 is output to terminal Q. Here, by setting signal BK[3] = "H", the data D5 output to terminal Q is stored in node SN[3] of memory circuit 131a[3] (period T16-1 in Figure 12(B)). Subsequently, by setting signal BK[3] = "L", the data D5 stored in node SN[3] is retained. Also, the write privilege for memory circuit 131a[3] is set to denied.

[0154] Next, by setting signal RE[2]=“H”, data D2 stored in node SN[2] of memory circuit 131a[2] is supplied to terminal SD. Although data D6 is supplied to terminal D, terminal SD is selected by setting signal SE=“H”. At this point, synchronized with the rising edge of signal CLK, data D2 supplied to terminal SD is stored in scan flip-flop 120 and output to terminal Q (period T16-2 in Figure 12(B)). After that, signal RE[2]=“L”, and signal SE=“L”. Also, the write permission of memory circuit 131a[2] is set to write permission enabled.

[0155] During period T17, first, the write permission for memory circuit 131a[2] is granted, while the write permission for memory circuits 131a[1] and 131a[3] is denied. Also, the data D2 stored in scan flip-flop 120 is output to terminal Q (period T17-1 in Figure 12(C)).

[0156] Next, by setting signal RE[3]=“H”, data D5 stored in node SN[3] of memory circuit 131a[3] is supplied to terminal SD. Data D7 is supplied to terminal D, but by setting signal SE=“H”, terminal SD is selected. At this point, synchronized with the rising edge of signal CLK, data D5 supplied to terminal SD is stored in scan flip-flop 120 and output to terminal Q (period T17-2 in Figure 12(C)). After that, signal RE[3]=“L”, and signal SE=“L”. Also, the write permission of memory circuit 131a[3] is set to write permission enabled.

[0157] During period T18, first, the write permissions for memory circuits 131a[2] and 131a[3] are granted, while the write permission for memory circuit 131a[1] is denied. Also, the data D5 stored in the scan flip-flop 120 is output to terminal Q (period T18-1 in Figure 12(D)).

[0158] [Configuration example Ab] The memory circuits 131[1] to 131[k] of the data retention circuit 130A can also be configured with a different circuit configuration than that of the memory circuit 131a described above. Here, as an example, a data retention circuit 130Ab equipped with a memory circuit 131b and a semiconductor device 110Ab equipped with a data retention circuit 130Ab will be described. Note that the semiconductor device 110Ab is a modified version of the semiconductor device 110Aa described above. Therefore, the above explanation can be appropriately referenced, and explanations of similar points may be omitted.

[0159] Figure 13 is a circuit diagram illustrating an example configuration of a semiconductor device 110Ab equipped with a data retention circuit 130Ab.

[0160] The semiconductor device 110Ab differs from the semiconductor device 110Aa in that it includes a data retention circuit 130Ab instead of the data retention circuit 130Aa. Furthermore, the data retention circuit 130Ab differs from the data retention circuit 130Aa in that it includes memory circuits 131b[1] to 131b[k] instead of memory circuits 131a[1] to 131a[k].

[0161] In this embodiment, etc., the contents common to each of the memory circuits 131b[1] to 131b[k] may be described as memory circuit 131b.

[0162] Furthermore, the semiconductor device 110Ab includes, in addition to the configuration of the semiconductor device 110Aa, an inverter 124, a precharge circuit 125, and a sense amplifier 126. Each of the inverter 124, the precharge circuit 125, and the sense amplifier 126 is formed on one side of the substrate 171.

[0163] A signal PC_EN, which controls the operation of the precharge circuit 125, is supplied to the semiconductor device 110Ab. The signal PC_EN can be generated by the state control unit 101 described above.

[0164] As shown in Figure 13, the memory circuit 131b is connected to terminal Q, terminal QB, node BLb, and node BLBb. In the memory circuit 131b, the terminal (wiring) connected to terminal Q is one of the input terminals, and the terminal (wiring) connected to terminal QB is the other of the input terminals. Also, in the memory circuit 131b, the terminal (wiring) connected to node BLb is one of the output terminals, and the terminal to which node BLBb is connected is the other of the output terminals.

[0165] As shown in Figure 13, terminal Q is connected to the input terminal of inverter 124, and terminal QB is connected to the output terminal of inverter 124. Node BLb is connected to one of the input terminals of sense amplifier 126 via precharge circuit 125, and node BLBb is connected to the other input terminal of sense amplifier 126 via precharge circuit 125. Terminal SD is connected to the output terminal of sense amplifier 126.

[0166] In other words, in semiconductor device 110Ab, the output terminal Qf of the flip-flop 122 is electrically connected to one of the input terminals of the memory circuit 131b, and is electrically connected to the other input terminal of the memory circuit 131b via the inverter 124. Also, the input terminal Df of the flip-flop is electrically connected to the output terminal of the sense amplifier 126 via the selector 121. Furthermore, one of the input terminals of the sense amplifier 126 is electrically connected to one of the output terminals of the memory circuit 131b via the precharge circuit 125 and node BLb, and the other input terminal of the sense amplifier 126 is electrically connected to the other output terminal of the memory circuit 131b via the precharge circuit 125 and node BLBb.

[0167] The memory circuit 131b includes inverter 13a, inverter 13b, transistor 136, transistor 137, transistor 138, and transistor 139.

[0168] In the memory circuit 131b, one source or drain of transistor 136 is electrically connected to the output terminal of inverter 13a, the input terminal of inverter 13b, and one source or drain of transistor 138. One source or drain of transistor 137 is electrically connected to the input terminal of inverter 13a, the output terminal of inverter 13b, and one source or drain of transistor 139. The other source or drain of transistor 136 is electrically connected to terminal Q. The other source or drain of transistor 137 is electrically connected to terminal QB. The other source or drain of transistor 138 is electrically connected to node BLb. The other source or drain of transistor 139 is electrically connected to node BLBb.

[0169] In other words, the other source or drain of transistor 136 is one of the input terminals of memory circuit 131b, and the other source or drain of transistor 137 is the other input terminal of memory circuit 131b. Also, the other source or drain of transistor 138 is one of the output terminals of memory circuit 131b, and the other source or drain of transistor 139 is the other output terminal of memory circuit 131b.

[0170] The signal BK is supplied to the gates of transistor 136 and transistor 137.

[0171] Transistors 136 and 137 become either conductive or non-conductive depending on the signal BK. For example, transistors 136 and 137 become conductive when the signal BK = "H", or non-conductive when the signal BK = "L".

[0172] The signal RE is supplied to the gates of transistor 138 and transistor 139.

[0173] Transistors 138 and 139 become conductive or non-conductive depending on the signal RE. For example, transistors 138 and 139 become conductive when the signal RE = "H", or non-conductive when the signal BK = "L".

[0174] The memory circuit 131b can write the data held by the flip-flop 122 to node SN by setting the signal BK = "H". Furthermore, the memory circuit 131b can write the data held by node SN back to the flip-flop 122 via the pre-charge circuit 125 and the sense amplifier 126 by setting the signal RE = "H" and the signal SE = "H".

[0175] The precharge circuit 125 has the function of precharging nodes BLb and BLBb respectively just before the signal RE = "H" by controlling the signal PC_EN. For example, the precharge circuit 125 can precharge nodes BLb and BLBb respectively to an intermediate potential between high level and low level by controlling the signal PC_EN.

[0176] The sense amplifier 126 has the function of amplifying the potential difference between one input terminal and the other and outputting it to the output terminal. For example, after precharging nodes BLb and BLBb respectively with the precharge circuit 125, setting the signal RE = "H" causes one of nodes BLb or BLBb to be at a higher potential than the precharged potential, and the other node BLb or BLBb to be at a lower potential than the precharged potential by the precharge circuit 125. As a result, a potential difference is created between nodes BLb and BLBb. The sense amplifier 126 can amplify the potential difference created between nodes BLb and BLBb and output it to terminal SD.

[0177] [Example of operation Ab] The operation of the data retention circuit 130Ab will be explained.

[0178] Figure 14 is a timing chart illustrating an example of the operation of a semiconductor device 110Ab equipped with a data retention circuit 130Ab. As an example, the case where the data retention circuit 130Ab within the semiconductor device 110Ab has three memory circuits 131b is described.

[0179] The timing chart shown in Figure 14 illustrates the state of the signal PC_EN (high level or low level) in addition to the timing chart shown in Figure 10. The states of signals other than PC_EN are the same as those shown in the timing chart in Figure 10.

[0180] The timing chart in Figure 14 shows that in each of the periods T13, T16, and T17, the signal PC_EN="H" is set for a certain period before the signal RE="H". Setting the signal PC_EN="H" starts precharging to nodes BLb and BLBb, respectively. After a certain period, setting the signal PC_EN="L" stops the precharging to nodes BLb and BLBb, respectively. Subsequently, setting the signal RE="H" creates a potential difference between nodes BLb and BLBb according to the data held in node SN. Furthermore, setting the signal SE="H" allows the potential difference between nodes BLb and BLBb to be amplified by the sense amplifier 126 and written back to the flip-flop 122.

[0181] The configurations of the semiconductor device 110Aa shown in Figure 9 and the semiconductor device 110Ab shown in Figure 13 can be used interchangeably depending on the specific features of each device. For example, the memory circuit 131b in the semiconductor device 110Ab has fewer transistors than the memory circuit 131a in the semiconductor device 110Aa. Therefore, the semiconductor device 110Ab can achieve a higher memory density than the semiconductor device 110Aa. On the other hand, for example, the semiconductor device 110Aa does not require precharging when writing data from node SN back to the flip-flop 122. Therefore, the semiconductor device 110Aa can operate at a faster speed than the semiconductor device 110Ab.

[0182] <Configuration example B> As a register 110 according to one aspect of the present invention, a configuration different from the semiconductor device 110A described above can also be used. Here, as an example, semiconductor device 110B will be described. Note that semiconductor device 110B is a modified version of semiconductor device 110A described above. Therefore, the above description can be appropriately referenced, and mainly the differences will be described, while the explanation of similar points may be omitted.

[0183] Figure 15(A) is a schematic diagram illustrating an example configuration of a semiconductor device 110B according to one aspect of the present invention. The semiconductor device 110B is an example of a configuration that can be suitably used in the above-described register 110.

[0184] The semiconductor device 110B differs from the semiconductor device 110A in that it is equipped with a data retention circuit 130B instead of the data retention circuit 130A.

[0185] In addition to the configuration of the data holding circuit 130A, the data holding circuit 130B is formed such that each of the layers 182[1] to 182[k] corresponds one-to-one on one side of each die 180[1] to 180[k]. Each of the layers 182[1] to 182[k] is a layer on which an OS transistor or a circuit including an OS transistor is provided.

[0186] OS transistors have the characteristic of extremely low off-current (the current that flows between the source and drain when the transistor is in the off state) because the band gap of the oxide semiconductor in which the channel is formed is 2 eV or more. At room temperature, the off-current value of an OS transistor per 1 μm of channel width is 1 aA (1 × 10⁻¹⁶). -18 A) Below, 1zA(1×10 -21 A) Less than or equal to 1yA(1×10 -24 A) It can be less than or equal to the following. Note that in the case of a Si transistor, the off-current value per 1 μm of channel width at room temperature is 1 fA (1 × 10⁻¹⁶). -15 A) and 1pA(1×10 -12 A) The answer is as follows. Therefore, it can be said that the off-current of an OS transistor is about 10 orders of magnitude lower than that of a Si transistor.

[0187] Furthermore, OS transistors exhibit almost no increase in off-current even in high-temperature environments. Specifically, the off-current hardly increases even at ambient temperatures between room temperature and 200°C. Also, OS transistors do not experience a significant decrease in on-current even in high-temperature environments. On the other hand, Si transistors experience a decrease in on-current at high temperatures. In other words, OS transistors have a higher on-current than Si transistors at high temperatures. Moreover, OS transistors maintain a large on-current-to-off-current ratio even at ambient temperatures between 125°C and 150°C, enabling smooth switching operation. Therefore, semiconductor devices containing OS transistors operate stably and with high reliability even in high-temperature environments.

[0188] The semiconductor layer of the OS transistor preferably contains at least one of indium and zinc. Furthermore, the semiconductor layer of the OS transistor preferably contains, for example, indium, M (where M is one or more selected from gallium, aluminum, yttrium, tin, silicon, boron, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, and cobalt), and zinc. In particular, M is preferably one or more selected from gallium, aluminum, yttrium, and tin.

[0189] In particular, it is preferable to use an oxide containing indium (In), gallium (Ga), and zinc (Zn) (also referred to as "IGZO") as the semiconductor layer. Alternatively, an oxide containing indium (In), aluminum (Al), and zinc (Zn) (also referred to as "IAZO") may be used as the semiconductor layer. Alternatively, an oxide containing indium (In), aluminum (Al), gallium (Ga), and zinc (Zn) (also referred to as "IAGZO") may be used as the semiconductor layer.

[0190] When the semiconductor layer is an In-M-Zn oxide, it is preferable that the atomic ratio of In in the In-M-Zn oxide is equal to or greater than the atomic ratio of M. Examples of atomic ratios of metal elements in such In-M-Zn oxides include compositions where In:M:Zn = 1:1:1 or close to it, In:M:Zn = 1:1:1.2 or close to it, In:M:Zn = 2:1:3 or close to it, In:M:Zn = 3:1:2 or close to it, In:M:Zn = 4:2:3 or close to it, In:M:Zn = 4:2:4.1 or close to it, In:M:Zn = 5:1:3 or close to it, In:M:Zn = 5:1:6 or close to it, In:M:Zn = 5:1:7 or close to it, In:M:Zn = 5:1:8 or close to it, In:M:Zn = 6:1:6 or close to it, or In:M:Zn = 5:2:5 or close to it. Furthermore, the atomic ratio of In in the In-M-Zn oxide may be smaller than the atomic ratio of M. Examples of such In-M-Zn oxide atomic ratios include In:M:Zn = 1:3:2 or a composition close to it, or In:M:Zn = 1:3:4 or a composition close to it. Note that a composition close to it includes a range of plus or minus 30% of the desired atomic ratio.

[0191] In each of layers 182[1] to 182[k], a conductor 172 is formed to electrically connect the electrode 173 and the plug 175. The conductor 172 functions as either a plug or wiring. That is, the electrode 173 is electrically connected to the electrode 174 via the conductor 172 and the plug 175 in sequence. In this specification, the wiring and the plug to which the wiring is electrically connected may be an integrated unit. That is, a part of the conductor may function as wiring, and a part of the conductor may function as a plug.

[0192] Furthermore, conductive materials such as metal materials, alloy materials, metal nitride materials, or metal oxide materials can be used as the material for the conductor 172, either in a single layer or in a laminated form. It is preferable to use a high-melting-point material such as tungsten or molybdenum as the material for the conductor 172, which provides both heat resistance and conductivity. Alternatively, it is preferable to use a low-resistance conductive material such as aluminum or copper as the material for the conductor 172. By using a low-resistance conductive material for the conductor 172, the wiring resistance can be reduced. In the semiconductor device 110B, by reducing the wiring resistance of the conductor 172, the signal delay time is shortened, and therefore the time required for saving or restoring can be reduced. Thus, the operating speed of the semiconductor device 110B can be improved.

[0193] Figure 15(B) is a circuit diagram illustrating an example configuration of the semiconductor device 110B.

[0194] As shown in Figure 15(B), the data retention circuit 130B of the semiconductor device 110B includes layers 182[1] to 182[k] in addition to the configuration of the data retention circuit 130A. Each of layers 182[1] to 182[k] is formed to have a one-to-one correspondence with each of transistors MS1[1] to MS1[k] and each of transistors MS2[1] to MS2[k].

[0195] Each of the signals SW[1] through SW[k] is supplied in a one-to-one correspondence to the respective gates of transistors MS1[1] through MS1[k] and transistors MS2[1] through MS2[k]. Each of the signals SW[1] through SW[k] can be generated by the state control unit 101 described above.

[0196] Each of the transistors MS1[1] through MS1[k] and each of the transistors MS2[1] through MS2[k] will be either conducting or non-conducting depending on the signal SW[1] through signal SW[k]. For example, transistors MS1[1] and MS2[1] will be conducting when signal SW[1] = "H", or non-conducting when signal SW[1] = "L". Similarly, for example, transistors MS1[k] and MS2[k] will be conducting when signal SW[k] = "H", or non-conducting when signal SW[k] = "L". The same applies to each of the transistors MS1[2] through MS1[k-1] and each of the transistors MS2[2] through MS2[k-1].

[0197] One source or drain of each transistor MS1[1] through MS1[k] is electrically connected to each of the memory circuits 131[1] through MS1[k] in a one-to-one correspondence. The other source or drain of transistor MS1[1] is electrically connected to terminal Q. The other source or drain of each transistor MS1[2] through MS1[k] is electrically connected to one source or drain of each transistor MS1[1] through MS1[k-1] in a one-to-one correspondence.

[0198] One source or drain of each transistor MS2[1] through MS2[k] is electrically connected to each of the memory circuits 131[1] through MS2[k] in a one-to-one correspondence. The other source or drain of transistor MS2[1] is electrically connected to terminal SD. The other source or drain of each transistor MS2[2] through MS2[k] is electrically connected to one source or drain of each transistor MS2[1] through MS2[k-1] in a one-to-one correspondence.

[0199] <Example of operation B> In one aspect of the present invention, the semiconductor device 110B, similar to the semiconductor device 110A described above, is controlled by the state control unit 101 to save the state of the scan flip-flop 120 for each task that occurs when switching between multiple tasks, so as to store the data in the memory circuits 131[1] to 131[k] in order from the one closest to the scan flip-flop 120.

[0200] In this case, the semiconductor device 110B can, by controlling signal SW[1] to signal SW[k], make the memory circuit 131 in which data is held and terminal Q and terminal SD conductive, and make the memory circuit 131 in which data is not held and terminal Q and terminal SD non-conductive. For example, if data is held in memory circuit 131[1] and no data is held in memory circuits 131[2] to 131[k], setting signal SW[1] to "H" will make transistor MS1[1] and transistor MS2[1] conductive, and setting signal SW[2] to signal SW[k] to "L" will make transistor MS1[2] to transistor MS1[k] and transistor MS2[2] to transistor MS2[k] non-conductive.

[0201] The semiconductor device 110B can reduce parasitic capacitance in the wiring between the memory circuit 131 (which holds data) and terminals Q and SD by making the connection between the memory circuit 131 (which does not hold data) and terminals Q and SD non-conductive. In other words, for example, when the number of tasks being performed is small, the semiconductor device 110B can reduce parasitic capacitance in the wiring between the scan flip-flop 120 and the memory circuit 131 (which holds data) by controlling signals SW[1] to SW[k]. As a result, energy consumption associated with saving or restoring can be reduced. In addition, the signal delay time is shortened, so the time required for saving or restoring can be reduced. Thus, the power consumption of the semiconductor device 110B can be reduced and the operating speed can be improved.

[0202] As mentioned above, each of the transistors MS1[1] to MS1[k] and each of the transistors MS2[1] to MS2[k] are OS transistors, and therefore have extremely low off-currents in the non-conductive state. Furthermore, even in environments susceptible to heat generation due to calculation processing in the arithmetic unit 104 within the semiconductor device 100, for example, the off-current hardly increases.

[0203] Therefore, if there is a task that is not used for a long period of time, for example, the semiconductor device 110B can reduce parasitic capacitance in the wiring while retaining the data corresponding to that task for a long period of time by making the connection between the memory circuit 131, which holds the data corresponding to that task, and terminals Q and SD non-conductive. As a result, the power consumption of the semiconductor device 110B can be reduced and the operating speed can be improved.

[0204] Figures 16, 17, and 18(A) to 18(C) are flowcharts illustrating an example of the operation of the semiconductor device 110B. Figures 4, 5, 6(D), and 7(A) to 7(D) may also be referenced as appropriate in the following examples of the operation of the semiconductor device 110B.

[0205] In the following example of the operation of the semiconductor device 110B, we will describe the case where the data holding circuit 130B within the semiconductor device 110B has three memory circuits 131. As an example of the operation of the semiconductor device 110B, the flowchart shown in Figure 16 is used instead of the flowchart shown in Figure 3. In the flowchart shown in Figure 16, in addition to the flowchart shown in Figure 3, step S202 is performed. Also, the flowchart shown in Figure 16 differs from the flowchart shown in Figure 3 in that steps S205, S207, and S209 are performed instead of steps S105, S107, and S109, respectively.

[0206] Data saving is performed according to the flowchart shown in Figure 16. The flowchart shown in Figure 16 will be explained below with reference to Figures 5, 6(D), 17, and 18(A) through 18(C).

[0207] First, process A1 is performed (step S101 in Figure 16).

[0208] Next, Process B2 is performed (step S202 in Figure 16).

[0209] In process B2, according to the flowchart shown in Figure 17, each of the signals SW[1] to SW[3] is set to either high or low level, depending on whether or not there is write permission for each of the memory circuits 131[1] to 131[3].

[0210] First, it is determined whether or not the memory circuit 131[3] has write permission (step S241 in Figure 17).

[0211] If the memory circuit 131[3] is unwritable, process B2 is completed. If the memory circuit 131[3] is writable, the signal SW[3] is set to "L" (step S242 in Figure 17).

[0212] Next, it is determined whether or not the memory circuit 131[2] has write permission (step S243 in Figure 17).

[0213] If the memory circuit 131[2] is unwritable, process B2 is completed. If the memory circuit 131[2] is writable, the signal SW[2] is set to "L" (step S244 in Figure 17).

[0214] Next, it is determined whether or not the memory circuit 131[1] has write permission (step S245 in Figure 17).

[0215] If the memory circuit 131[1] is unwritable, process B2 is completed. If the memory circuit 131[1] is writable, the signal SW[1] is set to "L" (step S246 in Figure 17), and process B2 is completed.

[0216] After process B2 is completed, it is determined whether a task switch has occurred (step S103 in Figure 16).

[0217] When a task switch occurs, the state of scan flip-flop 120 corresponding to the currently running task is saved first.

[0218] First, it is determined whether or not the memory circuit 131[1] has write permission (step S104 in Figure 16).

[0219] If the memory circuit 131[1] is writable, process B31 is performed (step S205 in Figure 16).

[0220] If the memory circuit 131[1] is unwritable, it is determined whether the memory circuit 131[2] has write permissions (step S106 in Figure 16).

[0221] If the memory circuit 131[2] is writable, process B32 is performed (step S207 in Figure 16).

[0222] If the memory circuit 131[2] is unwritable, it is determined whether the memory circuit 131[3] has write permissions (step S108 in Figure 16).

[0223] If the memory circuit 131[3] is writable, process B33 is performed (step S209 in Figure 16).

[0224] If the memory circuit 131[3] is unwritable, process A4 is performed (step S110 in Figure 16).

[0225] In process B31, first, signal SW[1] is set to "H" (step S2511 in Figure 18(A)). Then, the state of the scan flip-flop 120 corresponding to the task currently being executed is saved to the memory circuit 131[1] (step S1512 in Figure 18(A)), and the memory circuit 131[1] is set to unwritable (step S1513 in Figure 18(A)).

[0226] In process B32, first, signal SW[2] is set to "H" (step S2521 in Figure 18(B)). Then, the state of the scan flip-flop 120 corresponding to the task currently being executed is saved to the memory circuit 131[2] (step S1522 in Figure 18(B)), and the memory circuit 131[2] is set to unwritable (step S1523 in Figure 18(B)).

[0227] In process B33, first, signal SW[3] is set to "H" (step S2531 in Figure 18(C)). Then, the state of the scan flip-flop 120 corresponding to the task currently being executed is saved to the memory circuit 131[3] (step S1532 in Figure 18(C)), and the memory circuit 131[3] is set to unwritable (step S1533 in Figure 18(C)).

[0228] After process B31, process B32, process B33, or process A4 is completed and the task is interrupted, the state of the scan flip-flop 120 corresponding to the task to be resumed is restored by an operation similar to the flowchart shown in Figure 4.

[0229] In other words, in the flowchart shown in Figure 4, after process A51, process A52, process A53, or process A6 is completed and the task is restarted, the process returns to process B2 (step S202 in Figure 16).

[0230] Figure 19 illustrates an example of the operation of the semiconductor device 110B in conjunction with task switching.

[0231] In addition to Figure 8, Figure 19 illustrates the state of each signal (high level or low level) of signal SW1[1] to signal SW[3] when the task switches.

[0232] It should be assumed that immediately before time T1, the signals of signals SW[1] to SW[3] are set to "L". In other words, there is no conduction between each of the memory circuits 131[1] to 131[3] and terminals Q and SD.

[0233] At time T1, before saving the data in the scan flip-flop 120 to the memory circuit 131[1], the signal SW[1] is set to "H". This creates a conductive state between the memory circuit 131[1] and terminals Q and SD. Therefore, it becomes possible to save or restore data to the memory circuit 131[1].

[0234] At time T2, before saving the data in the scan flip-flop 120 to the memory circuit 131[2], the signal SW[2] is set to "H". This creates a conductive state between the memory circuit 131[2] and terminals Q and SD. Therefore, it becomes possible to save or restore data to the memory circuit 131[2].

[0235] At time T4, before saving the data in the scan flip-flop 120 to the memory circuit 131[3], the signal SW[3] is set to "H". This creates a conductive state between the memory circuit 131[3] and terminals Q and SD. Therefore, it becomes possible to save or restore data to the memory circuit 131[3].

[0236] At time T5, after the data from memory circuit 131[3] is restored to scan flip-flop 120, signal SW[3] is set to "L". This results in a non-conductive state between memory circuit 131[3] and terminals Q and SD. Also, at time T4, since the data from memory circuit 131[2] has been restored to scan flip-flop 120, signal SW[2] is set to "L". This results in a non-conductive state between memory circuit 131[2] and terminals Q and SD.

[0237] At time T6, before saving the data in the scan flip-flop 120 to the memory circuit 131[2], the signal SW[2] is set to "H". This creates a conductive state between the memory circuit 131[2] and terminals Q and SD. Therefore, it becomes possible to save or restore data to the memory circuit 131[2].

[0238] By operating the semiconductor device 110B as described above, the parasitic capacitance of the wiring between the scan flip-flop 120 and the memory circuit 131 where the data is held can be reduced when the number of tasks being performed is small. For example, the operation at time T5 can reduce the parasitic capacitance of the wiring between the memory circuit 131[1] and terminals Q and SD. As a result, energy consumption associated with saving or restoring can be reduced. In addition, the signal delay time is shortened, so the time required for saving or restoring can be reduced. Thus, the power consumption of the semiconductor device 110B can be reduced and the operating speed can be improved.

[0239] [Configuration Example Ba] As described above, various circuit configurations can be used as the memory circuits 131[1] to 131[k] provided in the data holding circuit 130B.

[0240] Figure 20 is a circuit diagram illustrating an example configuration of a semiconductor device 110Ba equipped with a data retention circuit 130Ba.

[0241] The data retention circuit 130Ba shown in Figure 20 is configured such that the memory circuits 131[1] to 131[k] provided in the data retention circuit 130B are the same as the memory circuits 131a[1] to 131a[k] shown in Figure 9.

[0242] [Example of operation Ba] The operation of the data retention circuit 130Ba will be explained.

[0243] Figure 21 is a timing chart illustrating an example of the operation of a semiconductor device 110Ba equipped with a data retention circuit 130Ba. As an example, the case where the data retention circuit 130Ba within the semiconductor device 110Ba has three memory circuits 131a is described.

[0244] The timing chart shown in Figure 21 illustrates the state (high level or low level) of each signal SW[1] to SW[3], in addition to the timing chart shown in Figure 10. The state of signals other than SW[1] to SW[3] is the same as that shown in the timing chart in Figure 10.

[0245] Figures 22(A) to 22(D) and 23(A) to 23(D) are schematic diagrams illustrating the state of the semiconductor device 110Ba during each period of the timing chart shown in Figure 21.

[0246] In Figures 22(A) to 22(D) and Figures 23(A) to 23(D), the illustration of transistors MS1[1] to MS1[3] and MS2[1] to MS2[3] is omitted for each period T11 to T18, and transistors in a conducting state are shown as short circuits in the wiring, and transistors in a non-conducting state are shown as open circuits in the wiring.

[0247] During period T11, the signals SW[1] through SW[3] are assumed to be "L". Therefore, transistors MS1[1] through MS1[3] and transistors MS2[1] through MS2[3] are in a non-conductive state. Thus, there is a non-conductive state between each of the memory circuits 131[1] through 131[3] and terminals Q and SD. (Period T11-2 in Figure 22(A)). In the following explanation, unless otherwise specified, the state of each signal and each transistor in the immediately preceding period is assumed to be maintained.

[0248] During period T12, setting signal SW[1] = "H" causes transistors MS1[1] and MS2[1] to conduct. Therefore, the memory circuit 131[1] and terminals Q and SD become conductive (periods T12-1 and T12-2 in Figure 22(B)).

[0249] During period T13, by setting signal SW[2] = “H”, transistors MS1[2] and transistor MS2[2] become conductive. Therefore, the connection between memory circuit 131[2], terminal Q, and terminal SD becomes conductive (periods T13-1 and T13-2 in Fig. 22(C)).

[0250] In each of period T14 and period T15, each signal of signals SW[1] to SW[3] maintains the state in the previous period. Therefore, the conductive or non-conductive states of each of transistors MS1[1] to MS1[3] and each of transistors MS2[1] to MS2[3] are maintained. Thus, the conductive or non-conductive states between each of memory circuits 131[1] to 131[3] and terminal Q and terminal SD are maintained (period T14-1 and period T14-2 in Fig. 22(D), period T15-1 and period T15-2 in Fig. 23(A)).

[0251] During period T16, by setting signal SW[3] = “H”, transistors MS1[3] and transistor MS2[3] become conductive. Therefore, the connection between memory circuit 131[3], terminal Q, and terminal SD becomes conductive (periods T16-1 and T16-2 in Fig. 23(B)).

[0252] In period T17, each signal of signals SW[1] to SW[3] maintains the state in the previous period. Therefore, the conductive or non-conductive states of each of transistors MS1[1] to MS1[3] and each of transistors MS2[1] to MS2[3] are maintained. Thus, the conductive or non-conductive states between each of memory circuits 131[1] to 131[3] and terminal Q and terminal SD are maintained (period T17-1 and period T17-2 in Fig. 23(C)).

[0253] During period T18, setting signal SW[3] = "L" causes transistors MS1[3] and MS2[3] to become non-conductive. Therefore, the connection between memory circuit 131[3] and terminals Q and SD becomes non-conductive. Also, setting signal SW[2] = "L" causes transistors MS1[2] and MS2[2] to become non-conductive. Therefore, the connection between memory circuit 131[2] and terminals Q and SD becomes non-conductive. (Period T18-1 in Figure 23(D)).

[0254] It should be noted that the semiconductor device according to one aspect of the present invention is not limited to the semiconductor device described in this embodiment. The configuration examples, operation examples, and corresponding drawings etc. illustrated in this embodiment can be appropriately combined with other configuration examples, other operation examples, other drawings, and other embodiments etc. described herein.

[0255] (Embodiment 2) This embodiment describes a transistor configuration applicable to the semiconductor device described in the above embodiment. As an example, a configuration in which transistors with different electrical characteristics are stacked together is described. This configuration increases the design flexibility of the semiconductor device. Furthermore, stacking transistors with different electrical characteristics increases the integration density of the semiconductor device.

[0256] A portion of the cross-sectional structure of the semiconductor device is shown in Figure 24. The semiconductor device shown in Figure 24 has a transistor 550, a transistor 500, and a capacitor 600. Figure 25(A) is a cross-sectional view of transistor 500 in the channel length direction, Figure 25(B) is a cross-sectional view of transistor 500 in the channel width direction, and Figure 25(C) is a cross-sectional view of transistor 550 in the channel width direction. For example, transistor 500 corresponds to the OS transistor shown in the above embodiment, and transistor 550 corresponds to a Si transistor.

[0257] In Figure 24, transistor 500 is located above transistor 550, and capacitor 600 is located above both transistor 550 and transistor 500.

[0258] The transistor 550 is provided on a substrate 311 and has a conductor 316, an insulator 315, a semiconductor region 313 consisting of a part of the substrate 311, a low-resistance region 314a that functions as a source region or a drain region, and a low-resistance region 314b.

[0259] As shown in Figure 25(C), the transistor 550 has its semiconductor region 313's top surface and side surface in the channel width direction covered by a conductor 316 via an insulator 315. By making the transistor 550 a Fin type in this way, the effective channel width is increased, thereby improving the on-characteristics of the transistor 550. In addition, the contribution of the gate electrode's electric field can be increased, thus improving the off-characteristics of the transistor 550.

[0260] Note that transistor 550 can be either a p-channel or n-channel type.

[0261] The transistor 550 preferably contains a semiconductor, such as a silicon-based semiconductor, in areas such as the region where the channel of the semiconductor region 313 is formed, the region near it, the low-resistance region 314a which is either the source region or the drain region, and the low-resistance region 314b which is the other source region or the drain region, and preferably contains single-crystal silicon. Alternatively, the transistor 550 may be formed from a material having, for example, Ge (germanium), SiGe (silicon germanium), GaAs (gallium arsenide), or GaAlAs (gallium aluminum arsenide). Alternatively, the transistor 550 may be a silicon configuration in which the effective mass is controlled by applying stress to the crystal lattice and changing the lattice spacing. Alternatively, the transistor 550 may be a HEMT (High Electron Mobility Transistor) using, for example, GaAs and GaAlAs.

[0262] The low-resistance regions 314a and 314b include, in addition to the semiconductor material applied to the semiconductor region 313, an element that imparts n-type conductivity, such as arsenic or phosphorus, or an element that imparts p-type conductivity, such as boron.

[0263] The conductor 316, which functions as the gate electrode, can be a semiconductor material such as silicon containing an element that imparts n-type conductivity, such as arsenic or phosphorus, or an element that imparts p-type conductivity, such as boron. Alternatively, a conductive material such as a metallic material, alloy material, or metal oxide material can be used.

[0264] Furthermore, since the work function is determined by the material of the conductor, the threshold voltage of the transistor can be adjusted by selecting the material of the conductor. Specifically, it is preferable to use materials such as titanium nitride or tantalum nitride as the conductor. In addition, in order to achieve both conductivity and embedding properties, it is preferable to use a laminate of metal materials such as tungsten or aluminum as the conductor, and tungsten is particularly preferable in terms of heat resistance.

[0265] The transistor 550 may be formed using, for example, an SOI (Silicon on Insulator) substrate.

[0266] Furthermore, as the SOI substrate, a SIMOX (Separation by Implanted Oxygen) substrate may be used, which is formed by implanting oxygen ions into a mirror-polished wafer and then heating it at a high temperature to form an oxide layer to a certain depth from the surface and eliminate defects that have formed in the surface layer. Alternatively, an SOI substrate may be used that is formed using a smart-cut method, which cleaves the semiconductor substrate by utilizing the growth of minute voids formed by hydrogen ion implantation through heat treatment, or an ELTRAN method (registered trademark: Epitaxial Layer Transfer). Note that a transistor formed using a single-crystal substrate has a single-crystal semiconductor in the channel formation region.

[0267] The transistor 550 is covered by insulators 320, 322, 324, and 326, which are stacked in that order.

[0268] For insulators 320, 322, 324, and 326, for example, silicon oxide, silicon oxide nitride, silicon oxide nitride, silicon nitride, aluminum oxide, aluminum oxide nitride, aluminum oxide nitride, or aluminum nitride may be used.

[0269] In this specification, silicon oxidizride refers to a material in which the oxygen content is greater than the nitrogen content, and silicon nitride refers to a material in which the nitrogen content is greater than the oxygen content. Furthermore, in this specification, aluminum oxidizride refers to a material in which the oxygen content is greater than the nitrogen content, and aluminum nitride refers to a material in which the nitrogen content is greater than the oxygen content.

[0270] The insulator 322 may also function as a planarizing film that flattens steps caused by, for example, a transistor 550 located below it. For example, the upper surface of the insulator 322 may be planarized by a planarizing treatment, such as chemical mechanical polishing (CMP), in order to improve its flatness.

[0271] In addition, for the insulator 324, for example, a film having a barrier property such that, for example, hydrogen or impurities do not diffuse into the region where the transistor 500 is provided from the substrate 311 or the transistor 550 is preferably used.

[0272] As an example of a film having a barrier property against hydrogen, for example, silicon nitride formed by CVD can be used. For example, when hydrogen diffuses into a semiconductor element having an oxide semiconductor such as the transistor 500, the characteristics of the semiconductor element may deteriorate. Therefore, it is preferable to use a film that suppresses the diffusion of hydrogen between the transistor 500 and the transistor 550. Specifically, the film that suppresses the diffusion of hydrogen is a film with a small amount of hydrogen desorption.

[0273] The amount of hydrogen desorption can be analyzed using, for example, temperature-programmed desorption gas analysis (TDS). For example, the amount of hydrogen desorption of the insulator 324 is such that in TDS analysis, in the range where the surface temperature of the film is from 50°C to 500°C, the desorption amount converted to hydrogen atoms, when converted per unit area of the insulator 324, is 1×10 16 atoms / cm 2 Hereinafter, preferably 5×10 15 atoms / cm 2 or less may be sufficient.

[0274] Note that the insulator 326 preferably has a lower dielectric constant than the insulator 324. For example, the relative dielectric constant of the insulator 326 is preferably less than 4, more preferably less than 3. Also, for example, the relative dielectric constant of the insulator 326 is preferably 0.7 times or less, more preferably 0.6 times or less, the relative dielectric constant of the insulator 324. By using a material with a low dielectric constant as the interlayer film, the parasitic capacitance generated between the wirings can be reduced.

[0275] Furthermore, insulators 320, 322, 324, and 326 have embedded conductors such as conductors 328 and 330, which are connected to the capacitor 600 or the transistor 500. Conductors 328 and 330 function as plugs or wires. Conductors that function as plugs or wires may be grouped together and assigned the same reference numeral. Also, in this specification, the wiring and the plug that electrically connects to the wiring may be an integrated unit. That is, a part of the conductor may function as wiring, and a part of the conductor may function as a plug.

[0276] The material for each plug or wiring (e.g., conductor 328 or conductor 330) can be a conductive material such as a metal, alloy, metal nitride, or metal oxide, used in a single layer or in a laminated configuration. It is preferable to use a high-melting-point material such as tungsten or molybdenum, which provides both heat resistance and conductivity, for the plug or wiring. Alternatively, it is preferable to form the plug or wiring from a low-resistance conductive material such as aluminum or copper. Using a low-resistance conductive material for the plug or wiring can reduce the wiring resistance.

[0277] A wiring layer may be provided on the insulator 326 and the conductor 330. For example, in Figure 24, insulators 350, 352, and 354 are stacked in order. Conductors 356 are formed on insulators 350, 352, and 354. Conductors 356 function as a plug or wiring to connect to the transistor 550. Conductors 356 can be provided using the same material as conductors 328 and 330.

[0278] Furthermore, it is preferable that the insulator 350, like the insulator 324, be an insulator having barrier properties against hydrogen. It is also preferable that the conductor 356 includes a conductor having barrier properties against hydrogen. In particular, a conductor having barrier properties against hydrogen is formed in the openings of the hydrogen barrier insulator 350. With this configuration, transistors 550 and 500 can be separated by the barrier layer. Therefore, the diffusion of hydrogen from transistor 550 to transistor 500 can be suppressed.

[0279] For example, tantalum nitride can be used as the conductor that has barrier properties against hydrogen. Alternatively, tantalum nitride can be laminated with tungsten, which has high conductivity. By laminating tantalum nitride and tungsten as the conductor 356, the conductor 356 can suppress the diffusion of hydrogen from the transistor 550 while maintaining its conductivity as a wiring. In this case, it is preferable that the tantalum nitride layer of the hydrogen-barrier conductor 356 is in contact with the hydrogen-barrier insulator 350.

[0280] A wiring layer may be provided on the insulator 354 and the conductor 356. For example, in Figure 24, insulators 360, 362, and 364 are stacked in order. Conductors 366 are formed on insulators 360, 362, and 364. Conductors 366 function as a plug or wiring. Conductors 366 can be provided using the same material as conductors 328 and 330.

[0281] For example, it is preferable that the insulator 360, like the insulator 324, be an insulator having barrier properties against hydrogen. Furthermore, it is preferable that the conductor 366 includes a conductor having barrier properties against hydrogen. In particular, a conductor having barrier properties against hydrogen is formed in the openings of the hydrogen barrier insulator 360. With this configuration, transistors 550 and 500 can be separated by the barrier layer. Therefore, the diffusion of hydrogen from transistor 550 to transistor 500 can be suppressed.

[0282] A wiring layer may be provided on the insulator 364 and the conductor 366. For example, in Figure 24, insulators 370, 372, and 374 are stacked in order. Conductors 376 are formed on insulators 370, 372, and 374. Conductors 376 function as a plug or wiring. Conductors 376 can be provided using the same material as conductors 328 and 330.

[0283] Furthermore, for example, it is preferable to use an insulator 370 that has hydrogen barrier properties, similar to the insulator 324. It is also preferable that the conductor 376 includes a conductor that has hydrogen barrier properties. In particular, a conductor with hydrogen barrier properties is formed in the openings of the hydrogen barrier insulator 370. With this configuration, transistors 550 and 500 can be separated by the barrier layer. Therefore, the diffusion of hydrogen from transistor 550 to transistor 500 can be suppressed.

[0284] A wiring layer may be provided on the insulator 374 and the conductor 376. For example, in Figure 24, insulators 380, 382, ​​and 384 are stacked in order. Furthermore, a conductor 386 is formed on insulators 380, 382, ​​and 384. The conductor 386 functions as a plug or wiring. The conductor 386 can be provided using the same material as the conductors 328 and 330.

[0285] For example, it is preferable that the insulator 380, like the insulator 324, be an insulator having barrier properties against hydrogen. Furthermore, it is preferable that the conductor 386 includes a conductor having barrier properties against hydrogen. In particular, a conductor having barrier properties against hydrogen is formed in the openings of the hydrogen barrier insulator 380. With this configuration, transistors 550 and 500 can be separated by the barrier layer. Therefore, the diffusion of hydrogen from transistor 550 to transistor 500 can be suppressed.

[0286] In the above description, an example was given in which four wiring layers similar to the wiring layer containing conductor 356 are used, namely, a wiring layer containing conductor 356, a wiring layer containing conductor 366, a wiring layer containing conductor 376, and a wiring layer containing conductor 386. However, the semiconductor device according to this embodiment is not limited to this. Three or fewer wiring layers similar to the wiring layer containing conductor 356 may be used, or five or more wiring layers similar to the wiring layer containing conductor 356 may be used.

[0287] Insulators 510, 512, 514, and 516 are arranged in order on the insulator 384. It is preferable that one of the insulators 510, 512, 514, and 516 is made of a material that has barrier properties against oxygen and hydrogen, for example.

[0288] For example, it is preferable to use a film for insulators 510 and 514 that has barrier properties to prevent the diffusion of, for example, hydrogen or impurities from the substrate 311 or the region where transistor 550 is installed to the region where transistor 500 is installed. Therefore, the same materials as insulator 324 can be used for insulators 510 and 514.

[0289] As an example of a film having hydrogen barrier properties, silicon nitride formed by the CVD method can be used. For example, when hydrogen diffuses into a semiconductor device having an oxide semiconductor, such as transistor 500, the properties of the semiconductor device may deteriorate. Therefore, it is preferable to use a film that suppresses hydrogen diffusion between transistor 500 and transistor 550. Specifically, a film that suppresses hydrogen diffusion is a film that has a low hydrogen desorption rate.

[0290] Furthermore, as a film having barrier properties against hydrogen, it is preferable to use metal oxides such as aluminum oxide, hafnium oxide, or tantalum oxide for insulators 510 and 514.

[0291] In particular, aluminum oxide has a high barrier effect that prevents the film from passing through to both oxygen and impurities such as hydrogen or moisture, which can cause fluctuations in the electrical properties of transistors. Therefore, aluminum oxide can prevent the ingress of impurities such as hydrogen or moisture into the transistor 500 during and after the transistor manufacturing process. Furthermore, aluminum oxide can suppress the release of oxygen from the oxides that make up the transistor 500. For this reason, aluminum oxide is suitable for use as a protective film for transistor 500.

[0292] Furthermore, for example, the same materials as those used for insulator 320 can be used for insulator 512 and insulator 516. Additionally, by applying materials with relatively low dielectric constants to these insulators, parasitic capacitance between wiring can be reduced. For example, silicon oxide films or silicon oxynitride films can be used as insulators 512 and 516.

[0293] Insulators 510, 512, 514, and 516 have, for example, a conductor 518 and a conductor constituting the transistor 500 (for example, conductor 503) embedded in them. The conductor 518 functions as a plug or wiring for connecting to the capacitor 600 or the transistor 550. The conductor 518 can be provided using the same material as conductors 328 and 330.

[0294] In particular, the conductor 518 in the region in contact with the insulator 510 and the insulator 514 is preferably a conductor having barrier properties against oxygen, hydrogen, and water. With this configuration, transistor 550 and transistor 500 can be separated by a layer having barrier properties against oxygen, hydrogen, and water, and the diffusion of hydrogen from transistor 550 to transistor 500 can be suppressed.

[0295] A transistor 500 is provided above the insulator 516.

[0296] As shown in Figures 25(A) and 25(B), the transistor 500 includes a conductor 503 arranged to be embedded in insulators 514 and 516, an insulator 520 arranged on top of insulators 516 and 503, an insulator 522 arranged on top of insulator 520, an insulator 524 arranged on top of insulator 522, an oxide 530a arranged on top of insulator 524, an oxide 530b arranged on top of oxide 530a, conductors 542a and 542b arranged spaced apart from each other on oxide 530b, an insulator 580 arranged on top of conductors 542a and 542b with an opening formed between conductors 542a and 542b, an insulator 545 arranged on the bottom and side surfaces of the opening, and a conductor 560 arranged on the forming surface of insulator 545.

[0297] Furthermore, as shown in Figures 25(A) and 25(B), it is preferable that an insulator 544 is placed between the oxide 530a, oxide 530b, conductor 542a, and conductor 542b and the insulator 580. Also, as shown in Figures 25(A) and 25(B), it is preferable that the conductor 560 has a conductor 560a provided inside the insulator 545 and a conductor 560b provided so as to be embedded inside the conductor 560a. Furthermore, as shown in Figures 25(A) and 25(B), it is preferable that an insulator 574 is placed on top of the insulator 580, conductor 560, and insulator 545.

[0298] In this specification, oxides 530a and 530b are sometimes collectively referred to as oxide 530.

[0299] Although the transistor 500 shows a configuration in which two layers of oxide 530a and oxide 530b are stacked in the region where the channel is formed and its vicinity, the present invention is not limited to this. For example, a single layer of oxide 530b or a stacked configuration of three or more layers may be provided in the region where the channel is formed and its vicinity.

[0300] Furthermore, although the transistor 500 is shown with a two-layer stacked structure for the conductor 560, the present invention is not limited to this. For example, the conductor 560 may be a single layer or a stacked structure of three or more layers. Also, the transistor 500 shown in Figures 24 and 25(A) is just an example and is not limited to that configuration; for example, an appropriate transistor may be used depending on the circuit configuration or driving method.

[0301] Here, the conductor 560 functions as the gate electrode of the transistor, and the conductors 542a and 542b function as the source electrode or drain electrode, respectively. As described above, the conductor 560 is formed to be embedded in the opening of the insulator 580 and in the region sandwiched between the conductors 542a and 542b. The arrangement of the conductor 560 and the conductors 542a and 542b is selected in a self-aligned manner with respect to the opening of the insulator 580. In other words, in the transistor 500, the gate electrode can be positioned in a self-aligned manner between the source electrode and the drain electrode. Therefore, the conductor 560 can be formed without providing a margin for alignment. As a result, the occupied area of ​​the transistor 500 can be reduced. This enables miniaturization and high integration of semiconductor devices.

[0302] Furthermore, since the conductor 560 is formed self-aligned in the region between the conductors 542a and 542b, the conductor 560 does not have any region that overlaps with the conductors 542a or 542b. This reduces the parasitic capacitance formed between the conductor 560 and the conductors 542a and 542b. Therefore, the switching speed of the transistor 500 can be improved, and it can be given high frequency characteristics.

[0303] Here, the conductor 560 may function as a first gate (also called a top gate) electrode. Also, the conductor 503 may function as a second gate (also called a bottom gate) electrode. In that case, the threshold voltage of transistor 500 can be controlled by changing the potential applied to conductor 503 independently of the potential applied to conductor 560. In particular, by applying a negative potential to conductor 503, it is possible to make the threshold voltage of transistor 500 greater than 0V and reduce the off-current. Therefore, applying a negative potential to conductor 503 reduces the drain current when the potential applied to conductor 560 is 0V compared to not applying a negative potential.

[0304] The conductor 503 is positioned so as to overlap with the oxide 530 and the conductor 560. As a result, when a potential is applied to the conductor 560 and the conductor 503, the electric field generated from the conductor 560 and the electric field generated from the conductor 503 connect, and can cover the channel-forming region formed in the oxide 530.

[0305] In this specification, a transistor structure in which the channel formation region is electrically surrounded by the electric field of the first gate electrode is called a surrounded channel (S-channel) structure. The S-channel structure disclosed in this specification has a structure different from that of a Fin-type structure and a planar-type structure. On the other hand, the S-channel structure disclosed in this specification can also be considered as a type of Fin-type structure. In this specification, a Fin-type structure refers to a structure in which the gate electrode is arranged to surround at least two or more sides of the channel (specifically, two, three, or four sides, etc.). By adopting a Fin-type structure and an S-channel structure, it is possible to create a transistor with increased resistance to short-channel effects. In other words, it is possible to create a transistor in which short-channel effects are less likely to occur.

[0306] By using the S-channel structure described above for the transistor, the channel formation region can be electrically enclosed. Since the S-channel structure electrically encloses the channel formation region, it can be considered essentially equivalent to a GAA (Gate All Around) structure or an LGAA (Lateral Gate All Around) structure. By using an S-channel, GAA, or LGAA structure for the transistor, the channel formation region formed at or near the interface between the oxide 530 and the gate insulator can be made from the entire bulk of the oxide 530. Therefore, it becomes possible to improve the current density flowing through the transistor, resulting in improved on-current or improved field-effect mobility.

[0307] Furthermore, the conductor 503 has a similar configuration to the conductor 518, with conductor 503a formed in contact with the inner walls of the openings of the insulators 514 and 516, and conductor 503b formed further inside. Although the transistor 500 shows a configuration in which conductors 503a and conductor 503b are stacked, the present invention is not limited to this. For example, the conductor 503 may be provided as a single layer or as a stacked configuration of three or more layers.

[0308] Here, it is preferable to use a conductive material for the conductor 503a that has the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, or copper atoms (i.e., the above impurities are less permeable). Alternatively, it is preferable to use a conductive material for the conductor 503a that has the function of suppressing the diffusion of oxygen (i.e., at least one such as oxygen atoms and oxygen molecules) (i.e., the above oxygen is less permeable). In this specification, the function of suppressing the diffusion of impurities or oxygen means the function of suppressing the diffusion of one or all of the above impurities or oxygen.

[0309] For example, the conductor 503a has a function of suppressing oxygen diffusion, which can prevent the conductor 503b from oxidizing and reducing its conductivity.

[0310] Furthermore, if the conductor 503 also functions as wiring, it is preferable that the conductor 503b be made of a highly conductive material mainly composed of tungsten, copper, or aluminum. In this embodiment, the conductor 503 is shown as a laminate of conductor 503a and conductor 503b, but the conductor 503 may also be in a single-layer configuration.

[0311] Insulators 520, 522, and 524 function as second gate insulating films.

[0312] Here, it is preferable to use an insulator 524 that contains more oxygen than satisfactorily satisfactorily satisfactorily to be in contact with the oxide 530. This oxygen is easily released from the film by heating. In this specification, the oxygen released by heating is sometimes referred to as "excess oxygen." In other words, it is preferable that the insulator 524 has a region containing excess oxygen (also called an "excess oxygen region"). By providing such an insulator containing excess oxygen in contact with the oxide 530, oxygen deficiencies (V) in the oxide 530 can be reduced. O This reduces the oxygen vacancy (also known as the oxygen vacancy) and improves the reliability of the transistor 500. Furthermore, if hydrogen enters the oxygen vacancy in the oxide 530, the defect (hereinafter referred to as V) can be reduced. O Sometimes referred to as H, hydrogen acts as a donor, and can generate electrons, which are carriers. In addition, some hydrogen can combine with oxygen that is bonded to a metal atom, generating electrons, which are carriers. Therefore, transistors using oxide semiconductors with a high hydrogen content tend to exhibit normally-on characteristics. Furthermore, since hydrogen in oxide semiconductors is easily moved by stress such as heat or electric fields, the reliability of the transistor may deteriorate if the oxide semiconductor contains a large amount of hydrogen. In one embodiment of the present invention, V in oxide 530 O It is preferable to reduce H as much as possible and make it high-purity intrinsic or substantially high-purity intrinsic. Thus, V O To obtain an oxide semiconductor with sufficiently reduced H content, it is important to remove impurities such as water or hydrogen from the oxide semiconductor (also called "dehydration" or "dehydrogenation") and to supply oxygen to the oxide semiconductor to compensate for oxygen deficiencies (also called "oxygenation"). For example, V O By using an oxide semiconductor with sufficiently reduced impurities such as H in the channel formation region of a transistor, stable electrical characteristics can be provided.

[0313] Specifically, as an insulator having an excess oxygen region, it is preferable to use an oxide material in which some of the oxygen is desorbed upon heating. An oxide that desorbs oxygen upon heating is one in which the amount of oxygen desorbed, converted to oxygen atoms, is 1.0 × 10⁻⁶ as determined by TDS (Thermal Desorption Spectroscopy) analysis. 18 atoms / cm 3 Preferably 1.0 × 10 19 atoms / cm 3 More preferably 2.0 × 10 19 atoms / cm 3 Above, or 3.0 × 10 20 atoms / cm 3 The oxide film is as described above. The surface temperature of the film during the TDS analysis is preferably in the range of 100°C to 700°C, or 100°C to 400°C.

[0314] Furthermore, the insulator having the excess oxygen region described above and the oxide 530 may be brought into contact and one or more of the following treatments may be performed: heat treatment, microwave treatment, or RF treatment. By performing this treatment, water or hydrogen in the oxide 530 can be removed. For example, in the oxide 530, a reaction occurs in which the VoH bond is broken, thereby dehydrogenation can be achieved. In other words, in the oxide 530, "V O The reaction H → Vo + H occurs, allowing for dehydrogenation. Some of the hydrogen generated at this time may be removed from oxide 530 or the insulator near oxide 530 as H2O, which is formed by bonding with oxygen. In addition, some of the hydrogen may be gettered by conductor 542 (conductors 542a and 542b).

[0315] Furthermore, the above microwave processing is preferably carried out using, for example, a device having a power supply that generates high-density plasma, or a device having a power supply that applies RF to the substrate side. For example, by using an oxygen-containing gas and a high-density plasma, high-density oxygen radicals can be generated, and by applying RF to the substrate side, the oxygen radicals generated by the high-density plasma can be efficiently introduced into the oxide 530 or the insulator near the oxide 530. In addition, the above microwave processing should be carried out at a pressure of 133 Pa or higher, preferably 200 Pa or higher, and even more preferably 400 Pa or higher. In addition, as the gas introduced into the device for microwave processing, for example, oxygen and argon should be used, and the oxygen flow rate ratio (O2 / (O2+Ar)) should be 50% or less, preferably 10% to 30% or less.

[0316] Furthermore, during the manufacturing process of the transistor 500, it is preferable to perform a heat treatment while the surface of the oxide 530 is exposed. This heat treatment may be performed, for example, at a temperature of 100°C to 450°C, more preferably 350°C to 400°C. The heat treatment should be performed in an atmosphere of nitrogen gas or an inert gas, or in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. For example, it is preferable to perform the heat treatment in an oxygen atmosphere. This supplies oxygen to the oxide 530, thereby preventing oxygen deficiency (V O This can reduce the amount of oxygen released. The heat treatment may also be performed under reduced pressure. Alternatively, the heat treatment may be performed in an atmosphere of nitrogen gas or an inert gas, and then in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas to replenish the oxygen that has been removed. Alternatively, the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas, and then continuously in an atmosphere of nitrogen gas or an inert gas.

[0317] Furthermore, by performing an oxygenation treatment on oxide 530, oxygen vacancies in oxide 530 can be repaired by the supplied oxygen, in other words, the reaction "Vo + O → null" can be promoted. In addition, the hydrogen remaining in oxide 530 can be removed as H2O (dehydrated) by reacting with the supplied oxygen. As a result, the hydrogen remaining in oxide 530 recombines with the oxygen vacancies and V O This can suppress the formation of H.

[0318] Furthermore, if the insulator 524 has an excess oxygen region, it is preferable that the insulator 522 has a function to suppress the diffusion of oxygen (for example, at least one such as oxygen atoms and oxygen molecules) (i.e., the oxygen is less permeable).

[0319] The insulator 522 has a function to suppress the diffusion of, for example, oxygen or impurities, so that the oxygen contained in the oxide 530 does not diffuse towards the insulator 520, which is preferable. Furthermore, it is possible to suppress the reaction of the conductor 503 with, for example, the oxygen contained in the insulator 524 or the oxide 530.

[0320] For the insulator 522, it is preferable to use an insulator made of a high-dielectric constant (high-k) material (a material with a high relative permittivity). For example, the insulator 522 preferably uses an insulator containing aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO3), or (Ba,Sr)TiO3 (BST) in a single layer or multilayer configuration. As transistors become smaller and more integrated, thinning of the gate insulating film can lead to problems such as leakage current. By using a high-k material as the insulator that functions as the gate insulating film, it is possible to reduce the gate potential during transistor operation while maintaining the physical film thickness.

[0321] In particular, it is preferable to use an insulator containing an oxide of either aluminum or hafnium, or both, which is an insulating material that has the function of suppressing the diffusion of impurities and oxygen (i.e., the above-mentioned oxygen is not easily permeable). As an insulator containing an oxide of either aluminum or hafnium, or both, it is preferable to use, for example, aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate). When an insulator 522 is formed using such a material, the insulator 522 functions as a layer that suppresses the release of oxygen from the oxide 530, or the incorporation of impurities such as hydrogen from the periphery of the transistor 500 into the oxide 530.

[0322] Alternatively, these insulators may be supplemented with, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide. Alternatively, these insulators may be nitrided. Silicon oxide, silicon oxide nitride, or silicon nitride may be laminated onto the above insulators.

[0323] Furthermore, it is preferable that the insulator 520 is thermally stable. For example, silicon oxide and silicon oxynitride are suitable because they are thermally stable. Also, by combining a high-k material insulator with silicon oxide or silicon oxynitride, an insulator 520 with a thermally stable and high dielectric constant laminated structure can be obtained.

[0324] In Figures 25(A) and 25(B), the transistor 500 is shown with insulators 520, 522, and 524 as a second gate insulating film consisting of three layers. However, the second gate insulating film may have a single layer, two layers, or a multilayer structure of four or more layers. In that case, the second gate insulating film is not limited to a multilayer structure made of the same material, but may also have a multilayer structure made of different materials.

[0325] In transistor 500, a metal oxide that functions as an oxide semiconductor is used for the oxide 530 including the channel formation region. As the oxide 530, for example, a metal oxide having indium, M (where M is one or more selected from gallium, aluminum, yttrium, tin, silicon, boron, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, and cobalt) and zinc is preferable.

[0326] The metal oxide that functions as an oxide semiconductor may be formed by sputtering or by Atomic Layer Deposition (ALD). The metal oxide that functions as an oxide semiconductor will be described in detail in other embodiments.

[0327] Furthermore, in oxide 530, it is preferable to use a metal oxide that functions as a channel-forming region and has a band gap of 2 eV or more, preferably 2.5 eV or more. By using a metal oxide with a large band gap in oxide 530 in this way, the off-current of transistor 500 can be reduced.

[0328] By having oxide 530a below oxide 530b, oxide 530 can suppress the diffusion of impurities from components formed below oxide 530a to oxide 530b.

[0329] Furthermore, it is preferable that the oxide 530 has a configuration of multiple oxide layers with different atomic ratios of each metal atom. Specifically, it is preferable that in the metal oxide used for oxide 530a, the atomic ratio of element M in the constituent elements is greater than the atomic ratio of element M in the constituent elements of the metal oxide used for oxide 530b. Also, it is preferable that in the metal oxide used for oxide 530a, the atomic ratio of element M to In is greater than the atomic ratio of element M to In in the metal oxide used for oxide 530b. Furthermore, it is preferable that in the metal oxide used for oxide 530b, the atomic ratio of In to element M is greater than the atomic ratio of In to element M in the metal oxide used for oxide 530a.

[0330] Furthermore, it is preferable that the energy at the lower end of the conduction band of oxide 530a is higher than the energy at the lower end of the conduction band of oxide 530b. In other words, it is preferable that the electron affinity of oxide 530a is smaller than that of oxide 530b.

[0331] Here, at the junction of oxide 530a and oxide 530b, the energy level at the lower end of the conduction band changes smoothly. In other words, the energy level at the lower end of the conduction band at the junction of oxide 530a and oxide 530b changes continuously, or it can be said that they are continuously joined. To achieve this, it is desirable to lower the defect level density of the mixed layer formed at the interface between oxide 530a and oxide 530b.

[0332] Specifically, a mixed layer with a low defect level density can be formed if oxide 530a and oxide 530b have a common element other than oxygen (as the main component). For example, if oxide 530b is In-Ga-Zn oxide, oxide 530a can be, for example, In-Ga-Zn oxide, Ga-Zn oxide, or gallium oxide.

[0333] In this case, the primary carrier pathway is oxide 530b. By configuring oxide 530a as described above, the defect level density at the interface between oxide 530a and oxide 530b can be reduced. As a result, the influence of interface scattering on carrier conduction is reduced, and transistor 500 can obtain a high on-current.

[0334] Conductors 542a and 542b, which function as source electrodes or drain electrodes, are provided on the oxide 530b. For example, it is preferable to use metallic elements selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, or lanthanum, alloys composed of the above-mentioned metallic elements, or alloys combining the above-mentioned metallic elements. For example, it is preferable to use tantalum nitride, titanium nitride, tungsten, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, or oxides containing lanthanum and nickel. Furthermore, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, or oxides containing lanthanum and nickel are preferred because they are conductive materials that are resistant to oxidation or maintain conductivity even when absorbing oxygen. Moreover, metal nitride films such as tantalum nitride are preferred because they have barrier properties against hydrogen or oxygen.

[0335] Furthermore, although the conductors 542a and 542b are shown as single-layer structures in Figure 25(A), they may also be laminated in two or more layers. For example, a tantalum nitride film and a tungsten film may be laminated as the conductors 542a and 542b. Alternatively, a titanium film and an aluminum film may be laminated as the conductors 542a and 542b. Alternatively, the conductors 542a and 542b may be a two-layer structure in which an aluminum film is laminated on a tungsten film, a two-layer structure in which a copper film is laminated on a copper-magnesium-aluminum alloy film, a two-layer structure in which a copper film is laminated on a titanium film, or a two-layer structure in which a copper film is laminated on a tungsten film.

[0336] Furthermore, the conductors 542a and 542b may be, for example, a three-layer structure in which an aluminum film or copper film is laminated on top of a titanium film or titanium nitride film, and then a titanium film or titanium nitride film is formed on top of that, or a three-layer structure in which an aluminum film or copper film is laminated on top of a molybdenum film or molybdenum nitride film, and then a molybdenum film or molybdenum nitride film is formed on top of that. Note that, for example, transparent conductive materials containing indium oxide, tin oxide, or zinc oxide may be used as the conductors 542a and 542b.

[0337] Furthermore, as shown in Figure 25(A), regions 543a and 543b may be formed as low-resistance regions at and near the interface between the oxide 530 and the conductor 542a (conductor 542b). In this case, region 543a functions as either a source region or a drain region, and region 543b functions as either a source region or a drain region. In addition, a channel-forming region is formed in the region sandwiched between regions 543a and 543b.

[0338] By providing the conductor 542a (conductor 542b) in contact with the oxide 530, the oxygen concentration in region 543a (region 543b) may be reduced. In addition, a metal compound layer containing the metal contained in the conductor 542a (conductor 542b) and the components of the oxide 530 may be formed in region 543a (region 543b). In such a case, the carrier concentration in region 543a (region 543b) increases, and region 543a (region 543b) becomes a low-resistance region.

[0339] The insulator 544 is provided so as to cover the conductors 542a and 542b, thereby suppressing oxidation of the conductors 542a and 542b. In this case, the insulator 544 may be provided so as to cover the side surface of the oxide 530 and be in contact with the insulator 524.

[0340] As the insulator 544, one or more metal oxides selected from, for example, hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, neodymium, lanthanum, or magnesium can be used. Alternatively, as the insulator 544, for example, silicon nitride or silicon nitride can also be used.

[0341] In particular, it is preferable to use an insulator 544 that contains an oxide of either or both aluminum or hafnium, such as aluminum oxide, hafnium oxide, or an oxide containing both aluminum and hafnium (hafnium aluminate). Hafnium aluminate is especially preferable because it has higher heat resistance than hafnium oxide film. Therefore, it is preferable because it is less likely to crystallize during heat treatment in a later process. Note that if the conductors 542a and 542b are materials that have oxidation resistance or materials whose conductivity does not significantly decrease even when oxygen is absorbed, the insulator 544 is not an essential component. The insulator 544 can be appropriately designed according to the desired transistor characteristics.

[0342] The presence of the insulator 544 suppresses the diffusion of impurities, such as water or hydrogen, contained in the insulator 580 into the oxide 530b. Furthermore, it suppresses the oxidation of the conductor 542 (conductors 542a and 542b) due to excess oxygen present in the insulator 580.

[0343] The insulator 545 functions as the first gate insulating film. The insulator 545 is preferably formed using an insulator that contains an excess of oxygen and releases oxygen upon heating, similar to the insulator 524 described above.

[0344] Specifically, silicon oxide with excess oxygen, silicon oxide nitride, silicon nitride, silicon nitride, silicon oxide with added fluorine, silicon oxide with added carbon, silicon oxide with added carbon and nitrogen, or silicon oxide with vacancies can be used. Silicon oxide or silicon oxide nitride is particularly preferred because it is stable to heat.

[0345] By providing an insulator containing excess oxygen as insulator 545, oxygen can be effectively supplied from insulator 545 to the channel-forming region of oxide 530b. Furthermore, similar to insulator 524, it is preferable that the concentration of impurities such as water or hydrogen in insulator 545 is reduced. The film thickness of insulator 545 is preferably between 1 nm and 20 nm.

[0346] Furthermore, in order to efficiently supply excess oxygen from the insulator 545 to the oxide 530, a metal oxide may be provided between the insulator 545 and the conductor 560. It is preferable that the metal oxide suppresses oxygen diffusion from the insulator 545 to the conductor 560. By providing a metal oxide that suppresses oxygen diffusion between the insulator 545 and the conductor 560, the diffusion of excess oxygen from the insulator 545 to the conductor 560 is suppressed. In other words, the reduction in the amount of excess oxygen supplied to the oxide 530 can be suppressed. In addition, oxidation of the conductor 560 due to excess oxygen can be suppressed. As the metal oxide, any material that can be used for the insulator 544 may be used.

[0347] Furthermore, the insulator 545 may be in a multilayer configuration, similar to the second gate insulating film. As transistors become smaller and more integrated, thinning of the gate insulating film can lead to problems such as leakage current. Therefore, by using a multilayer configuration of a high-k material and a thermally stable material for the insulator 545, it is possible to maintain the physical film thickness of the insulator 545 while reducing the gate potential during operation of the transistor 500. In addition, the insulator 545 can be in a multilayer configuration that is thermally stable and has a high dielectric constant.

[0348] Although the conductor 560, which functions as the first gate electrode, is shown as a two-layer structure in Figures 25(A) and 25(B), it may also be a single-layer structure or a stacked structure of three or more layers.

[0349] The conductor 560a is preferably a conductive material that has the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (e.g., N2O, NO, or NO2), or copper atoms. Alternatively, it is preferable to use a conductive material that has the function of suppressing the diffusion of oxygen (e.g., at least one such as oxygen atoms and oxygen molecules). By having the function of suppressing oxygen diffusion in the conductor 560a, it is possible to suppress the oxidation of the conductor 560b by the oxygen contained in the insulator 545, which reduces its conductivity. As a conductive material that has the function of suppressing oxygen diffusion, it is preferable to use, for example, tantalum, tantalum nitride, ruthenium, or ruthenium oxide. Furthermore, an oxide semiconductor applicable to the oxide 530 can be used as the conductor 560a. In that case, by depositing the conductor 560b by sputtering, the electrical resistance of the conductor 560a can be reduced, making it a conductor. This can be called an OC (Oxide Conductor) electrode.

[0350] Furthermore, it is preferable that the conductor 560b is made of a conductive material mainly composed of tungsten, copper, or aluminum. Also, since the conductor 560b functions as wiring, it is preferable to use a conductor with high conductivity. For example, a conductive material mainly composed of tungsten, copper, or aluminum can be used. The conductor 560b may also be in a laminated structure. For example, the conductor 560b may be in a laminated structure of titanium or titanium nitride and the above conductive material.

[0351] The insulator 580 is provided on the conductors 542a and 542b via the insulator 544. The insulator 580 preferably has an excess oxygen region. The insulator 580 preferably includes, for example, silicon oxide, silicon oxynitride, silicon nitride, silicon nitride, fluorine-added silicon oxide, carbon-added silicon oxide, carbon and nitrogen-added silicon oxide, porous silicon oxide, or a resin. Silicon oxide or silicon oxynitride is particularly preferred because it is thermally stable. Silicon oxide or porous silicon oxide is particularly preferred because it can easily form an excess oxygen region in a later step.

[0352] The insulator 580 preferably has an excess oxygen region. By providing an insulator 580 that releases oxygen upon heating, oxygen in the insulator 580 can be efficiently supplied to the oxide 530. It is also preferable that the concentration of impurities such as water or hydrogen in the insulator 580 is reduced.

[0353] The opening in the insulator 580 is formed superimposed on the region between the conductors 542a and 542b. As a result, the conductor 560 is formed to be embedded in the opening in the insulator 580 and in the region sandwiched between the conductors 542a and 542b.

[0354] When miniaturizing semiconductor devices, it is necessary to shorten the gate length, but it is also necessary to ensure that the conductivity of the conductor 560 does not decrease. If the film thickness of the conductor 560 is increased to achieve this, the conductor 560 may take on a shape with a high aspect ratio. In this embodiment, the conductor 560 is provided embedded in the opening of the insulator 580. Therefore, even if the conductor 560 has a shape with a high aspect ratio, it can be formed without collapsing during the manufacturing process.

[0355] The insulator 574 is preferably provided in contact with the upper surface of the insulator 580, the upper surface of the conductor 560, and the upper surface of the insulator 545. By forming the insulator 574 by sputtering, an excess oxygen region can be created in the insulator 545 and the insulator 580. This allows oxygen to be supplied to the oxide 530 from the excess oxygen region.

[0356] As the insulator 574, for example, one or more metal oxides selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, or magnesium can be used.

[0357] In particular, aluminum oxide has high barrier properties and can suppress the diffusion of hydrogen and nitrogen even in thin films between 0.5 nm and 3.0 nm in thickness. Therefore, aluminum oxide deposited by sputtering can function not only as an oxygen source but also as a barrier film against impurities such as hydrogen.

[0358] Furthermore, it is preferable to provide an insulator 581 that functions as an interlayer film on top of the insulator 574. It is preferable that the insulator 581, like the insulator 524, has a reduced concentration of impurities such as water or hydrogen in the film.

[0359] Furthermore, conductors 540a and 540b are placed in the openings formed in insulators 581, 574, 580, and 544. Conductors 540a and 540b are provided facing each other with conductor 560 in between. Conductors 540a and 540b have the same configuration as conductors 546 and 548, which will be described later.

[0360] An insulator 582 is provided on the insulator 581. It is preferable that the insulator 582 be made of a material that has barrier properties against oxygen and hydrogen, for example. Therefore, the same material as the insulator 514 can be used for the insulator 582. It is preferable that the insulator 582 be made of a metal oxide such as aluminum oxide, hafnium oxide, or tantalum oxide, for example.

[0361] In particular, aluminum oxide exhibits a high barrier effect, preventing the penetration of both oxygen and impurities such as hydrogen or moisture, which can cause fluctuations in the electrical properties of transistors. Therefore, aluminum oxide can prevent the incorporation of impurities such as hydrogen or moisture into the transistor 500 during and after the transistor manufacturing process. It can also suppress the release of oxygen from the oxides constituting the transistor 500. For this reason, it is suitable for use as a protective film for transistor 500.

[0362] Furthermore, an insulator 586 is provided on the insulator 582. The insulator 586 can be made of the same material as the insulator 320. By applying materials with relatively low dielectric constants to these insulators, parasitic capacitance between the wiring can be reduced. As the insulator 586, for example, a silicon oxide film or a silicon oxynitride film can be used.

[0363] Furthermore, insulators 520, 522, 524, 544, 580, 574, 581, 582, and 586 have, for example, conductors 546 and 548 embedded in them.

[0364] Conductors 546 and 548 function as plugs or wires for connecting to capacitor 600, transistor 500, or transistor 550. Conductors 546 and 548 can be provided using the same materials as conductors 328 and 330.

[0365] Furthermore, after the formation of the transistor 500, an opening may be formed to surround the transistor 500, and an insulator with high barrier properties against hydrogen or water may be formed to cover the opening. By enclosing the transistor 500 with the above-mentioned high-barrier insulator, it is possible to prevent moisture and hydrogen from entering from the outside. Alternatively, multiple transistors 500 may be grouped together and enclosed in an insulator with high barrier properties against hydrogen or water. When forming an opening to surround the transistor 500, for example, forming an opening that reaches the insulator 522 or insulator 514, and forming the above-mentioned high-barrier insulator in contact with the insulator 522 or insulator 514 is preferable because it can also serve as part of the manufacturing process for the transistor 500. As the insulator with high barrier properties against hydrogen or water, for example, the same material as insulator 522 or insulator 514 may be used.

[0366] It should be noted that the transistor that can be used in the present invention is not limited to the transistor 500 shown in Figure 25. For example, a transistor 500 with the structure shown in Figure 26 may be used. The transistor 500 shown in Figure 26 differs from the transistor shown in Figure 25 in that an insulator 555 is used and that the conductors 542a and 542b have a layered structure.

[0367] Conductor 542a has a laminated structure consisting of conductor 542a1 and conductor 542a2 on conductor 542a1. Conductor 542b has a laminated structure consisting of conductor 542b1 and conductor 542b2 on conductor 542b1. It is preferable that conductors 542a1 and 542b1, which are in contact with oxide 530b, are conductors that are difficult to oxidize, such as metal nitrides. This prevents conductors 542a and 542b from being excessively oxidized by oxygen contained in oxide 530b. It is also preferable that conductors 542a2 and 542b2 are conductors with higher conductivity than conductors 542a1 and 542b1, such as metal layers. This allows conductors 542a and 542b to function as highly conductive wiring or electrodes. In this way, a semiconductor device can be provided in which conductors 542a and 542b, which function as wiring or electrodes, are provided in contact with the upper surface of an oxide 530 that functions as an active layer.

[0368] It is preferable to use metal nitrides as the conductors 542a1 and 542b1. For example, it is preferable to use nitrides containing tantalum, nitrides containing titanium, nitrides containing molybdenum, nitrides containing tungsten, nitrides containing tantalum and aluminum, or nitrides containing titanium and aluminum. In one embodiment of the present invention, nitrides containing tantalum are particularly preferred. Alternatively, for example, ruthenium, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, or oxides containing lanthanum and nickel may be used. These materials are preferred because they are conductive materials that are resistant to oxidation, or materials that maintain conductivity even when absorbing oxygen.

[0369] Furthermore, it is preferable that conductors 542a2 and 542b2 have higher conductivity than conductors 542a1 and 542b1. For example, it is preferable to make the film thickness of conductors 542a2 and 542b2 greater than the film thickness of conductors 542a1 and 542b1. As conductors 542a2 and 542b2, any conductors that can be used in the above-mentioned conductor 560b may be used. By adopting the above-described structure, the resistance of conductors 542a2 and 542b2 can be reduced.

[0370] For example, tantalum nitride or titanium nitride can be used as conductors 542a1 and 542b1, and tungsten can be used as conductors 542a2 and 542b2.

[0371] As shown in Figure 26, in a cross-sectional view of transistor 500 in the channel length direction, the distance between conductor 542a1 and conductor 542b1 is smaller than the distance between conductor 542a2 and conductor 542b2. This configuration allows for a shorter distance between the source and drain, and consequently, a shorter channel length. Therefore, the frequency characteristics of transistor 500 can be improved. In this way, by miniaturizing the semiconductor device, it is possible to provide a semiconductor device with improved operating speed.

[0372] The insulator 555 is preferably an insulator that is resistant to oxidation, such as a nitride. The insulator 555 is formed in contact with the side surfaces of the conductor 542a2 and the conductor 542b2, and has the function of protecting the conductors 542a2 and 542b2. Since the insulator 555 is exposed to an oxidizing atmosphere, an inorganic insulator that is resistant to oxidation is preferred. Furthermore, since the insulator 555 is in contact with the conductors 542a2 and 542b2, it is preferable that it be an inorganic insulator that does not easily oxidize the conductors 542a2 and 542b2. Therefore, it is preferable that the insulator 555 be an insulating material that has barrier properties against oxygen. For example, silicon nitride can be used as the insulator 555.

[0373] The transistor 500 shown in Figure 26 is formed by creating openings in insulators 580 and 544, forming an insulator 555 in contact with the side wall of the opening, and further separating the conductor 542a1 and conductor 542b1 using a mask. Here, the opening overlaps with the region between conductors 542a2 and 542b2. Also, parts of conductors 542a1 and 542b1 are formed to protrude into the opening. Therefore, within the opening, the insulator 555 is in contact with the upper surface of conductor 542a1, the upper surface of conductor 542b1, the side surface of conductor 542a2, and the side surface of conductor 542b2. In addition, the insulator 545 is in contact with the upper surface of the oxide 530 in the region between conductors 542a1 and 542b1.

[0374] It is preferable to perform heat treatment in an oxygen-containing atmosphere after separating the conductor 542a1 and conductor 542b1, and before forming the insulator 545. This supplies oxygen to oxides 530a and 530b, thereby reducing oxygen deficiency. Furthermore, since the insulator 555 is formed in contact with the sides of conductor 542a2 and conductor 542b2, it is possible to prevent excessive oxidation of conductors 542a2 and 542b2. As a result, the electrical characteristics and reliability of the transistor can be improved. In addition, variations in the electrical characteristics of multiple transistors formed on the same substrate can be suppressed.

[0375] Furthermore, in transistor 500, the insulator 524 may be formed in an island shape, as shown in Figure 26. Here, the insulator 524 may be formed such that the side edge of the insulator 524 and the side edge of the oxide 530 roughly coincide.

[0376] Furthermore, in transistor 500, as shown in Figure 26, the insulator 522 may be in contact with the insulator 516 and the conductor 503. In other words, the insulator 520 shown in Figures 25(A) and 25(B) may be omitted.

[0377] Next, a capacitor 600 is provided above the transistor 500. The capacitor 600 has a conductor 610, a conductor 620, and an insulator 630.

[0378] Furthermore, a conductor 612 may be provided on the conductors 546 and 548. The conductor 612 functions as a plug or wiring for connecting to the transistor 500. The conductor 610 functions as an electrode with capacitance 600. Note that the conductors 612 and 610 can be formed simultaneously.

[0379] For conductors 612 and 610, for example, a metal film containing an element selected from molybdenum, titanium, tantalum, tungsten, aluminum, copper, chromium, neodymium, and scandium, or a metal nitride film (tantalum nitride film, titanium nitride film, molybdenum nitride film, or tungsten nitride film) composed of the above elements can be used. Alternatively, conductive materials such as indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, or indium tin oxide with silicon oxide added can be applied to conductors 612 and 610.

[0380] In this embodiment, the conductors 612 and 610 are shown as single-layer structures, but the embodiment is not limited to this configuration, and the conductors 612 and 610 may be laminated in two or more layers. For example, a conductor with barrier properties and a conductor with high adhesion to the highly conductive conductor may be formed between a conductor with barrier properties and a conductor with high conductivity.

[0381] A conductor 620 is provided so as to overlap the conductor 610 via an insulator 630. The conductor 620 can be made of a conductive material such as a metal, alloy, or metal oxide. Preferably, the conductor 620 is made of a high-melting-point material such as tungsten or molybdenum, which provides both heat resistance and conductivity, and tungsten is particularly preferred. If the conductor 620 is formed simultaneously with other components, such as other conductors, a low-resistance metallic material such as copper or aluminum may be used.

[0382] An insulator 640 is provided on the conductor 620 and the insulator 630. The insulator 640 can be provided using the same material as the insulator 320. The insulator 640 may also function as a planarizing film that covers the uneven shape below it.

[0383] By using this configuration, it is possible to achieve miniaturization or high integration in semiconductor devices using transistors having oxide semiconductors.

[0384] In addition, as substrates that can be used in a semiconductor device according to one embodiment of the present invention, for example, glass substrates, quartz substrates, sapphire substrates, ceramic substrates, metal substrates (for example, stainless steel substrates, substrates with stainless steel foil, tungsten substrates, or substrates with tungsten foil, etc.), semiconductor substrates (for example, single-crystal semiconductor substrates, polycrystalline semiconductor substrates, or compound semiconductor substrates, etc.), or SOI (Silicon on Insulator) substrates can be used. Furthermore, a plastic substrate having heat resistance that can withstand the processing temperature of this embodiment may be used as the substrate. Examples of glass substrates include barium borosilicate glass, aluminosilicate glass, aluminoborosilicate glass, or soda-lime glass. Other glass substrates that can be used include, for example, crystallized glass.

[0385] Furthermore, as substrates, for example, flexible substrates, laminated films, paper containing fibrous materials, or base films can be used. For example, flexible substrates, laminated films, or base films include plastics such as polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyethersulfone (PES), or polytetrafluoroethylene (PTFE). Alternatively, synthetic resins such as acrylic can be used. Alternatively, polypropylene, polyester, polyvinyl fluoride, or polyvinyl chloride can be used. Alternatively, polyamide, polyimide, aramid resin, epoxy resin, inorganic vapor-deposited film, or paper can be used. In particular, by manufacturing transistors using semiconductor substrates, single-crystal substrates, or SOI substrates, for example, transistors with less variation in characteristics, size, or shape, high current capability, and small size can be manufactured. By configuring circuits with such transistors, it is possible to reduce the power consumption of the circuit or increase the integration of the circuit.

[0386] Furthermore, a flexible substrate may be used as the substrate, and one or more components such as transistors, resistors, and capacitors may be formed directly on the flexible substrate. Alternatively, a release layer may be provided between the substrate and one or more components such as transistors, resistors, and capacitors. The release layer can be separated from the substrate after a semiconductor device is partially or completely completed on it, and then transferred to another substrate. In this case, one or more components such as transistors, resistors, and capacitors can be transferred to substrates with poor heat resistance, or flexible substrates, for example. The release layer can be, for example, a structure in which an inorganic film of a tungsten film and a silicon oxide film is laminated, a structure in which an organic resin film such as polyimide is formed on the substrate, or a silicon film containing hydrogen.

[0387] In other words, a semiconductor device may be formed on one substrate and then transferred to another substrate. Examples of substrates to which the semiconductor device is transferred include, in addition to the substrates on which transistors can be formed as described above, paper substrates, cellophane substrates, aramid film substrates, polyimide film substrates, stone substrates, wood substrates, cloth substrates (including, for example, natural fibers (silk, cotton, or hemp), synthetic fibers (nylon, polyurethane, or polyester), or recycled fibers (acetate, cupro, rayon, or recycled polyester)), leather substrates, or rubber substrates. By using these substrates, it is possible to manufacture flexible semiconductor devices or semiconductor devices that are less prone to breakage. It is also possible to impart heat resistance to the semiconductor device. Furthermore, it is possible to make the semiconductor device lighter or thinner.

[0388] By mounting a semiconductor device on a flexible substrate, it is possible to provide a semiconductor device that is less prone to damage and has a reduced increase in weight.

[0389] Note that the transistor 550 shown in Figure 24 is just one example, and the configuration is not limited to this. For example, an appropriate transistor can be used depending on the circuit configuration or driving method. For example, if the semiconductor device is a unipolar circuit consisting only of OS transistors (meaning a circuit consisting only of n-channel transistors, or a circuit consisting only of p-channel transistors), the configuration of transistor 550 can be the same as that of transistor 500.

[0390] The configurations, structures, or methods shown in this embodiment can be used in appropriate combination with the configurations, structures, or methods shown in other embodiments and examples.

[0391] (Embodiment 3) This embodiment describes cross-sectional configuration examples of memory devices having OS transistors as described in the above embodiment, such as DOSRAM and NOSRAM.

[0392] Figure 27 shows an example of a cross-sectional configuration using the circuit configuration of DOSRAM. Figure 27 illustrates a case where memory layers 400[1] to 400[4] are stacked on top of the drive circuit layer 401.

[0393] Furthermore, Figure 27 illustrates a transistor 550 in the drive circuit layer 401. The transistor 550 can be the same as the transistor 550 described in the above embodiment. Therefore, the above description of the transistor 550 can be taken into consideration as appropriate.

[0394] Note that the transistor 550 shown in Figure 27 is just one example, and its structure is not limited to this; any appropriate transistor can be used depending on the circuit configuration or driving method.

[0395] Between the drive circuit layer 401 and the storage layer 400, or between the k-th storage layer 400 and the (k+1)th storage layer 400, a wiring layer may be provided, for example, with an interlayer film, wiring, and plugs. In this embodiment, the k-th storage layer 400 may be referred to as storage layer 400[k], and the (k+1)th storage layer 400 may be referred to as storage layer 400[k+1]. Here, k is an integer of 1 or more.

[0396] Furthermore, multiple wiring layers can be provided depending on the design. Also, in this specification, the wiring and the plug that electrically connects to the wiring may be an integrated unit. That is, a part of the conductor may function as wiring, and a part of the conductor may function as a plug.

[0397] For example, on the transistor 550, insulators 320, 322, 324, and 326 are layered in order as interlayer films. Insulators 320 and 322 have, for example, a conductor 328 embedded in them. Insulators 324 and 326 have, for example, a conductor 330 embedded in them. Conductors 328 and 330 function as contact plugs or wiring.

[0398] Furthermore, the insulator functioning as an interlayer film may also function as a planarizing film that covers the uneven shape beneath it. For example, the upper surface of the insulator 320 may be planarized by a planarizing treatment, such as chemical mechanical polishing (CMP), in order to improve its flatness.

[0399] A wiring layer may be provided on the insulator 326 and the conductor 330. For example, in Figure 27, insulators 350, 357, 352, and 354 are sequentially stacked on the insulator 326 and the conductor 330. Conductors 356 are formed on insulators 350, 357, and 352. The conductor 356 functions as a contact plug or wiring.

[0400] An insulator 514 of the memory layer 400[1] is provided on top of the insulator 354. Conductors 358 are embedded in the insulators 514 and 354. Conductors 358 function as contact plugs or wires. For example, the bit line BL and the transistor 550 are electrically connected via, for example, the conductors 358, 356, and 330.

[0401] Figure 28(A) shows an example of the cross-sectional structure of the 400k memory layer. Figure 28(B) shows the equivalent circuit diagram of Figure 28(A). Figure 28(A) shows an example in which two memory cells MC are electrically connected to one bit line BL.

[0402] The memory cell MC shown in Figures 27, 28(A), and 28(B) has a transistor M1 and a capacitance C. For example, the transistor 500 shown in the above embodiment can be used as the transistor M1. Therefore, the above description of the transistor 500 can be taken into consideration as appropriate.

[0403] In this embodiment, transistor M1 is shown as a modified version of transistor 500. Specifically, transistor M1 differs from transistor 500 in that the conductors 542a and 542b extend beyond the edges of the metal oxide 531 (oxide 531a and oxide 531b).

[0404] The memory cell MC shown in Figures 27 and 28(A) includes a conductor 156 that functions as one terminal of capacitance C, an insulator 153 that functions as a dielectric, and a conductor 160 (conductor 160a and conductor 160b) that functions as the other terminal of capacitance C. Conductor 156 is electrically connected to a portion of conductor 542b. Conductor 160 is also electrically connected to wiring PL (not shown in Figure 28(A)).

[0405] Furthermore, one of the sources or drains of transistor M1 is electrically connected to a portion of conductor 542b. The other of the sources or drains of transistor M1 is electrically connected to a portion of conductor 542a. The gate of transistor M1 is electrically connected to the word line WL. A portion of conductor 542a is electrically connected to the bit line BL.

[0406] Capacitance C is formed in an opening created by removing a portion of insulators 574, 580, and 554. Since the conductor 156, insulators 580, and insulators 554 are formed along the sides of the opening, it is preferable to deposit them using, for example, the ALD method or the CVD method.

[0407] Furthermore, conductors 156 and 160 may be any conductor that can be used for conductor 505 or conductor 560. For example, titanium nitride formed by the ALD method may be used as conductor 156. Also, titanium nitride formed by the ALD method may be used as conductor 160a, and tungsten formed by the CVD method may be used as conductor 160b. If the adhesion of tungsten to insulator 153 is sufficiently high, a single layer film of tungsten formed by the CVD method may be used as conductor 160.

[0408] For the insulator 153, it is preferable to use an insulator made of a high-dielectric constant (high-k) material (a material with a high relative permittivity). For example, as a high-dielectric constant insulator, an oxide, oxidized nitride, nitride oxide, or nitride containing one or more metal elements selected from, for example, aluminum, hafnium, zirconium, and gallium can be used. Silicon may also be included in the above oxide, oxidized nitride, nitride oxide, or nitride. Alternatively, an insulating layer made of the above materials can be laminated and used as a high-dielectric constant insulator.

[0409] Furthermore, as an insulator made of high dielectric constant material, for example, aluminum oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxiditrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxiditrides containing silicon and hafnium, oxides containing silicon and zirconium, oxiditrides containing silicon and zirconium, oxides containing hafnium and zirconium, or oxiditrides containing hafnium and zirconium can be used. By using such high dielectric constant material, the insulator 153 can be made thick enough to suppress leakage current, and the capacitance C can be sufficiently secured.

[0410] Furthermore, it is preferable to use an insulating layer made of the above materials as the insulator 153, and it is preferable to use a laminated structure of a high dielectric constant material and a material with greater dielectric strength than the high dielectric constant material. As the insulator 153, for example, an insulating film can be used in which zirconium oxide, aluminum oxide, and zirconium oxide are laminated in this order. Alternatively, for example, an insulating film can be used in which zirconium oxide, aluminum oxide, zirconium oxide, and aluminum oxide are laminated in this order. Alternatively, for example, an insulating film can be used in which hafnium zirconium oxide, aluminum oxide, hafnium zirconium oxide, and aluminum oxide are laminated in this order. By using an insulating material with relatively high dielectric strength, such as aluminum oxide, as the insulator 153, the dielectric strength can be improved and electrostatic breakdown of capacitance C can be suppressed.

[0411] Figure 29 shows an example of a cross-sectional configuration using the circuit configuration of a NOSRAM memory cell. Note that Figure 29 is also a modified version of Figure 27. Furthermore, Figure 30(A) shows an example of a cross-sectional structure of the memory layer 400[k]. Furthermore, Figure 30(B) shows the equivalent circuit diagram of Figure 30(A).

[0412] The memory cell MC shown in Figures 29 and 30(A) has transistors M1, M2, and M3 on an insulator 514. A conductor 215 is provided so as to be embedded in an insulator 516 on top of the insulator 514. The conductor 215 can be formed simultaneously using the same material and process as the conductor 505.

[0413] Furthermore, transistors M2 and M3, shown in Figures 29 and 30(A), share a single island-shaped metal oxide 531. In other words, a portion of the island-shaped metal oxide 531 functions as the channel formation region for transistor M2, and the other portion functions as the channel formation region for transistor M3. Also, the source of transistor M2 and the drain of transistor M3, or the drain of transistor M2 and the source of transistor M3, are shared. Therefore, the area occupied by the transistors is smaller than when transistors M2 and M3 are provided independently.

[0414] Furthermore, in the memory cell MC shown in Figures 29 and 30(A), an insulator 287 is provided on top of an insulator 581, and a conductor 161 is embedded in the insulator 287. In addition, an insulator 514 of the memory layer 400[k+1] is provided on top of the insulator 287 and the conductor 161.

[0415] A region where a portion of the conductor 161 of memory layer 400[k] and a portion of the conductor 215 of memory layer 400[k+1] are superimposed via the insulator 514 functions as capacitance C. That is, the conductor 161 of memory layer 400[k] functions as one terminal of capacitance C, the insulator 514 of memory layer 400[k+1] functions as the dielectric of capacitance C, and the conductor 215 of memory layer 400[k+1] functions as the other terminal of capacitance C. In addition, one of the sources or drains of transistor M1 is electrically connected to conductor 161 via a contact plug, and the gate of transistor M2 is electrically connected to conductor 161 via the other contact plug. Conductor 161 functions as a charge-holding node FN. Conductor 215 is electrically connected to wiring PL.

[0416] Furthermore, the other source or drain of transistor M1 is electrically connected to the bit line WBL. The gate of transistor M1 is electrically connected to the word line WWL. One source or drain of transistor M2 is electrically connected to one source or drain of transistor M3 by sharing the metal oxide 531. The other source or drain of transistor M2 is electrically connected to the source line SL (not shown in Figure 30(A)). The other source or drain of transistor M3 is electrically connected to the bit line RBL. The gate of transistor M3 is electrically connected to the word line RWL.

[0417] This embodiment can be implemented in appropriate combination with other embodiments described herein.

[0418] (Embodiment 4) In this embodiment, a transistor containing an oxide semiconductor in the channel formation region (OS transistor) will be described. A brief comparison with a transistor containing silicon in the channel formation region (also called a Si transistor) will also be provided in the description of the OS transistor.

[0419] [OS Transistor] For OS transistors, it is preferable to use oxide semiconductors with low carrier concentrations. For example, the carrier concentration in the channel formation region of an oxide semiconductor is 1 × 10⁻⁶. 18 cm -3 The following is preferably 1 × 10 17 cm -3 Less than 1 × 10 16 cm -3 Less than 1 × 10 13 cm -3 Less than 1 × 10 10 cm -3 It is less than 1 × 10 -9 cm -3This concludes the explanation. Furthermore, when lowering the carrier concentration of an oxide semiconductor film, the impurity concentration in the oxide semiconductor film should be lowered to reduce the defect level density. In this specification, a low impurity concentration and low defect level density are referred to as high-purity intrinsic or substantially high-purity intrinsic. Note that oxide semiconductors with low carrier concentrations are sometimes referred to as high-purity intrinsic or substantially high-purity intrinsic oxide semiconductors.

[0420] Furthermore, oxide semiconductors that are high-purity intrinsic or substantially high-purity intrinsic have a low defect level density, which can result in a low trap level density. In addition, charges trapped in the trap levels of oxide semiconductors can take a long time to disappear and may behave like fixed charges. Therefore, transistors in which channel formation regions are formed in oxide semiconductors with a high trap level density may exhibit unstable electrical properties.

[0421] Therefore, reducing the impurity concentration in the oxide semiconductor is effective in stabilizing the electrical characteristics of a transistor. Furthermore, in order to reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in adjacent films. Examples of impurities include hydrogen and nitrogen. Note that impurities in an oxide semiconductor refer to elements other than the main components that make up the oxide semiconductor. For example, elements with a concentration of less than 0.1 atomic percent can be considered impurities.

[0422] Furthermore, if impurities or oxygen vacancies are present in the channel formation region of an OS transistor, its electrical properties are prone to fluctuation, potentially leading to poor reliability. Additionally, OS transistors may form defects (sometimes referred to as VOHs) where hydrogen atoms are trapped in oxygen vacancies in the oxide semiconductor, generating electron carriers. Moreover, the formation of VOHs in the channel formation region of an OS transistor can increase the donor concentration within that region. This can cause the threshold voltage of the OS transistor to fluctuate as the donor concentration in the channel formation region increases. Therefore, if oxygen vacancies are present in the channel formation region of an OS transistor, it is more likely to exhibit normally-on characteristics (where a channel exists and current flows through the transistor even without applying voltage to the gate electrode). Consequently, it is preferable to minimize impurities, oxygen vacancies, and VOHs in the channel formation region of the oxide semiconductor as much as possible.

[0423] Furthermore, the band gap of the oxide semiconductor is preferably larger than that of silicon (typically 1.1 eV), preferably 2 eV or more, more preferably 2.5 eV or more, and even more preferably 3.0 eV or more. By using an oxide semiconductor with a larger band gap than silicon, the off-current (also called Ioff) of the transistor can be reduced.

[0424] Furthermore, in Si transistors, as the transistor miniaturization progresses, the short channel effect (also known as SCE) emerges. Therefore, miniaturization becomes difficult with Si transistors. One factor contributing to the short channel effect is the small bandgap of silicon. On the other hand, OS transistors use oxide semiconductors, which are semiconductor materials with a large bandgap, thus suppressing the short channel effect. In other words, OS transistors are transistors that have no short channel effect, or only a very small short channel effect.

[0425] Short-channel effects refer to the degradation of electrical characteristics that becomes apparent with the miniaturization of transistors (reduction of channel length). Specific examples of short-channel effects include a decrease in threshold voltage, an increase in the subthreshold swing value (sometimes denoted as the S value), and an increase in leakage current. Here, the S value refers to the change in gate voltage when the drain current is changed by one order of magnitude while the drain voltage remains constant in the subthreshold region.

[0426] Furthermore, characteristic length is widely used as an indicator of resistance to short-channel effects. Characteristic length is an indicator of how easily the potential in the channel-forming region bends. The smaller the characteristic length, the steeper the rise of the potential, and therefore the more resistant the system is to short-channel effects.

[0427] OS transistors are storage-type transistors, while Si transistors are inverting-type transistors. Therefore, OS transistors have smaller characteristic lengths between the source region and the channel formation region, and between the drain region and the channel formation region, compared to Si transistors. Consequently, OS transistors are more resistant to short-channel effects than Si transistors. In other words, when it is necessary to fabricate transistors with short channel lengths, OS transistors are preferable to Si transistors.

[0428] Even when the carrier concentration of the oxide semiconductor is reduced until the channel formation region is i-type or substantially i-type, in short-channel transistors, the Conduction-Band-Lowering (CBL) effect lowers the lower edge of the conduction band in the channel formation region. As a result, the energy difference at the lower edge of the conduction band between the source or drain region and the channel formation region can be reduced to between 0.1 eV and 0.2 eV. Consequently, OS transistors can also be viewed as n+ / n- / n+ storage-type junction-less transistor structures, or n+ / n- / n+ storage-type non-junction transistor structures, where the channel formation region is an n-type region and the source and drain regions are both n+-type regions.

[0429] OS transistors, by adopting the above structure, can maintain good electrical characteristics even when miniaturized or highly integrated. For example, OS transistors can obtain good electrical characteristics even when the gate length is 20 nm or less, 15 nm or less, 10 nm or less, 7 nm or less, or 6 nm or less, and also 1 nm or more, 3 nm or more, or 5 nm or more. On the other hand, Si transistors exhibit short-channel effects, making it difficult to achieve gate lengths of 20 nm or less or 15 nm or less. Therefore, OS transistors can be suitably used in transistors with shorter channel lengths compared to Si transistors. Note that gate length refers to the length of the gate electrode in the direction in which carriers move within the channel formation region during transistor operation, and is the width of the bottom surface of the gate electrode in a plan view of the transistor.

[0430] Furthermore, miniaturizing the OS transistor can improve the high-frequency characteristics of the transistor. Specifically, the cutoff frequency of the transistor can be improved. When the gate length of the OS transistor is within the above range, the cutoff frequency of the transistor can be set to, for example, 50 GHz or higher, preferably 100 GHz or higher, and more preferably 150 GHz or higher, under room temperature conditions.

[0431] As explained above, OS transistors have superior advantages compared to Si transistors, such as lower off-current and the ability to fabricate transistors with shorter channel lengths.

[0432] The configurations, structures, and methods shown in this embodiment can be used in appropriate combination with the configurations, structures, and methods shown in other embodiments.

[0433] (Embodiment 5) This embodiment describes electronic components, electronic devices, large computers, space equipment, and data centers (also referred to as DCs) that can use the semiconductor device described in the above embodiment. Electronic components, electronic devices, large computers, space equipment, and data centers using a semiconductor device according to one aspect of the present invention are effective in achieving high performance, such as low power consumption.

[0434] [Electronic components] Figure 31(A) is a perspective view of an electronic component 700 and a substrate (mounted substrate 704) on which the electronic component 700 is mounted. The electronic component 700 shown in Figure 31(A) has a semiconductor device 710 within a mold 711. Some details are omitted in Figure 31(A) to show the inside of the electronic component 700. The electronic component 700 has a land 712 on the outside of the mold 711. The land 712 is electrically connected to an electrode pad 713. The electrode pad 713 is electrically connected to the semiconductor device 710 by a wire 714. The electronic component 700 is mounted, for example, on a printed circuit board 702. Multiple such electronic components are combined and each electronic component is electrically connected on the printed circuit board 702 to complete the mounted substrate 704.

[0435] Furthermore, the semiconductor device 710 includes a drive circuit layer 715 and a storage layer 716. The storage layer 716 has a configuration in which multiple memory cell arrays are stacked. The configuration in which the drive circuit layer 715 and the storage layer 716 are stacked can be a monolithic stack configuration. In a monolithic stack configuration, the layers can be connected without using through-electrode technologies such as TSV (Through Silicon Via) and bonding technologies such as Cu-Cu direct bonding. By configuring the drive circuit layer 715 and the storage layer 716 in a monolithic stack configuration, for example, a so-called on-chip memory configuration can be achieved in which memory is directly formed on the processor. By using an on-chip memory configuration, it is possible to speed up the operation of the interface portion between the processor and the memory.

[0436] Furthermore, by using an on-chip memory configuration, it is possible to reduce the size of connection wiring, for example, compared to technologies that use through-electrodes such as TSV, and thus increase the number of connection pins. Increasing the number of connection pins enables parallel operation, which in turn improves the memory bandwidth (also called memory bandwidth).

[0437] Furthermore, it is preferable to form the multiple memory cell arrays of the memory layer 716 using OS transistors and to stack these multiple memory cell arrays monolithically. By configuring the multiple memory cell arrays in a monolithic stack, it is possible to improve either or both of the memory bandwidth and / or memory access latency. Bandwidth refers to the amount of data transferred per unit time. Access latency refers to the time from access to the start of data exchange. In the case of a configuration using Si transistors in the memory layer 716, it is difficult to create a monolithic stack configuration compared to OS transistors. Therefore, in a monolithic stack configuration, OS transistors can be said to have a superior structure compared to Si transistors.

[0438] In other words, OS transistors have superior advantages compared to Si transistors, such as the ability to achieve a wider memory bandwidth.

[0439] The semiconductor device 710 may also be referred to as a die. In this specification, a die refers to a chip piece obtained in the semiconductor chip manufacturing process by forming a circuit pattern on, for example, a disc-shaped substrate (also called a wafer) and cutting it into cubes. Examples of semiconductor materials that can be used for dies include silicon, silicon carbide, or gallium nitride. For example, a die obtained from a silicon substrate (also called a silicon wafer) is sometimes called a silicon die.

[0440] Figure 31(B) is a perspective view of the electronic component 730. The electronic component 730 is an example of a SiP (System in Package) or MCM (Multi Chip Module). The electronic component 730 has an interposer 731 on a package substrate 732 (printed circuit board), and a semiconductor device 735 and a plurality of semiconductor devices 710 are provided on the interposer 731.

[0441] In the electronic component 730, the semiconductor device 710 can be used, for example, as a high-bandwidth memory (HBM). Furthermore, the semiconductor device 735 can be used, for example, as an integrated circuit (semiconductor device) such as a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), or an FPGA (Field Programmable Gate Array).

[0442] The package substrate 732 can be, for example, a ceramic substrate, a plastic substrate, or a glass epoxy substrate. The interposer 731 can be, for example, a silicon interposer or a resin interposer.

[0443] The interposer 731 has multiple wirings, each of which electrically connects multiple integrated circuits with different terminal pitches. The multiple wirings are provided in a single layer or multiple layers. The interposer 731 also has the function of electrically connecting integrated circuits provided on the interposer 731 to electrodes provided on the package substrate 732. For these reasons, the interposer 731 is sometimes called a "redistribution board" or "intermediate board". In addition, the interposer 731 may also be provided with through electrodes, which are used to electrically connect the integrated circuits to the package substrate 732. Furthermore, when using a silicon interposer, TSV (Through Silicon Via) can be used as the through electrode in the interposer 731.

[0444] It is preferable to use a silicon interposer for the interposer 731. Since silicon interposers do not require active elements, they can be manufactured at a lower cost than integrated circuits. In addition, because the wiring of a silicon interposer can be formed using a semiconductor process, it is easy to form fine wiring, which is difficult with resin interposers.

[0445] HBMs require numerous connections to achieve a wide memory bandwidth. Therefore, interposers for mounting HBMs require fine and high-density wiring. For this reason, it is preferable to use silicon interposers for mounting HBMs.

[0446] Furthermore, SiP or MCM using a silicon interposer, for example, are less susceptible to reliability degradation due to differences in expansion coefficients between the integrated circuit and the interposer. Also, because silicon interposers have high surface flatness, connection failures between the integrated circuit placed on the silicon interposer and the silicon interposer are less likely to occur. In particular, for 2.5D packages (2.5-dimensional packaging) where multiple integrated circuits are arranged side by side on the interposer, it is preferable to use a silicon interposer.

[0447] On the other hand, when electrically connecting multiple integrated circuits with different terminal pitches using, for example, a silicon interposer and a TSV, space is required, such as the width of the terminal pitch. Therefore, when trying to reduce the size of the electronic component 730, the width of the terminal pitch becomes a problem, and it may become difficult to provide the many wires necessary to achieve a wide memory bandwidth. For this reason, as described above, a monolithic stacked configuration using OS transistors is preferable. A composite structure combining a memory cell array stacked using TSVs and a monolithic stacked memory cell array may also be used.

[0448] A heat sink (heat dissipation plate) may be provided on top of the electronic component 730 on the substrate on which the electronic component 730 is mounted. When a heat sink is provided, it is preferable that the heights of the integrated circuits provided on the interposer 731 be the same. For example, in the electronic component 730 shown in this embodiment, it is preferable that the heights of the semiconductor device 710 and the semiconductor device 735 be the same.

[0449] To mount the electronic component 730 onto another substrate, the package substrate 732 may have electrodes 733 at its bottom. Figure 31(B) shows an example where the electrodes 733 are formed with solder balls. The electronic component 730 can be mounted using BGA (Ball Grid Array) mounting by arranging solder balls in a matrix at the bottom of the package substrate 732. The electrodes 733 may also be formed with conductive pins. The electronic component 730 can be mounted using PGA (Pin Grid Array) mounting by arranging conductive pins in a matrix at the bottom of the package substrate 732.

[0450] The electronic component 730 can be mounted on other boards using various mounting methods, not limited to BGA or PGA. For example, mounting methods such as SPGA (Staggered Pin Grid Array), LGA (Land Grid Array), QFP (Quad Flat Package), QFJ (Quad Flat J-leaded package), or QFN (Quad Flat Non-leaded package) can be used.

[0451] [Electronic equipment] Figure 32(A) is a perspective view of the electronic device 6500. The electronic device 6500 shown in Figure 32(A) is a portable information terminal that can be used as a smartphone. The electronic device 6500 includes, for example, a housing 6501, a display unit 6502, a power button 6503, a button 6504, a speaker 6505, a microphone 6506, a camera 6507, a light source 6508, and a control device 6509. The control device 6509 includes, for example, one or more selected from a CPU, a GPU, and a storage device. One embodiment of the semiconductor device of the present invention can be applied, for example, to the display unit 6502 or the control device 6509. Using the semiconductor device of one embodiment of the present invention in the control device 6509 is preferable because it can reduce power consumption.

[0452] Figure 32(B) is a perspective view of the electronic device 6600. The electronic device 6600 shown in Figure 32(B) is an information terminal that can be used as a notebook personal computer. The electronic device 6600 includes, for example, a housing 6611, a keyboard 6612, a pointing device 6613, an external connection port 6614, a display unit 6615, and a control device 6616. The control device 6616 includes, for example, one or more selected from a CPU, a GPU, and a storage device. One embodiment of the semiconductor device of the present invention can be applied to, for example, a control device 6509 or a control device 6616. Using the semiconductor device of one embodiment of the present invention in the control device 6616 is preferable because it can reduce power consumption.

[0453] [Large computer] Figure 32(C) is a perspective view of the large-scale computer 5600. The large-scale computer 5600 shown in Figure 32(C) contains multiple rack-mount type computers 5620 housed in rack 5610. The large-scale computer 5600 may also be referred to as a supercomputer.

[0454] Figure 32(D) is a perspective view illustrating an example configuration of computer 5620. In Figure 32(D), computer 5620 has a motherboard 5630. The motherboard 5630 has multiple slots 5631 and multiple connection terminals (not shown). A PC card 5621 is inserted into slot 5631. In addition, the PC card 5621 has connection terminals 5623, 5624, and 5625, which are connected to the motherboard 5630.

[0455] The PC card 5621 shown in Figure 32(E) is an example of a processing board equipped with, for example, a CPU, GPU, and storage device. The PC card 5621 has a board 5622. The board 5622 has connection terminals 5623, 5624, and 5625, as well as semiconductor devices 5626, 5627, 5628, and 5629. Although Figure 32(E) shows semiconductor devices other than semiconductor devices 5626, 5627, and 5628, for information on these semiconductor devices, please refer to the descriptions of semiconductor devices 5626, 5627, and 5628 below.

[0456] The connector 5629 has a shape that allows it to be inserted into slot 5631 of the motherboard 5630, and the connector 5629 functions as an interface for connecting the PC card 5621 and the motherboard 5630. Examples of standards for the connector 5629 include PCIe (Peripheral Component Interconnect Express).

[0457] Each of the connection terminals 5623, 5624, and 5625 can serve as an interface for, for example, power supply or signal input to the PC card 5621. They can also serve as an interface for, for example, outputting signals calculated by the PC card 5621. Examples of the standards for each of the connection terminals 5623, 5624, and 5625 include USB (Universal Serial Bus), SATA (Serial ATA), and SCSI (Small Computer System Interface). Furthermore, when outputting video signals from each of the connection terminals 5623, 5624, and 5625, examples of the standards include HDMI (registered trademark) (High-Definition Multimedia Interface).

[0458] The semiconductor device 5626 has terminals (not shown) for inputting and outputting signals, and the semiconductor device 5626 and the board 5622 can be electrically connected by inserting these terminals into sockets (not shown) provided on the board 5622.

[0459] The semiconductor device 5627 has multiple terminals, and the semiconductor device 5627 and the board 5622 can be electrically connected by, for example, reflow soldering, to the terminals on the board 5622. Examples of the semiconductor device 5627 include FPGAs, GPUs, and CPUs. For example, the electronic component 730 described above can be used as the semiconductor device 5627.

[0460] The semiconductor device 5628 has multiple terminals, and the semiconductor device 5628 and the board 5622 can be electrically connected by, for example, reflow soldering, to the terminals on the board 5622. Examples of the semiconductor device 5628 include a memory device. For example, the electronic component 700 described above can be used as the semiconductor device 5628.

[0461] The 5600 mainframe computer can also function as a parallel computer. By using the 5600 mainframe computer as a parallel computer, it is possible to perform large-scale calculations necessary for, for example, artificial intelligence training and inference.

[0462] [Space equipment] A semiconductor device according to one aspect of the present invention can be suitably used in space equipment such as devices that process and store information.

[0463] A semiconductor device according to one aspect of the present invention may include an OS transistor. The OS transistor exhibits small fluctuations in electrical properties due to radiation exposure. In other words, because the OS transistor has high resistance to radiation, it can be suitably used in environments where radiation may be incident. For example, the OS transistor can be suitably used in outer space.

[0464] Figure 33 shows satellite 6800 as an example of space equipment. Satellite 6800 comprises a body 6801, solar panels 6802, an antenna 6803, a secondary battery 6805, and a control device 6807. Figure 33 also illustrates planet 6804 in outer space. Outer space refers to, for example, an altitude of 100 km or more, but as described herein, outer space may also include the thermosphere, mesosphere, and stratosphere.

[0465] Furthermore, although not shown in Figure 33, a battery management system (also known as a BMS) or a battery control circuit may be provided with the secondary battery 6805. Using an OS transistor in the aforementioned battery management system or battery control circuit is preferable because it consumes little power and has high reliability even in outer space.

[0466] Furthermore, outer space is an environment with radiation levels more than 100 times higher than those on Earth. Radiation can be categorized into electromagnetic waves (electromagnetic radiation), such as X-rays or gamma rays, or particle radiation, such as alpha rays, beta rays, neutrons, protons, heavy ions, or mesons.

[0467] The solar panel 6802 generates the power necessary for the satellite 6800 to operate when exposed to sunlight. However, in situations where the solar panel 6802 is not exposed to sunlight, or where the amount of sunlight it receives is low, the solar panel 6802 generates less power. Therefore, the satellite 6800 may not generate enough power to operate. To ensure the satellite 6800 operates even when the power generated by the solar panel 6802 is low, the satellite 6800 should be equipped with a secondary battery 6805. The solar panel 6802 is sometimes referred to as a solar cell module.

[0468] Satellite 6800 can generate a signal, which is transmitted via antenna 6803. A receiver on the ground, or another satellite, can receive this signal. For example, a receiver can determine its position by receiving the signal transmitted by satellite 6800. Thus, satellite 6800 can constitute a satellite positioning system.

[0469] Furthermore, the control device 6807 has the function of controlling the artificial satellite 6800. The control device 6807 is configured using one or more selected from, for example, a CPU, a GPU, and a memory device. It is preferable that the control device 6807 uses a semiconductor device including an OS transistor, which is one embodiment of the present invention. Compared to Si transistors, OS transistors exhibit smaller fluctuations in electrical characteristics due to radiation irradiation. In other words, OS transistors are highly reliable and can be suitably used even in environments where radiation may be incident.

[0470] In other words, OS transistors have superior effects compared to Si transistors, such as higher radiation resistance.

[0471] Furthermore, the satellite 6800 can be configured to include sensors. For example, by configuring the satellite 6800 to include a visible light sensor, it can have the function of detecting sunlight reflected from objects on the ground. Also, by configuring the satellite 6800 to include a thermal infrared sensor, it can have the function of detecting thermal infrared radiation emitted from the Earth's surface. Therefore, the satellite 6800 can function, for example, as an Earth observation satellite.

[0472] In this embodiment, an artificial satellite was used as an example of space equipment, but the invention is not limited thereto. For example, a semiconductor device according to one aspect of the present invention can be suitably used in space equipment such as spacecraft, space capsules, or space probes.

[0473] [Data Center] One embodiment of the present invention is suitably used in storage systems applied to data centers, for example. Data centers are required to manage data over the long term, such as ensuring data immutability. Managing data over the long term requires, for example, the installation of storage and servers to store vast amounts of data, securing a stable power supply to hold the data, or securing cooling equipment required for data storage. For this reason, for example, the size of the data center building needs to be increased.

[0474] By using a semiconductor device according to one aspect of the present invention in a storage system applied to a data center, it is possible to reduce the power required to retain data and to miniaturize the semiconductor device that retains the data. Therefore, for example, it is possible to miniaturize the storage system, the power supply for retaining data, and the cooling equipment. As a result, it is possible to save space in the data center.

[0475] Furthermore, since the semiconductor device according to one aspect of the present invention consumes less power, heat generation from the circuit can be reduced. Therefore, adverse effects on the circuit itself, peripheral circuits, and peripheral modules due to such heat generation can be reduced. In addition, by using the semiconductor device according to one aspect of the present invention, a data center that operates stably even in high-temperature environments can be realized. Therefore, the reliability of the data center can be improved.

[0476] Figure 34 shows a storage system applicable to a data center. The storage system 7000 shown in Figure 34 has multiple servers 7001sb as hosts 7001 (shown as Host Computer). It also has multiple storage devices 7003md as storage 7003 (shown as Storage). The hosts 7001 and storage 7003 are connected via a storage area network 7004 (shown as SAN: Storage Area Network) and a storage control circuit 7002 (shown as Storage Controller).

[0477] Host 7001 corresponds to a computer that accesses data stored in storage 7003. The hosts 7001 may be connected to each other via a network.

[0478] While Storage 7003 uses flash memory to shorten data access speed, i.e., the time required to write or read data, this time is significantly longer than the time required by DRAM, which can be used as cache memory within the storage. To address the problem of the long access speed of Storage 7003, storage systems typically include cache memory within the storage to shorten the time required to write or read data.

[0479] The aforementioned cache memory is used within the storage control circuit 7002 and storage 7003. Data exchanged between the host 7001 and storage 7003 is stored in the cache memory within the storage control circuit 7002 and storage 7003, and then output to the host 7001 or storage 7003.

[0480] By using OS transistors as the transistors for storing the data in the aforementioned cache memory, and by maintaining a potential corresponding to the data, the frequency of refreshing the cache memory can be reduced, and the power consumption of the cache memory can be lowered. Furthermore, by using a stacked configuration of memory cell arrays, the cache memory can be miniaturized.

[0481] Furthermore, by applying a semiconductor device according to one aspect of the present invention to one or more selected from electronic components, electronic devices, large computers, space equipment, and data centers, power consumption can be reduced. Therefore, as energy demand is expected to increase due to the increased performance or integration of semiconductor devices, using a semiconductor device according to one aspect of the present invention makes it possible to reduce emissions of greenhouse gases, such as carbon dioxide (CO2). In addition, because a semiconductor device according to one aspect of the present invention consumes little power, it is also effective as a measure against global warming.

[0482] The configurations, structures, and methods shown in this embodiment can be used in appropriate combination with the configurations, structures, and methods shown in other embodiments.

[0483] (Notes regarding the descriptions in this specification, etc.) The above embodiments and a description of each component in those embodiments are provided below.

[0484] Where it is stated in this specification that X and Y are connected, this specification discloses the following: an electrically connected X and Y, a functionally connected X and Y, and a directly connected X and Y. Therefore, it is not limited to predetermined connection relationships, such as those shown in the figures or text, but also includes connection relationships other than those shown in the figures or text. X and Y are objects (e.g., devices, elements, circuits, wiring, electrodes, terminals, conductive films, or layers).

[0485] When X and Y are said to be electrically connected, it means that there is an object between X and Y that has some kind of electrical effect, enabling the exchange of electrical signals between X and Y. An example of when X and Y are electrically connected is when one or more elements that enable electrical connection between X and Y (for example, a switch, transistor, capacitive element, inductor, resistive element, diode, display device, light-emitting device, or load) can be connected between X and Y.

[0486] One example of a functional connection between X and Y is when one or more circuits that enable the functional connection between X and Y (e.g., logic circuits (e.g., inverters, NAND gates, or NOR gates), signal conversion circuits (e.g., digital-to-analog conversion circuits, analog-to-digital conversion circuits, or gamma correction circuits), potential level conversion circuits (e.g., power supply circuits (e.g., boost circuits, or buck circuits), or level shifter circuits that change the potential level of a signal), voltage sources, current sources, switching circuits, amplification circuits (e.g., circuits that can increase signal amplitude or current, such as operational amplifiers, differential amplifiers, source follower circuits, or buffer circuits), signal generation circuits, memory circuits, or control circuits) can be connected between X and Y.

[0487] Furthermore, when it is explicitly stated that X and Y are electrically connected, this includes both cases where X and Y are electrically connected (i.e., connected with another element or circuit in between) and cases where X and Y are directly connected (i.e., connected without another element or circuit in between).

[0488] Furthermore, for example, it can be expressed as, "X, Y, the source (which may be referred to as one of the first and second terminals in this specification, etc.) and the drain (which may be referred to as the other of the first and second terminals in this specification, etc.) are electrically connected to each other, and are electrically connected in the order of X, transistor source, transistor drain, and Y." Alternatively, it can be expressed as, "The source of the transistor is electrically connected to X, and the drain of the transistor is electrically connected to Y, and X, transistor source, transistor drain, and Y are electrically connected in this order." Alternatively, it can be expressed as, "X is electrically connected to Y via the source and drain of the transistor, and X, transistor source, transistor drain, and Y are provided in this connection order." By specifying the order of connections in the circuit configuration using similar methods of expression as these examples, the source and drain of the transistor can be distinguished and the technical scope can be determined. Note that these methods of expression are examples and are not limited to these methods of expression. Here, X and Y are objects (e.g., devices, elements, circuits, wiring, electrodes, terminals, conductive films, or layers).

[0489] Even if independent components are shown as electrically connected in a circuit diagram, a single component may possess the functions of multiple components. For example, if part of a wiring also functions as an electrode, a single conductive film possesses the functions of both the wiring and the electrode. Therefore, in this specification, "electrically connected" includes cases where a single conductive film possesses the functions of multiple components.

[0490] Furthermore, in this specification, the term "resistive element" can refer to, for example, a circuit element or wiring having a resistance value higher than 0Ω. Therefore, in this specification, the term "resistive element" includes, for example, wiring having a resistance value, a transistor, diode, or coil through which current flows between the source and drain. Therefore, the term "resistive element" can be replaced with terms such as "resistance," "load," or "region having a resistance value." Conversely, the terms "resistance," "load," or "region having a resistance value" can be replaced with terms such as "resistive element." The resistance value can be, for example, preferably 1mΩ or more and 10Ω or less, more preferably 5mΩ or more and 5Ω or less, and even more preferably 10mΩ or more and 1Ω or less. Also, for example, 1Ω or more and 1 × 10 9 It may also be less than or equal to Ω.

[0491] Furthermore, when wiring is used as a resistive element, the resistance value of the resistive element may be determined by the length of the wiring. Alternatively, the resistive element may use a conductor with a different resistivity than the conductor used as the wiring. Or, when a semiconductor is used as a resistive element, the resistance value of the resistive element may be determined by doping the semiconductor with impurities.

[0492] Furthermore, in this specification, "capacitive element" may refer to, for example, a circuit element having a capacitance value higher than 0F, a region of wiring having a capacitance value higher than 0F, parasitic capacitance, or the gate capacitance of a transistor. Therefore, in this specification, "capacitive element" is not limited to a circuit element including a pair of electrodes and a dielectric material contained between the electrodes. "Capacitive element" includes, for example, parasitic capacitance occurring between wiring, or gate capacitance occurring between one of the source or drain of a transistor and the gate. Also, terms such as "capacitive element," "parasitic capacitance," or "gate capacitance" can be replaced with terms such as "capacitance." Conversely, the term "capacitance" can be replaced with terms such as "capacitive element," "parasitic capacitance," or "gate capacitance." Furthermore, the term "pair of electrodes" in "capacitance" can be replaced with terms such as "pair of conductors," "pair of conductive regions," or "pair of regions." The capacitance value can be, for example, 0.05fF or more and 10pF or less. Alternatively, for example, it may be set to between 1 pF and 10 μF.

[0493] Furthermore, in this specification, a transistor has three terminals called the gate (also called the gate terminal, gate region, or gate electrode), the source (also called the source terminal, source region, or source electrode), and the drain (also called the drain terminal, drain region, or drain electrode). A transistor also has a region between the drain and the source where a channel is formed (also called the channel-forming region). A transistor can pass current between the source and the drain through the channel-forming region. The channel-forming region is the region where current primarily flows. The gate is a control terminal that controls the amount of current flowing through the channel-forming region between the source and the drain. The two terminals that function as either the source or the drain are the input and output terminals of the transistor.

[0494] The two input / output terminals function as either a source or a drain, depending on the transistor's conductivity type (n-channel or p-channel) and the potential applied to its three terminals. Furthermore, the functions of the source and drain may be reversed, for example, when the direction of current changes during circuit operation. Therefore, in this specification, the terms "source" and "drain" are interchangeable. Additionally, when describing the connection relationships of a transistor, the notation "one of the source or drain" (or the first electrode or first terminal) or "the other of the source or drain" (or the second electrode or second terminal) is used.

[0495] Furthermore, depending on its structure, a transistor may have a back gate in addition to the three terminals described above. In this case, in this specification, one of the gates or back gates of the transistor may be referred to as the first gate, and the other of the gates or back gates of the transistor may be referred to as the second gate. In addition, in the same transistor, the terms "gate" and "back gate" may be interchangeable. Also, if a transistor has three or more gates, in this specification, each gate may be referred to as, for example, the first gate, the second gate, or the third gate.

[0496] In this specification, a transistor with a multi-gate structure having two or more gate electrodes can be used. In a multi-gate transistor, the channel formation regions are connected in series, resulting in a structure where multiple transistors are connected in series. Therefore, a multi-gate transistor can reduce the off-current and improve the transistor's breakdown voltage (improve reliability). In addition, when operating in the saturation region, a multi-gate transistor can obtain a voltage-current characteristic with a flat slope, where the current between the drain and source does not change much even when the voltage between the drain and source changes. A transistor with a flat voltage-current characteristic can realize an ideal current source circuit or an active load with a very high resistance value. As a result, a transistor with a flat voltage-current characteristic can realize, for example, a differential circuit or a current mirror circuit with good characteristics.

[0497] Furthermore, in this specification, when a single circuit element is shown in a circuit diagram, that circuit element may have multiple circuit elements. For example, if one resistor is shown in a circuit diagram, that resistor includes cases where two or more resistors are electrically connected in series. Also, for example, if one capacitor is shown in a circuit diagram, that capacitor includes cases where two or more capacitors are electrically connected in parallel. Also, for example, if one transistor is shown in a circuit diagram, that transistor includes cases where two or more transistors are electrically connected in series and the gates of each transistor are electrically connected to each other. Similarly, for example, if one switch is shown in a circuit diagram, that switch includes cases where two or more transistors are electrically connected in series or in parallel and the gates of each transistor are electrically connected to each other.

[0498] Furthermore, in this specification, the term "node" can be replaced with other terms such as "terminal," "wiring," "electrode," "conductive layer," "conductor," or "impurity region," depending on the circuit configuration or device structure. Also, terms such as "terminal" or "wiring" can be replaced with "node."

[0499] Furthermore, in this specification, "voltage" and "potential" may be used interchangeably as appropriate. "Voltage" refers to the potential difference from a reference potential. For example, if the reference potential is the ground potential (earth potential), then "voltage" can be replaced with "potential." Note that the ground potential does not necessarily mean 0V. Also, potential is relative. That is, when the reference potential changes, the potential applied to wiring, the potential applied to a circuit, or the potential output from a circuit also changes.

[0500] Furthermore, in this specification, the terms "high-level potential" (also referred to as "high-level potential," "H potential," or "H") or "low-level potential" (also referred to as "low-level potential," "L potential," or "L") do not mean specific potentials. For example, if two wires are both described as "functioning as wires that supply a high-level potential," the high-level potentials provided by each wire do not have to be equal. Similarly, if two wires are both described as "functioning as wires that supply a low-level potential," the low-level potentials provided by each wire do not have to be equal.

[0501] Furthermore, in this specification, "electric current" refers to the phenomenon of electric charge movement (electrical conduction). For example, the statement "electrical conduction of positively charged elements is occurring" can be rephrased as "electrical conduction of negatively charged elements is occurring in the opposite direction." Therefore, in this specification, unless otherwise specified, "electric current" refers to the phenomenon of electric charge movement (electrical conduction) associated with the movement of carriers. Carriers here include, for example, electrons, holes, anions, cations, or complex ions. Note that carriers differ depending on the system through which the current flows (for example, semiconductors, metals, electrolytes, or in a vacuum). Also, for example, the "direction of current" in wiring is the direction in which positive carriers move and is expressed as a positive current quantity. In other words, the direction in which negative carriers move is the opposite direction to the direction of current and is expressed as a negative current quantity. Therefore, in this specification, if there is no indication of the positive or negative (or direction) of the current, a statement such as "current flows from element A to element B" may be rephrased as, for example, "current flows from element B to element A." Similarly, a statement such as "current is input to element A" may be rephrased as "current is output from element A."

[0502] Furthermore, in this specification, the ordinal numbers "first," "second," or "third" are used to avoid confusion of constituent elements. Therefore, they do not limit the number of constituent elements, nor do they limit the order of the constituent elements. For example, a constituent element referred to as "first" in one embodiment of this specification may be referred to as "second" in another embodiment or claim. Also, for example, a constituent element referred to as "first" in one embodiment of this specification may be omitted in another embodiment or claim.

[0503] Furthermore, in this specification, phrases indicating arrangement, such as "above," "below," "upward," or "downward," are sometimes used for convenience to explain the positional relationships between components with reference to the drawings. The positional relationships between components also change as appropriate depending on the direction in which each component is depicted. Therefore, the phrases indicating arrangement described in this specification are not limited to those described and can be appropriately rephrased depending on the situation. For example, the expression "insulator located on the upper surface of the conductor" can be rephrased as "insulator located on the lower surface of the conductor" by rotating the orientation of the drawing by 180 degrees. Similarly, the expression "insulator located on the upper surface of the conductor" can be rephrased as "insulator located on the left (or right) side of the conductor" by rotating the orientation of the drawing by 90 degrees.

[0504] Furthermore, the terms "above" or "below" do not limit the positional relationship of the components to being directly above or below each other and in direct contact. For example, the expression "electrode B on insulating layer A" does not require that electrode B be formed in direct contact with insulating layer A, and does not exclude cases where other components are included between insulating layer A and electrode B.

[0505] Furthermore, in this specification, terms such as "row" or "column" may be used to describe the matrix-like arrangement of components and their positional relationships. The positional relationships between components change as appropriate depending on the direction in which each component is depicted. Therefore, terms such as "row" or "column" as described in this specification are not limited to these and can be appropriately rephrased depending on the situation. For example, the expression "row direction" can be rephrased as "column direction" by rotating the orientation of the diagram shown by 90 degrees.

[0506] Furthermore, in this specification, terms such as "overlapping" do not limit the state of the components, such as the stacking order. For example, the expression "electrode B overlapping insulating layer A" is not limited to a state in which electrode B is formed on top of insulating layer A. The expression "electrode B overlapping insulating layer A" does not exclude, for example, a state in which electrode B is formed below insulating layer A, or a state in which electrode B is formed to the right (or left) of insulating layer A.

[0507] Furthermore, in this specification, the terms "adjacent" or "proximity" are not limited to direct contact between components. For example, the expression "electrode B adjacent to insulating layer A" does not require that insulating layer A and electrode B be formed in direct contact, and does not exclude cases where other components are included between insulating layer A and electrode B.

[0508] Furthermore, in this specification, terms such as "film" or "layer" may be interchangeable depending on the context. For example, the term "conductive layer" may be changed to the term "conductive film." For example, the term "insulating film" may be changed to the term "insulating layer." Furthermore, terms such as "film" or "layer" may be replaced with other terms depending on the context, without using those terms. For example, the term "conductive layer" or "conductive film" may be changed to the term "conductor." Furthermore, the term "conductor" may be changed to the term "conductive layer" or "conductive film." For example, the term "insulating layer" or "insulating film" may be changed to the term "insulator." Furthermore, the term "insulator" may be changed to the term "insulating layer" or "insulating film."

[0509] Furthermore, in this specification, terms such as "electrode," "wiring," or "terminal" do not functionally limit these components. For example, "electrode" may be used as part of "wiring," and vice versa. Moreover, the terms "electrode" or "wiring" also include cases where multiple "electrodes" or "wiring" are formed as a single unit. Similarly, for example, "terminal" may be used as part of "wiring" or "electrode," and vice versa. Furthermore, the term "terminal" also includes cases where multiple "electrodes," "wiring," or "terminals" are formed as a single unit. Therefore, for example, "electrode" can be part of "wiring" or "terminal." Also, for example, "terminal" can be part of "wiring" or "electrode." In addition, terms such as "electrode," "wiring," or "terminal" may be replaced with terms such as "region."

[0510] Furthermore, in this specification, terms such as "wiring," "signal line," or "power line" may be interchangeable depending on the context. For example, the term "wiring" may be changed to the term "signal line." Similarly, the term "wiring" may be changed to the term "power line." The same applies in reverse; for example, terms such as "signal line" or "power line" may be changed to the term "wiring." Similarly, terms such as "power line" may be changed to the term "signal line." Similarly, the same applies in reverse; for example, terms such as "signal line" may be changed to the term "power line." Furthermore, the term "potential" applied to wiring may be changed to the term "signal," depending on the context. Similarly, the same applies in reverse; for example, terms such as "signal" may be changed to the term "potential."

[0511] Furthermore, in this specification, "switch" refers to a device having multiple terminals and a function to switch (select) between continuity and non-continuity between those terminals. For example, if a switch has two terminals and there is continuity between both terminals, the switch is said to be in a "conductive state" or "on state." If there is no continuity between both terminals, the switch is said to be in a "non-conductive state" or "off state." Note that switching the switch to either a continuative or non-conductive state, or maintaining either a continuative or non-conductive state, may be referred to as "controlling the continuity state."

[0512] In short, a switch is a device that controls whether or not an electric current flows. Alternatively, a switch is a device that selects and switches the path through which an electric current flows. Examples of switches include electrical switches and mechanical switches. In other words, a switch can be anything that can control an electric current, and is not limited to any particular type.

[0513] Furthermore, there are types of switches that are normally non-conductive and can become conductive by controlling the conductive state; these switches are sometimes called "A-contacts." Also, there are types of switches that are normally conductive and can become non-conductive by controlling the conductive state; these switches are sometimes called "B-contacts."

[0514] Examples of electrical switches include transistors (e.g., bipolar transistors or MOS transistors), diodes (e.g., PN diodes, PIN diodes, Schottky diodes, MIM (Metal Insulator Metal) diodes, MIS (Metal Insulator Semiconductor) diodes, or diode-connected transistors), or logic circuits combining these. Note that when a transistor is used simply as a switch, its polarity (conductivity type) is not particularly limited.

[0515] One example of a mechanical switch is a switch using MEMS (Micro-Electro-Mechanical Systems) technology. This switch has mechanically movable electrodes, and the movement of these electrodes selects between a conductive state and a non-conductive state.

[0516] In this specification, the "channel length" of a transistor means, for example, the distance between the source and drain in the region where the semiconductor (or the part of the semiconductor through which current flows when the transistor is ON) and the gate overlap in a top view of the transistor, or the distance between the source and drain in the region where the channel is formed.

[0517] Furthermore, in this specification, the "channel width" of a transistor means, for example, the length of the portion where the source and drain face each other in the region where the semiconductor (or the portion in the semiconductor through which current flows when the transistor is ON) and the gate overlap in a top view of the transistor, or the length of the portion where the source and drain face each other in the region where the channel is formed.

[0518] In this specification, terms such as "substrate," "wafer," or "die" do not functionally limit these components. For example, terms such as "substrate," "wafer," or "die" may be interchangeable depending on the context.

[0519] In this specification, "parallel" means that two lines are positioned at an angle of -10° or more and 10° or less. Therefore, the case of -5° or more and 5° or less is also included. "Approximately parallel" or "roughly parallel" means that two lines are positioned at an angle of -30° or more and 30° or less. "Perpendicular" means that two lines are positioned at an angle of 80° or more and 100° or less. Therefore, the case of 85° or more and 95° or less is also included. "Approximately perpendicular" or "roughly perpendicular" means that two lines are positioned at an angle of 60° or more and 120° or less.

[0520] In this specification, "heights match or roughly match" means that, in a cross-sectional view, the heights from a reference surface (for example, a flat surface such as the substrate surface) are equal. For example, in the manufacturing process of semiconductor devices, planarization may expose the surfaces of one or more layers. In this case, the heights of the surfaces to be planarized will be equal from the reference surface. However, depending on the processing apparatus, processing method, or material of the surface to be processed during the planarization process, the heights of the multiple layers may not be exactly equal. In this specification, this is also referred to as "heights match or roughly match." For example, if there are two layers with different heights relative to a reference surface (here, a first layer and a second layer), if the difference between the height of the top surface of the first layer and the height of the top surface of the second layer is 20 nm or less, it is also referred to as "heights match or roughly match."

[0521] In this specification, "edges coincide or roughly coincide" means that, when viewed from above, at least a portion of the contours of the stacked layers overlap. For example, this includes cases in the manufacturing process of semiconductor devices where the upper and lower layers are processed with the same mask pattern, or partially with the same mask pattern. However, strictly speaking, the contours may not overlap, and the contour of the upper layer may be located inside the contour of the lower layer, or the contour of the upper layer may be located outside the contour of the lower layer. In this specification, this is also referred to as "edges coincide or roughly coincide."

[0522] In this specification, when we refer to, for example, count values ​​and measured values, or objects, methods, and events that can be converted to count values ​​or measured values, as "identical," "same," "equal," or "uniform" (including synonyms), these terms shall include an error margin of plus or minus 20%, unless otherwise explicitly stated.

[0523] In this specification, semiconductor impurities refer to elements other than the main components constituting the semiconductor layer. For example, elements with a concentration of less than 0.1 atomic percent are impurities. The presence of impurities in a semiconductor can lead to various problems, such as increased defect level density, decreased carrier mobility, or reduced crystallinity. In the case of an oxide semiconductor, impurities that alter its properties include, for example, Group 1, Group 2, Group 13, Group 14, Group 15 elements, or transition metals other than the main components of the oxide semiconductor. In particular, examples include hydrogen (also found in water), lithium, sodium, silicon, boron, phosphorus, carbon, or nitrogen. In oxide semiconductors, for example, the inclusion of impurities can lead to oxygen vacancies (V) in the oxide semiconductor. O (Also known as an oxygen vacancy) may form.

[0524] In this specification, "metal oxide" refers to an oxide of a metal in a broad sense. Metal oxides are classified into, for example, oxide insulators, oxide conductors (including transparent oxide conductors), or oxide semiconductors (also called oxide semiconductors or simply OS). For example, when a metal oxide is used in the semiconductor layer of a transistor, the metal oxide may be referred to as an oxide semiconductor. In other words, when a metal oxide is used to constitute the channel-forming region of a transistor having at least one of amplification, rectification, and switching functions, the metal oxide can be referred to as a metal oxide semiconductor. Furthermore, the term "OS transistor" can be replaced with "a transistor having a metal oxide or oxide semiconductor."

[0525] Furthermore, in this specification, metal oxides containing nitrogen may also be collectively referred to as metal oxides. Additionally, metal oxides containing nitrogen may be called metal oxynitrides.

[0526] Furthermore, in drawings and other illustrations relating to this specification, arrows indicating the X, Y, and Z directions may be included. In this specification, the "X direction" is the direction along the X-axis, and unless explicitly stated, the forward and reverse directions may not be distinguished. The same applies to the "Y direction" and "Z direction". Also, the X, Y, and Z directions are directions that intersect each other. More specifically, the X, Y, and Z directions are directions that are orthogonal to each other. In this specification, one of the X, Y, or Z directions may be referred to as the "first direction" or "first direction". Another may be referred to as the "second direction" or "second direction". The remaining one may be referred to as the "third direction" or "third direction". [Explanation of Symbols]

[0527] 100 Semiconductor Equipment 101 State Control Unit 102 CPU cores 103 Register section 104 Arithmetic section 105 Register Bank 106 General-purpose registers 110 registers 110A Semiconductor Equipment 120 scan flip-flops 121 Selector 122 Flip-flops 123 Transistors 130A Data Hold Circuit 131 Memory Circuit 171 circuit boards 173 Electrode 174 Electrode 175 plug 180 Die BK signal RE signal SE signal CLK signal D terminal SD terminal Q terminal Df Input Terminal Qf output terminal SD_IN terminal S101 Step S103 Step S104 Step S105 Step S106 Step S107 Step S108 Step S109 Step S110 Step S121 Step S122 Step S123 Step S124 Step S125 Step S131 Step S1512 Step S1513 Step S1522 Step S1523 Step S1532 Step S1533 Step S161 Step S1711 Step S1712 Step S1721 Step S1722 Step S1731 Step S1732 Step S181 Step T1 time T2 time T3 time T4 time T5 time 110Aa Semiconductor Equipment 130Aa Data Hold Circuit 131a Memory Circuit 13A Inverter 13b Inverter 132 Clocked Inverter 133 Inverter 134 Clocked Inverter 135 Inverter SN node T11 Period T12 period T13 Period T14 Period T15 Period T16 period T17 Period T18 period D1 Data D2 Data D3 data D4 Data D5 Data D6 Data D7 Data 110Ab Semiconductor equipment 124 Inverter 125 Pre-charge circuit 126 SenseAmp 130Ab Data Hold Circuit 131b Memory Circuit 136 transistors 137 transistors 138 transistors 139 transistors PC_EN signal QB terminal BLb node BLBb node 110B Semiconductor Equipment 130B Data Hold Circuit 182 layers MS1 transistor MS2 transistor SW signal S202 Step S205 Step S207 Step S209 Step S241 Step S242 Step S243 Step S244 Step S245 Step S246 Step S2511 Step S2521 Step S2531 Step 110Ba Semiconductor 130Ba data retention circuit 311 circuit board 500 transistors 550 transistors 710 Semiconductor Equipment 733 Electrode 735 Semiconductor Equipment 5626 Semiconductor Equipment 5627 Semiconductor equipment 5628 Semiconductor equipment

Claims

1. It comprises a flip-flop, a first memory circuit, a second memory circuit, and a state control unit. The aforementioned flip-flop is formed on a substrate, The first memory circuit is formed on the first die on the substrate, The second memory circuit is formed on the second die above the first die, The flip-flop is electrically connected to the first memory circuit and the second memory circuit, The aforementioned flip-flop has the function of holding first data corresponding to the task being executed, The first memory circuit has the function of holding the first data when a task is switched. The second memory circuit has a function to retain the first data if, upon switching of the task, the first memory circuit already holds second data different from the first data. The state control unit has a function to control the first and second memory circuits to hold data in order from the one closest to the flip-flop, The first die comprises a first transistor, The aforementioned second die includes a second transistor, The first transistor has the function of making the flip-flop and the first memory circuit non-conductive when no data is held in the first memory circuit and the second memory circuit, respectively. The second transistor has the function of making the connection between the flip-flop and the second memory circuit non-conductive when no data is held in the second memory circuit. Semiconductor equipment.

2. In claim 1, The substrate is equipped with a first electrode, The first die comprises a second electrode formed on one side of the first die and a third electrode formed on the other side of the first die. The second die is equipped with a fourth electrode, The first electrode is joined to the second electrode, The third electrode is joined to the fourth electrode. Semiconductor equipment.

3. In claim 1, The first transistor and the second transistor are transistors that include an oxide semiconductor in the channel formation region. Semiconductor equipment.

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