Drive unit

Abstract

To determine an ON failure and a normality in a lower-stage driving element.SOLUTION: A driving apparatus for causing a driving current to flow to a prescribed load, includes: an upper-stage driving element that is disposed between a power source and one end of the load; a lower-stage driving element that is disposed between the earth and the other end of the load; a control circuit that drives the upper-stage driving element by supplying an upper-stage driving pulse thereto, and controls the lower-stage driving element by supplying a lower-stage driving pulse thereto; and failure detection means that detects a failure in the lower-stage driving element on the basis of a voltage at the other end. The control circuit generates an upper-stage driving pulse and a lower-stage driving pulse for failure diagnosis such that transition timings of the driving pulses are deviated from each other by a prescribed time. The failure detection means detects a failure in the lower-stage driving element on the basis of the voltage in a state where the upper-stage driving pulse for failure diagnosis is supplied to the upper-stage driving element while the lower-stage driving pulse for failure diagnosis is supplied to the lower-stage driving element.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a drive device.

Background Art

[0002] Patent Document 1 below discloses a brake drive control circuit. This brake drive control circuit supplies / shuts off the drive current to the brake by turning on / off the switching transistors provided at both ends of the brake. That is, this brake drive control circuit provides one switching transistor between the upper stage side of the brake, that is, between one end of the brake and the 24V power supply VB, and the other switching transistor between the lower stage side of the brake, that is, between the other end of the brake and the ground, and conducts / shuts off the connection between one end of the brake and the 24V power supply VB by one switching transistor and conducts / shuts off the connection between the other end of the brake and the ground by the other switching transistor.

Prior Art Document

Patent Document

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] By the way, in the above background art, the presence or absence of the voltage applied to the load is detected by the voltage detection means connected in parallel with the brake (load), thereby detecting the failure of each switching transistor (drive element). However, such a failure detection method has a problem that it is impossible to discriminate between the ON failure and the normal state of the other switching transistor (lower stage drive element).

[0005] This invention has been made in view of the circumstances described above, and aims to provide a drive device capable of distinguishing between an ON failure and a normal operation of the lower drive element. [Means for solving the problem]

[0006] To achieve the above objective, Embodiment 1 of the present invention provides a drive device for supplying a drive current to a predetermined load, comprising: an upper drive element provided between a power source and one end of the load; a lower drive element provided between ground and the other end of the load; a control circuit that drives the upper drive element by supplying an upper drive pulse and controls the lower drive element by supplying a lower drive pulse; and a fault detection means for detecting a fault in the lower drive element based on the voltage at the other end, wherein the control circuit generates, as transition timings, an upper drive pulse for fault diagnosis that transitions from a low level to a high level at a first time, and a lower drive pulse for fault diagnosis that transitions from a low level to a high level at a second time delayed by a predetermined time from the first time, and the fault detection means supplies the upper drive pulse for fault diagnosis to the upper drive element. A first timing based on the first time, The lower stage drive pulse for fault diagnosis is supplied to the lower stage drive element. Based on the second timing based on the second time, according to the first timing Voltage at the other end Based on the first state and the second state of the voltage at the other end corresponding to the second timing, the first state From low level to high level This is a change to the second state From Hi (high level) to Lo (low level) If the change is to the state described above, the lower drive element is functioning normally, and if there is no change in the first state and the second state, The lower drive element is ON breakdown It was determined that We will adopt the method of diagnosis.

[0007] According to this embodiment 1 of the drive device, it is possible to provide a drive device that can distinguish between an ON failure and a normal state of the lower drive element that drives the load.

[0008] A second aspect of the present invention further comprises a second fault detection means for detecting a fault in the upper drive element based on the voltage at one end of the drive device according to the first aspect of the present invention, wherein the control circuit generates the upper drive pulse and the lower drive pulse for fault diagnosis with synchronized transition timings, and the second fault detection means detects a fault in the upper drive element based on the voltage at one end when the upper drive pulse for fault diagnosis with synchronized transition timings is supplied to the upper drive element and the lower drive pulse for fault diagnosis is supplied to the lower drive element.

[0009] According to this embodiment 2 of the drive device, in addition to distinguishing between an ON failure and normal operation of the lower drive element that drives the load, it is possible to distinguish between an ON failure and normal operation of the upper drive element that drives the load together with the lower drive element.

[0010] A third aspect of the present invention is a drive device according to aspect 1 or aspect 2, wherein the fault detection means determines that a change has occurred when the voltage, which is discretely acquired on the time axis, continuously exceeds a predetermined voltage threshold for a predetermined number of times.

[0011] According to the drive device of this embodiment 3, when determining whether the lower drive element is ON or normal, it is possible to more accurately distinguish between an ON failure and a normal operation of the lower drive element that drives the load.

[0012] Aspect 4 of the present invention employs a means in which, in any one of the driving devices of aspects 1 to 3, the upper driving element is a switching transistor that changes from an OFF state to an ON state when the upper driving pulse transitions from a Lo (low) level to a Hi (high) level, the lower driving element is a switching transistor that changes from an OFF state to an ON state when the lower driving pulse transitions from a Lo (low) level to a Hi (high) level, and the transition timing is a transition from a Lo (low) level to a Hi (high) level.

[0013] According to the drive device of Mode 4 as described above, when the transition timing is a transition from the Lo (low) level to the Hi (high) level, it is possible to discriminate between an ON failure and normal operation of the lower-stage drive element that drives the load.

[0014] In Mode 5 of the present invention, in any one of the drive devices of Modes 1 to 4, the means is adopted that the load is an electromagnetic brake.

[0015] According to the drive device of Mode 5 as described above, it is possible to discriminate between an ON failure and normal operation of the lower-stage drive element in the case where the electromagnetic brake is used as the load.

Advantages of the Invention

[0016] According to the present invention, it is possible to provide a drive device capable of discriminating between an ON failure and normal operation of a lower-stage drive element.

Brief Description of the Drawings

[0017] [Figure 1] It is a circuit diagram showing the configuration of a drive device A according to an embodiment of the present invention. [Figure 2] It is a first timing chart showing the operation of a drive device A according to an embodiment of the present invention. [Figure 3] It is a reference timing chart in an embodiment of the present invention. [Figure 4] It is a second timing chart showing the operation of a drive device A according to an embodiment of the present invention.

Modes for Carrying Out the Invention

[0018] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. As shown in FIG. 1, the drive device A according to the present embodiment drives a drive motor M and an electromagnetic brake L as drive targets. This drive device A is provided in an electric vehicle such as an electric transport cart and drives the drive motor M and the electromagnetic brake L.

[0019] The drive motor M is the first drive target in the drive device A, and generates driving power for the electric vehicle by being rotationally driven by the drive device A. That is, this drive motor M is the power source of the electric vehicle. On the other hand, the electromagnetic brake L is the second drive target in the drive device A, and is a braking device that decelerates or stops (halts) the electric vehicle. This electromagnetic brake L is an inductive load (coil) as shown in the figure, and corresponds to the load of the present invention.

[0020] The drive device A is actually configured as a printed wiring board on which a large number of electronic components are mounted, and includes a plurality of connection terminals for electrically connecting to external components such as the drive motor M and the electromagnetic brake L. That is, the drive device A is connected to external components such as the drive motor M, the electromagnetic brake L, the upper ECU (Electronic Control Unit), and the LED (Light Emitting Diode) via the connection terminals.

[0021] Such a drive device A includes an upper switch 1, a lower switch 2, a protection diode 3, an upper voltage detection circuit 4, a lower voltage detection circuit 5, a CPU 6, an upper drive circuit 7, a lower drive circuit 8, an inverter 9, and an LED drive circuit 10 as shown in the figure.

[0022] One input / output terminal of the upper switch 1 is connected to the drive source voltage VB, the other input / output terminal is connected to one end of the electromagnetic brake L, the cathode terminal of the protection diode 3, and the input terminal of the upper voltage detection circuit 4, and the control terminal is connected to the output terminal of the upper drive circuit 7. This upper switch 1 is a switching transistor whose conduction / non-conduction (i.e., ON / OFF) between one input / output terminal and the other input / output terminal is set by an upper drive pulse input from the output terminal of the upper drive circuit 7 to the control terminal. Note that the upper switch 1 corresponds to the upper drive element of the present invention.

[0023] The lower switch 2 has one input / output terminal connected to the other terminal of the electromagnetic brake L, the anode terminal of the protection diode 3, and the input terminal of the lower voltage detection circuit 5, the other input / output terminal connected to earth (grounded), and the control terminal connected to the output terminal of the lower drive circuit 8. This lower switch 2 is a switching transistor in which conduction / non-conductivity (i.e., ON / OFF) between one input / output terminal and the other input / output terminal is set by a lower drive pulse input from the output terminal of the lower drive circuit 8 to the control terminal. Note that the lower switch 2 corresponds to the lower drive element of the present invention.

[0024] The protection diode 3 has its cathode terminal connected to one end of the electromagnetic brake L, and its anode terminal connected to the other end of the electromagnetic brake L. In other words, the protection diode 3 is connected in parallel with the electromagnetic brake L, and protects the electromagnetic brake L from overvoltage by preventing overvoltage caused by disturbances from being applied to the electromagnetic brake L.

[0025] The upper voltage detection circuit 4 has its input terminal connected to the other input / output terminal of the upper switch 1, one end of the electromagnetic brake L, and the cathode terminal of the protection diode 3, and its output terminal connected to the first input terminal of the CPU 6. The upper voltage detection circuit 4 detects the voltage applied from the drive power source VB to one end of the electromagnetic brake L via the upper switch 1, and outputs the voltage at that end as the upper detection voltage to the CPU 6.

[0026] The lower voltage detection circuit 5 has its input terminal connected to one input / output terminal of the lower switch 1, the other terminal of the electromagnetic brake L, and the anode terminal of the protection diode 3, and its output terminal connected to the second input terminal of the CPU 6. The lower voltage detection circuit 5 detects the voltage applied from the drive power source VB to the other terminal of the electromagnetic brake L via the upper switch 1 and the electromagnetic brake L, and outputs it to the CPU 6 as the lower detection voltage.

[0027] The CPU 6 is a software control device that controls the upper drive circuit 7, lower drive circuit 8, inverter 9, and LED drive circuit 10 based on a control program pre-stored in its internal memory, the upper detection voltage input from the upper voltage detection circuit 4, the lower detection voltage input from the lower voltage detection circuit 5, and control commands input from the higher-level ECU.

[0028] In other words, the CPU 6 is equipped with at least internal memory, an arithmetic unit for executing control programs, and input / output circuits for exchanging signals with an upper voltage detection circuit 4, a lower voltage detection circuit 5, a higher-level ECU, an upper drive circuit 7, a lower drive circuit 8, an inverter 9, and an LED drive circuit 10 as hardware resources, and performs the desired control function through the cooperation of these hardware resources and the control program, which is a software resource.

[0029] The upper stage drive circuit 7 has its input terminal connected to the first output terminal of the CPU 6, and its output terminal connected to the control terminal of the upper stage switch 1. The upper stage drive circuit 7 generates an upper stage drive pulse based on the upper stage control signal input from the CPU 6 and outputs the upper stage drive pulse to the control terminal of the upper stage switch 1.

[0030] The lower stage drive circuit 8 has its input terminal connected to the second output terminal of the CPU 6, and its output terminal connected to the control terminal of the lower stage switch 2. The lower stage drive circuit 8 generates a lower stage drive pulse based on the upper and lower stage signals input from the CPU 6, and outputs the lower stage drive pulse to the control terminal of the lower stage switch 2.

[0031] Here, the CPU 6, upper drive circuit 7, and lower drive circuit 8 described above correspond to the control circuit of the present invention. That is, the CPU 6, upper drive circuit 7, and lower drive circuit 8 drive the upper switch 1 (upper drive element) by supplying upper drive pulses based on the upper control signal, and control the lower switch 2 (lower drive element) by supplying lower drive pulses based on the lower control signal.

[0032] Furthermore, when the CPU 6, upper drive circuit 7, and lower drive circuit 8 detect a failure in the lower switch 2 (lower drive element), they generate upper and lower drive pulses for fault diagnosis with a transition timing shifted by a predetermined time td, outputting the upper drive pulse for fault diagnosis to the upper switch 1 and the lower drive pulse to the lower switch 2.

[0033] On the other hand, the lower voltage detection circuit 5 and CPU 6 described above correspond to the fault detection means of the present invention. As will be described in detail later, the lower voltage detection circuit 5 and CPU 6 detect (determine) an ON fault of the lower switch 2 (lower drive element) based on the voltage (lower detection voltage) at the other end of the electromagnetic brake L (load).

[0034] In other words, when detecting a fault in the lower switch 2, the lower voltage detection circuit 5 and CPU 6 detect an ON fault in the lower switch 2 based on the lower detection voltage when an upper drive pulse for fault diagnosis is supplied to the upper switch 1 and a lower drive pulse for fault diagnosis is supplied to the lower switch 2.

[0035] Furthermore, the upper voltage detection circuit 4 and CPU 6 in this embodiment correspond to the second fault detection means in the present invention. That is, the upper voltage detection circuit 4 and CPU 6 detect an ON fault of the upper switch 1 (upper drive element). As will be described in detail later, the upper voltage detection circuit 4 and CPU 6 detect (determine) an ON fault of the upper switch 1 (upper drive element) based on the voltage (upper detection voltage) at one end of the electromagnetic brake L (load).

[0036] The inverter 9 is a three-phase inverter equipped with a pair of U-phase input terminals, a pair of V-phase input terminals, and a pair of W-phase input terminals, as well as a U-phase output terminal, a V-phase output terminal, and a W-phase output terminal, and three switching legs corresponding to the U-phase, V-phase, and W-phase (U-phase switching leg, V-phase switching leg, and W-phase switching leg).

[0037] The inverter 9 has its U-phase input terminal connected to the U-phase output of the CPU 6, its V-phase input terminal connected to the V-phase output of the CPU 6, and its W-phase input terminal connected to the W-phase output of the CPU 6. Furthermore, the inverter 9 has its U-phase output terminal connected to the U-phase winding of the drive motor M, its V-phase output terminal connected to the V-phase winding of the drive motor M, and its W-phase output terminal connected to the W-phase winding of the drive motor M.

[0038] In this inverter 9, the U-phase switching legs, V-phase switching legs, and W-phase switching legs are controlled based on a pair of U-phase control signals, a pair of V-phase control signals, and a pair of W-phase control signals input from the CPU 6 to a pair of U-phase input terminals, a pair of V-phase input terminals, and a pair of W-phase input terminals. This controls the DC power input from the drive power source VB, and the inverter 9 outputs this three-phase AC power to the drive motor M from the U-phase output terminals, V-phase output terminals, and W-phase output terminals.

[0039] The LED driver circuit 10 has its input terminal connected to the third output terminal of the CPU 6 and its output terminal connected to the anode terminal of the LED. The LED driver circuit 10 amplifies the notification signal input from the CPU 6 and supplies it to the LED. The notification signal is a pulse signal indicating the operating status of the drive device A, such as a malfunction of the upper switch 1 and the lower switch 2. The LED notifies the outside of the operating status of the drive device A by emitting light based on the notification current input from the LED driver circuit 10.

[0040] The higher-level ECU's output terminals are connected to a pair of higher-level input terminals provided on the CPU 6. The higher-level ECU is the control device that comprehensively controls the electric vehicle, and is a software control device in which hardware resources and software resources work together. This higher-level ECU outputs higher-level control commands, such as driving instructions for the electric vehicle, to the CPU 6.

[0041] Next, the operation of the drive device A according to this embodiment will be described in detail with reference to Figures 2 and 3.

[0042] As described above, this drive unit A drives the drive motor M and the electromagnetic brake L, and in normal operation it drives the drive motor M and the electromagnetic brake L as follows: That is, the drive unit A drives the electric vehicle by driving the drive motor M based on a driving command input from the higher-level ECU. In addition, the drive unit A decelerates or stops (brings the electric vehicle to a halt) by driving the electromagnetic brake L based on a braking command input from the higher-level ECU.

[0043] In response to such normal operation, the drive unit A periodically or when predetermined conditions are met, performs fault diagnosis of the upper switch 1 and lower switch 2 using the upper voltage detection circuit 4 and the lower voltage detection circuit 5. Specifically, the CPU 6 generates an upper control signal for fault diagnosis and outputs it to the upper drive circuit 7, and generates a lower control signal and outputs it to the lower drive circuit 8, when the electric vehicle is at least stationary.

[0044] Figure 2(a) is a timing chart of drive unit A when both the upper switch 1 and the lower switch 2 are functioning normally. As shown in Figure 2(a), the upper drive circuit 7 generates an upper drive pulse based on the upper control signal and outputs it to the upper switch 1. On the other hand, as shown in Figure 2(a), the lower drive circuit 8 generates a lower drive pulse based on the lower control signal and outputs it to the lower switch 2.

[0045] Here, the upper drive pulse is a pulse signal that transitions from a low level to a high level at time t1, as shown in the figure. In contrast, the lower drive pulse is a pulse signal that transitions from a low level to a high level at time t2, which is delayed by a time width td (a predetermined time) from time t1, as shown in the figure.

[0046] As shown in the figure, the upper switch 1 changes state from OFF (off state) to ON (conducting state) at time t1. That is, the upper switch 1 changes state from OFF (off state) to ON (conducting state) in synchronization with the transition of the upper drive pulse from Lo (low) level to Hi (high) level, without malfunction and under normal conditions.

[0047] In contrast, the lower switch 2 changes state from OFF (off state) to ON (conducting state) at time t2, which is delayed by a time width td from time t1. That is, the lower switch 2 changes state from OFF (off state) to ON (conducting state) in a normal state without failure, in synchronization with the transition of the lower drive pulse from Lo (low) level to Hi (high) level.

[0048] When the upper switch 1 and lower switch 2 are functioning normally, the lower detection voltage of the lower voltage detection circuit 5 transitions from a low level to a high level at time t1, and from a high level to a low level at time t2. In other words, these changes in the lower detection voltage at time t1 and time t2 indicate the normal operation of the upper switch 1 and lower switch 2.

[0049] The CPU 6 outputs an upper control signal to the upper drive circuit 7 and a lower control signal to the lower drive circuit 8, and determines the normality of the upper switch 1 and lower switch 2 based on the change in the lower detection voltage. As shown in Figure 2(a), the drive current is supplied to the electromagnetic brake L at time t2 when both the upper switch 1 and lower switch 2 are in the ON state (conducting state).

[0050] Specifically, the CPU 6 controls the upper drive circuit 7 to output an upper drive pulse that transitions from a low level to a high level to the upper switch 1 at time t1, and controls the lower drive circuit 8 to output a lower drive pulse that transitions from a low level to a high level to the lower switch 2 at time t2. The CPU 6 determines the normality of the upper switch 1 and the lower switch 2 by evaluating the change in the lower detection voltage input from the lower voltage detection circuit 5 when the CPU 6 controls the upper drive circuit 7 to output an upper drive pulse that transitions from a low level to a high level to the lower switch 2 at time t2.

[0051] Figure 2(b) shows the timing chart of drive unit A when the upper switch 1 is functioning normally but the lower switch 2 is malfunctioning and ON. In this case, the upper drive circuit 7 generates an upper drive pulse based on the upper control signal and outputs it to the upper switch 1, and the lower drive circuit 8 generates a lower drive pulse based on the lower control signal and outputs it to the lower switch 2.

[0052] As shown in the diagram, the upper switch 1 changes state from OFF (off state) to ON (conductive state) at time t1 in synchronization with the upper drive pulse. In contrast, the lower switch 2 is ON, so it remains in the ON state without changing state due to the lower drive pulse.

[0053] As a result, the lower detection voltage of the lower voltage detection circuit 5 remains at a low level without transitioning from a low level to a high level. This lower detection voltage is clearly different from the change that occurs when the upper switch 1 and lower switch 2 are functioning normally.

[0054] In other words, the CPU 6 controls the upper stage drive circuit 7 to output an upper stage drive pulse that transitions from a low level to a high level to the upper stage switch 1 at time t1, and controls the lower stage drive circuit 8 to output a lower stage drive pulse that transitions from a low level to a high level to the lower stage switch 2 at time t2. If the lower stage detection voltage remains at a low level and does not change, the CPU 6 determines that the lower stage switch 2 is ON faulty.

[0055] The drive device A according to this embodiment supplies a drive current to an electromagnetic brake L (load) and comprises an upper switch 1 (upper drive element) provided between a power source and one end of the electromagnetic brake L (load), a lower switch 2 (lower drive element) provided between ground and the other end of the electromagnetic brake L (load), a control circuit (upper voltage detection circuit 4, lower voltage detection circuit 5 and CPU 6) that drives the upper switch 1 (upper drive element) by supplying an upper drive pulse and controls the lower switch 2 (lower drive element) by supplying a lower drive pulse, and fault detection means (lower voltage detection circuit 5 and CPU 6) that detects a failure of at least the lower switch 2 (lower drive element) based on the voltage at least at the other end.

[0056] Furthermore, the control circuit generates upper and lower drive pulses for fault diagnosis with transition timings shifted by a predetermined time, and the fault detection means detects a fault in the lower switch 2 (lower drive element) based on the voltage when the upper drive pulse for fault diagnosis is supplied to the upper drive element and the lower drive pulse for fault diagnosis is supplied to the lower drive element. According to this embodiment, it is possible to provide a drive device A that can distinguish between an ON fault and a normal state of the lower switch 2 (lower drive element).

[0057] Here, with reference to Figure 3, the reference operation of the drive device A according to this embodiment will be described. In this reference operation, the upper drive pulse and the lower drive pulse transition from a Lo (low) level to a Hi (high) level at the same timing, and it is an example of operation in which it is not possible to distinguish between an ON failure and a normal state of the lower switch 2 (lower drive element).

[0058] In other words, when the upper and lower drive pulses transition synchronously from a low level to a high level, there is no difference in the lower detection voltage between the normal operation of the upper switch 1 and lower switch 2 shown in Figure 3(a) and the ON fault of the lower switch 2 shown in Figure 3(b). Therefore, this reference operation cannot distinguish between an ON fault and a normal operation of the lower switch 2 (lower drive element).

[0059] Next, with reference to Figure 4, the detection (determination) operation for an ON failure of the upper switch 1 (upper drive element) in the drive unit A will be explained. Figure 4(a) shows the detection (determination) operation when both the upper switch 1 and the lower switch 2 are functioning normally, and Figure 4(b) shows the detection (determination) operation when the upper switch 1 is in an ON state.

[0060] When detecting an ON fault in the upper switch 1, the CPU 6 outputs an upper control signal to the upper drive circuit 7 and a lower control signal to the lower drive circuit 8. In this case, the upper and lower control signals generate upper and lower drive pulses with synchronized transition timings from a low level to a high level.

[0061] Specifically, the upper drive circuit 7 generates an upper drive pulse that transitions from a low level to a high level at time t3 based on the upper control signal, as shown in the figure, and outputs it to the upper switch 1. On the other hand, the lower drive circuit 8 generates a lower drive pulse that transitions from a low level to a high level in synchronization with the upper drive pulse, based on the lower control signal, and outputs it to the lower switch 2.

[0062] When the upper switch 1 is functioning normally without any ON failures, it changes state from the OFF state (cutoff state) to the ON state (conductive state) at time t3 in synchronization with the upper drive pulse, as shown in the figure. Similarly, when the lower switch 2 is functioning normally without any ON failures, it changes state from the OFF state (cutoff state) to the ON state (conductive state) at time t3 in synchronization with the lower drive pulse, as shown in the figure.

[0063] As a result, the upper detection voltage of the upper voltage detection circuit 4 changes from a low level to a high level at time t3. In contrast, the lower detection voltage of the lower voltage detection circuit 5 remains at a low level without changing if the upper switch 1 and lower switch 2 are functioning normally.

[0064] In contrast to this normal operation, if the upper switch 1 is ON due to a malfunction, the upper switch 1 will remain ON regardless of the upper drive pulse, as shown in Figure 4(b). Therefore, the upper detection voltage of the upper voltage detection circuit 4 will remain at a Hi (high) level regardless of the upper drive pulse. This upper detection voltage is clearly different from that when the upper switch 1 and lower switch 2 are functioning normally.

[0065] In other words, at time t0, the CPU 6 detects (determines) an ON fault in the upper switch 1 based on the fact that the upper detection voltage has transitioned to a Hi level.

[0066] Here, the CPU 6 determines that the upper detection voltage has changed if the upper detection voltage, which is acquired discretely on the time axis, continuously exceeds a predetermined voltage threshold for a predetermined number of times n. For example, the CPU 6 samples the upper detection voltage (analog signal) with a predetermined sampling period tcpu and acquires it as upper detection data (digital signal) obtained by A / D conversion of the upper detection voltage.

[0067] The CPU 6 detects (determines) an ON failure of the upper switch 1 if, after time t0 when the electromagnetic brake command signal input from the higher-level ECU transitions from braking to release, the upper detection data continuously exceeds a predetermined voltage threshold Vr for a predetermined number of times n (for example, 4 times).

[0068] The predetermined number n is not a fixed value, but is set variably according to the acquisition status of the upper detection data. For example, if the fourth detection data does not exceed the voltage threshold Vr due to the effect of a disturbance, the CPU 6 changes the predetermined number n from 4 to, for example, 8 (double), and determines whether the detection data exceeds the voltage threshold Vr for 8 consecutive times from the 5th to the 12th time. The CPU 6 then detects (determines) an ON failure of the upper switch 1 if the detection data exceeds the voltage threshold Vr for 8 consecutive times.

[0069] Furthermore, the predetermined time td mentioned above is set based on the following formula (1), which consists, for example, the sampling period tcpu, a predetermined number of steps n, and a constant a. The constant a is the maximum value of the A / D conversion time in CPU6 (a catalog intrinsic value of CPU6), and is an extremely small value compared to the sampling period tcpu. td = tcpu × n + a (1)

[0070] The drive device A according to this embodiment further includes a second fault detection means (upper voltage detection circuit 4 and CPU 6) that detects an ON fault of the upper switch 1 (upper drive element) based on the voltage (upper detection voltage) at one end of the electromagnetic brake L (load). The control circuit (upper voltage detection circuit 4, lower voltage detection circuit 5 and CPU 6) generates upper drive pulses and lower drive pulses for fault diagnosis with synchronized transition timings. The second fault detection means detects an ON fault of the lower switch 2 (lower drive element) based on the voltage (upper detection voltage) at the aforementioned end when the upper drive pulses for fault diagnosis with synchronized transition timings are supplied to the upper switch 1 (upper drive element) and the lower drive pulses for fault diagnosis are supplied to the lower switch 2 (lower drive element).

[0071] According to this embodiment, it is possible to provide a drive device A that can distinguish between an ON failure and a normal state of the lower switch 2 (lower drive element), as well as an ON failure and a normal state of the upper switch 1 (upper drive element).

[0072] Furthermore, according to this embodiment, it is possible to contribute to the promotion of carbon-free technology in the field of drive systems and electric vehicles equipped with such drive systems, thereby contributing to the Sustainable Development Goals (SDGs) led by the United Nations.

[0073] The present invention is not limited to the embodiments described above, and for example, the following modifications are possible. (1) In the above embodiment, an electromagnetic brake L was used as the load, but the present invention is not limited thereto. The present invention is also applicable to inductive loads other than electromagnetic brakes L or loads other than inductive loads.

[0074] (2) In the above embodiment, an upper switch 1 (switching transistor) is used as the upper drive element and a lower switch 2 (switching transistor) is used as the lower drive element, but the present invention is not limited thereto.

[0075] (3) In the above embodiment, the control circuit is configured by the upper voltage detection circuit 4, the lower voltage detection circuit 5 and the CPU 6, but the present invention is not limited thereto.

[0076] (4) In the above embodiment, the fault detection means is configured by the lower voltage detection circuit 5 and the CPU 6, but the present invention is not limited thereto. [Explanation of Symbols]

[0077] A...Drive unit, L...Electromagnetic brake (load), M...Drive motor, 1...Upper switch (upper drive element), 2...Lower switch (lower drive element), 3...Protection diode, 4...Upper voltage detection circuit, 5...Lower voltage detection circuit, 6...CPU, 7...Upper drive circuit, 8...Lower drive circuit, 9...Inverter, 10...LED drive circuit

Claims

1. A drive device that supplies drive current to a predetermined load, An upper drive element is provided between the power supply and one end of the load, A lower drive element is provided between the earth and the other end of the load, A control circuit that drives the upper drive element by supplying an upper drive pulse and controls the lower drive element by supplying a lower drive pulse, The system includes fault detection means for detecting a fault in the lower drive element based on the voltage at the other end, The control circuit generates, as transition timings, an upper-stage drive pulse for fault diagnosis that transitions from a low level to a high level at a first time, and a lower-stage drive pulse for fault diagnosis that transitions from a low level to a high level at a second time, delayed by a predetermined time from the first time. The fault detection means determines and diagnoses an ON fault in the lower drive element based on a first timing based on a first time when the upper drive pulse for fault diagnosis is supplied to the upper drive element, and a second timing based on a second time when the lower drive pulse for fault diagnosis is supplied to the lower drive element, and determines a first state of voltage at the other end according to the first timing and a second state of voltage at the other end according to the second timing, and determines that the lower drive element is normal if the first state is a change from a Lo (low) level to a Hi (high) level and the second state is a change from a Hi (high) level to a Lo (low) level, and if there is no change in the first state and the second state, the lower drive element is ON fault.

2. The system further comprises a second fault detection means for detecting a fault in the upper drive element based on the voltage at one end, The control circuit generates the upper and lower drive pulses for fault diagnosis, whose transition timings are synchronized. The drive device according to claim 1, wherein the second fault detection means detects a fault in the upper drive element based on the voltage at one end when the upper drive pulse for fault diagnosis, whose transition timing is synchronized, is supplied to the upper drive element and the lower drive pulse for fault diagnosis is supplied to the lower drive element.

3. The drive device according to claim 1 or 2, wherein the fault detection means determines that a change has occurred when the voltage, which is discretely acquired on the time axis, continuously exceeds a predetermined voltage threshold for a predetermined number of times.

4. The aforementioned upper-stage drive element is a switching transistor that changes from an OFF state to an ON state when the upper-stage drive pulse transitions from a Lo (low) level to a Hi (high) level. The lower drive element is a switching transistor that changes from an OFF state to an ON state when the lower drive pulse transitions from a Lo (low) level to a Hi (high) level. The drive device according to claim 1 or 2, wherein the transition timing is a transition from a low level to a high level.

5. The drive device according to claim 1 or 2, wherein the load is an electromagnetic brake.

Images