Semiconductor equipment

Abstract

This semiconductor device includes: a chip having a first principal surface on one side and a second principal surface on the other side; a pn junction formed inside the chip so as to extend along the first principal surface; a device region provided on the first principal surface; a first trench structure which is formed in the first principal surface so as to penetrate through the pn junction, and which demarcates the device region in the first principal surface; and a second trench structure which is formed in the first principal surface so as to penetrate through the pn junction, and which demarcates the device region in a region that is more on the device region side than the first trench structure.

Description

[Technical Field]

[0001] This application corresponds to Japanese Patent Application Nos. 2021-005307, 2021-005308, 2021-005309, and 2021-005310, all filed with the Japan Patent Office on January 15, 2021, and the full disclosures of these applications are incorporated herein by reference. The present invention relates to a semiconductor device. [Background technology]

[0002] Patent Document 1 discloses a semiconductor device comprising a p-type region, a first p-epitaxial region, an n-type embedded region, a second p-epitaxial region, and a DTI structure (deep trench isolation structure). The first p-type epitaxial layer is formed on the p-type region. The n-type embedded region is formed on the first p-epitaxial region. The second p-epitaxial region is formed on the n-type embedded region. The DTI structure surrounds the formation region of a high-voltage lateral MOS transistor in a plan view. The DTI structure penetrates the second p-epitaxial region, the n-type embedded region, and the first p-epitaxial region to reach the p-type region. [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2015-122543 [Overview of the Initiative] [Problems that the invention aims to solve]

[0004] One embodiment provides a semiconductor device that can improve voltage resistance. [Means for solving the problem]

[0005] One embodiment provides a semiconductor device comprising: a chip having a first main surface on one side and a second main surface on the other side; a pn junction formed inside the chip so as to extend along the first main surface; a device region provided on the first main surface; a first trench structure formed on the first main surface so as to penetrate the pn junction and to partition the device region on the first main surface; and a second trench structure formed on the first main surface so as to penetrate the pn junction and to partition the device region in a region closer to the device region than the first trench structure.

[0006] One embodiment provides a semiconductor device comprising: a first layer of a first conductivity type; a second layer of either a first or second conductivity type laminated on the first layer; a third layer of a second conductivity type interposed between the first and second layers; a device region provided on the second layer; a first trench structure penetrating the second and third layers to reach the first layer and defining the device region in the second layer; and a second trench structure penetrating the second and third layers to reach the first layer and defining the device region in the second layer in a region closer to the device region than the first trench structure.

[0007] One embodiment provides a semiconductor device comprising: a first layer of a first conductivity type; a second layer of a second conductivity type laminated on the first layer; a device region provided in the second layer; a first trench structure that penetrates the second layer to reach the first layer and demarcates the device region in the second layer; and a second trench structure that penetrates the second layer to reach the first layer and demarcates the device region in the region of the second layer closer to the device region than the first trench structure.

[0008] One embodiment provides a semiconductor device comprising: a chip having a first main surface on one side and a second main surface on the other side; a pn junction formed inside the chip so as to extend along the first main surface; a device region provided on the first main surface; a first trench structure formed on the first main surface so as to penetrate the pn junction and to partition the device region on the first main surface; a second trench structure formed on the first main surface so as to penetrate the pn junction and to partition the device region in a region closer to the device region than the first trench structure; and an inter-trench region partitioned between the first trench structure and the second trench structure, to which a potential of 0V or higher is applied.

[0009] One embodiment provides a semiconductor device comprising: a chip having a first main surface on one side and a second main surface on the other side; a pn junction formed inside the chip so as to extend along the first main surface; a device region provided on the first main surface; a first trench structure formed on the first main surface so as to penetrate the pn junction and to partition the device region on the first main surface; and a second trench structure formed on the first main surface so as to penetrate the pn junction, to partition the device region in a region closer to the device region than the first trench structure, and to which a different potential from the first trench structure is applied.

[0010] One embodiment provides a semiconductor device comprising: a chip having a first main surface on one side and a second main surface on the other side; a pn junction formed inside the chip so as to extend along the first main surface; a device region provided on the first main surface; a trench structure formed on the first main surface so as to penetrate the pn junction and to demarcate the device region on the first main surface; and a pn junction extension extended from the intersection of the pn junction and the trench structure toward the bottom wall side of the trench structure so as to extend the pn junction in the device region.

[0011] One embodiment provides a semiconductor device comprising: a chip having a first main surface on one side and a second main surface on the other side; a pn junction formed inside the chip so as to extend along the first main surface; a device region provided on the first main surface; a first trench structure formed on the first main surface so as to penetrate the pn junction and to partition the device region on the first main surface; a second trench structure formed on the first main surface so as to penetrate the pn junction and to partition the device region in a region on the device region side of the first trench structure; and a pn junction extension extended from the intersection of the pn junction and the second trench structure toward the bottom wall side of the second trench structure so as to extend the pn junction in the device region.

[0012] One embodiment provides a semiconductor device comprising: a first layer of a first conductivity type; a second layer of a second conductivity type laminated on the first layer; a device region provided in the second layer; a trench structure penetrating the second layer to reach the first layer and defining the device region in the second layer; and an embedded layer of a second conductivity type formed in the device region at a distance from the trench structure and spanning the boundary between the first and second layers.

[0013] One embodiment provides a semiconductor device comprising: a first layer of a first conductivity type; a second layer of a second conductivity type laminated on the first layer; a device region provided on the second layer; a first trench structure electrically connected to the first layer, penetrating the second layer to be electrically insulated from the second layer, and defining the device region in the second layer; a second trench structure penetrating the second layer to be electrically insulated from the first and second layers, and defining the device region in the region of the second layer on the device region side of the first trench structure; and a second embedded layer of a second conductivity type formed in the device region at a distance from the second trench structure and spanning the boundary between the first and second layers.

[0014] The above or further other objects, features, and effects will be clarified by the embodiments described with reference to the accompanying drawings.

Brief Description of the Drawings

[0015] [Figure 1] FIG. 1 is a schematic plan view showing a semiconductor device according to a first embodiment. [Figure 2] FIG. 2 is an enlarged view of region II shown in FIG. 1. [Figure 3] FIG. 3 is a cross-sectional view showing a cross-sectional structure along line III-III shown in FIG. 2 together with a second trench structure according to a first configuration example. [Figure 4] FIG. 4 is an enlarged cross-sectional view of a main part of the structure shown in FIG. 3. [Figure 5A] FIG. 5A is a cross-sectional view showing the cross-sectional structure shown in FIG. 4 together with a second trench structure according to a second configuration example. [Figure 5B] FIG. 5B is a cross-sectional view showing the cross-sectional structure shown in FIG. 4 together with a second trench structure according to a third configuration example. [Figure 6] FIG. 6 is a graph showing the breakdown voltage of the semiconductor devices shown in FIGS. 1, 5A, and 5B together with the breakdown voltage of a semiconductor device according to a reference example. [Figure 7] FIG. 7 is a cross-sectional view corresponding to FIG. 3 and showing a semiconductor device according to a second embodiment. [Figure 8] FIG. 8 is a graph showing the breakdown voltage of the semiconductor device shown in FIG. 7. [Figure 9] FIG. 9 is a cross-sectional view corresponding to FIG. 7 and showing a semiconductor device according to a third embodiment. [Figure 10] FIG. 10 is a graph showing the breakdown voltage of the semiconductor device shown in FIG. 9. [Figure 11] FIG. 11 is a cross-sectional view corresponding to FIG. 7 and showing a semiconductor device according to a fourth embodiment. [Figure 12] FIG. 12 is a cross-sectional view corresponding to FIG. 3 and showing a semiconductor device according to a fifth embodiment. [Figure 13]Figure 13 is an enlarged cross-sectional view of the main part of the structure shown in Figure 12. [Figure 14] Figure 14 is a graph showing the breakdown voltage of the semiconductor device shown in Figure 12. [Figure 15] Figure 15 corresponds to Figure 12 and is a cross-sectional view showing a semiconductor device according to the sixth embodiment. [Figure 16] Figure 16 corresponds to Figure 12 and is a cross-sectional view showing a semiconductor device according to the seventh embodiment. [Figure 17] Figure 17 corresponds to Figure 3 and is a cross-sectional view showing a semiconductor device according to the eighth embodiment. [Figure 18] Figure 18 is a graph showing the breakdown voltage of the semiconductor device shown in Figure 17. [Figure 19] Figure 19 corresponds to Figure 17 and is a cross-sectional view showing a semiconductor device according to the ninth embodiment. [Figure 20] Figure 20 corresponds to Figure 4 and is a cross-sectional view showing the semiconductor device according to the 10th embodiment together with the trench structure according to the first configuration example. [Figure 21A] Figure 21A is a cross-sectional view showing the cross-sectional structure shown in Figure 20 together with the trench structure according to the second configuration example. [Figure 21B] Figure 21B is a cross-sectional view showing the cross-sectional structure shown in Figure 20 together with the trench structure according to the third configuration example. [Figure 22] Figure 22 is a graph showing the breakdown voltage of the semiconductor device shown in Figure 20, along with the breakdown voltage of a semiconductor device related to a reference example. [Figure 23] Figure 23 is a cross-sectional view showing a first modified example of the chip according to the first to tenth embodiments. [Figure 24] Figure 24 is a cross-sectional view showing a second modified example of the chip according to the first to tenth embodiments. [Figure 25] Figure 25 is a cross-sectional view showing a third modified example of the chip according to the first to tenth embodiments. [Figure 26] Figure 26 is a cross-sectional view showing a fourth modified example of the chip according to the first to tenth embodiments. [Figure 27]Figure 27 is a cross-sectional view showing a modified example of the sinker region according to the first to tenth embodiments. [Modes for carrying out the invention]

[0016] The attached drawings are not necessarily strictly accurate but are schematic diagrams, and the scale and other aspects do not necessarily match. The phrase "approximately equal" in this specification includes cases where the numerical value of the measurement target (measurement location) is exactly the same as the numerical value of the comparison target (comparison location), as well as a range in which the numerical value of the measurement target (measurement location) can be considered equivalent to the numerical value of the comparison target (comparison location) (for example, a range of 0.9 times or more and 1.1 times or less).

[0017] Figure 1 is a schematic plan view showing a semiconductor device 1 according to the first embodiment. Figure 2 is an enlarged view of region II shown in Figure 1. Figure 3 is a cross-sectional view showing the cross-sectional structure along line III-III shown in Figure 2, together with the second trench structure 12 according to the first configuration example. Figure 4 is an enlarged cross-sectional view of the main part of the structure shown in Figure 3.

[0018] Referring to Figures 1 to 4, the semiconductor device 1 includes a rectangular parallelepiped-shaped chip 2 (semiconductor chip). In this embodiment, the chip 2 is made of Si (silicon). The chip 2 has a first main surface 3 on one side, a second main surface 4 on the other side, and first to fourth side surfaces 5A to 5D connecting the first main surface 3 and the second main surface 4.

[0019] The first main surface 3 and the second main surface 4 are formed in a rectangular shape when viewed from their normal direction Z (hereinafter simply referred to as "plan view"). The normal direction Z is also the thickness direction of the chip 2. The first side surface 5A and the second side surface 5B extend in the first direction X along the first main surface 3 and face the second direction Y which intersects (specifically orthogonal to) the first direction X. The third side surface 5C and the fourth side surface 5D extend in the second direction Y and face the first direction X.

[0020] The semiconductor device 1 includes a p-type (first conductivity type) first layer 6, a p-type (second conductivity type) or n-type second layer 7, and an n-type third layer 8 formed within the chip 2. The first layer 6 may be referred to as the "base layer." The second layer 7 may be referred to as the "device formation layer." The third layer 8 may be referred to as the "embedded layer." The first layer 6, the second layer 7, and the third layer 8 may be considered components of the chip 2.

[0021] The first layer 6 is formed in the region on the second main surface 4 side within the chip 2, and forms part of the second main surface 4 and the first to fourth side surfaces 5A to 5D. The first layer 6 has a concentration gradient in which the p-type impurity concentration on the first main surface 3 side is lower than the p-type impurity concentration on the second main surface 4 side. Specifically, the first layer 6 has a laminated structure including a high-concentration layer 6a and a low-concentration layer 6b that are stacked in this order from the second main surface 4 side.

[0022] The high-concentration layer 6a has a relatively high concentration of p-type impurities. The p-type impurity concentration of the high-concentration layer 6a is 1 × 10⁻⁶ 16 cm -3 The above 1 x 10 20 cm -3 The following may also apply: The high-concentration layer 6a may have a thickness of 100 μm or more and 1000 μm or less. In this configuration, the high-concentration layer 6a is made of a p-type semiconductor substrate (Si substrate). The low-concentration layer 6b has a lower p-type impurity concentration than the high-concentration layer 6a and is laminated on top of the high-concentration layer 6a. The p-type impurity concentration of the low-concentration layer 6b is 1 × 10⁻⁶ 14 cm -3 The above 1 x 10 17 cm -3 The following may also apply: The low-concentration layer 6b has a thickness less than the thickness of the high-concentration layer 6a. The thickness of the low-concentration layer 6b may be 0.5 μm or more and 20 μm or less. In this configuration, the low-concentration layer 6b consists of a p-type epitaxial layer (Si epitaxial layer).

[0023] The second layer 7 is formed in a region on the first main surface 3 side within the chip 2, and forms a part of the first main surface 3 and the first to fourth side surfaces 5A to 5D. The conductivity type (n-type or p-type) of the second layer 7 is arbitrary and is selected according to the specifications of the semiconductor device 1. In this embodiment, an example in which the second layer 7 has an n-type conductivity type will be described, but it is not intended to limit the conductivity type of the second layer 7 to n-type.

[0024] The second layer 7 may have a uniform n-type impurity concentration in the thickness direction, or may have an n-type impurity concentration gradient that increases toward the first main surface 3. The n-type impurity concentration of the second layer 7 is 1×10 14 cm -3 or more and 1×10 17 cm -3 or less. The second layer 7 may have a thickness of 0.5 μm or more and 20 μm or less. In this embodiment, the second layer 7 is composed of an n-type epitaxial layer (Si epitaxial layer).

[0025] The third layer 8 is interposed in a region between the first layer 6 and the second layer 7 within the chip 2, and forms a part of the first to fourth side surfaces 5A to 5D of the chip 2. The third layer 8 forms a pn junction J at the boundary with the first layer 6. That is, in the chip 2, a pn junction portion J (a pn-junction portion) extending in the horizontal direction (the direction orthogonal to the thickness direction) along the first main surface 3 is formed in the middle portion in the thickness direction between the first main surface 3 and the second main surface 4. The pn junction J may be referred to as "a pn-connection portion" or "a pn-boundary portion".

[0026] The third layer 8 has a higher n-type impurity concentration than the second layer 7. Specifically, the third layer 8 has a concentration gradient in which the p-type impurity concentration on the first main surface 3 side is higher than the p-type impurity concentration on the second main surface 4 side. More specifically, the third layer 8 has a stacked structure including a low-concentration buried layer 8a and a high-concentration buried layer 8b stacked in this order from the first layer 6 side. [[ID=​​The low-concentration burial layer 8a has a relatively low n-type impurity concentration and is laminated on top of the low-concentration layer 6b of the first layer 6. The low-concentration burial layer 8a forms a pn junction J with the low-concentration layer 6b. The low-concentration burial layer 8a may have a lower n-type impurity concentration than the second layer 7, or it may have a higher n-type impurity concentration than the second layer 7. The n-type impurity concentration of the low-concentration burial layer 8a is 1 × 10⁻⁶. 14 cm -3 The above 1 x 10 18 cm -3 The following is also possible: The low-concentration burial layer 8a may have a thickness of 0.1 μm or more and 5 μm or less. In this configuration, the low-concentration burial layer 8a consists of an n-type epitaxial layer (Si epitaxial layer).

[0028] The high-concentration burial layer 8b has a higher n-type impurity concentration than the low-concentration burial layer 8a and is laminated on top of the low-concentration burial layer 8a. It is preferable that the high-concentration burial layer 8b has a higher n-type impurity concentration than the second layer 7. The n-type impurity concentration of the high-concentration burial layer 8b is 1 × 10⁻⁶. 16 cm -3 The above 1 x 10 21 cm -3 The following may also apply: The high-concentration burial layer 8b may have a thickness of 0.1 μm or more and 5 μm or less. In this configuration, the high-concentration burial layer 8b consists of an n-type epitaxial layer (Si epitaxial layer).

[0029] The semiconductor device 1 includes a plurality of device regions 9 provided on the first main surface 3 (second layer 7). Each of the plurality of device regions 9 is a region on which various functional devices are formed. In a plan view, the plurality of device regions 9 are partitioned inward from the first to fourth sides 5A to 5D, with spacing between them. The number, arrangement, and shape of the device regions 9 are arbitrary and are not limited to a specific number, arrangement, or shape.

[0030] Multiple functional devices may each include at least one of a semiconductor switching device, a semiconductor rectifier, and a passive device. The semiconductor switching device may include at least one of a JFET (Junction Field Effect Transistor), MISFET (Metal Insulator Semiconductor Field Effect Transistor), BJT (Bipolar Junction Transistor), and IGBT (Insulated Gate Bipolar Junction Transistor).

[0031] The semiconductor rectifier device may include at least one of a pn junction diode, a pin junction diode, a Zener diode, a Schottky barrier diode, and a fast recovery diode. The passive device may include at least one of a resistor, a capacitor, an inductor, and a fuse. In this embodiment, the multiple device regions 9 include at least one transistor region 9A. The structure of the transistor region 9A will be described in detail below.

[0032] Referring to Figures 2 to 4, the semiconductor device 1 includes a trench separation structure 10 as an example of a region separation structure that demarcates a transistor region 9A on the first main surface 3. The trench separation structure 10 includes a plurality of trench structures and demarcates a transistor region 9A of a predetermined shape in a plan view.

[0033] The trench separation structure 10 has a multi-trench structure including at least one first trench structure 11 and at least one second trench structure 12 having a structure different from the first trench structure 11. In this embodiment, the trench separation structure 10 has a double trench structure including a single first trench structure 11 and a single second trench structure 12. The first trench structure 11 may be referred to as the "first trench electrode structure". The second trench structure 12 may be referred to as the "second trench electrode structure".

[0034] Referring to Figure 2, the first trench structure 11 is formed in a strip shape extending along the transistor region 9A in a plan view. In this embodiment, the first trench structure 11 is formed in an annular shape (a quadrangular annular shape in this embodiment) in a plan view and demarcates a transistor region 9A of a predetermined shape (a quadrangular shape in this embodiment). In this embodiment, the four corners of the first trench structure 11 are curved in a direction away from the transistor region 9A in a plan view. The planar shape of the first trench structure 11 (the planar shape of the transistor region 9A) is arbitrary. The first trench structure 11 may be formed in a polygonal annular shape, a circular annular shape, or an elliptical annular shape in a plan view and demarcate a transistor region 9A that is polygonal, circular, or elliptical in a plan view.

[0035] The first trench structure 11 has a first trench width W1. The first trench width W1 is the width in a direction perpendicular to the direction in which the first trench structure 11 extends in a plan view. The first trench width W1 may be 0.5 μm or more and 10 μm or less. Preferably, the first trench width W1 is 2 μm or more and 4 μm or less.

[0036] Referring to Figures 3 and 4, the first trench structure 11 is formed on the first main surface 3 so as to penetrate the pn junction J and demarcates the transistor region 9A on the first main surface 3. Specifically, the first trench structure 11 penetrates the second layer 7 and the third layer 8 so as to reach the first layer 6, and demarcates the transistor region 9A in the second layer 7. In this embodiment, the first trench structure 11 extends from the first main surface 3 toward the second main surface 4 so as to reach the high-density layer 6a of the first layer 6, and penetrates the second layer 7, the third layer 8, and the low-density layer 6b of the first layer 6.

[0037] The first trench structure 11 includes an inner circumferential wall on the transistor region 9A side, an outer circumferential wall on the opposite side of the inner circumferential wall (the peripheral edge side of the chip 2), and a bottom wall connecting the inner circumferential wall and the outer circumferential wall. The first trench structure 11 may be formed in a vertical shape having a substantially constant opening width in cross-sectional view. The first trench structure 11 may be formed in a tapered shape having an opening width that narrows toward the second main surface 4 in cross-sectional view. The bottom wall of the first trench structure 11 may be formed in a curved shape toward the second main surface 4. The bottom wall of the first trench structure 11 may have a flat surface parallel to the first main surface 3.

[0038] Referring to Figure 4, the first trench structure 11 protrudes from the pn junction J (the boundary between the first layer 6 and the third layer 8) toward the second main surface 4 with a first value P1. The first value P1 may be 1 μm or more and 30 μm or less. Preferably, the first value P1 is 5 μm or more.

[0039] The first trench structure 11 is electrically connected to the chip 2 at its bottom wall and electrically insulated from the chip 2 at its side walls (inner and outer walls). In other words, the first trench structure 11 has a lower end that is electrically connected to the chip 2. Specifically, the first trench structure 11 is electrically connected to the first layer 6 and electrically insulated from the second layer 7 and the third layer 8. In other words, the first trench structure 11 is fixed at the same potential as the first layer 6.

[0040] The first trench structure 11 includes a first trench 13, a first insulating film 14, and a first electrode 15. The first trench 13 is formed in the first main surface 3 so as to penetrate the pn junction J. Specifically, the first trench 13 penetrates the second layer 7 and the third layer 8 so as to reach the first layer 6. In this embodiment, the first trench 13 extends from the first main surface 3 toward the second main surface 4 so as to reach the high-density layer 6a of the first layer 6, and penetrates the second layer 7, the third layer 8, and the low-density layer 6b of the first layer 6.

[0041] The first insulating film 14 covers the inner wall of the first trench 13 so as to expose the chip 2 from the bottom wall of the first trench 13. Specifically, the first insulating film 14 exposes the first layer 6 from the bottom wall of the first trench 13. In this embodiment, the first insulating film 14 exposes the high-concentration layer 6a of the first layer 6 from the bottom wall of the first trench 13. It is preferable that the first insulating film 14 covers the entire inner and outer circumferential walls of the first trench 13. The first insulating film 14 may contain a silicon oxide film. It is preferable that the first insulating film 14 contains a silicon oxide film made of the oxide of the chip 2.

[0042] The first electrode 15 is embedded in the first trench 13 with the first insulating film 14 in between, and is electrically connected to the chip 2 at the bottom wall of the first trench 13. Specifically, the first electrode 15 is electrically connected to the first layer 6 and electrically insulated from the second layer 7 and the third layer 8. More specifically, the first electrode 15 has an exposed portion that is exposed from the bottom wall of the first trench 13, and at this exposed portion, is mechanically and electrically connected to the high-concentration layer 6a of the first layer 6. The first electrode 15 preferably contains conductive polysilicon. The first electrode 15 preferably contains conductive polysilicon of the same conductivity type (p-type in this embodiment) as the first layer 6. The p-type impurity of the first electrode 15 is preferably boron.

[0043] Referring to FIG. 2, the second trench structure 12 is formed at a distance from the first trench structure 11 toward the transistor region 9A in a plan view, and extends in a strip shape along the transistor region 9A. In this form, the second trench structure 12 is formed in an annular shape (a square annular shape in this form) extending parallel to the first trench structure 11 in a plan view, and partitions the transistor region 9A having a predetermined shape (a square shape in this form). In this form, the four corners of the second trench structure 12 are curved in a direction away from the transistor region 9A along the four corners of the first trench structure 11 in a plan view.

[0044] The planar shape of the second trench structure 12 (the planar shape of the transistor region 9A) is arbitrary. The second trench structure 12 may be formed in a polygonal annular shape, a circular annular shape or an elliptical annular shape in a plan view, and partition the transistor region 9A having a polygonal shape, a circular shape or an elliptical shape in a plan view. The planar shape of the second trench structure 12 does not necessarily need to be similar to the planar shape of the first trench structure 11.

[0045] The second trench structure 12 has a second trench width W2. The second trench width W2 is the width in a direction orthogonal to the direction in which the second trench structure 12 extends in a plan view. It is preferable that the second trench width W2 is not more than the first trench width W1 (W2≦W1). It is particularly preferable that the second trench width W2 is less than the first trench width W1 (W2<W1). The second trench width W2 may be not less than 0.5 μm and not more than 10 μm. It is preferable that the second trench width W2 is not less than 1 μm and not more than 2 μm.

[0046] The second trench structure 12 is formed at a predetermined trench interval IT from the first trench structure 11. The trench interval IT may be not less than 0.5 μm and not more than 20 μm. It is preferable that the trench interval IT is not less than 1 μm and not more than 5 μm. It is preferable that the trench interval IT is less than the first trench width W1 (IT<W1).

[0047] Referring to FIGS. 3 and 4, the second trench structure 12 is formed on the first main surface 3 so as to penetrate the pn junction J, and partitions the transistor region 9A in a region on the transistor region 9A side of the first trench structure 11 on the first main surface 3. Specifically, the second trench structure 12 penetrates the second layer 7 and the third layer 8 so as to reach the first layer 6, and partitions the transistor region 9A in a region on the transistor region 9A side of the first trench structure 11 in the second layer 7. In this form, the second trench structure 12 extends from the first main surface 3 toward the second main surface 4 so as to reach the high-concentration layer 6a of the first layer 6, and penetrates the second layer 7, the third layer 8, and the low-concentration layer 6b of the first layer 6.

[0048] The second trench structure 12 includes an inner peripheral wall on the transistor region 9A side, an outer peripheral wall on the first trench structure 11 side, and a bottom wall connecting the inner peripheral wall and the outer peripheral wall. The second trench structure 12 may be formed in a vertical shape having a substantially constant opening width in a cross-sectional view. The second trench structure 12 may be formed in a tapered shape having an opening width that narrows toward the first layer 6 side in a cross-sectional view. The bottom wall of the second trench structure 12 may be formed in a curved shape toward the second main surface 4. The bottom wall of the second trench structure 12 may have a flat surface parallel to the first main surface 3.

[0049] Referring to FIG. 4, the second trench structure 12 protrudes at a second value P2 from the pn junction J (the boundary between the first layer 6 and the third layer 8) toward the second main surface 4 side. It is preferable that the second value P2 is substantially equal to the first value P1 of the first trench structure 11 (P1≈P2). That is, the second trench structure 12 may have a depth substantially equal to the depth of the first trench structure 11. The second value P2 may be less than the first value P1 (P2<P1). That is, the second trench structure 12 may have a depth less than the depth of the first trench structure 11. The second value P2 may be 1 μm or more and 30 μm or less. The second value P2 is preferably 5 μm or more.

[0050] The second trench structure 12 has a different structure from the first trench structure 11 and is electrically insulated from the first layer 6, the second layer 7, and the third layer 8. The second trench structure 12 is electrically isolated from the first trench structure 11. In this configuration, the second trench structure 12 is formed in an electrically floating state. The potential generated (applied) to the second trench structure 12 varies depending on the potential (electric field) applied to the transistor region 9A. The potential generated to the second trench structure 12 is less than or equal to the maximum potential applied to the transistor region 9A.

[0051] The second trench structure 12 includes a second trench 16, a second insulating film 17, and a second electrode 18. The second trench 16 is formed in the first main surface 3 so as to penetrate the pn junction J. Specifically, the second trench 16 penetrates the second layer 7 and the third layer 8 so as to reach the first layer 6. In this embodiment, the second trench 16 extends from the first main surface 3 toward the second main surface 4 so as to reach the high-density layer 6a of the first layer 6, and penetrates the second layer 7, the third layer 8, and the low-density layer 6b of the first layer 6.

[0052] The second insulating film 17 covers the inner wall of the second trench 16. Specifically, the second insulating film 17 covers the entire inner wall of the second trench 16 (inner peripheral wall, outer peripheral wall, and bottom wall). The second insulating film 17 may contain a silicon oxide film. Preferably, the second insulating film 17 contains a silicon oxide film made of the oxide of the chip 2.

[0053] In this embodiment, the second insulating film 17 forms a bottom-side insulator 19 that is thicker in the portion covering the bottom wall of the second trench 16 than in the portion covering the side walls (inner and outer walls) of the second trench 16. In other words, the second trench structure 12 includes a bottom-side insulator 19 embedded on the bottom wall side of the second trench 16 so as to be continuous with the second insulating film 17, and having a thickness exceeding that of the second insulating film 17.

[0054] It is preferable that the bottom insulator 19 is embedded in a region of the second trench 16 that is closer to the bottom wall than the pn junction J (the boundary between the first layer 6 and the third layer 8) with respect to the depth direction of the second trench 16. It is particularly preferable that the bottom insulator 19 is in contact with the high-concentration layer 6a and the low-concentration layer 6b of the first layer 6 with respect to the depth direction of the second trench 16. Of course, the bottom insulator 19 may be embedded so as to cross the pn junction J (the boundary between the first layer 6 and the third layer 8) with respect to the depth direction of the second trench 16. In this case, the bottom insulator 19 may be in contact with either or both of the low-concentration embedded layer 8a and the high-concentration embedded layer 8b of the third layer 8. Also, the bottom insulator 19 may be in contact with a part of the second layer 7.

[0055] The second electrode 18 is embedded in the second trench 16 with the second insulating film 17 in between, and is electrically insulated from the chip 2. Specifically, the second electrode 18 is electrically insulated from the first layer 6, the second layer 7, and the third layer 8 with the second insulating film 17 in between. In this configuration, the second electrode 18 faces the first layer 6 (specifically the high-concentration layer 6a) on the bottom wall side of the second trench 16, with a relatively thick bottom insulator 19 in between. The parasitic capacitance between the second electrode 18 and the first layer 6 is reduced by the bottom insulator 19.

[0056] The second electrode 18 is electrically isolated from the first electrode 15 of the first trench structure 11. In this embodiment, the second electrode 18 is formed in an electrically floating state. The second electrode 18 preferably contains conductive polysilicon. The second electrode 18 preferably contains conductive polysilicon of the same conductivity type (p-type in this embodiment) as the first layer 6. The p-type impurity of the second electrode 18 is preferably boron.

[0057] The semiconductor device 1 includes an inter-trench region 20 partitioned in the chip 2 between a first trench structure 11 and a second trench structure 12. The inter-trench region 20 is partitioned between the inner circumferential wall of the first trench structure 11 and the outer circumferential wall of the second trench structure 12, and includes a portion of the first layer 6, a portion of the third layer 8, and a portion of the second layer 7. The width of the inter-trench region 20 is adjusted by the trench spacing IT.

[0058] The inter-trench region 20 is electrically isolated from the first trench structure 11. The inter-trench region 20 is electrically isolated from the second trench structure 12. In this configuration, the inter-trench region 20 is formed in an electrically floating state. The potential generated (applied) in the inter-trench region 20 varies depending on the potential (electric field) applied to the transistor region 9A. The potential generated in the inter-trench region 20 is less than or equal to the maximum potential applied to the transistor region 9A.

[0059] The semiconductor device 1 includes an n-type sinker region 21 that covers the sidewall of the second trench structure 12 within the chip 2. The sinker region 21 is formed within the second layer 7 so as to extend along the sidewall of the second trench structure 12. In this embodiment, the sinker region 21 is formed as a film that extends along both the inner and outer circumferential walls of the second trench structure 12. The sinker region 21 has a higher n-type impurity concentration than the second layer 7. The n-type impurity concentration of the sinker region 21 is 1 × 10⁻⁶. 15 cm -3 The above 1 x 10 19 cm -3 The following is also acceptable.

[0060] The sinker region 21 is formed in an annular shape extending along the side wall of the second trench 16 in a plan view. The lower end of the sinker region 21 is connected to the third layer 8 (high-density buried layer 8b). In this embodiment, the sinker region 21 is formed along the second trench structure 12 at a distance from the first trench structure 11 and does not cover either or both (both in this embodiment) of the inner and outer circumferential walls of the first trench structure 11.

[0061] The semiconductor device 1 includes a p-type impurity region 22 formed in a region along the bottom wall of the first trench structure 11 within the chip 2. The impurity region 22 is formed in the first layer 6 so as to cover the bottom wall of the first trench structure 11. The impurity region 22 has a higher p-type impurity concentration than the first layer 6. Specifically, the impurity region 22 is formed within the high-concentration layer 6a in the first layer 6 and has a higher p-type impurity concentration than the high-concentration layer 6a.

[0062] In this configuration, the first electrode 15 is formed as a source of p-type impurities for the first layer 6, and the impurity region 22 contains p-type impurities from the first layer 6 and p-type impurities from the first electrode 15. The impurity region 22 also covers the side walls of the first trench structure 11. In this configuration, the impurity region 22 bulges laterally from the bottom wall of the first trench structure 11 along the first main surface 3 and covers the bottom wall of the second trench structure 12. Preferably, the impurity region 22 is formed within the high-concentration layer 6a of the first layer 6, spaced apart from the low-concentration layer 6b of the first layer 6.

[0063] Referring to Figure 3, the semiconductor device 1 includes a planar gate type MISFET 30 as an example of a functional device formed in the transistor region 9A. In Figure 2, the MISFET 30 is not shown. Depending on the magnitude of the drain-source voltage applied between the drain and source, the MISFET 30 can take one of the following forms: HV (high voltage)-MISFET (e.g., 100V to 1000V), MV (middle voltage)-MISFET (e.g., 30V to 100V), and LV (low voltage)-MISFET (e.g., 1V to 30V). In this configuration, an example in which the MISFET 30 consists of an HV-MISFET is described, but this does not mean that the form of the MISFET 30 is limited to an HV-MISFET.

[0064] The MISFET 30 is composed of at least one MISFET cell formed in the transistor region 9A. In this embodiment, the MISFET cell, in cross-sectional view, includes at least one (one in this embodiment) n-type first well region 31, at least one (multiple in this embodiment) p-type second well region 32, at least one (multiple in this embodiment) n-type drain region 33, at least one (multiple in this embodiment) n-type source region 34, at least one (multiple in this embodiment) p-type channel region 35, at least one (multiple in this embodiment) p-type contact region 36, multiple shallow trench structures 37, and at least one (multiple in this embodiment) planar gate structure 38. The shallow trench structure 37 may be referred to as an "STI (shallow trench isolation) structure".

[0065] The first well region 31 is formed on the surface of the second layer 7 in the transistor region 9A. The first well region 31 has a higher n-type impurity concentration than the second layer 7. Multiple second well regions 32 are formed on the surface of the second layer 7 in the transistor region 9A, spaced apart from the first well region 31. One second well region 32 is formed spaced apart from the first well region 31 on one side of the first direction X, and the other second well region 32 is formed spaced apart from the first well region 31 on the other side of the first direction X.

[0066] The drain region 33 is formed on the surface of the first well region 31, spaced inward from its periphery. Multiple source regions 34 are each formed on the surface of the corresponding second well region 32, spaced inward from its periphery. Multiple channel regions 35 are each formed on the surface of the corresponding second well region 32, between the second layer 7 and the corresponding source region 34. Multiple contact regions 36 are each formed on the surface of the corresponding second well region 32, spaced inward from its periphery. Multiple contact regions 36 are adjacent to the corresponding source region 34.

[0067] Multiple shallow trench structures 37 are formed in the second layer 7, spaced apart from the third layer 8 in the thickness direction of the second layer 7. Preferably, the multiple shallow trench structures 37 are formed at depths spaced apart from the bottom of the first well region 31 and the bottom of the second well region 32 toward the first main surface 3. The multiple shallow trench structures 37 are formed along the periphery of the drain region 33, separating the drain region 33 from other regions.

[0068] Multiple shallow trench structures 37 are formed along the outer edges (periphery on the trench separation structure 10 side) of multiple second well regions 32, and demarcate the multiple second well regions 32 from other regions. Each of the multiple shallow trench structures 37 includes a shallow trench 39 and an embedded insulator 40. Each shallow trench 39 is formed in the first main surface 3. Each embedded insulator 40 is embedded in the shallow trench 39.

[0069] Multiple planar gate structures 38 are each formed on the second layer 7 (first main surface 3) so as to cover the corresponding channel region 35 and control the on / off state of the corresponding channel region 35. In this embodiment, multiple planar gate structures 38 are each formed to span the first well region 31 and the corresponding source region 34. Multiple planar gate structures 38 may also cover a portion of the shallow trench structure 37 that demarcates the drain region 33.

[0070] The multiple planar gate structures 38 include gate insulating films 41 and gate electrodes 42 stacked in this order from the second layer 7 side. The gate insulating film 41 may include a silicon oxide film. Preferably, the gate insulating film 41 includes a silicon oxide film made of the oxide of the chip 2. Preferably, the gate electrodes 42 include conductive polysilicon. Preferably, the gate electrodes 42 include conductive polysilicon having the same conductivity type as the first layer 6 (i.e., p-type). Preferably, the p-type impurity of the gate electrodes 42 is boron. Of course, the gate electrodes 42 may have an n-type conductivity.

[0071] The second trench structure 12 can take forms other than those shown in Figures 3 and 4. Other configuration examples of the second trench structure 12 are shown below with reference to Figures 5A and 5B. Figure 5A is a cross-sectional view showing the cross-sectional structure shown in Figure 4 together with the second trench structure 12 relating to the second configuration example. Hereafter, structures corresponding to those described with reference to Figures 1 to 4 are given the same reference numerals, and their descriptions are omitted.

[0072] Referring to Figure 5A, a second trench structure 12 without a bottom insulator 19 may be adopted. In other words, the second trench structure 12 may include a second insulating film 17 that covers the inner walls (inner peripheral wall, outer peripheral wall, and bottom wall) of the second trench 16 with a substantially uniform thickness. In this case, it is preferable that the second insulating film 17 has a thickness of less than half the width W2 of the second trench of the second trench structure 12. The thickness of the second insulating film 17 is the thickness along the direction normal to the wall surface of the second trench structure 12 (second trench 16).

[0073] It is particularly preferable that the thickness of the second insulating film 17 is less than half the width of the bottom wall of the second trench structure 12. The width of the bottom wall of the second trench structure 12 is the width in the direction perpendicular to the direction in which the second trench structure 12 extends in a plan view. Under this condition, the second trench width W2 may be greater than or equal to the first trench width W1 of the first trench structure 11 (W1 ≤ W2), or less than the first trench width W1 (W1 > W2).

[0074] Figure 5B is a cross-sectional view showing the cross-sectional structure shown in Figure 4 together with the second trench structure 12 relating to the third configuration example. Hereafter, the same reference numerals are used for structures corresponding to those described with reference to Figures 1 to 4, and their descriptions are omitted.

[0075] Referring to Figure 5B, a second trench structure 12 without a second electrode 18 may be adopted. In other words, the second trench structure 12 may include a second insulating film 17 embedded in the second trench 16 as an integrated member. In this case, the second trench structure 12 may be called a "trench insulating structure". Under these conditions, the second trench width W2 may be greater than or equal to the first trench width W1 of the first trench structure 11 (W1 ≤ W2), or less than the first trench width W1 (W1 > W2).

[0076] Figure 6 is a graph showing the breakdown voltage VB of semiconductor device 1 shown in Figures 1, 5A, and 5B, along with the breakdown voltage VB of a semiconductor device related to a reference example. In Figure 6, the vertical axis represents the breakdown voltage VB [V], and the horizontal axis represents the item (semiconductor device being measured). Here, a potential of 0V is applied to the first layer 6 and the first trench structure 11. The voltage here is the voltage relative to the potential of the first layer 6 (=0V).

[0077] Figure 6 shows the first bar graph G1, the second bar graph G2, the third bar graph G3, and the fourth bar graph G4. The first bar graph G1 shows the breakdown voltage VB of the semiconductor device according to the reference example. The semiconductor device according to the reference example has the same structure as semiconductor device 1, except that it does not have the second trench structure 12. Further description of the semiconductor device according to the reference example is omitted.

[0078] The second bar graph G2 shows the breakdown voltage VB of the semiconductor device 1 (see Figure 5B) including the second trench structure 12 according to the third configuration example. The third bar graph G3 shows the breakdown voltage VB of the semiconductor device 1 (see Figure 5A) including the second trench structure 12 according to the second configuration example. The fourth bar graph G4 shows the breakdown voltage VB of the semiconductor device 1 (see Figures 3-4) including the second trench structure 12 according to the first configuration example.

[0079] Referring to the first to fourth bar graphs G1 to G4, the breakdown voltage VB increased in the following order: semiconductor device according to the reference example, semiconductor device 1 including the second trench structure 12 according to the third configuration example, semiconductor device 1 including the second trench structure 12 according to the second configuration example, and semiconductor device 1 including the second trench structure 12 according to the first configuration example.

[0080] These results indicate that it is preferable for the trench isolation structure 10 to have a multi-trench structure including a first trench structure 11 and a second trench structure 12 (see bar graphs G2 to G4 of the second to fourth sections). In this structure, the electric field concentration in the first trench structure 11 is mitigated by the second trench structure 12, improving the breakdown voltage VB.

[0081] When the trench separation structure 10 has a multi-trench structure, it was found to be particularly preferable that the first trench structure 11 consists of a first trench electrode structure including a first electrode 15, and the second trench structure 12 consists of a second trench electrode structure including a second electrode 18 (see bar graphs G3 to G4 of the third to fourth sections). With this structure, electric field concentration on the second trench structure 12 is further reduced, and the breakdown voltage VB is further improved.

[0082] Furthermore, it was found that the second trench structure 12 preferably includes a bottom insulator 19 in a structure including a second electrode 18 (see bar graph G4 in the fourth section). When the bottom insulator 19 is included, the opposing area between the first layer 6 and the second electrode 18 in the second trench structure 12 is reduced, and the parasitic capacitance of the second trench structure 12 is reduced. As a result, electric field concentration in the second trench structure 12 is further mitigated, and the breakdown voltage VB is further improved.

[0083] As described above, the semiconductor device 1 includes a chip 2, a pn junction J, a transistor region 9A (device region 9), a first trench structure 11, and a second trench structure 12. The chip 2 has a first main surface 3 on one side and a second main surface 4 on the other side. The pn junction J is formed in the chip 2 at an intermediate point between the first main surface 3 and the second main surface 4, extending horizontally along the first main surface 3. The transistor region 9A is provided on the first main surface 3.

[0084] The first trench structure 11 is formed on the first main surface 3 so as to penetrate the pn junction J, and defines the transistor region 9A on the first main surface 3. The second trench structure 12 is formed on the first main surface 3 so as to penetrate the pn junction J, and defines the transistor region 9A in a region closer to the transistor region 9A than the first trench structure 11. This structure makes it possible to provide a semiconductor device 1 that can improve the breakdown voltage (specifically, the breakdown voltage VB).

[0085] Alternatively, the semiconductor device 1 includes a p-type first layer 6, a p-type or n-type (n-type in this embodiment) second layer 7, an n-type third layer 8, a transistor region 9A (device region 9), a first trench structure 11 (first trench electrode structure), and a second trench structure 12 (second trench electrode structure). The second layer 7 is stacked on top of the first layer 6. The third layer 8 is interposed between the first layer 6 and the second layer 7. The device region 9 is provided on the second layer 7.

[0086] The first trench structure 11 penetrates the second layer 7 and the third layer 8 so as to reach the first layer 6. The first trench structure 11 demarcates the transistor region 9A in the second layer 7. The second trench structure 12 penetrates the second layer 7 and the third layer 8 so as to reach the first layer 6. The second trench structure 12 demarcates the transistor region 9A in the region of the second layer 7 that is closer to the transistor region 9A than the first trench structure 11. This structure makes it possible to provide a semiconductor device 1 that can improve the breakdown voltage (specifically, the breakdown voltage VB).

[0087] The first trench structure 11 is preferably electrically connected to the chip 2. Specifically, the first trench structure 11 preferably comprises a first trench electrode structure that is electrically connected to the first layer 6 and electrically insulated from the second layer 7 and the third layer 8. The second trench structure 12 is preferably electrically insulated from the chip 2. Specifically, the second trench structure 12 preferably comprises a second trench electrode structure that is electrically insulated from the first layer 6, the second layer 7, and the third layer 8. That is, the second trench structure 12 preferably has an electrode structure different from that of the first trench structure 11. According to this structure, the electric field concentration on the second trench structure 12 can be alleviated, whereby the breakdown voltage VB can be further improved.

[0088] The second trench structure 12 is preferably electrically separated from the first trench structure 11. The second trench structure 12 is preferably formed in an electrically floating state. A potential different from that of the first trench structure 11 preferably occurs in the second trench structure 12.

[0089] The first trench structure 11 has a first trench width W1, and the second trench structure 12 preferably has a second trench width W2 (W2 < W1) that is not greater than the first trench width W1. The second trench structure 12 is preferably formed at an interval not greater than the first trench width W1. The first trench width W1 may be not less than 0.5 μm and not greater than 10 μm.

[0090] The first trench structure 11 is preferably formed in a tapered shape toward the thickness direction (the second main surface 4 side). The second trench structure 12 is preferably formed in a tapered shape toward the thickness direction (the second main surface 4 side). The first trench structure 11 preferably surrounds the device region 9 in plan view. The second trench structure 12 preferably surrounds the device region 9 in plan view.

[0091] The first trench structure 11 preferably includes a first trench 13 that penetrates the second layer 7 and the third layer 8 to reach the first layer 6, a first insulating film 14 that covers the inner wall of the first trench 13 so as to expose the first layer 6, and a first electrode 15 that is electrically connected to the first layer 6 and embedded in the first trench 13 with the first insulating film 14 in between so as to be electrically insulated from the second layer 7 and the third layer 8.

[0092] The second trench structure 12 preferably includes a second trench 16 that penetrates the second layer 7 and the third layer 8 to reach the first layer 6, a second insulating film 17 that covers the inner wall of the second trench 16, and a second electrode 18 embedded in the second trench 16 with the second insulating film 17 in between so as to be electrically insulated from the first layer 6, the second layer 7 and the third layer 8.

[0093] The first electrode 15 preferably contains p-type conductive polysilicon. The second electrode 18 preferably contains p-type conductive polysilicon. The second trench structure 12 is preferably embedded on the bottom wall side of the second trench 16 so as to be connected to the second insulating film 17 and includes a bottom insulator 19 having a thickness exceeding the thickness of the second insulating film 17. The second electrode 18 is preferably embedded in the second trench 16 with the second insulating film 17 and the bottom insulator 19 in between. This structure can mitigate electric field concentration in the second trench structure 12, thereby further improving the breakdown voltage VB.

[0094] The first layer 6 preferably includes a p-type high-concentration layer 6a having a relatively high impurity concentration, and a p-type low-concentration layer 6b laminated on the high-concentration layer 6a and having a lower impurity concentration than the high-concentration layer 6a. The third layer 8 is preferably laminated on the low-concentration layer 6b. In this case, the high-concentration layer 6a is preferably made of a p-type semiconductor substrate.

[0095] Preferably, the third layer 8 is laminated on the first layer 6 and includes an n-type low-concentration burial layer 8a having a relatively low impurity concentration, and an n-type high-concentration burial layer 8b having a higher impurity concentration than the low-concentration burial layer 8a. In this case, it is preferable that the second layer 7 is laminated on the high-concentration burial layer 8b. With this structure, electric field concentration in the second trench structure 12 can be mitigated by the low-concentration burial layer 8a. Therefore, the pressure resistance can be improved compared to the case where the third layer 8 has a single-layer structure consisting only of the high-concentration burial layer 8b.

[0096] The semiconductor device 1 preferably includes a p-type impurity region 22 formed in the chip 2 in a region along the bottom wall of the first trench structure 11. The impurity region 22 is preferably formed in the first layer 6 and has a higher impurity concentration than the first layer 6. The impurity region 22 preferably covers the bottom wall of the second trench structure 12. The semiconductor device 1 preferably includes an n-type sinker region 21 that covers the side wall of the second trench structure 12 in the chip 2. The sinker region 21 is preferably formed in the second layer 7 so as to extend along the side wall of the second trench structure 12.

[0097] Figure 7 corresponds to Figure 3 and is a cross-sectional view showing a semiconductor device 51 according to the second embodiment. Hereinafter, the same reference numerals are used for structures corresponding to those described in the first embodiment, and their descriptions are omitted.

[0098] The semiconductor device 51 includes, as in the first embodiment, a first trench structure 11 electrically connected to the chip 2 (first layer 6), and a second trench structure 12 electrically isolated from the chip 2. The second trench structure 12 is formed in an electrically floating state. In this embodiment, unlike in the first embodiment, the semiconductor device 51 includes an inter-trench region 20 to which an inter-trench potential VI of 0V or higher is applied. The inter-trench potential VI is applied to the inter-trench region 20 from outside the chip 2.

[0099] The trench potential VI is preferably set to any value within a potential range that is 0V or greater and less than or equal to the maximum potential applied to the transistor region 9A (MISFET 30). The trench potential VI is preferably greater than 0V. The trench potential VI is preferably different from the potential applied to the first trench structure 11. The trench potential VI is preferably different from the potential applied to the second trench structure 12.

[0100] The trench potential VI is preferably different from the potential applied to the MISFET 30 (transistor region 9B). The potential of the trench region 20 is raised to the trench potential VI. When the trench potential VI is applied, a potential gradient is formed in the trench region 20 that gradually decreases from the first main surface 3 side to the first layer 6 side.

[0101] In this embodiment, the semiconductor device 51 includes a first contact electrode 52 electrically connected to the inter-trench region 20 on the chip 2 (second layer 7). In Figure 7, the first contact electrode 52 is shown in a simplified form by lines. The first contact electrode 52 applies an inter-trench potential VI to the inter-trench region 20.

[0102] Figure 8 is a graph showing the breakdown voltage VB of the semiconductor device 51 shown in Figure 7. In Figure 8, the vertical axis represents the breakdown voltage VB [V], and the horizontal axis represents the trench potential VI [V]. Here, an arbitrary trench potential VI between 0V and 30V is applied to the trench region 20. Also, a potential of 0V is applied to the first layer 6 and the first trench structure 11. The voltage here is the voltage with respect to the potential of the first layer 6 (=0V). The trench potential VI may be read as the trench voltage with respect to the potential of the first layer 6 (=0V).

[0103] Figure 8 shows the first line L1 (see solid line in the black circle plot), the second line L2 (see dashed line in the white circle plot), and the third line L3 (see dashed line in the square plot). The first line L1 shows the breakdown voltage VB of the semiconductor device 51. The second line L2 shows the voltage of the second trench structure 12. The third line L3 shows the difference voltage obtained by subtracting the voltage of the second trench structure 12 from the breakdown voltage VB.

[0104] Referring to the first broken line L1, the breakdown voltage VB increased with increasing trench potential VI. Similarly, referring to the second broken line L2, the voltage across the second trench structure 12 increased with increasing trench potential VI. On the other hand, referring to the third broken line L3, the differential voltage remained approximately constant regardless of the increase in trench potential VI.

[0105] From these findings, it was found that it is preferable for the inter-trench region 20 to be fixed at an inter-trench potential VI of 0V or higher, rather than being formed in an electrically floating state. Furthermore, it was found that when the voltage of the second trench structure 12 when the inter-trench potential VI is 0V is used as a reference value, the increase in the voltage of the second trench structure 12 from this reference value is added to the breakdown voltage VB. In this configuration, the increase in the voltage of the second trench structure 12 fell within the range of 40% to 50% of the inter-trench potential VI. In other words, a value belonging to the range of 40% to 50% of the inter-trench potential VI was added to the breakdown voltage VB (voltage of the second trench structure 12).

[0106] As described above, the semiconductor device 51 includes an inter-trench region 20 between the first trench structure 11 and the second trench structure 12, to which an inter-trench potential VI of 0V or higher is applied. This structure makes it possible to provide a semiconductor device 51 that can improve the breakdown voltage (specifically, the breakdown voltage VB).

[0107] Figure 9 corresponds to Figure 7 and is a cross-sectional view showing the semiconductor device 53 according to the third embodiment. Hereinafter, the same reference numerals are used for structures corresponding to those described in the first and second embodiments, and their descriptions are omitted.

[0108] The semiconductor device 53 includes a first trench structure 11 electrically connected to the chip 2 (first layer 6), and an inter-trench region 20 formed in an electrically floating state, similar to the first embodiment. In this embodiment, unlike the first embodiment, the semiconductor device 53 includes a second trench structure 12 to which a trench potential VT of 0V or higher is applied. The trench potential VT is applied to the second trench structure 12 from outside the chip 2.

[0109] The trench potential VT is preferably set to any value within a potential range that is 0V or greater and less than or equal to the maximum potential applied to the transistor region 9A (MISFET 30). The trench potential VT is preferably greater than 0V. The trench potential VT is preferably different from the potential applied to the first trench structure 11. The trench potential VT is preferably different from the potential applied to the inter-trench region 20. The inter-trench potential VI is preferably different from the potential applied to the MISFET 30 (transistor region 9B). The potential of the second trench structure 12 is raised to the trench potential VT. When the trench potential VT is applied, a potential gradient that gradually decreases from the first main surface 3 side to the first layer 6 side is formed in the second trench structure 12.

[0110] In this embodiment, the semiconductor device 53 includes a second contact electrode 54 electrically connected to the second trench structure 12 on the chip 2 (second layer 7). In Figure 9, the first contact electrode 52 is shown in a simplified form by a line. The second contact electrode 54 applies a trench potential VT to the second trench structure 12.

[0111] Figure 10 is a graph showing the breakdown voltage VB of the semiconductor device 53 shown in Figure 9. In Figure 10, the vertical axis represents the breakdown voltage VB [V], and the horizontal axis represents the trench potential VT [V]. Here, an arbitrary trench potential VT in the range of 0V to 60V is applied to the second trench structure 12. Also, a potential of 0V is applied to the first layer 6 and the first trench structure 11. The voltage here is the voltage with respect to the potential of the first layer 6 (=0V). The trench potential VT may also be read as the trench voltage with respect to the potential of the first layer 6 (=0V).

[0112] Figure 10 shows a single broken line LA. The single broken line LA represents the breakdown voltage VB of the semiconductor device 53. Referring to the single broken line LA, the breakdown voltage VB increased with increasing trench potential VT. From this, it was found that it is preferable for the second trench structure 12 to be fixed at a trench potential VT of at least 0V rather than being formed in an electrically floating state.

[0113] As described above, the semiconductor device 53 includes a second trench structure 12 to which a trench potential VT of 0V or higher is applied. This structure makes it possible to provide a semiconductor device 53 that can improve the breakdown voltage (specifically, the breakdown voltage VB).

[0114] Figure 11 corresponds to Figure 7 and is a cross-sectional view showing a semiconductor device 55 according to the fourth embodiment. Hereinafter, the same reference numerals are used for structures corresponding to those described in the first to third embodiments, and their descriptions are omitted.

[0115] Referring to Figure 11, the semiconductor device 55 has a structure that combines the semiconductor device 51 according to the second embodiment and the semiconductor device 53 according to the third embodiment. That is, the semiconductor device 55 includes a first trench structure 11 electrically connected to the chip 2 (first layer 6), a second trench structure 12 to which a trench potential VT of 0V or higher is applied, and an inter-trench region 20 to which an inter-trench potential VI of 0V or higher is applied. The semiconductor device 55 also includes a first contact electrode 52 electrically connected to the inter-trench region 20 on the chip 2 (second layer 7), and a second contact electrode 54 electrically connected to the second trench structure 12. In Figure 11, the first contact electrode 52 and the second contact electrode 54 are shown simplified by lines.

[0116] As described above, the semiconductor device 55 provides a breakdown voltage improvement effect using the trench potential VI and a breakdown voltage improvement effect using the trench potential VT. Therefore, a semiconductor device 55 that can improve breakdown voltage (specifically breakdown voltage VB) can be provided.

[0117] Figure 12 corresponds to Figure 3 and is a cross-sectional view showing a semiconductor device 61 according to the fifth embodiment. Figure 13 is an enlarged cross-sectional view of the main part of the structure shown in Figure 12. Hereinafter, the same reference numerals are used for structures corresponding to those described in the first to fourth embodiments, and their descriptions are omitted.

[0118] Referring to Figures 12 and 13, the semiconductor device 61 includes an n-type sidewall buffer layer 62. The sidewall buffer layer 62 protrudes from the intersection 63 of the sidewalls of the third layer 8 and the second trench structure 12 toward the first layer 6 in the device region 9 and extends in a film-like manner along the sidewall of the second trench structure 12. The intersection 63 is also the intersection of the pn junction J and the sidewall of the second trench structure 12.

[0119] The sidewall buffer layer 62 extends from the intersection 63 of the second trench structure 12, which is closest to the device region 9 of the trench separation structure 10, toward the bottom wall of the second trench structure 12. In this configuration, the intersection 63 is formed by the low-density buried layer 8a of the third layer 8 and the second trench structure 12. Therefore, the sidewall buffer layer 62 protrudes from the low-density buried layer 8a toward the bottom wall of the second trench 16.

[0120] In this embodiment, the sidewall buffer layer 62 includes one sidewall buffer layer 62 and the other sidewall buffer layer 62. The one sidewall buffer layer 62 extends from the intersection 63 on the inner circumferential wall side of the second trench structure 12 toward the bottom wall of the second trench structure 12. The other sidewall buffer layer 62 extends from the intersection 63 on the outer circumferential wall side of the second trench structure 12 toward the bottom wall of the second trench structure 12. In this embodiment, the sidewall buffer layer 62 is formed at a distance from the first trench structure 11 that is not adjacent to the device area 9, and is formed only along the second trench structure 12 that is adjacent to the device area 9.

[0121] The sidewall buffer layer 62 is preferably formed at a depth position between the third layer 8 and the bottom wall of the second trench structure 12. The sidewall buffer layer 62 is preferably formed with a gap between the bottom wall of the second trench structure 12 and the third layer 8. The sidewall buffer layer 62 is preferably projected from the intersection 63 into the low-concentration layer 6b. The sidewall buffer layer 62 is preferably formed within the low-concentration layer 6b with a gap between the high-concentration layer 6a and the third layer 8. The sidewall buffer layer 62 has an n-type impurity concentration lower than the p-type impurity concentration of the high-concentration layer 6a. The n-type impurity concentration of the sidewall buffer layer 62 exceeds the p-type impurity concentration of the low-concentration layer 6b.

[0122] The sidewall buffer layer 62 faces the second electrode 18 with the second insulating film 17 interposed therebetween. The sidewall buffer layer 62 is formed on the first main surface 3 side with respect to the depth position of the bottom insulator 19. Therefore, in this form, the sidewall buffer layer 62 faces only the second electrode 18 with the second insulating film 17 interposed therebetween. Of course, a sidewall buffer layer 62 covering the bottom insulator 19 may be formed.

[0123] The sidewall buffer layer 62 has a predetermined region width WB. The region width WB is the width in a direction orthogonal to the direction in which the sidewall buffer layer 62 extends in a plan view. In other words, the region width WB is the width of the sidewall buffer layer 62 that appears when a portion of the second trench structure 12 extending in the first direction X (second direction Y) is cut in the second direction Y (first direction X).

[0124] Preferably, the region width WB is less than the first trench width W1 of the first trench structure 11 (WB < W1). Preferably, the region width WB is less than the second trench width W2 of the second trench structure 12 (WB < W2). Preferably, the region width WB is less than the width of the inter-trench region 20 (trench interval IT) (WB < IT). The region width WB may be greater than 0 μm and less than or equal to 10 μm. Preferably, the region width WB is 3 μm or less.

[0125] In this form, the semiconductor device 61 includes a p-type compensation region 64 (a compensation region) formed in the region on the bottom wall side of the second trench structure 12 in the first layer 6. In FIGS. 12 and 13, the compensation region 64 is indicated by a broken line. The compensation region 64 may be referred to as a "canceling region" or a "canceling compensation region". The compensation region 64 includes both n-type impurities and p-type impurities and is a p-type region having a p-type impurity concentration exceeding the n-type impurity concentration.

[0126] The compensation region 64 is formed along the walls (side walls and bottom walls) of the second trench structure 12 in the region on the bottom wall side of the second trench structure 12, compared to the side wall buffer layer 62 in the first layer 6. In this configuration, the side wall buffer layer 62 is formed by introducing n-type impurities into the chip 2 by ion implantation through the inner wall of the second trench 16. The region width WB of the side wall buffer layer 62 is adjusted by adjusting the amount of n-type impurities introduced through the inner wall of the second trench 16.

[0127] The n-type impurity concentration of the portion of n-type impurities introduced into the high-concentration layer 6a is less than the p-type impurity concentration of the high-concentration layer 6a. Therefore, the n-type impurities introduced into the high-concentration layer 6a are canceled out with the p-type impurities in a manner that maintains the function of the high-concentration layer 6a, forming a p-type compensation region 64 with the high-concentration layer 6a. On the other hand, the n-type impurity concentration of the portion of n-type impurities introduced into the low-concentration layer 6b exceeds the p-type impurity concentration of the low-concentration layer 6b. Therefore, the n-type impurities introduced into the low-concentration layer 6b are canceled out with the p-type impurities in a manner that eliminates the function of the low-concentration layer 6b, replacing the low-concentration layer 6b with the sidewall buffer layer 62.

[0128] The low-concentration layer 6b has a concentration gradient in which the concentration of p-type impurities gradually increases toward the high-concentration layer 6a due to p-type impurities diffused from the high-concentration layer 6a. Therefore, the portion of n-type impurities introduced to the bottom of the low-concentration layer 6b is offset from the high-concentration layer 6a side toward the third layer 8 (low-concentration buried layer 8a) side and cancels out the p-type impurities. As a result, the sidewall buffer layer 62 is formed within the low-concentration layer 6b with a gap between it and the third layer 8 (low-concentration buried layer 8a) side. On the other hand, the compensation region 64 is formed from the middle of the thickness direction of the low-concentration layer 6b along the sidewall and bottom wall of the second trench structure 12. The compensation region 64 may be connected to the impurity region 22 at its lower end.

[0129] The sidewall buffer layer 62 forms a pn-junction expansion portion JE that extends the pn junction J with the first layer 6 (specifically, the low-density layer 6b). In other words, the semiconductor device 61 includes a pn-junction expansion portion JE that is drawn out from the intersection 63 towards the bottom wall side of the second trench structure 12, so as to extend a part of the pn junction J within the chip 2 (transistor region 9A) towards the bottom wall side of the second trench structure 12. The pn-junction expansion portion JE may also be called a "pn-connection expansion portion" or a "pn-boundary expansion portion". The pn-junction expansion portion JE is synonymous with "sidewall buffer layer 62". The explanation of "pn-junction expansion portion JE" can be obtained by replacing "sidewall buffer layer 62" with "pn-junction expansion portion JE".

[0130] Figure 14 is a graph showing the breakdown voltage VB of the semiconductor device 61 shown in Figure 12. In Figure 14, the vertical axis represents the breakdown voltage VB [V], and the horizontal axis represents the region width WB [μm]. Figure 14 shows a single piecewise line LB. The single piecewise line LB represents the breakdown voltage VB of the semiconductor device 61. Here, the region width WB is adjusted within the range of 0 μm to 2 μm. Also, a potential of 0V is applied to the first layer 6 and the first trench structure 11. The voltage here is the voltage relative to the potential of the first layer 6 (=0V).

[0131] Referring to a single piecewise curve LB, the breakdown voltage VB increased with increasing region width WB. This indicates that the formation of the pn junction extension JE (sidewall buffer layer 62) is preferable. This is because the electric field concentration at the intersection 63 is mitigated by the pn junction extension JE (sidewall buffer layer 62).

[0132] As described above, the semiconductor device 61 includes a pn junction extension JE that extends from the intersection 63 of the pn junction J and the side wall of the second trench structure 12 toward the bottom wall of the second trench structure 12, so as to extend the pn junction J in the transistor region 9A (device region 9). With this structure, electric field concentration at the intersection 63 can be mitigated by the pn junction extension JE. Therefore, a semiconductor device 61 that can improve breakdown voltage (specifically breakdown voltage VB) can be provided.

[0133] Alternatively, the semiconductor device 61 includes an n-type sidewall buffer layer 62 that protrudes from the intersection 63 of the third layer 8 and the second trench structure 12 toward the first layer 6 in the device region 9 and extends along the sidewall of the second trench structure 12. This structure allows the electric field concentration at the intersection 63 to be mitigated by the sidewall buffer layer 62. Thus, a semiconductor device 61 with improved breakdown voltage (specifically, breakdown voltage VB) can be provided.

[0134] Of course, features of the second to fourth embodiments may be combined in the semiconductor device 61. That is, the semiconductor device 61 may include a second trench structure 12 to which a trench potential VT of 0V or higher is applied. The semiconductor device 61 may also include an inter-trench region 20 to which an inter-trench potential VI of 0V or higher is applied.

[0135] Figure 15 is a cross-sectional view corresponding to Figure 12, showing a semiconductor device 65 according to the sixth embodiment. The semiconductor device 65 has a modified form of the semiconductor device 61. Hereinafter, the same reference numerals are used for structures corresponding to those described in the first to fifth embodiments, and their descriptions are omitted.

[0136] In semiconductor device 61, the sidewall buffer layer 62 was formed only along the second trench structure 12. In contrast, referring to Figure 15, semiconductor device 65 includes a plurality of sidewall buffer layers 62 along the first trench structure 11 and the second trench structure 12. One sidewall buffer layer 62 is formed along the second trench structure 12 in the same manner as in the fifth embodiment, and the other sidewall buffer layer 62 is formed along the first trench structure 11 in the same manner as the other sidewall buffer layer 62.

[0137] A detailed explanation of the sidewall buffer layer 62 on the first trench structure 11 side can be obtained by replacing "second trench structure 12" with "first trench structure 11" in the description of the semiconductor device 61 mentioned above. The sidewall buffer layer 62 on the second trench structure 12 side may be integrated with the sidewall buffer layer 62 on the first trench structure 11 side in the inter-trench region 20. In summary, the semiconductor device 65 also produces the same effects as those described for the semiconductor device 61.

[0138] Figure 16 corresponds to Figure 12 and is a cross-sectional view showing a semiconductor device 66 according to the seventh embodiment. The semiconductor device 66 has a modified form of the semiconductor device 61. Hereinafter, the same reference numerals are used for structures corresponding to the structures described in the first to sixth embodiments, and their descriptions are omitted.

[0139] In semiconductor device 61, the trench separation structure 10 included a first trench structure 11 and a second trench structure 12, and the sidewall buffer layer 62 was formed along the second trench structure 12. In contrast, referring to Figure 16, in semiconductor device 66, the trench separation structure 10 does not have a second trench structure 12 and includes only the first trench structure 11, and the sidewall buffer layer 62 is formed only along the first trench structure 11. A specific explanation of the sidewall buffer layer 62 can be obtained by replacing "second trench structure 12" with "first trench structure 11" in the above explanation of semiconductor device 61. Thus, semiconductor device 66 also produces the same effects as semiconductor device 61.

[0140] In the fifth to seventh embodiments, an example was described in which the sidewall buffer layer 62 was formed by introducing n-type impurities into the interior of the chip 2 by ion implantation through the inner wall of the first trench 13 and / or the inner wall of the second trench 16. However, the sidewall buffer layer 62 may also be introduced into the interior of the chip 2 by ion implantation through the first main surface 3 before the formation of the first trench 13 and / or the second trench 16.

[0141] The first trench 13 and / or the second trench 16 are formed in the first main surface 3 after the step of forming the sidewall buffer layer 62, so as to penetrate the sidewall buffer layer 62. In this step, the compensation region 64 according to the fifth to seventh embodiments is not formed. In this case, the sidewall buffer layer 62 may be connected to the high-concentration layer 6a of the first layer 6, or it may be formed at a distance from the high-concentration layer 6a toward the third layer 8. The sidewall buffer layer 62 may be formed at the same time as the sinker region 21.

[0142] Figure 17 corresponds to Figure 3 and is a cross-sectional view showing a semiconductor device 71 according to the eighth embodiment. Hereinafter, the same reference numerals are used for structures corresponding to those described in the first to seventh embodiments, and their descriptions are omitted.

[0143] Referring to Figure 17, the semiconductor device 71 includes a first layer 6, a second layer 7, a third layer 8, a transistor region 9A (device region 9), a trench isolation structure 10 (trench structure), and a MISFET 30, similar to the first embodiment. In this embodiment, the second layer 7 is directly stacked on top of the first layer 6. In this embodiment, the third layer 8 is formed in the transistor region 9A, spaced apart from the trench isolation structure 10 (second trench structure 12 in this embodiment), and straddles the boundary between the first layer 6 and the second layer 7. The third layer 8 forms a pn junction J with the first layer 6.

[0144] The third layer 8 includes a low-concentration embedding layer 8a and a high-concentration embedding layer 8b, similar to the first embodiment. The low-concentration embedding layer 8a is formed in the region on the first layer 6 side with respect to the boundary between the first layer 6 and the second layer 7. Specifically, the low-concentration embedding layer 8a is formed within the low-concentration layer 6b with a gap from the boundary between the low-concentration layer 6b and the second layer 7 of the first layer 6 with respect to the thickness direction of the chip 2. The low-concentration embedding layer 8a is formed within the low-concentration layer 6b with a gap from the high-concentration layer 6a of the first layer 6 towards the second layer 7 with respect to the thickness direction of the chip 2. The low-concentration embedding layer 8a is formed with a gap from the second trench structure 12 with respect to the width direction of the device region 9. The low-concentration embedding layer 8a forms a pn junction J with the first layer 6 (high-concentration layer 6a).

[0145] The high-concentration burial layer 8b is formed to straddle the boundary between the first layer 6 and the second layer 7. Specifically, the high-concentration burial layer 8b is interposed between the low-concentration burial layer 8a and the second layer 7, straddling the boundary between the low-concentration layer 6b and the second layer 7 of the first layer 6, and is electrically connected to the low-concentration burial layer 8a and the second layer 7. The high-concentration burial layer 8b is formed at a distance from the second trench structure 12 with respect to the width direction of the device region 9.

[0146] The third layer 8 (low-concentration buried layer 8a and high-concentration buried layer 8b) is formed with a predetermined region interval IR (a region interval) from the trench separation structure 10 (second trench structure 12). In other words, the third layer 8 exposes the first layer 6 between itself and the trench separation structure 10. The region interval IR may be greater than 0 μm and less than or equal to 10 μm. Preferably, the region interval IR is 5 μm or less.

[0147] In this embodiment, the aforementioned sinker region 21 is formed in the region between the third layer 8 and the trench separation structure 10 (second trench structure 12) in a plan view. Preferably, the sinker region 21 is formed with a gap between it and the trench separation structure 10 (second trench structure 12) in a plan view. In other words, it is preferable that the sinker region 21 is not connected to the third layer 8. The lower end of the sinker region 21 may be connected to the first layer 6, or it may be formed within the second layer 7 with a gap between it and the first layer 6.

[0148] Figure 18 is a graph showing the breakdown voltage VB of the semiconductor device 71 shown in Figure 17. In Figure 18, the vertical axis represents the breakdown voltage VB [V], and the horizontal axis represents the region spacing IR [μm]. Here, the region spacing IR is adjusted within the range of 0 μm to 5 μm. Here, a potential of 0 V is applied to the first layer 6 and the first trench structure 11. The voltage here is the voltage relative to the potential of the first layer 6 (=0 V).

[0149] Figure 18 shows a single piecewise linear LC. The single piecewise linear LC represents the breakdown voltage VB of the semiconductor device 71. Referring to the single piecewise linear LC, the breakdown voltage VB increased with increasing region spacing IR. This is because the electric field concentration with respect to the second trench structure 12 was mitigated by forming the third layer 8 in a setback manner relative to the second trench structure 12.

[0150] As described above, the semiconductor device 71 includes a p-type first layer 6, a p-type or n-type second layer 7, a transistor region 9A (device region 9), a trench isolation structure 10 (trench structure), and an n-type third layer 8 (embedded layer). The second layer 7 is stacked on top of the first layer 6. The transistor region 9A is provided in the second layer 7. The trench isolation structure 10 penetrates the third layer 8 to reach the first layer 6, and partitions the transistor region 9A in the third layer 8. The third layer 8 is formed to straddle the boundary between the first layer 6 and the third layer 8, spaced apart from the trench isolation structure 10 in the transistor region 9A. This structure makes it possible to provide a semiconductor device 71 that can improve breakdown voltage (specifically, breakdown voltage VB).

[0151] Specifically, the trench isolation structure 10 has a multi-trench structure that includes a plurality of trench structures, each formed penetrating the second layer 7 to reach the first layer 6, and arranged at intervals away from the transistor region 9A in the second layer 7 to partition the transistor region 9A.

[0152] In this embodiment, the multiple trench structures include a first trench structure 11 and a second trench structure 12. The first trench structure 11 is electrically connected to the first layer 6 and electrically isolated from the second layer 7. The second trench structure 12 is electrically isolated from both the first layer 6 and the second layer 7. In this embodiment, the third layer 8 is formed at a distance from the second trench structure 12. The breakdown voltage (specifically the breakdown voltage VB) of the semiconductor device 71 is increased by such a structure.

[0153] Figure 19 is a cross-sectional view corresponding to Figure 17, showing a semiconductor device 72 according to the ninth embodiment. The semiconductor device 72 has a modified form of the semiconductor device 71. Hereinafter, the same reference numerals are used for structures corresponding to those described in the first to eighth embodiments, and their descriptions are omitted.

[0154] In the semiconductor device 71, the trench isolation structure 10 has the first trench structure 11 and the second trench structure 12, and the third layer 8 was formed at an interval from the second trench structure 12. On the other hand, referring to FIG. 19, in the semiconductor device 72, the trench isolation structure 10 does not have the second trench structure 12 and includes only the first trench structure 11, and the third layer 8 is formed at an interval from the first trench structure 11. A specific description of the third layer 8 can be obtained by replacing "the second trench structure 12" with "the first trench structure 11" in the description of the semiconductor device 71 described above. As described above, the semiconductor device 72 can also achieve the same effects as those described for the semiconductor device 71.

[0155] FIG. 20 corresponds to FIG. 4 and is a cross-sectional view showing a semiconductor device 81 according to the tenth embodiment together with a trench structure according to the first configuration example. Hereinafter, the same reference numerals are given to the structures corresponding to the structures described in the first to ninth embodiments, and the description thereof is omitted.

[0156] Referring to FIG. 20, in the semiconductor device 81, the second trench structure 12 is formed so as to penetrate the pn junction J at a depth position shallower than the first trench structure 11. Specifically, the second trench structure 12 penetrates the second layer 7 and the third layer 8 so as to reach the first layer 6 at a depth position shallower than the first trench structure 11. The first trench structure 11 protrudes at a first value P1 from the pn junction J toward the second main surface 4 side. On the other hand, the second trench structure 12 protrudes at a second value P2 (P2 < P1) less than the first value P1 from the pn junction J toward the second main surface 4 side. Other descriptions of the second trench structure 12 according to this embodiment are applicable to the description of the second trench structure 12 according to the first embodiment.

[0157] In this embodiment, the impurity region 22 described above is formed at an interval from the bottom wall of the second trench structure 12 toward the bottom wall side of the first trench structure 11. Therefore, the impurity region 22 does not cover the bottom wall of the second trench structure 12. The impurity region 22 may face the bottom wall of the second trench structure 12 across a part of the first layer 6 (high-concentration layer 6a) in the thickness direction of the first layer 6.

[0158] The second trench structure 12 can take on a form other than that shown in Figure 20. Other configuration examples of the second trench structure 12 are shown below with reference to Figures 21A and 21B. Figure 21A is a cross-sectional view showing the cross-sectional structure shown in Figure 20 together with the second trench structure 12 according to the second configuration example. Hereafter, the same reference numerals are used for structures corresponding to those described in Figure 20, and their descriptions are omitted.

[0159] Referring to Figure 21A, a second trench structure 12 without a bottom insulator 19 may be adopted. In other words, the second trench structure 12 may include a second insulating film 17 that covers the inner walls (inner peripheral wall, outer peripheral wall, and bottom wall) of the second trench 16 with a substantially uniform thickness. In this case, it is preferable that the second insulating film 17 has a thickness of less than half the width W2 of the second trench of the second trench structure 12. The thickness of the second insulating film 17 is the thickness along the direction normal to the wall surface of the second trench structure 12 (second trench 16).

[0160] It is particularly preferable that the thickness of the second insulating film 17 is less than half the width of the bottom wall of the second trench structure 12. The width of the bottom wall of the second trench structure 12 is the width in the direction perpendicular to the direction in which the second trench structure 12 extends in a plan view. Under this condition, the second trench width W2 may be greater than or equal to the first trench width W1 of the first trench structure 11 (W1 ≤ W2), or less than the first trench width W1 (W1 > W2).

[0161] Figure 21B is a cross-sectional view showing the cross-sectional structure shown in Figure 20 together with the second trench structure 12 relating to the third configuration example. Hereafter, the same reference numerals are used for structures corresponding to the structure described in Figure 20, and their descriptions are omitted.

[0162] Referring to Figure 21B, a second trench structure 12 without a second electrode 18 may be adopted. In other words, the second trench structure 12 may include a second insulating film 17 embedded in the second trench 16 as an integrated member. In this case, the second trench structure 12 may be called a "trench insulating structure". Under these conditions, the second trench width W2 may be greater than or equal to the first trench width W1 of the first trench structure 11 (W1 ≤ W2), or less than the first trench width W1 (W1 > W2).

[0163] Figure 22 is a graph showing the breakdown voltage VB of the semiconductor device 81 shown in Figure 20, along with the breakdown voltage VB of a semiconductor device related to a reference example. In Figure 22, the vertical axis represents the breakdown voltage VB [V], and the horizontal axis represents the item (semiconductor device being measured). Here, a potential of 0V is applied to the first layer 6 and the first trench structure 11. The voltage here is the voltage relative to the potential of the first layer 6 (=0V).

[0164] Figure 22 shows the first bar graph GA and the second bar graph GB. The first bar graph GA shows the breakdown voltage VB of the semiconductor device according to the reference example. The second bar graph GB shows the breakdown voltage VB of the semiconductor device 81. The semiconductor device according to the reference example has the same structure as the semiconductor device 81, except that it does not have the second trench structure 12. A description of the semiconductor device according to the reference example is omitted.

[0165] Referring to the first and second bar graphs GA to GB, the breakdown voltage VB increased by forming a second trench structure 12 that was shallower than the first trench structure 11. From this, it was found that even when a second trench structure 12 shallower than the first trench structure 11 is formed, the breakdown voltage VB improves.

[0166] Compared to the second trench structure 12 in semiconductor device 1 (see Figures 3 and 4), the second trench structure 12 in semiconductor device 81 reduces the opposing area between the first layer 6 and the second electrode 18 (i.e., the parasitic capacitance of the second trench structure 12). Therefore, even when a second trench structure 12 shallower than the first trench structure 11 is formed, the breakdown voltage VB increases. The parasitic capacitance of the second trench structure 12 is also reduced when the configurations shown in Figures 21A and 21B are applied. Therefore, the breakdown voltage VB also increases in the cases of Figures 21A and 21B.

[0167] As described above, the semiconductor device 81 has a second trench structure 12 that is shallower than the first trench structure 11. This structure makes it possible to provide a semiconductor device 81 that can improve the breakdown voltage (specifically, the breakdown voltage VB).

[0168] Hereinafter, with reference to Figures 23 to 27, modified examples applicable to the first to tenth embodiments are shown. Figure 23 is a cross-sectional view showing a first modified example of the chip 2 according to the first to tenth embodiments. Here, an example in which the chip 2 according to the first modified example is applied to the semiconductor device 1 according to the first embodiment is described, but the chip 2 according to the first modified example can also be applied to the second to tenth embodiments. Hereinafter, the same reference numerals are used for structures corresponding to the structures described in the first to tenth embodiments, and their descriptions are omitted.

[0169] In the first embodiment, the first layer 6 had a laminated structure including a high-concentration layer 6a and a low-concentration layer 6b. However, as shown in Figure 23, the chip 2 may include a first layer 6 having a single-layer structure. The first layer 6 may be made of a p-type semiconductor substrate. In this case, the first layer 6 may have the impurity concentration of the high-concentration layer 6a or the impurity concentration of the low-concentration layer 6b. In this case as well, the pn junction J is formed at the boundary between the first layer 6 and the third layer 8 (low-concentration embedded layer 8a).

[0170] Figure 24 is a cross-sectional view showing a second modified example of the chip 2 according to the first to tenth embodiments. An example in which the chip 2 according to the second modified example is applied to the semiconductor device 1 according to the first embodiment will be described, but the chip 2 according to the second modified example can also be applied to the second to tenth embodiments. Hereinafter, the same reference numerals are used for structures corresponding to the structures described in the first to tenth embodiments, and their descriptions will be omitted.

[0171] In the first embodiment, the third layer 8 had a laminated structure including a low-concentration burial layer 8a and a high-concentration burial layer 8b. However, as shown in Figure 24, the chip 2 may include a third layer 8 having a single-layer structure. In this case, the third layer 8 may have the impurity concentration of the low-concentration burial layer 8a or the impurity concentration of the high-concentration burial layer 8b. In this case as well, the pn junction J is formed at the boundary between the first layer 6 (low-concentration layer 6b) and the third layer 8. When an n-type second layer 7 is applied, the second layer 7 may have a lower impurity concentration than the third layer 8.

[0172] Figure 25 is a cross-sectional view showing a third modified example of the chip 2 according to the first to tenth embodiments. Here, an example in which the chip 2 according to the third modified example is applied to the semiconductor device 1 according to the first embodiment will be described, but the chip 2 according to the third modified example can also be applied to the second to tenth embodiments. Hereafter, the same reference numerals are used for structures corresponding to the structures described in the first to tenth embodiments, and their descriptions will be omitted.

[0173] In the first embodiment, an n-type second layer 7 (n-type epitaxial layer) was formed. However, as shown in Figure 25, the chip 2 may also include a p-type second layer 7 (p-type epitaxial layer). When a p-type second layer 7 is used, the structure within the transistor region 9A is adjusted accordingly. An example of the structure within the transistor region 9A is described below.

[0174] In this embodiment, the semiconductor device 1 includes a p-type isolation region 92 as an example of a region isolation structure that partitions the cell region 91 in the transistor region 9A. The isolation region 92 is formed in a plan view, spaced inward from the inner peripheral wall of the second trench structure 12. The isolation region 92 is formed in a cylindrical shape that surrounds the inner part of the second layer 7 from the bottom side to the surface side. In this embodiment, the isolation region 92 includes a p-type embedded region 93 and a p-type column region 94.

[0175] The buried area 93 is formed at the boundary between the third layer 8 (specifically, the high-density buried layer 8b) and the second layer 7. The buried area 93 is formed at a distance inward from the inner circumferential wall of the second trench structure 12, and a portion of the third layer 8 is exposed between it and the second trench structure 12. The column area 94 is formed in the second layer 7 in the region between the first main surface 3 and the periphery of the buried area 93, and is electrically connected to the buried area 93. The number of stacked column areas 94 is arbitrary, and two or more column areas 94 may be stacked from the buried area 93 side to the first main surface 3 side.

[0176] The aforementioned sinker region 21 is formed in the transistor region 9A in the region between the second trench structure 12 and the isolation region 92. The sinker region 21 is formed within the second layer 7 and extends along the side wall of the second trench structure 12. In this configuration, the sinker region 21 is formed as a film that extends only along the inner circumferential wall of the second trench structure 12. In a plan view, the sinker region 21 extends along the inner circumferential wall of the second trench structure 12 and is formed in an annular shape surrounding the isolation region 92. The lower end of the sinker region 21 is electrically connected to the third layer 8 (high-concentration buried layer 8b).

[0177] The aforementioned MISFET 30 is formed in the same manner as in the first embodiment within the cell region 91 partitioned by the isolation region 92. In this embodiment, the channel region 35 is formed in the surface portion of the second layer 7 in the region between the first well region 31 and the source region 34. Further description of the MISFET 30 is omitted as the description of the MISFET 30 according to the first embodiment applies.

[0178] Figure 26 is a cross-sectional view showing a fourth modified example of the chip 2 according to the first to tenth embodiments. Here, an example in which the chip 2 according to the fourth modified example is applied to the semiconductor device 1 according to the first embodiment will be described, but the chip 2 according to the fourth modified example can also be applied to the second to tenth embodiments. Hereafter, the same reference numerals are used for structures corresponding to the structures described in the first to tenth embodiments, and their descriptions will be omitted.

[0179] In the first embodiment, an example was described in which the chip 2 includes a first layer 6, a second layer 7, and a third layer 8. However, as shown in Figure 26, a chip 2 may be adopted that includes a p-type first layer 6 and an n-type second layer 7, but does not include a third layer 8. In this embodiment, the second layer 7 forms a pn junction J with the first layer 6. Of course, the chip 2 may also include a first layer 6 having a single-layer structure. In this case, the first layer 6 may have the impurity concentration of a high-concentration layer 6a or the impurity concentration of a low-concentration layer 6b.

[0180] The features of the chip 2 according to the first to fourth modifications can be combined in any manner among them. Therefore, a chip 2 having at least two of the features of the chip 2 according to the first to fourth modifications simultaneously may be combined with any one of the first to tenth embodiments.

[0181] Figure 27 is a cross-sectional view showing a modified example of the sinker region 21 according to the first to tenth embodiments. Here, an example in which the modified sinker region 21 is applied to the semiconductor device 1 according to the first embodiment will be described, but the modified sinker region 21 can also be applied to the second to tenth embodiments. Hereafter, the same reference numerals are used for structures corresponding to the structures described in the first to tenth embodiments, and their descriptions will be omitted.

[0182] In the first embodiment, a configuration example was described in which the sinker region 21 covers only the second trench structure 12. However, as shown in Figure 27, the sinker region 21 may cover the first trench structure 11 in addition to the second trench structure 12. The sinker region 21 is formed along either the inner circumferential wall or the outer circumferential wall of the first trench structure 11, or both (both in this embodiment). The sinker region 21 covering the inner circumferential wall of the first trench structure 11 may be integrated with the sinker region 21 covering the outer circumferential wall of the second trench structure 12 in the inter-trench region 20.

[0183] Each of the embodiments described above can be implemented in other forms. In each of the embodiments described above, an example configuration was described in which the trench isolation structure 10 partitions the transistor region 9A. However, the device region 9 partitioned by the trench isolation structure 10 is not limited to the transistor region 9A. In other words, the trench isolation structure 10 may partition any device region 9 in which at least one of a semiconductor switching device, a semiconductor rectifier device, and a passive device is formed, not limited to the transistor region 9A.

[0184] In each of the embodiments described above, the trench separation structure 10 may include any number of first trench structures 11 and any number of second trench structures 12. That is, the trench separation structure 10 may include a plurality of first trench structures 11 and a plurality of second trench structures 12. The trench separation structure 10 may include a single first trench structure 11 and a plurality of second trench structures 12. The trench separation structure 10 may include a plurality of first trench structures 11 and a single second trench structure 12.

[0185] If the trench isolation structure 10 includes a plurality of first trench structures 11, the plurality of first trench structures 11 may be formed spaced apart from each other (e.g., trench spacing IT) so as to surround the device region 9. If the trench isolation structure 10 includes a plurality of second trench structures 12, the plurality of second trench structures 12 may be formed spaced apart from each other (e.g., trench spacing IT) in the region between the device region 9 and the first trench structures 11 so as to surround the device region 9.

[0186] In the embodiments described above, an example was given in which the first conductivity type is p-type and the second conductivity type is n-type. However, the first conductivity type may be n-type and the second conductivity type may be p-type. The specific configuration in this case can be obtained by replacing the n-type region with a p-type region and the p-type region with an n-type region in the above description and attached drawings. In the embodiments described above, an example was given in which the p-type was expressed as "first conductivity type" and the n-type as "second conductivity type." However, these terms are used to clarify the order of the explanation, and the p-type may be expressed as "second conductivity type" and the n-type as "first conductivity type."

[0187] The features of the first to tenth embodiments described above can be combined in any manner. Therefore, a semiconductor device having at least two of the features of the first to tenth embodiments simultaneously may be employed.

[0188] In other words, the features of the second embodiment may be combined with the features of the first embodiment. Also, the features of the third embodiment may be combined with any one of the features of the first to second embodiments. Also, the features of the fourth embodiment may be combined with any one of the features of the first to third embodiments. Also, the features of the fifth embodiment may be combined with any one of the features of the first to fourth embodiments. Also, the features of the sixth embodiment may be combined with any one of the features of the first to fifth embodiments.

[0189] Furthermore, the features of the seventh embodiment may be combined with any one of the features of the first to sixth embodiments. Also, the features of the eighth embodiment may be combined with any one of the features of the first to seventh embodiments. Furthermore, the features of the ninth embodiment may be combined with any one of the features of the first to eighth embodiments. Furthermore, the features of the tenth embodiment may be combined with any one of the features of the first to ninth embodiments.

[0190] The following are examples of features extracted from this specification and drawings. [A1] to [A20], [B1] to [B20], [C1] to [C22], and [D1] to [D20] below provide semiconductor devices capable of improved voltage resistance. The alphanumeric characters in parentheses below represent corresponding components in the embodiments described above, but this is not intended to limit the scope of each item to the embodiments.

[0191] [A1] A semiconductor device (1, 51, 53, 55, 61, 65, 66, 71, 72, 81 (hereinafter simply referred to as "1 etc.")) comprising: a chip (2) having a first main surface (3) on one side and a second main surface (4) on the other side; a pn junction (J) formed inside the chip (2) so as to extend along the first main surface (3); a device region (9, 9A) provided on the first main surface (3); a first trench structure (11) formed on the first main surface (3) so as to penetrate the pn junction (J) and defining the device region (9, 9A) on the first main surface (3); and a second trench structure (12) formed on the first main surface (3) so as to penetrate the pn junction (J) and defining the device region (9, 9A) in a region closer to the device region (9, 9A) than the first trench structure (11).

[0192] [A2] The semiconductor device (1, etc.) according to A1, wherein the first trench structure (11) consists of a first trench electrode structure (11) electrically connected to the chip (2), and the second trench structure (12) consists of a second trench electrode structure (12) electrically insulated from the chip (2).

[0193] [A3] The semiconductor device (1, etc.) according to A1 or A2, wherein the first trench structure (11) has a lower end that is electrically connected to the chip (2).

[0194] [A4] The semiconductor device (1, etc.) described in any one of A1 to A3, wherein the second trench structure (12) is electrically isolated from the first trench structure (11).

[0195] [A5] The second trench structure (12) is formed in an electrically floating state, as described in any one of A1 to A4 (e.g., semiconductor device (1, etc.).

[0196] [A6] A semiconductor device (1, etc.) according to any one of A1 to A5, wherein a potential different from that of the first trench structure (11) is generated in the second trench structure (12).

[0197] [A7] The semiconductor device (1, etc.) according to any one of A1 to A6, wherein the first trench structure (11) has a first width (W1), and the second trench structure (12) has a second width (W2) that is less than or equal to the first width (W1).

[0198] [A8] The semiconductor device (1, etc.) described in A7, wherein the second trench structure (12) is formed at a distance (IT) of the first width (W1) or less from the first trench structure (11).

[0199] [A9] The semiconductor device (1, etc.) according to any one of A1 to A8, wherein the first trench structure (11) includes a first trench (13) penetrating the pn junction (J), a first insulating film (14) covering the inner wall of the first trench (13) such that the chip (2) is exposed from the bottom wall of the first trench (13), and a first electrode (15) embedded in the first trench (13) with the first insulating film (14) in between and electrically connected to the chip (2) at the bottom wall of the first trench (13); and the second trench structure (12) includes a second trench (16) penetrating the pn junction (J), a second insulating film (17) covering the inner wall of the second trench (16), and a second electrode (18) embedded in the second trench (16) with the second insulating film (17) in between and electrically insulated from the chip (2).

[0200] [A10] The semiconductor device (1, etc.) according to A9, wherein the second trench structure (12) is embedded on the bottom wall side of the second trench (16) so as to be continuous with the second insulating film (17) and includes a bottom insulator (19) having a thickness exceeding the thickness of the second insulating film (17), and the second electrode (18) is embedded in the second trench (16) with the second insulating film (17) and the bottom insulator (19) in between.

[0201] [A11] The first trench structure (11) further includes: a first layer (6) of a first conductivity type formed in the region on the second main surface (4) side within the chip (2); a second layer (7) of a first or second conductivity type formed in the region on the first main surface (3) side within the chip (2); and a third layer (8) of a second conductivity type interposed in the region between the first layer (6) and the second layer (7) within the chip (2) and forming the pn junction (J) with the first layer (6), wherein the first trench structure (11) is formed in the region on the second main surface (6) A semiconductor device (1, etc.) according to any one of A1 to A10, wherein the second trench structure (12) penetrates the second layer (7) and the third layer (8) to reach the first layer (6), and partitions the device region (9, 9A) in the second layer (7), and the second trench structure (12) penetrates the second layer (7) and the third layer (8) to reach the first layer (6), and partitions the device region (9, 9A) in the region of the second layer (7) that is closer to the device region (9, 9A) than the first trench structure (11) in the second layer (7).

[0202] [A12] The semiconductor device (1, etc.) according to A11, wherein the first trench structure (11) is electrically connected to the first layer (6) and electrically insulated from the second layer (7) and the third layer (8), and the second trench structure (12) is electrically insulated from the first layer (6), the second layer (7), and the third layer (8).

[0203] [A13] A semiconductor device (1, etc.) according to any one of A1 to A10, further comprising: a first layer (6) of a first conductivity type formed in the region on the second main surface (4) side within the chip (2); and a second layer (7) of a second conductivity type formed in the region on the first main surface (3) side within the chip (2) and forming a pn junction (J) with the first layer (6), wherein the first trench structure (11) penetrates the second layer (7) to reach the first layer (6) and partitions the device region (9, 9A) in the second layer (7); and the second trench structure (12) penetrates the second layer (7) to reach the first layer (6) and partitions the device region (9, 9A) in the region of the second layer (7) that is closer to the device region (9, 9A) than the first trench structure (11).

[0204] [A14] The semiconductor device (1, etc.) according to A13, wherein the first trench structure (11) is electrically connected to the first layer (6) and electrically insulated from the second layer (7), and the second trench structure (12) is electrically insulated from the first layer (6) and the second layer (7).

[0205] [A15] A semiconductor device (1, etc.) according to any one of A1 to A14, further comprising an inter-trench region (20) partitioned in the region between the first trench structure (11) and the second trench structure (12) and formed in an electrically floating state.

[0206] [A16] A semiconductor device (1, etc.) according to any one of A1 to A15, further comprising a transistor (30) formed in the device region (9, 9A).

[0207] [A17] A semiconductor device (1, etc.) comprising: a first layer (6) of a first conductivity type; a second layer (7) of a first or second conductivity type laminated on the first layer (6); a third layer (8) of a second conductivity type interposed between the first layer (6) and the second layer (7); a device region (9, 9A) provided on the second layer (7); a first trench structure (11) that penetrates the second layer (7) and the third layer (8) to reach the first layer (6) and demarcates the device region (9, 9A) in the second layer (7); and a second trench structure (12) that penetrates the second layer (7) and the third layer (8) to reach the first layer (6) and demarcates the device region (9, 9A) in the second layer (7) in a region closer to the device region (9, 9A) than the first trench structure (11).

[0208] [A18] The semiconductor device (1, etc.) according to A17, wherein the first trench structure (11) consists of a first trench electrode structure (11) electrically connected to the first layer (6) and electrically insulated from the second layer (7) and the third layer (8), and the second trench structure (12) consists of a second trench electrode structure (12) electrically insulated from the first layer (6), the second layer (7) and the third layer (8).

[0209] [A19] A semiconductor device (1, etc.) comprising: a first layer (6) of a first conductivity type; a second layer (7) of a second conductivity type laminated on the first layer (6); a device region (9, 9A) provided in the second layer (7); a first trench structure (11) that penetrates the second layer (7) to reach the first layer (6) and demarcates the device region (9, 9A) in the second layer (7); and a second trench structure (12) that penetrates the second layer (7) to reach the first layer (6) and demarcates the device region (9, 9A) in the region of the second layer (7) that is closer to the device region (9, 9A) than the first trench structure (11).

[0210] [A20] The semiconductor device (1, etc.) according to A19, wherein the first trench structure (11) consists of a first trench (13) electrode structure electrically connected to the first layer (6) and electrically insulated from the second layer (7), and the second trench structure (12) consists of a second trench (16) electrode structure electrically insulated from the first layer (6) and the second layer (7).

[0211] [B1] A chip (2) having a first main surface (3) on one side and a second main surface (4) on the other side; a pn junction (J) formed inside the chip (2) so as to extend along the first main surface (3); a device region (9, 9A) provided on the first main surface (3); a first trench structure (11) formed on the first main surface (3) so as to penetrate the pn junction (J) and partitioning the device region (9, 9A) on the first main surface (3); and the pn junction (J) A semiconductor device (51, 53, 55 (hereinafter simply referred to as "51 etc.")) comprising: a second trench structure (12) formed on the first main surface (3) so as to penetrate the first trench structure (11) and partitioning the device region (9, 9A) in a region on the side of the device region (9, 9A) that is closer to the first trench structure (11); and an inter-trench region (20) partitioned in the region between the first trench structure (11) and the second trench structure (12), to which a potential (VI) of 0V or higher is applied.

[0212] [B2] The semiconductor device (51, etc.) according to B1, wherein a potential (VI) different from that of the first trench structure (11) is applied to the inter-trench region (20).

[0213] [B3] A semiconductor device (51, etc.) according to B1 or B2, wherein a potential (VI) different from that of the second trench structure (12) is applied to the inter-trench region (20).

[0214] [B4] The semiconductor device (51, etc.) described in any one of B1 to B3, wherein the second trench structure (12) is electrically isolated from the first trench structure (11).

[0215] [B5] The second trench structure (12) is formed in an electrically floating state, as described in any one of B1 to B4 (e.g., semiconductor device (51, etc.)).

[0216] [B6] A semiconductor device (51, etc.) according to any one of B1 to B4, wherein a potential (VT) different from that of the first trench structure (11) is applied to the second trench structure (12).

[0217] [B7] A semiconductor device (51, etc.) according to any one of B1 to B6, further comprising a contact electrode (52) electrically connected to the trench region (20).

[0218] [B8] A semiconductor device (51, etc.) comprising: a chip (2) having a first main surface (3) on one side and a second main surface (4) on the other side; a pn junction (J) formed inside the chip (2) so as to extend along the first main surface (3); a device region (9, 9A) provided on the first main surface (3); a first trench structure (11) formed on the first main surface (3) so as to penetrate the pn junction (J) and defining the device region (9, 9A) on the first main surface (3); and a second trench structure (12) formed on the first main surface (3) so as to penetrate the pn junction (J), defining the device region (9, 9A) in a region closer to the device region (9, 9A) than the first trench structure (11), and to which a different potential (VT) than that of the first trench structure (11) is applied.

[0219] [B9] The semiconductor device (51, etc.) described in B8, wherein a potential (VT) of 0V or higher is applied to the second trench structure (12).

[0220] [B10] The semiconductor device (51, etc.) according to B8 or B9, further comprising a contact electrode (54) electrically connected to the second trench structure (12).

[0221] [B11] The semiconductor device (51, etc.) according to any one of B1 to B10, wherein the first trench structure (11) has a first width (W1), and the second trench structure (12) has a second width (W2) that is less than or equal to the first width (W1).

[0222] [B12] The semiconductor device (51, etc.) according to B11, wherein the second trench structure (12) is formed at a distance (IT) of the first width (W1) or less from the first trench structure (11).

[0223] [B13] A semiconductor device (51, etc.) according to any one of B1 to B12, wherein the first trench structure (11) is electrically connected to the chip (2), and the second trench structure (12) is electrically insulated from the chip (2).

[0224] [B14] The semiconductor device (51, etc.) according to any one of B1 to B13, wherein the first trench structure (11) includes a first trench (13) penetrating the pn junction (J), a first insulating film (14) covering the inner wall of the first trench (13) such that the chip (2) is exposed from the bottom wall of the first trench (13), and a first electrode (15) embedded in the first trench (13) with the first insulating film (14) in between and electrically connected to the chip (2) at the bottom wall of the first trench (13); and the second trench structure (12) includes a second trench (16) penetrating the pn junction (J), a second insulating film (17) covering the inner wall of the second trench (16), and a second electrode (18) embedded in the second trench (16) with the second insulating film (17) in between and electrically insulated from the chip (2).

[0225] [B15] The semiconductor device (51, etc.) according to B14, wherein the second trench structure (12) is embedded on the bottom wall side of the second trench (16) so as to be continuous with the second insulating film (17) and includes a bottom insulator (19) having a thickness exceeding the thickness of the second insulating film (17), and the second electrode (18) is embedded in the second trench (16) with the second insulating film (17) and the bottom insulator (19) in between.

[0226] [B16] The first trench structure (11) further comprises: a first layer (6) of a first conductivity type formed in the region on the second main surface (4) side within the chip (2); a second layer (7) of a first or second conductivity type formed in the region on the first main surface (3) side within the chip (2); and a third layer (8) of a second conductivity type interposed in the region between the first layer (6) and the second layer (7) within the chip (2) and forming the pn junction (J) with the first layer (6), wherein the first trench structure (11) is the first layer (6) A semiconductor device (51, etc.) according to any one of B1 to B15, wherein the second trench structure (12) penetrates the second layer (7) and the third layer (8) to reach the first layer (6), and partitions the device region (9, 9A) in the second layer (7), and the second trench structure (12) penetrates the second layer (7) and the third layer (8) to reach the first layer (6), and partitions the device region (9, 9A) in the region of the second layer (7) that is closer to the device region (9, 9A) than the first trench structure (11) in the second layer (7).

[0227] [B17] The semiconductor device (51, etc.) according to B16, wherein the first trench structure (11) is electrically connected to the first layer (6) and electrically insulated from the second layer (7) and the third layer (8), and the second trench structure (12) is electrically insulated from the first layer (6), the second layer (7), and the third layer (8).

[0228] [B18] A semiconductor device (51, etc.) according to any one of B1 to B15, further comprising: a first layer (6) of a first conductivity type formed in the region on the second main surface (4) side within the chip (2); and a second layer (7) of a second conductivity type formed in the region on the first main surface (3) side within the chip (2) and forming a pn junction (J) with the first layer (6), wherein the first trench structure (11) penetrates the second layer (7) to reach the first layer (6) and partitions the device region (9, 9A) in the second layer (7); and the second trench structure (12) penetrates the second layer (7) to reach the first layer (6) and partitions the device region (9, 9A) in the region of the second layer (7) that is closer to the device region (9, 9A) than the first trench structure (11).

[0229] [B19] The semiconductor device (51, etc.) according to B18, wherein the first trench structure (11) is electrically connected to the first layer (6) and electrically insulated from the second layer (7), and the second trench structure (12) is electrically insulated from the first layer (6) and the second layer (7).

[0230] [B20] A semiconductor device (51, etc.) according to any one of B1 to B19, further comprising a transistor (30) formed in the device region (9, 9A).

[0231] [C1] A chip (2) having a first main surface (3) on one side and a second main surface (4) on the other side; a pn junction (J) formed inside the chip (2) so as to extend along the first main surface (3); a device region (9, 9A) provided on the first main surface (3); and a part formed on the first main surface (3) so as to penetrate the pn junction (J) and dividing the device region (9, 9A) on the first main surface (3). A semiconductor device (61, 65, 66 (hereinafter simply referred to as "61 etc.")) comprising a trench structure (10, 11, 12) and a pn junction extension (JE) drawn out from the intersection (63) of the pn junction (J) and the trench structure (10, 11, 12) toward the bottom wall side of the trench structure (10, 11, 12) so as to extend the pn junction (J) in the device region (9, 9A).

[0232] [C2] The semiconductor device (61, etc.) described in C1, wherein the pn junction extension portion (JE) is formed with a gap from the bottom wall of the trench structure (10, 11, 12) toward the first main surface (3).

[0233] [C3] The semiconductor device (61, etc.) according to C1 or C2, wherein the pn junction extension (JE) has a width less than the width of the trench structure (10, 11, 12).

[0234] [C4] The trench structure (10, 11, 12) is electrically insulated from the chip (2) by a semiconductor device (61, etc.) as described in any one of C1 to C3.

[0235] [C5] The trench structure (10, 11, 12) is formed in an electrically floating state, and is a semiconductor device (61, etc.) according to any one of C1 to C4.

[0236] [C6] A semiconductor device (61, etc.) according to any one of C1 to C4, to which a different potential (VT) than that of the chip (2) is applied to the trench structure (10, 11, 12).

[0237] [C7] The trench structure (10, 11, 12) includes trenches (13, 16) penetrating the pn junction (J), insulating films (14, 17) covering the inner walls of the trenches (13, 16), and electrodes (15, 18) embedded in the trenches (13, 16) with the insulating films (14, 17) in between, and electrically insulated from the chip (2), wherein the pn junction extension (JE) faces the electrodes (15, 18) with the insulating films (14, 17) in between, the semiconductor device (61, etc.) according to any one of C4 to C6.

[0238] [C8] The trench structures (10, 11, 12) are electrically connected to the chip (2) by a semiconductor device (61, etc.) described in any one of C1 to C3.

[0239] [C9] The trench structure (10, 11, 12) includes trenches (13, 16) penetrating the pn junction (J), insulating films (14, 17) covering the inner walls of the trenches (13, 16) so as to expose the chip (2) from the bottom walls of the trenches (13, 16), and electrodes (15, 18) embedded in the trenches (13, 16) with the insulating films (14, 17) in between, and electrically connected to the chip (2) at the bottom walls of the trenches (13, 16), and the pn junction extension (JE) is opposite the electrodes (15, 18) with the insulating films (14, 17) in between, the semiconductor device (61, etc.) as described in C8.

[0240] [C10] A first layer (6) of a first conductivity type formed in the region on the second main surface (4) side within the chip (2), a second layer (7) of a first or second conductivity type formed in the region on the first main surface (3) side within the chip (2), a third layer (8) of a second conductivity type interposed in the region between the first layer (6) and the second layer (7) within the chip (2) and forming the pn junction (J) with the first layer (6), and a second layer (7) that penetrates the second layer (7) and the third layer (8) to reach the first layer (6). A semiconductor device (61, etc.) according to any one of C1 to C9, further comprising: trench structures (10, 11, 12) that demarcate the device region (9, 9A) in the device region (9, 9A); and a second conductivity type sidewall buffer layer (62) that extends from the intersection (63) of the third layer (8) and the trench structures (10, 11, 12) towards the bottom wall side of the trench structures (10, 11, 12) so as to extend the pn junction (J) in the device region (9, 9A), and forms the pn junction extension (JE) with the first layer (6).

[0241] [C11] A first layer (6) of a first conductivity type formed in the region on the second main surface (4) side within the chip (2), a second layer (7) of a second conductivity type formed in the region on the first main surface (3) side within the chip (2) and forming the pn junction (J) with the first layer (6), and the trench structure (10, 1) that penetrates the second layer (7) to reach the first layer (6) and demarcates the device region (9, 9A) in the second layer (7). A semiconductor device (61, etc.) according to any one of C1 to C9, further comprising: 1, 12) and a second conductivity type sidewall buffer layer (62) which is drawn out from the intersection (63) of the second layer (7) and the trench structure (10, 11, 12) toward the bottom wall side of the trench structure (10, 11, 12) so as to extend the pn junction (J) in the device region (9, 9A), and which forms the pn junction extension (JE) with the first layer (6).

[0242] [C12] The semiconductor device (61, etc.) according to C10 or C11, wherein the first layer (6) includes a first conductivity type high-concentration layer (6a) formed in the region on the second main surface (4) side, and a first conductivity type low-concentration layer (6b) formed in the region on the first main surface (3) side with a lower impurity concentration than the high-concentration layer (6a), and the sidewall buffer layer (62) extends from the intersection (63) into the low-concentration layer (6b).

[0243] [C13] The semiconductor device (61, etc.) described in C12, wherein the sidewall buffer layer (62) is formed with a gap between it and the first main surface (3) from the high-density layer (6a).

[0244] [C14] The semiconductor device (61, etc.) according to C12 or C13, wherein the sidewall buffer layer (62) has an impurity concentration that is higher than that of the low-concentration layer (6b) and lower than that of the high-concentration layer (6a).

[0245] [C15] A chip (2) having a first main surface (3) on one side and a second main surface (4) on the other side; a pn junction (J) formed inside the chip (2) so as to extend along the first main surface (3); a device region (9, 9A) provided on the first main surface (3); a first trench structure (11) formed on the first main surface (3) so as to penetrate the pn junction (J) and demarcating the device region (9, 9A) on the first main surface (3); and the pn junction (J) A semiconductor device (61, etc.) comprising: a second trench structure (12) formed on a first main surface (3) and defining the device region (9, 9A) in a region on the side of the device region (9, 9A) that is closer to the device region (9, 9A) than the first trench structure (11); and a pn junction extension (JE) that is drawn out from the intersection (63) of the pn junction (J) and the side wall of the second trench structure (12) toward the bottom wall side of the second trench structure (12) so as to extend the pn junction (J) in the device region (9, 9A).

[0246] [C16] The semiconductor device (61, etc.) described in C15, wherein the pn junction extension portion (JE) is formed with a gap between the bottom wall of the second trench structure (12) and the first main surface (3).

[0247] [C17] The semiconductor device (61, etc.) described in C15 or C16, wherein the second trench structure (12) is electrically isolated from the first trench structure (11).

[0248] [C18] The semiconductor device (61, etc.) according to any one of C15 to C17, wherein the first trench structure (11) is electrically connected to the chip (2), and the second trench structure (12) is electrically insulated from the chip (2).

[0249] [C19] The second trench structure (12) is formed in an electrically floating state, as described in any one of C15 to C18 (e.g., semiconductor device (61, etc.)).

[0250] [C20] A semiconductor device (61, etc.) according to any one of C15 to C19, wherein a different potential (VT) than that of the first trench structure (11) is applied to the second trench structure (12).

[0251] [C21] A semiconductor device (61, etc.) comprising: a first layer (6) of a first conductivity type; a second layer (7) of a first or second conductivity type laminated on the first layer (6); a third layer (8) of a second conductivity type interposed in the region between the first layer (6) and the second layer (7); a device region (9, 9A) provided on the second layer (7); a trench structure (10, 11, 12) penetrating the second layer (7) and the third layer (8) to reach the first layer (6) and demarcating the device region (9, 9A) in the second layer (7); and a sidewall buffer layer (62) of a second conductivity type drawn out from the intersection (63) of the third layer (8) and the trench structure (10, 11, 12) toward the bottom wall side of the trench structure (10, 11, 12).

[0252] [C22] A semiconductor device (61, etc.) comprising: a first layer (6) of a first conductivity type; a second layer (7) of a second conductivity type laminated on the first layer (6); a device region (9, 9A) provided on the second layer (7); a trench structure (10, 11, 12) penetrating the second layer (7) to reach the first layer (6) and demarcating the device region (9, 9A) in the second layer (7); and a sidewall buffer layer (62) of a second conductivity type drawn out from the intersection (63) of the second layer (7) and the trench structure (10, 11, 12) towards the bottom wall side of the trench structure (10, 11, 12).

[0253] [D1] A semiconductor device (71, etc.) comprising: a first layer (6) of a first conductivity type; a second layer (7) of a second conductivity type laminated on the first layer (6); a device region (9, 9A) provided on the second layer (7); a trench structure (10, 11, 12) penetrating the second layer (7) to reach the first layer (6) and demarcating the device region (9, 9A) in the second layer (7); and a buried layer (8) of a second conductivity type formed in the device region (9, 9A) at a distance from the trench structure (10, 11, 12) and straddling the boundary between the first layer (6) and the second layer (7).

[0254] [D2] The semiconductor device (71, etc.) according to D1, wherein the embedded layer (8) includes a second conductivity type low-concentration embedded layer (8a) formed on the first layer (6) side, and a second conductivity type high-concentration embedded layer (8b) formed on the second layer (7) side and having a higher impurity concentration than the low-concentration embedded layer (8a).

[0255] [D3] The semiconductor device (71, etc.) according to D2, wherein the low-concentration embedding layer (8a) is formed in the region on the first layer (6) side with respect to the boundary between the first layer (6) and the second layer (7), and the high-concentration embedding layer (8b) straddles the boundary.

[0256] [D4] The semiconductor device (71, etc.) according to D2 or D3, wherein the low-concentration buried layer (8a) is formed at a distance from the trench structure (10, 11, 12), and the high-concentration buried layer (8b) is formed at a distance from the trench structure (10, 11, 12).

[0257] [D5] The semiconductor device (71, etc.) according to any one of D1 to D4, wherein the first layer (6) includes a first conductivity type high concentration layer (6a) and a first conductivity type low concentration layer (6b) laminated on the high concentration layer (6a) and having a lower impurity concentration than the high concentration layer (6a), the second layer (7) is laminated on the low concentration layer (6b), and the embedded layer (8) is embedded so as to straddle the boundary between the low concentration layer (6b) and the second layer (7).

[0258] [D6] The semiconductor device (71, etc.) according to D5, wherein the high-concentration layer (6a) is made of a semiconductor substrate and the low-concentration layer (6b) is made of an epitaxial layer.

[0259] [D7] The trench structure (10, 11, 12) is electrically connected to the first layer (6) and electrically insulated from the second layer (7) in the semiconductor device (71, etc.) described in any one of D1 to D6.

[0260] [D8] The trench structure (10, 11, 12) is electrically insulated from the first layer (6) and the second layer (7) of the semiconductor device (71, etc.) according to any one of D1 to D6.

[0261] [D9] A semiconductor device (71, etc.) according to any one of D1 to D6, comprising a plurality of trench structures (10, 11, 12) formed through the second layer (7) so as to reach the first layer (6), and arranged at intervals away from the device region (9, 9A) in the second layer (7) so as to demarcate the device region (9, 9A), wherein the embedded layer (8) is formed at an interval from the trench structure (10, 11, 12) closest to the device region (9, 9A).

[0262] [D10]The trench structure (10, 11, 12) includes a trench (13) that penetrates the second layer (7) so as to reach the first layer (6), an insulating film (14) that covers the inner wall of the trench (13) so as to expose the first layer (6), and an electrode (15) that is electrically connected to the first layer (6) and embedded in the trench (13) with the insulating film (14) interposed therebetween so as to be electrically insulated from the second layer (7), the semiconductor device (71, etc.) according to D7.

[0263] [D11]The trench structure (10, 11, 12) includes a trench (16) that penetrates the second layer (7) so as to reach the first layer (6), an insulating film (17) that covers the inner wall of the trench (16), and an electrode (18) that is embedded in the trench (16) with the insulating film (17) interposed therebetween so as to be electrically insulated from the first layer (6) and the second layer (7), the semiconductor device (71, etc.) according to D8.

[0264] [D12]Each of the trench structures (10, 11, 12) includes a trench (14, 17) that penetrates the second layer (7) so as to reach the first layer (6), an insulating film (14, 17) that covers the inner wall of the trench (14, 17), and an electrode (15, 18) that is embedded in the trench (14, 17) with the insulating film interposed therebetween, the semiconductor device (71, etc.) according to D9.

[0265] [D13]The electrodes (15, 18) include conductive polysilicon of a first conductivity type, the semiconductor device (71, etc.) according to any one of D10 to D12.

[0266] [D14]The trench structure (10, 11, 12) is formed in a tapered shape toward the first layer (6), the semiconductor device (71, etc.) according to any one of D1 to D13.

[0267] [D15]The trench structure (10, 11, 12) surrounds the device region (9, 9A) in plan view, the semiconductor device (71, etc.) according to any one of D1 to D14.

[0268] [D16] The semiconductor device (such as 71) according to any one of D1 to D15, further including a p-type sinker region (21) formed in the second layer (7) so as to cover the side walls of the trench structures (10, 11, 12) in the device regions (9, 9A).

[0269] [D17] The semiconductor device (such as 71) according to any one of D1 to D16, further including an n-type impurity region (22) formed in a region along the bottom wall of the trench structures (10, 11, 12) in the first layer (6) and having an impurity concentration higher than that of the first layer (6).

[0270] [D18] The semiconductor device (such as 71) according to any one of D1 to D17, further including a transistor (30) formed in the device regions (9, 9A).

[0271] [D19] A semiconductor device (such as 71) including an n-type first layer (6), a p-type second layer (7) laminated on the first layer (6), a device region (9, 9A) provided in the second layer (7), a first trench structure (11) that is electrically connected to the first layer (6), penetrates the second layer (7) so as to be electrically insulated from the second layer (7), and partitions the device region (9, 9A) in the second layer (7), a second trench structure (12) that penetrates the second layer (7) so as to be electrically insulated from the first layer (6) and the second layer (7), partitions the device region (9, 9A) in a region of the second layer (7) closer to the device region (9, 9A) than the first trench structure (11), and a p-type buried layer (8) formed in the device region (9, 9A) at an interval from the second trench structure (12) and straddling the boundary between the first layer (6) and the second layer (7).

[0272] [D20] The first trench structure (11) includes a first trench (13) penetrating the second layer (7) to reach the first layer (6), a first insulating film (14) covering the inner wall of the first trench (13) to expose the first layer (6), and a first electrode (15) embedded in the first trench (13) with the first insulating film (14) in between, electrically connected to the first layer (6) and electrically insulated from the second layer (7). The semiconductor device (71, etc.) according to D19, wherein the second trench structure (12) includes a second trench (16) penetrating the second layer (7) to reach the first layer (6), a second insulating film (17) covering the inner wall of the second trench (16), and a second electrode (18) embedded in the second trench (16) with the second insulating film (17) in between so as to be electrically insulated from the first layer (6) and the second layer (7).

[0273] Here, the features of the semiconductor device are shown item by item, but the features described in [A1] to [A20], the features described in [B1] to [B20], the features described in [C1] to [C22], and the features described in [D1] to [D20] can be combined in any manner among them. Although embodiments have been described in detail, these are merely specific examples used to clarify the technical content, and the present invention should not be interpreted as being limited to these specific examples, and the scope of the present invention is limited by the appended claims. [Explanation of symbols]

[0274] 1 Semiconductor device 6 1st layer 6a High concentration layer 6b Low concentration layer 7 2nd layer 8. Third layer (buried layer) 8a Low concentration buried layer 8b High concentration buried layer 9. Device Area 9A Transistor region 10. Trench separation structure (trench structure) 11. First Trench Structure 12. Second Trench Structure 13 Trench 1 14. First insulating film 15 1st electrode 16. Trench No. 2 17. Second insulating film 18 2nd electrode 19 Bottom insulator 20 Inter-trench regions 21. Thinker Area 22 Impurity region 30 MISFETs (Transistors) 51 Semiconductor Equipment 52 First contact electrode 53 Semiconductor Equipment 54. Second contact electrode 55 Semiconductor Equipment 61 Semiconductor Equipment 62 Sidewall buffer layer 63 Intersection 65 Semiconductor Equipment 66 Semiconductor Devices 71 Semiconductor Equipment 72 Semiconductor Equipment 81 Semiconductor Equipment J pn junction JE pn joint expansion section W1 First trench width W2 Second trench width

Claims

1. A chip having a first main surface on one side and a second main surface on the other side, Within the chip, a first layer formed in the region on the second main surface side, Within the chip, a second layer formed in the region on the first main surface side, Within the chip, a third layer interposed in the region between the first layer and the second layer, A pn joint formed inside the chip so as to extend along the first main surface, The device region provided on the first main surface, A first trench structure is formed on the first main surface so as to penetrate the pn joint and demarcates the device region on the first main surface, A second trench structure is formed on the first main surface so as to penetrate the pn joint, and demarcates the device region in a region on the device region side of the first trench structure, Includes an impurity region having a higher impurity concentration than the first layer, The impurity region is formed in the first layer so as to cover the bottom wall of the first trench structure and the bottom wall of the second trench structure. The first trench structure consists of a first trench electrode structure electrically connected to the tip, The semiconductor device comprises a second trench electrode structure which is electrically insulated from the chip.

2. The semiconductor device according to claim 1, wherein the first trench structure has a lower end that is electrically connected to the chip.

3. The semiconductor device according to claim 1 or 2, wherein the second trench structure is electrically isolated from the first trench structure.

4. The semiconductor device according to any one of claims 1 to 3, wherein the second trench structure is formed in an electrically floating state.

5. A semiconductor device according to any one of claims 1 to 4, wherein a potential different from that of the first trench structure is generated in the second trench structure.

6. The first trench structure has a first width, The semiconductor device according to any one of claims 1 to 5, wherein the second trench structure has a second width less than or equal to the first width.

7. The semiconductor device according to claim 6, wherein the second trench structure is formed at a distance of no more than the first width from the first trench structure.

8. The first trench structure includes a first trench penetrating the pn joint, a first insulating film covering the inner wall of the first trench so as to expose the chip from the bottom wall of the first trench, and a first electrode embedded in the first trench with the first insulating film in between, and electrically connected to the chip at the bottom wall of the first trench. The semiconductor device according to any one of claims 1 to 7, wherein the second trench structure includes a second trench penetrating the pn junction, a second insulating film covering the inner wall of the second trench, and a second electrode embedded in the second trench with the second insulating film in between, and electrically insulated from the chip.

9. The second trench structure includes a bottom insulator embedded on the bottom wall side of the second trench so as to be connected to the second insulating film, and having a thickness exceeding the thickness of the second insulating film. The semiconductor device according to claim 8, wherein the second electrode is embedded in the second trench with the second insulating film and the bottom insulator in between.

10. The first trench structure penetrates the second and third layers to reach the first layer, and in the second layer, it partitions the device region. The semiconductor device according to any one of claims 1 to 9, wherein the second trench structure penetrates the second and third layers to reach the first layer, and partitions the device region in the region of the second layer that is closer to the device region than the first trench structure.

11. The first trench structure is electrically connected to the first layer and electrically insulated from the second and third layers. The semiconductor device according to claim 10, wherein the second trench structure is electrically insulated from the first layer, the second layer and the third layer.

12. The first trench structure penetrates the second layer to reach the first layer, and in the second layer, it partitions the device region. The semiconductor device according to any one of claims 1 to 9, wherein the second trench structure penetrates the second layer to reach the first layer and partitions the device region in the region of the second layer that is closer to the device region than the first trench structure.

13. The first trench structure is electrically connected to the first layer and electrically insulated from the second layer. The semiconductor device according to claim 12, wherein the second trench structure is electrically insulated from the first layer and the second layer.

14. The semiconductor device according to any one of claims 1 to 13, further comprising an inter-trench region partitioned in the region between the first trench structure and the second trench structure and formed in an electrically floating state.

15. The semiconductor device according to any one of claims 1 to 14, further comprising a transistor formed in the device region.

16. The first layer of the first conductivity type, A second layer of a first conductivity type or a second conductivity type is laminated on the first layer, A third layer of second conductivity type interposed between the first layer and the second layer, The device region provided in the second layer, A first trench structure that penetrates the second and third layers to reach the first layer and demarcates the device region in the second layer, A second trench structure penetrates the second and third layers to reach the first layer, and demarcates the device region in the region of the second layer that is closer to the device region than the first trench structure, Includes an impurity region having a higher impurity concentration than the first layer, The impurity region is formed in the first layer so as to cover the bottom wall of the first trench structure and the bottom wall of the second trench structure. The first trench structure consists of a first trench electrode structure that is electrically connected to the first layer and electrically insulated from the second and third layers. The semiconductor device comprises a second trench electrode structure which is electrically insulated from the first layer, the second layer, and the third layer.

17. The first layer of the first conductivity type, A second layer of second conductivity type laminated on the first layer, The device region provided in the second layer, A first trench structure that penetrates the second layer to reach the first layer and demarcates the device region in the second layer, A second trench structure penetrates the second layer to reach the first layer and demarcates the device region in the region of the second layer that is closer to the device region than the first trench structure, Includes an impurity region having a higher impurity concentration than the first layer, The impurity region is formed in the first layer so as to cover the bottom wall of the first trench structure and the bottom wall of the second trench structure. The first trench structure consists of a first trench electrode structure that is electrically connected to the first layer and electrically insulated from the second layer. The semiconductor device comprises a second trench electrode structure which is electrically insulated from the first and second layers.

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