Semiconductor structure for testing

Abstract

A semiconductor structure for inspection includes: a semiconductor plate having a first main surface on one side and a second main surface on the other side; an inspection region provided on the first main surface; a main surface electrode of a first hardness that covers the first main surface in the inspection region; and a protective electrode of a second hardness exceeding the first hardness that covers the main surface electrode in the inspection region, the protective electrode forming a current path through the semiconductor plate between the protective electrode and the second main surface.

Description

Technical Field

[0001] This application corresponds to Japanese Patent Application No. 2021-053878 filed with the Japan Patent Office on March 26, 2021, and the entire disclosure of this application is incorporated herein by reference. The present invention relates to a semiconductor structure for inspection.

Background Art

[0002] Patent Document 1 discloses a semiconductor device for inspection used in the inspection of a semiconductor evaluation apparatus. The semiconductor evaluation apparatus includes a chuck stage, probes, and an evaluation unit. The chuck stage has a mounting surface on which a semiconductor wafer is placed during evaluation. The probes are arranged to be contactable with the semiconductor wafer placed on the mounting surface. The evaluation unit is electrically connected to the chuck stage and the probes and evaluates the electrical characteristics of the semiconductor wafer.

[0003] The semiconductor device for inspection is an inspection jig for inspecting the mounting surface of the chuck stage before evaluating the semiconductor wafer. The semiconductor device for inspection includes a silicon wafer and a plurality of resistors. The silicon wafer is connected to the mounting surface. The plurality of resistors are provided spaced apart on the silicon wafer and are connected to the probes. The mounting surface is inspected based on the contact resistance between the chuck stage and the silicon wafer.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] One embodiment provides a highly reliable semiconductor structure for inspection.

Means for Solving the Problems

[0006] One embodiment provides a semiconductor structure for inspection, comprising: a semiconductor plate having a first main surface on one side and a second main surface on the other side; an inspection area provided on the first main surface; a main surface electrode having a first hardness and covering the first main surface in the inspection area; and a protective electrode having a second hardness exceeding the first hardness, covering the main surface electrode in the inspection area, and forming a current path between it and the second main surface via the semiconductor plate.

[0007] The aforementioned or any other purposes, features, and effects will be made clearer by embodiments described with reference to the accompanying drawings. [Brief explanation of the drawing]

[0008] [Figure 1] Figure 1 is a schematic diagram showing a first example of a semiconductor evaluation apparatus. [Figure 2] Figure 2 is a plan view showing a semiconductor structure for testing according to the first embodiment. [Figure 3] Figure 3 is a cross-sectional view taken along the line III-III shown in Figure 2. [Figure 4] Figure 4 is a flowchart illustrating the manufacturing method of a semiconductor device using the semiconductor evaluation apparatus shown in Figure 1 and the inspection semiconductor structure shown in Figure 2. [Figure 5A] Figure 5A is a schematic diagram illustrating the flowchart shown in Figure 4. [Figure 5B] Figure 5B is a schematic diagram illustrating the process following Figure 5A. [Figure 5C] Figure 5C is a schematic diagram illustrating the process that follows Figure 5B. [Figure 5D] Figure 5D is a schematic diagram illustrating the process that follows Figure 5C. [Figure 5E] Figure 5E is a schematic diagram illustrating the process that follows Figure 5D. [Figure 5F] Figure 5F is a schematic diagram illustrating the process that follows Figure 5E. [Figure 6] Figure 6 is a graph showing the reliability of the semiconductor structure used for testing, as shown in Figure 2. [Figure 7] Figure 7 is a plan view showing a semiconductor structure for testing according to the second embodiment. [Figure 8] Figure 8 is a cross-sectional view along the line VIII-VIII shown in Figure 7. [Figure 9] Figure 9 is an enlarged cross-sectional view of the main part of the functional device shown in Figure 7. [Figure 10] Figure 10 is a schematic diagram showing a second example of the semiconductor evaluation apparatus shown in Figure 1. [Figure 11] Figure 11 is a schematic diagram showing a third example of the semiconductor evaluation apparatus shown in Figure 1. [Modes for carrying out the invention]

[0009] The embodiments will now be described in detail with reference to the attached drawings. The attached drawings are schematic diagrams and not strictly accurate; the scale and other aspects may not necessarily match. Corresponding structures in the attached drawings are given the same reference numerals, and redundant descriptions are omitted or simplified. For structures whose descriptions are omitted or simplified, the description given before the omission or simplification applies.

[0010] Figure 1 is a schematic diagram showing a first embodiment of the semiconductor evaluation apparatus 1. The semiconductor evaluation apparatus 1 is an apparatus for measuring the electrical characteristics of a semiconductor structure 2 (see dashed line) to be measured. The semiconductor evaluation apparatus 1 includes a probe device 3, a tester device 4, and a control device 5. The probe device 3 includes a stage unit 6 and a probe unit 7.

[0011] The stage unit 6 includes a chuck stage 8, an insulating plate 9, a supporting part 10, and a stage displacement unit 11. In this embodiment, the chuck stage 8 is formed in a disc shape. The chuck stage 8 has a conductive mounting surface 8a on which the semiconductor structure 2 is disposed, and a non-mounting surface 8b on the opposite side of the mounting surface 8a. In this embodiment, the chuck stage 8 is made of a conductive plate and has conductivity throughout the thickness direction including the mounting surface 8a and the non-mounting surface 8b. The chuck stage 8 may be configured to adsorb and support the semiconductor structure 2 on the mounting surface 8a.

[0012] The insulating plate 9 is made of an insulating plate-like member and is disposed on the non-mounting surface 8b side. The supporting part 10 supports the chuck stage 8 via the insulating plate 9. The stage displacement unit 11 is connected to the supporting part 10 and is configured to displace the chuck stage 8 via the supporting part 10. The stage displacement unit 11 may be configured to displace the chuck stage 8 in a first direction X along the mounting surface 8a, a second direction Y perpendicular to the first direction X along the mounting surface 8a, a vertical direction Z perpendicular to the mounting surface 8a, and a rotation direction θ with a vertical direction Z passing through the central part of the mounting surface 8a as a rotation axis in response to an external electrical signal.

[0013] In this embodiment, the probe unit 7 is of a manipulator type and includes a manipulator 12, a conductive probe needle 13, and a probe displacement unit 14. In this embodiment, the manipulator 12 includes a body part 12a and an arm part 12b. The form of the body part 12a is arbitrary and is not limited to a specific form. The arm part 12b is connected to the body part 12a and is formed in an arm shape (for example, shaft-like, columnar, cylindrical, plate-like, etc.) so as to extend from the body part 12a along the mounting surface 8a.

[0014] The shape of the arm portion 12b is arbitrary. The arm portion 12b may extend parallel to the mounting surface 8a or may extend obliquely with respect to the mounting surface 8a. Further, the arm portion 12b may be formed in a curved shape having a portion inclined from the body portion 12a toward the mounting surface 8a and a portion curved from the inclined portion so as to extend along the mounting surface 8a.

[0015] The probe needle 13 is composed of a needle-shaped member formed of a metal material and has a sharp needle tip that abuts against the semiconductor structure 2. The probe needle 13 may be formed of at least one of tungsten, a tungsten alloy, a palladium alloy, and a gold alloy. The probe needle 13 is supported by the manipulator 12. Specifically, the probe needle 13 is detachably attached to the arm portion 12b. The probe needle 13 is attached to the arm portion 12b in an inclined posture or a vertical posture with respect to the mounting surface 8a. Of course, the probe needle 13 may constitute a coaxial probe together with the arm portion 12b.

[0016] The probe displacement unit 14 is connected to the manipulator 12 and displaces the relative position of the probe needle 13 with respect to the mounting surface 8a (semiconductor structure 2) via the manipulator 12. The probe displacement unit 14 may be configured to displace the probe needle 13 in at least one of the first direction X, the second direction Y, and the vertical direction Z in response to an external electrical signal. The probe displacement unit 14 may be configured to move the probe needle 13 between an inspection position facing the mounting surface 8a and a retracted position located outside the mounting surface 8a.

[0017] The number of probe units 7 is adjusted according to the number of electrodes (contact locations) of the inspection target portion of the semiconductor structure 2. When the inspection target portion of the semiconductor structure 2 has a plurality of electrodes arranged in an array, a plurality of probe units 7 corresponding to the plurality of electrodes are provided. When the inspection target portion of the semiconductor structure 2 has a single electrode, one or a plurality of probe units 7 corresponding to the single electrode are provided.

[0018] The tester device 4 is electrically connected to the mounting surface 8a and the probe needle 13, and applies a predetermined electrical signal between the mounting surface 8a and the probe needle 13. The tester device 4 measures the electrical characteristics of the semiconductor structure 2 based on the current flow result between the mounting surface 8a and the probe needle 13. The tester device 4 also inspects the condition of the mounting surface 8a based on the current flow result between the mounting surface 8a and the probe needle 13. Specifically, the condition of the mounting surface 8a is inspected indirectly using an inspection jig for the mounting surface 8a.

[0019] The tester device 4 is configured to apply any voltage or any current between the mounting surface 8a and the probe needle 13. In this embodiment, the tester device 4 is configured to apply any current between the mounting surface 8a and the probe needle 13. Depending on the electrical specifications of the semiconductor structure 2, the tester device 4 may apply the current from the probe needle 13 side or from the chuck stage 8 side. In this embodiment, the tester device 4 applies the current from the probe needle 13 toward the chuck stage 8. The current may be between 1 mA and 200 A.

[0020] The tester device 4 is preferably configured to acquire either or both of the voltage value and / or resistance value between the mounting surface 8a and the probe needle 13. When the tester device 4 measures a voltage value, the voltage value may be 10V or less. When the tester device 4 measures a resistance value, the resistance value may be 200mΩ or less. The resistance value may also be the contact resistance value between the mounting surface 8a and the semiconductor structure 2.

[0021] The control device 5 is connected to the probe device 3 and the tester device 4, and controls the probe device 3 and the tester device 4. The control device 5 may be connected to the probe device 3 via a cable, or via a communication interface such as a wireless LAN or wired LAN. The control device 5 may be connected to the tester device 4 via a cable, or via a communication interface such as a wireless LAN or wired LAN.

[0022] The control device 5 may include a computer having a main control unit, an input unit, an output unit, a memory unit, and a display unit. The main control unit may include a CPU, RAM, and ROM. The input unit may include a keyboard, mouse, etc. The output unit may include a printer, etc.

[0023] The memory unit may include a storage medium in which processing recipes, etc. are stored. The storage medium may be a hard disk, optical disk, flash memory, etc. The display unit may display information related to the semiconductor structure 2, information related to the probe device 3, information related to the tester device 4, information related to the processing recipe, etc., in response to the functions of the main control unit, etc.

[0024] The control device 5 reads the processing recipe, generates control signals to control the prober device 3 and the tester device 4 with predetermined processing operations based on the processing recipe, and outputs these signals to the prober device 3 and the tester device 4. The control device 5 is configured to acquire measurement results from the tester device 4 and display the measurement results on the display unit.

[0025] The control device 5 may be configured to display the measurement results from the tester device 4 on a display unit using a map (for example, a wafer map or a map of the mounting surface 8a). Based on the measurement results from the tester device 4, the control device 5 performs a quality determination of the electrical characteristics of the semiconductor structure 2. The control device 5 also performs a quality determination of the mounting surface 8a based on the measurement results from the tester device 4.

[0026] Figure 2 is a plan view showing the inspection semiconductor structure 2A according to the first embodiment. Figure 3 is a cross-sectional view along the line III-III shown in Figure 2. The inspection semiconductor structure 2A is a jig used to inspect the mounting surface 8a prior to the evaluation of the manufacturing semiconductor structure 2B (see Figure 5E described later), which is in a stage before being processed into a semiconductor device, and differs in its application from the manufacturing semiconductor structure 2B in that it is not processed into a semiconductor device. The inspection semiconductor structure 2A, together with the semiconductor evaluation device 1, constitutes a chuck stage inspection device that inspects the mounting surface 8a of the chuck stage 8. Both the inspection semiconductor structure 2A and the manufacturing semiconductor structure 2B are examples of semiconductor structure 2.

[0027] Referring to Figures 2 and 3, the semiconductor structure 2A for testing includes a disc-shaped semiconductor wafer 20 as an example of a semiconductor plate. Preferably, the semiconductor wafer 20 does not contain a silicon (Si) single crystal. In this embodiment, the semiconductor wafer 20 consists of a wide-bandgap semiconductor wafer containing a wide-bandgap semiconductor. A wide-bandgap semiconductor is a semiconductor having a higher bandgap than Si.

[0028] In this embodiment, the semiconductor wafer 20 consists of a SiC semiconductor wafer containing a hexagonal SiC (silicon carbide) single crystal as an example of a wide-bandgap semiconductor. Figure 2 shows an example where the first direction X is the m-axis direction of the SiC single crystal and the second direction Y is the a-axis direction of the SiC single crystal. The hexagonal SiC single crystal has multiple polytypes, including 2H (Hexagonal)-SiC single crystals, 4H-SiC single crystals, 6H-SiC single crystals, etc. In this embodiment, an example is shown where the test semiconductor structure 2A consists of a 4H-SiC single crystal, but other polytypes are not excluded.

[0029] The semiconductor wafer 20 has a first main surface 21 on one side, a second main surface 22 on the other side, and a side surface 23 connecting the first main surface 21 and the second main surface 22. The first main surface 21 and the second main surface 22 face the c-plane of the SiC single crystal. Preferably, the first main surface 21 faces the silicon plane of the SiC single crystal, and the second main surface 22 faces the carbon plane of the SiC single crystal.

[0030] The first principal surface 21 and the second principal surface 22 may have an off-angle that is inclined at a predetermined angle in a predetermined off-direction with respect to the c-plane. In other words, the c-axis of the SiC single crystal may be inclined by the off-angle with respect to the vertical Z direction. The off-direction is preferably the a-axis direction ([11-20] direction) of the SiC single crystal. The off-angle may be greater than 0° and less than or equal to 10°. The off-angle is preferably 5° or less. The off-angle is particularly preferably 2° or more and less than or equal to 4.5°.

[0031] The semiconductor wafer 20 has a marker 24 on its side surface 23 that indicates the crystal orientation of the SiC single crystal. In this embodiment, the marker 24 includes an orientation flat that is linearly cut out in a plan view (hereinafter simply referred to as "plan view") as seen from the vertical Z direction. In this embodiment, the marker 24 extends in the a-axis direction of the SiC single crystal. The marker 24 does not necessarily have to extend in the a-axis direction, but may extend in the m-axis direction.

[0032] Of course, the semiconductor structure 2A for inspection may include a marker 24 extending in the a-axis direction and a marker 24 extending in the m-axis direction. In addition, the marker 24 may have an orientation notch that is recessed toward the center of the first main surface 21 along the a-axis or m-axis direction in a plan view, instead of or in addition to the orientation flat.

[0033] The semiconductor wafer 20 may have a diameter of 50 mm to 300 mm (i.e., 2 inches to 12 inches) in plan view. The diameter of the semiconductor wafer 20 is defined by the length of the chord passing through the center of the inspection semiconductor structure 2A outside the mark 24. The semiconductor wafer 20 may have a thickness of 100 μm to 1000 μm.

[0034] The test semiconductor structure 2A includes an n-type (first conductivity type) first semiconductor region 25 formed in the region on the second main surface 22 side within the semiconductor wafer 20. The first semiconductor region 25 is formed in a layered manner extending along the second main surface 22 and is exposed from the second main surface 22 and the side surface 23. The first semiconductor region 25 may have a thickness of 50 μm or more and 995 μm or less.

[0035] The test semiconductor structure 2A includes an n-type second semiconductor region 26 formed in the region on the first main surface 21 side within the semiconductor wafer 20. The second semiconductor region 26 has a lower n-type impurity concentration than the first semiconductor region 25 and is electrically connected to the first semiconductor region 25 within the semiconductor wafer 20. The second semiconductor region 26 is formed in a layered manner extending along the first main surface 21 and is exposed from the first main surface 21 and the side surface 23. The second semiconductor region 26 has a thickness in the vertical direction Z that is less than the thickness of the first semiconductor region 25. The thickness of the second semiconductor region 26 may be 5 μm or more and 50 μm or less. Preferably, the thickness of the second semiconductor region 26 is 30 μm or less.

[0036] In this configuration, the first semiconductor region 25 consists of a semiconductor substrate (specifically a SiC semiconductor substrate) and forms part of the second main surface 22 and side surface 23. In this configuration, the second semiconductor region 26 consists of an epitaxial layer (specifically a SiC epitaxial layer) and forms part of the first main surface 21 and side surface 23. In other words, the semiconductor wafer 20 has a laminated structure including a semiconductor substrate and an epitaxial layer.

[0037] The inspection semiconductor structure 2A includes a plurality of inspection areas 30 provided on the first main surface 21. Each of the plurality of inspection areas 30 is set in a rectangular shape in a plan view. In this configuration, the plurality of inspection areas 30 are arranged in a matrix along the first direction X and the second direction Y in a plan view. The plurality of inspection areas 30 define the minimum unit of measurement area with respect to the mounting surface 8a of the chuck stage 8. In other words, the ratio of the plurality of inspection areas 30 to the first main surface 21 defines the resolution with respect to the mounting surface 8a. By reducing the planar area of ​​the inspection areas 30 and increasing the number of inspection areas 30, the resolution with respect to the mounting surface 8a is improved, and the detection accuracy of foreign matter adhering to the mounting surface 8a is improved.

[0038] Preferably, each inspection area 30 has a flat area of ​​0.1 mm × 0.1 mm or more. Preferably, the flat area of ​​each inspection area 30 is 25 mm × 25 mm or less. Preferably, the multiple inspection areas 30 occupy 70% or more but less than 100% of the area of ​​the first main surface 21. Furthermore, when the inspection semiconductor structure 2A is placed on the mounting surface 8a, preferably the multiple inspection areas 30 occupy 70% or more but less than 100% of the contact area between the inspection semiconductor structure 2A and the mounting surface 8a.

[0039] The number of inspection areas 30 may be between 10 and 3000. When a semiconductor wafer 20 (SiC wafer) with a diameter of 100 mm or less (4 inches or less) is used, the number of inspection areas 30 may be between 10 and 100. When a semiconductor wafer 20 (SiC wafer) with a diameter of 100 mm or more (4 inches or more) is used, the number of inspection areas 30 may be between 100 and 3000.

[0040] The test semiconductor structure 2A further includes a plurality of functional devices 31 formed in each test region 30 on the first main surface 21. Each functional device 31 is formed using a portion of the second semiconductor region 26, spaced inward from the periphery of each test region 30. Preferably, all functional devices 31 consist of identical devices having equal electrical characteristics. Each functional device 31 may include at least one of a switching device, a rectifier device, and a passive device.

[0041] The switching device may include at least one of the following: MISFET (Metal Insulator Semiconductor Field Effect Transistor), BJT (Bipolar Junction Transistor), IGBT (Insulated Gate Bipolar Junction Transistor), and JFET (Junction Field Effect Transistor). The rectifier device may include at least one of the following: pn junction diode, pin junction diode, Zener diode, SBD (Schottky Barrier Diode), and FRD (Fast Recovery Diode). The passive device may include at least one of the following: resistor, capacitor, and inductor.

[0042] Each functional device 31 may include a circuit network (e.g., an integrated circuit such as an LSI) that combines at least two of the switching devices, rectifying devices, and passive devices. In this embodiment, each functional device 31 includes an SBD. Since the structures of multiple test areas 30 (functional devices 31) are similar, the structure of one test area 30 (functional device 31) will be described below.

[0043] The semiconductor structure 2A for testing includes a p-type (second conductivity type) guard region 32 formed on the surface layer of the first main surface 21 in the testing region 30. The guard region 32 is formed on the surface layer of the second semiconductor region 26, spaced inward from the periphery of the testing region 30. In a plan view, the guard region 32 is formed in an annular shape (a square annular shape in this form) surrounding the inner part of the testing region 30. Thus, the guard region 32 is formed as a guard ring region. The guard region 32 has an inner edge on the inner side of the testing region 30 and an outer edge on the periphery side of the testing region 30.

[0044] The semiconductor structure 2A for testing includes a main surface insulating film 33 that covers the first main surface 21 in the testing area 30. The main surface insulating film 33 includes at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. Preferably, the main surface insulating film 33 has a single-layer structure made of a silicon oxide film. Particularly preferably, the main surface insulating film 33 includes a silicon oxide film made of the oxide of the semiconductor wafer 20.

[0045] The main surface insulating film 33 has contact openings 34 that expose the inner portion of the inspection area 30 and the inner circumference of the guard area 32. The main surface insulating film 33 covers the inner portion of the inspection area 30 with a gap inward from the periphery of the inspection area 30, and exposes the first main surface 21 (second semiconductor area 26) from the periphery of the inspection area 30. In other words, the main surface insulating film 33 exposes the boundaries of multiple inspection areas 30. Of course, the main surface insulating film 33 may also cover the periphery of the inspection area 30 (the boundaries of multiple inspection areas 30).

[0046] The semiconductor structure 2A for inspection includes a first main surface electrode 40 in the inspection region 30 that has a first hardness (Vickers hardness [unit: Hv]) and covers the first main surface 21. The first hardness may be 15 Hv or more and 150 Hv or less. The first main surface electrode 40 is positioned at a distance from the periphery of the inspection region 30 inward. In this embodiment, the first main surface electrode 40 is formed in a rectangular shape along the periphery of the inspection region 30 in a plan view. The first main surface electrode 40 enters the contact opening 34 from above the main surface insulating film 33 and is electrically connected to the first main surface 21 and the inner edge of the guard region 32. The first main surface electrode 40 forms a Schottky junction with the second semiconductor region 26 (first main surface 21).

[0047] The thickness of the first main surface electrode 40 may be between 1 μm and 5.3 μm. Preferably, the first main surface electrode 40 is made of a metal film other than a plating film. In this embodiment, the first main surface electrode 40 has a laminated structure including a first metal film 41 and a second metal film 42 that are laminated in this order from the first main surface 21 side. Both the first metal film 41 and the second metal film 42 are formed by sputtering.

[0048] The first metal film 41 consists of a relatively thin metal barrier film that forms a Schottky barrier with the first main surface 21 (second semiconductor region 26). In this embodiment, the first metal film 41 includes a Ti-based metal film. The first metal film 41 may have a single-layer structure consisting of a Ti film or a TiN film. The first metal film 41 may have a multilayer structure containing a Ti film and a TiN film in any order. The first metal film 41 may have a thickness of 10 nm to 300 nm.

[0049] The second metal film 42 is made of an Al-based metal film that forms the main body of the first main surface electrode 40 and has a first hardness. The second metal film 42 may contain at least one of a pure Al film (an Al film with a purity of 99% or more), an AlCu alloy film, an AlSi alloy film, and an AlSiCu alloy film. The second metal film 42 has a thickness that exceeds the thickness of the first metal film 41. The thickness of the second metal film 42 may be 1 μm or more and 5 μm or less.

[0050] The semiconductor structure 2A for testing includes an insulating film 50 that covers the first main surface electrode 40 in the testing area 30. The insulating film 50 covers the peripheral portion of the first main surface electrode 40 with a gap extending inward from the periphery of the testing area 30. The insulating film 50 defines the pad opening 51 in the inner part of the testing area 30 and defines the street opening 52 at the periphery of the testing area 30.

[0051] The pad opening 51 exposes the inner portion of the first main surface electrode 40. In this configuration, the pad opening 51 is partitioned in a rectangular shape along the periphery of the first main surface electrode 40 in a plan view. The street opening 52 extends along the periphery of the inspection area 30 and exposes the first main surface 21. Specifically, the street opening 52 is partitioned in a grid pattern extending in the first direction X and the second direction Y by a plurality of adjacent insulating films 50 in the first direction X and the second direction Y, exposing the boundaries of a plurality of inspection areas 30. If a main surface insulating film 33 is formed covering the periphery of the inspection area 30, the insulating film 50 partitions the street opening 52 that exposes the main surface insulating film 33.

[0052] The insulating film 50 is preferably thicker than the first main surface electrode 40. The thickness of the insulating film 50 may be 5.5 μm or more and 25 μm or less. In this embodiment, the insulating film 50 has a laminated structure including an inorganic insulating film 53 (inorganic film) and an organic insulating film 54 (organic film) stacked in this order from the first main surface electrode 40 side. The inorganic insulating film 53 includes at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The inorganic insulating film 53 preferably includes an insulating material different from the main surface insulating film 33. In this embodiment, the inorganic insulating film 53 consists of a silicon nitride film.

[0053] The organic insulating film 54 forms the main body of the insulating film 50. The organic insulating film 54 is preferably made of a photosensitive resin. The organic insulating film 54 may be negative or positive. The organic insulating film 54 may contain at least one of a polyimide film, a polyamide film, and a polybenzoxazole film. In this embodiment, the inorganic insulating film 53 consists of a polybenzoxazole film.

[0054] The organic insulating film 54 may cover the inorganic insulating film 53 such that it exposes either or both of the inner and outer periphery of the inorganic insulating film 53. In this embodiment, the organic insulating film 54 exposes both the inner and outer periphery of the inorganic insulating film 53 and demarcates the inorganic insulating film 53 from the pad opening 51 and the street opening 52. The organic insulating film 54 may cover the entire area of ​​the inorganic insulating film 53. The inorganic insulating film 53 may have a thickness of 0.5 μm or more and 5 μm or less. It is preferable that the organic insulating film 54 is thicker than the inorganic insulating film 53. The thickness of the organic insulating film 54 may be 5 μm or more and 20 μm or less.

[0055] The semiconductor structure 2A for testing includes a protective electrode 60 that covers the first main surface electrode 40 and has a second hardness (Vickers hardness [unit: Hv]) exceeding the first hardness of the first main surface electrode 40 in the testing area 30. The second hardness may be greater than 150 Hv and less than or equal to 700 Hv (preferably 500 Hv or more).

[0056] The protective electrode 60 is the object that the probe needle 13 contacts and is electrically connected to the probe needle 13. The protective electrode 60 protects the first main surface electrode 40, the functional device 31, the semiconductor wafer 20, etc., from damage caused by the contact action of the probe needle 13. Therefore, it is preferable that the second hardness exceeds the hardness of the probe needle 13. The protective electrode 60 forms a current path between itself and the second main surface 22, via the functional device 31 and the first main surface electrode 40.

[0057] The protective electrode 60 is formed on the first main surface electrode 40, spaced inward from the periphery of the inspection area 30. In this embodiment, the protective electrode 60 is positioned within the pad opening 51 and covers the inner portion of the first main surface electrode 40. The protective electrode 60 has an electrode surface located within the pad opening 51 and is not positioned outside the pad opening 51. The electrode surface is the contact surface of the probe needle 13. In a plan view, the protective electrode 60 has a planar shape (a rectangular shape in this embodiment) that aligns with the pad opening 51. In a plan view, the protective electrode 60 has an area less than the area of ​​the first main surface electrode 40.

[0058] The protective electrode 60 covers the wall surfaces of the first main surface electrode 40 and the insulating film 50 within the pad opening 51. Specifically, within the pad opening 51, the protective electrode 60 overlaps the inner circumference of the inorganic insulating film 53 from above the first main surface electrode 40 and covers the organic insulating film 54. The protective electrode 60 is formed with a gap from the opening end of the pad opening 51 toward the first main surface electrode 40, so as to expose a portion of the wall surface of the pad opening 51. In other words, the protective electrode 60 is thinner than the insulating film 50.

[0059] The thickness of the protective electrode 60 is preferably greater than the depth of the contact mark left by the probe needle 13. In other words, the protective electrode 60 may have a contact mark left by the probe needle 13 after contact with it. The depth of the contact mark is determined to some extent by the specifications of the probe needle 13 (including its material and shape), as well as the pressure applied to the protective electrode 60 by the probe needle 13. The contact mark is also expanded by an increase in the number of times the probe needle 13 contacts the protective electrode 60. Therefore, the depth of the contact mark may be defined by the depth of the accumulated contact mark formed when the probe needle 13 contacts the same location on the protective electrode 60 for a target number of contacts.

[0060] The target number of contacts of the probe needle 13 is preferably set to the target number of reuses of the semiconductor structure 2A for inspection. In this case, the protective electrode 60 can withstand the target number of reuses of the semiconductor structure 2A for inspection. When the target number of reuses (target number of contacts) was set to 400 times and the probe needle 13 was brought into contact with the same location on the protective electrode 60 400 times, the depth of the contact marks on the protective electrode 60 was 0.02 μm or more and 0.04 μm or less. Therefore, it is preferable that the protective electrode 60 is 0.05 μm or more.

[0061] The thickness of the protective electrode 60 is preferably 25 μm or less (preferably less than 25 μm), taking into consideration the thickness of the insulating film 50. The thickness of the protective electrode 60 may also be 20 μm or less (preferably less than 20 μm), taking into consideration the upper limit of the thickness of the organic insulating film 54. Of course, the thickness of the protective electrode 60 may also be 10 μm or less. The thickness of the protective electrode 60 is preferably greater than or equal to the thickness of the inorganic insulating film 53 and less than or equal to the thickness of the organic insulating film 54. The thickness of the protective electrode 60 is particularly preferably greater than the thickness of the inorganic insulating film 53 and less than the thickness of the organic insulating film 54. Furthermore, it is preferable that the protective electrode 60 is thicker than the first main surface electrode 40.

[0062] The protective electrode 60 is preferably made of a plated film. In this embodiment, the protective electrode 60 has a laminated structure including a Ni film 61 laminated on the first main surface electrode 40, a Pd film 62 laminated on the Ni film 61, and an Au film 63 laminated on the Pd film 62. The Ni film 61 is formed by electroless plating starting from the first main surface electrode 40. The Pd film 62 is formed by electroless plating starting from the Ni film 61. The Au film 63 is formed by electroless plating starting from the Pd film 62.

[0063] The Ni film 61 forms the main body of the protective electrode 60 and has a second hardness exceeding the first hardness of the first metal film 41 (Al-based metal film). Preferably, the Ni film 61 occupies a thickness of 60% to 100% (less than 100% in this configuration) of the thickness of the protective electrode 60. Specifically, the Ni film 61 rides up on the inner circumference of the inorganic insulating film 53 from above the first main surface electrode 40 within the pad opening 51 and is in contact with the organic insulating film 54. The Ni film 61 is formed with a gap from the opening end of the pad opening 51 toward the first main surface electrode 40 so as to expose a part of the wall surface of the pad opening 51.

[0064] The Ni film 61 may have a thickness of 0.03 μm or more and 25 μm or less (in this embodiment, 0.03 μm or more and 24.6 μm or less). Preferably, the Ni film 61 has a thickness of 0.05 μm or more. The thickness of the Ni film 61 may be 20 μm or less (preferably less than 20 μm). Of course, the thickness of the Ni film 61 may be 10 μm or less. Preferably, the Ni film 61 has a thickness that exceeds the thickness of the first metal film 41 (Al-based metal film).

[0065] The Pd film 62 coats the Ni film 61 in a film-like manner within the pad opening 51 and is in contact with the organic insulating film 54. Preferably, the Pd film 62 has a thickness less than the thickness of the Ni film 61. Preferably, the Pd film 62 has a thickness of 0.01 μm or more and 0.2 μm or less.

[0066] The Au film 63 coats the Pd film 62 in a film-like manner within the pad opening 51 and is in contact with the organic insulating film 54. The Au forms an electrode surface within the pad opening 51. It is preferable that the Au film 63 has a thickness less than the thickness of the Ni film 61. It is preferable that the Au film 63 has a thickness of 0.01 μm or more and 0.2 μm or less.

[0067] The protective electrode 60 only needs to include a Ni film 61, and the presence or absence of a Pd film 62 and an Au film 63 is optional. Therefore, the protective electrode 60 may have a single-layer structure consisting of a Ni film 61. In this case, the Ni film 61 may have a thickness of 0.03 μm to 25 μm (preferably 0.05 μm or more). Alternatively, the protective electrode 60 may have a laminated structure including a Ni film 61 and an Au film 63 stacked in this order from the first main surface electrode 40 side.

[0068] Furthermore, the protective electrode 60 may have a laminated structure including a Ni film 61 and a Pd film 62 stacked in this order from the first main surface electrode 40 side. In addition, the protective electrode 60 may include metal films other than the Pd film 62 and the Au film 63. For example, in a structure having an Au film 63, the protective electrode 60 may include an Ag film that further coats the Au film 63. In this case, the Ag film coats the Au film 63 in a film-like manner within the pad opening 51 and is in contact with the organic insulating film 54. The Ag film forms the electrode surface.

[0069] The semiconductor structure 2A for testing includes a second main surface electrode 65 that covers the second main surface 22. The second main surface electrode 65 is in contact with the mounting surface 8a of the chuck stage 8 and is electrically connected to the mounting surface 8a. The second main surface electrode 65 covers the entire area of ​​the second main surface 22 and forms ohmic contact with the second main surface 22.

[0070] The second main surface electrode 65 forms a current path between itself and each protective electrode 60, through each functional device 31. The second main surface electrode 65 may have a laminated structure including at least one of a Ti film, a Ni film, a Pd film, an Au film, and an Ag film. For example, the second main surface electrode 65 may have a laminated structure including a Ti film, a Ni film, a Pd film, and an Au film stacked in this order from the second main surface 22 side.

[0071] Figure 4 is a flowchart illustrating a method for manufacturing a semiconductor device using the semiconductor evaluation apparatus 1 shown in Figure 1 and the test semiconductor structure 2A shown in Figure 2. Figures 5A to 5F are schematic diagrams illustrating the flowchart shown in Figure 4. Referring to Figure 4, the method for manufacturing a semiconductor device includes an inspection process of the chuck stage 8 using the test semiconductor structure 2A (steps S1 to S8), and an evaluation process of the manufacturing semiconductor structure 2B (see Figure 5E) (steps S9 to S11). Each step will be described in detail below.

[0072] Referring to Figure 5A, in the inspection process of the chuck stage 8, first, the semiconductor structure 2A for inspection is brought into the probe device 3 (step S1 in Figure 4). The semiconductor structure 2A for inspection is placed on the mounting surface 8a of the chuck stage 8 with the second main surface electrode 65 (second main surface 22) electrically connected to the mounting surface 8a and the protective electrode 60 connected to the probe needle 13.

[0073] Next, referring to Figure 5B, the inspection process of the mounting surface 8a is performed by the tester device 4 (step S2 in Figure 4). In this process, the probe needle 13 is brought into contact with the protective electrode 60, and the mounting surface 8a and the probe needle 13 are energized via the inspection semiconductor structure 2A. Specifically, in this process, the relative positions of the probe needle 13 and the inspection semiconductor structure 2A are changed so that the probe needle 13 sequentially contacts the protective electrode 60 of each inspection area 30, and an inspection current I1 is sequentially applied from the tester device 4 between the mounting surface 8a and the probe needle 13. The energization results of the mounting surface 8a and the probe needle 13 in each inspection area 30 are input to the tester device 4.

[0074] The energization result for each test area 30 is specifically either the voltage value and / or resistance value between the mounting surface 8a and the probe needle 13. The energization result for each test area 30 (measurement result from the tester device 4) is input from the tester device 4 to the control device 5. The control device 5 determines that the mounting surface 8a is normal if the energization result for each test area 30 is normal, and determines that the mounting surface 8a is abnormal if the energization result for each test area 30 is abnormal. When the mounting surface 8a is abnormal, this includes cases where foreign matter is attached to the mounting surface 8a or where the mounting surface 8a is deteriorated.

[0075] Referring to FIG. 5C, when it is determined that the mounting surface 8a is abnormal (step S3 in FIG. 4: YES), the test semiconductor structure 2A is unloaded from the prober device 3 (step S4 in FIG. 4), and a maintenance process of the chuck stage 8 is performed (step S5 in FIG. 4). The maintenance process of the chuck stage 8 may include a process of removing foreign matter from the mounting surface 8a or a process of replacing the chuck stage 8 with another chuck stage 8. Thereafter, steps S1 to S3 are performed again.

[0076] When it is determined that the mounting surface 8a is normal (step S3 in FIG. 4: NO), it may be selected whether to measure the electrical characteristics of the functional device 31 (SBD in this embodiment) of the test semiconductor structure 2A (step S6 in FIG. 4). Referring to FIG. 5D, when the electrical characteristics of the functional device 31 are measured (step S6 in FIG. 4: YES), an evaluation process of the electrical characteristics of the functional device 31 is performed by the tester device 4 (step S7 in FIG. 4).

[0077] In this process, the probe needle 13 is brought into contact with the protection electrode 60, and the mounting surface 8a and the probe needle 13 are energized through the test semiconductor structure 2A. Specifically, in this process, the relative positions of the probe needle 13 and the test semiconductor structure 2A are changed so that the probe needle 13 is sequentially brought into contact with the protection electrode 60 of each inspection region 30, and an evaluation current I2 is sequentially applied between the mounting surface 8a and the probe needle 13. The energization results of the mounting surface 8a and the probe needle 13 in each inspection region 30 are input to the tester device 4.

[0078] The evaluation current I2 of the functional device 31 is preferably larger than the inspection current I1 of the mounting surface 8a (I1 < I2). For example, a breakdown current as the evaluation current I2 may be applied to the functional device 31, and a breakdown voltage as the energization result may be measured by the tester device 4. According to this process, the performance of the prober device 3 (particularly the mounting surface 8a and the probe needle 13) and the tester device 4 when applying a large current and a large voltage to the measurement target can be inspected in advance, and the risk of defects in subsequent processes can be reduced.

[0079] The electrical characteristic data of the test semiconductor structure 2A obtained in this process (which may include wafer maps, etc.) may be used to evaluate the electrical characteristics of the manufactured semiconductor structure 2B, which will be evaluated later. For example, the electrical characteristic data of the test semiconductor structure 2A may be compared with the electrical characteristic data of the manufactured semiconductor structure 2B. After the evaluation of the electrical characteristics of the functional device 31, the test semiconductor structure 2A is removed from the prober device 3 (step S8 in Figure 4). If the electrical characteristics of the functional device 31 are not measured (step S6: NO in Figure 4), the test semiconductor structure 2A is removed from the prober device 3 (step S8 in Figure 4).

[0080] After the inspection process (inspection method) of Chuck Stage 8 is performed, the evaluation process (steps S9 to S11) of the semiconductor structure 2B for manufacturing is carried out. Referring to Figure 5E, in the evaluation process of the semiconductor structure 2B for manufacturing, the semiconductor structure 2B for manufacturing is first brought into the prober device 3 (step S9 in Figure 4). It is preferable that the semiconductor structure 2B for manufacturing has the same structure as the semiconductor structure 2A for inspection.

[0081] In other words, the semiconductor structure for manufacturing 2B preferably includes a semiconductor wafer 20 (wide bandgap semiconductor wafer), a first semiconductor region 25, a second semiconductor region 26, a functional device 31, a guard region 32, a main surface insulating film 33, a first main surface electrode 40, an insulating film 50, a protective electrode 60, and a second main surface electrode 65, similar to the semiconductor structure for inspection 2A. In the semiconductor structure for manufacturing 2B, the multiple inspection regions 30 are replaced with "multiple device regions (30)". The multiple device regions (30) have different properties from the multiple inspection regions 30 in that they are separated into individual pieces in a later dicing process and become semiconductor devices.

[0082] This structure allows for continuous evaluation of the semiconductor structure 2B for manufacturing using the same equipment and settings as the semiconductor structure 2A for testing after the inspection process of the chuck stage 8, thereby reducing manufacturing man-hours. Of course, the semiconductor structure 2B for manufacturing may have a different structure (for example, different functional devices 31) than the semiconductor structure 2A for testing.

[0083] The semiconductor structure 2B for manufacturing is placed on the mounting surface 8a in a posture where the second main surface electrode 65 (second main surface 22) is electrically connected to the mounting surface 8a of the chuck stage 8 and the protection electrode 60 is connected to a probe. In the evaluation process of the semiconductor structure 2B for manufacturing, since the mounting surface 8a has been inspected in advance, defects of the semiconductor structure 2B for manufacturing due to foreign matters or the like on the mounting surface 8a are suppressed. Therefore, in the semiconductor structure 2B for manufacturing including a semiconductor wafer 20 (wide bandgap semiconductor wafer) which is more expensive than a Si wafer, an increase in manufacturing cost due to such defects can be avoided.

[0084] Next, referring to FIG. 5F, an evaluation process of the electrical characteristics of the semiconductor structure 2B for manufacturing is executed by the tester device 4 (step S10 in FIG. 4). In this process, the probe needle 13 is brought into contact with the protection electrode 60, and the mounting surface 8a and the probe needle 13 are energized through the semiconductor structure 2B for manufacturing. Specifically, in this process, the relative positions of the probe needle 13 and the semiconductor structure 2B for manufacturing are changed so that the probe needle 13 is sequentially brought into contact with the protection electrode 60 of each device region (30), and an evaluation current I3 is sequentially applied between the mounting surface 8a and the probe needle 13 from the tester device 4. The energization results of the mounting surface 8a and the probe needle 13 in each device region (30) are input to the tester device 4.

[0085] It is preferable that the evaluation current I3 of the semiconductor structure 2B for manufacturing is larger than the inspection current I1 of the mounting surface 8a (I1 < I3). It is particularly preferable that the evaluation current I3 of the semiconductor structure 2B for manufacturing is the same as the evaluation current I2 of the semiconductor structure 2A for inspection (I2 = I3). For the semiconductor structure 2B for manufacturing, a breakdown current as the evaluation current I3 may be applied to the functional device 31, and a breakdown voltage as the energization result may be measured by the tester device 4.

[0086] The energization results for each device region (30) are input from the tester device 4 to the control device 5. The control device 5 determines that the electrical characteristics of the semiconductor structure 2B for manufacturing are normal if the energization results for each device region (30) are normal, and determines that the electrical characteristics of the semiconductor structure 2B for manufacturing are abnormal if the energization results for each device region (30) are abnormal. Subsequently, the semiconductor structure 2B for manufacturing is removed from the prober device 3 (step S11 in Figure 4), and the dicing process is carried out. A semiconductor device is manufactured through the process including the above.

[0087] The inspection process of the mounting surface 8a (steps S1 to S8 in Figure 4) is performed at any time, such as when the semiconductor evaluation apparatus 1 is started up or after the manufacturing semiconductor structure 2B is unloaded, and the inspection semiconductor structure 2A is reused each time. In other words, the inspection semiconductor structure 2A is used with the premise of long-term reuse, and the semiconductor device manufacturing method includes a process for reusing the inspection semiconductor structure 2A. The evaluation process of the electrical characteristics of the functional device 31 (step S7 in Figure 4) is one form of the process for reusing the inspection semiconductor structure 2A.

[0088] Figure 6 is a graph showing the reliability of the test semiconductor structure 2A shown in Figure 2. In Figure 6, the vertical axis represents the ratio [%] to the first measurement value, and the horizontal axis represents the number of measurements. Figure 6 shows a first plot group G1 composed of black circles and a second plot group G2 composed of white circles. The first plot group G1 shows the measurement results of a test semiconductor structure (not shown) related to a reference example, and the second plot group G2 shows the measurement results of the test semiconductor structure 2A according to the first embodiment. The test semiconductor structure related to the reference example has the same structure as the test semiconductor structure 2A according to the first embodiment, except that it does not have a protective electrode 60.

[0089] Referring to the first plot group G1, in the case of the semiconductor structure for testing according to the reference example, the measured values ​​became abnormal after approximately 30 reuses, making reuse impossible. In contrast, referring to the second plot group G2, in the case of the semiconductor structure for testing 2A according to the first embodiment, no abnormalities in the measured values ​​were observed even after more than 30 reuses, and it was possible to reuse it more than 100 times. Here, the target number of reuses was set to 400, and 400 reuses were performed, but the measured values ​​remained stable.

[0090] The semiconductor structure for testing in the reference example does not have a protective electrode 60. Therefore, contact marks caused by contact with the probe needle 13 occur on the first main surface electrode 40. In some cases, these contact marks penetrate the first main surface electrode 40 and reach the semiconductor wafer 20. These types of contact marks accumulate with reuse and cause abnormal measurement values. The semiconductor structure for testing in the reference example is relatively unreliable and requires replacement before reaching the number of reuses at which abnormalities are expected to occur. In other words, the semiconductor structure for testing in the reference example requires an increased replacement frequency (i.e., the number of semiconductor structures for testing manufactured), which increases manufacturing costs.

[0091] On the other hand, the semiconductor structure 2A for inspection according to the first embodiment includes a semiconductor wafer 20 (semiconductor plate), an inspection area 30, a first main surface electrode 40, and a protective electrode 60. The semiconductor wafer 20 has a first main surface 21 on one side and a second main surface 22 on the other side. The inspection area 30 is provided on the first main surface 21. The first main surface electrode 40 has a first hardness and covers the first main surface 21 in the inspection area 30.

[0092] The protective electrode 60 has a second hardness exceeding the first hardness, covers the first main surface electrode 40 in the inspection area 30, and forms a current path through the semiconductor wafer 20 between it and the second main surface 22. With this structure, the relatively hard protective electrode 60 can protect the first main surface electrode 40 and the semiconductor wafer 20 from contact marks of the probe needle 13. This suppresses fluctuations in measurement values ​​caused by contact marks, allowing the inspection semiconductor structure 2A to be reused over a long period of time. Thus, a highly reliable inspection semiconductor structure 2A can be provided.

[0093] Figure 7 is a plan view showing the semiconductor structure 2C for testing according to the second embodiment. Figure 8 is a cross-sectional view along the line VIII-VIII shown in Figure 7. Figure 9 is an enlarged cross-sectional view of the main part of the functional device 31 shown in Figure 7.

[0094] Referring to Figures 7 to 9, the test semiconductor structure 2C has a different structure from the aforementioned test semiconductor structure 2A in that the functional device 31 includes a MISFET (Metal Insulator Semiconductor Field Effect Transistor) instead of an SBD. In this configuration, the MISFET is of the trench gate type. The differences between the test semiconductor structure 2C and the test semiconductor structure 2A will be explained below. Also, since the structures of multiple test regions 30 (functional devices 31) are similar, the structure of one test region 30 (functional device 31) will be explained below.

[0095] The test semiconductor structure 2C includes a p-type body region 70 formed on the surface of the first main surface 21 in the test region 30. The body region 70 is formed on the surface of the second semiconductor region 26, spaced apart from the bottom of the second semiconductor region 26 toward the first main surface 21. The test semiconductor structure 2C includes an n-type source region 71 formed on the surface of the body region 70. The source region 71 has a higher n-type impurity concentration than the second semiconductor region 26. The source region 71 forms a channel of the MISFET with the second semiconductor region 26 within the body region 70.

[0096] The test semiconductor structure 2C includes a plurality of trench gate structures 72 formed on the first main surface 21 in the test region 30. The plurality of trench gate structures 72 control channel inversion and non-inversion. The plurality of trench gate structures 72 penetrate the body region 70 and the source region 71 to the second semiconductor region 26. The plurality of trench gate structures 72 may be arranged at intervals in the first direction X in a plan view and each may be formed in a strip shape extending in the second direction Y.

[0097] Each trench gate structure 72 includes a gate trench 73, a gate insulating film 74, and a gate electrode 75. The gate trench 73 is formed on the first main surface 21. The gate insulating film 74 covers the wall surface of the gate trench 73. The gate electrode 75 is embedded in the gate trench 73 with the gate insulating film 74 in between. The gate electrode 75 faces the channel with the gate insulating film 74 in between.

[0098] The test semiconductor structure 2C includes a plurality of trench source structures 76 formed on the first main surface 21 in the test region 30. The plurality of trench source structures 76 are each arranged in the region between two adjacent trench gate structures 72 on the first main surface 21. The plurality of trench source structures 76 may each be formed in a strip shape extending in the second direction Y in a plan view. The plurality of trench source structures 76 penetrate the body region 70 and the source region 71 to the second semiconductor region 26. The plurality of trench source structures 76 have a depth that exceeds the depth of the trench gate structure 72.

[0099] Each trench source structure 76 includes a source trench 77, a source insulating film 78, and a source electrode 79. The source trench 77 is formed on the first main surface 21. The source insulating film 78 covers the wall surface of the source trench 77. The source electrode 79 is embedded in the source trench 77, sandwiching the source insulating film 78.

[0100] The test semiconductor structure 2C includes a plurality of p-type contact regions 80 formed in the regions along the plurality of trench source structures 76 in the test region 30. The plurality of contact regions 80 have a higher p-type impurity concentration than the body region 70. Each contact region 80 covers the side and bottom walls of each trench source structure 76 and is electrically connected to the body region 70.

[0101] The test semiconductor structure 2C includes a plurality of p-type well regions 81 formed in the region along the plurality of trench source structures 76 in the test region 30. Each well region 81 has a p-type impurity concentration that is higher than that of the body region 70 and lower than that of the contact region 80. Each well region 81 covers the corresponding trench source structure 76, sandwiching the corresponding contact region 80. Each well region 81 covers the side and bottom walls of the corresponding trench source structure 76 and is electrically connected to the body region 70.

[0102] The semiconductor structure 2C for testing includes the aforementioned main surface insulating film 33 that covers the first main surface 21 in the testing region 30. The main surface insulating film 33 is continuous with the gate insulating film 74 and the source insulating film 78, and exposes the gate electrode 75 and the source electrode 79. In this embodiment, the main surface insulating film 33 covers the peripheral edge of the testing region 30 (the boundary between multiple testing regions 30). Of course, the main surface insulating film 33 may also expose the peripheral edge of the testing region 30 (the boundary between multiple testing regions 30).

[0103] The semiconductor structure 2C for inspection includes an interlayer insulating film 82 that covers the main surface insulating film 33 in the inspection region 30. The interlayer insulating film 82 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The interlayer insulating film 82 covers a plurality of trench gate structures 72 and a plurality of trench source structures 76. In this embodiment, the interlayer insulating film 82 covers the peripheral portion of the inspection region 30 (the boundary portion of the plurality of inspection regions 30) with the main surface insulating film 33 in between. Of course, the main surface insulating film 33 may expose the first main surface 21 or the main surface insulating film 33 at the peripheral portion of the inspection region 30 (the boundary portion of the plurality of inspection regions 30).

[0104] The inspection semiconductor structure 2C includes a plurality of the aforementioned first main surface electrodes 40 that cover the interlayer insulating film 82 in the inspection region 30. The plurality of first main surface electrodes 40 have a laminated structure including a first metal film 41 and a second metal film 42 stacked in this order from the first main surface 21 side, as in the first embodiment. In this embodiment, the first metal film 41 forms ohmic contact with the first main surface 21.

[0105] The multiple first main surface electrodes 40 include a gate main surface electrode 40a and a source main surface electrode 40b. In this embodiment, the gate main surface electrode 40a is located in a region adjacent to the center of one side of the inspection area 30 in a plan view. The gate main surface electrode 40a may be located at the corner of the inspection area 30 in a plan view. In this embodiment, the gate main surface electrode 40a is formed in a rectangular shape in a plan view.

[0106] The source main electrode 40b is positioned on the interlayer insulating film 82 at a distance from the gate main electrode 40a. In this embodiment, the source main electrode 40b is formed in a polygonal shape with a recess that is recessed along the gate main electrode 40a in a plan view. Of course, the source main electrode 40b may be formed in a square shape in a plan view. The source main electrode 40b penetrates the interlayer insulating film 82 and the main surface insulating film 33 and is electrically connected to a plurality of trench source structures 76, source regions 71 and a plurality of well regions 81.

[0107] The test semiconductor structure 2C includes a gate wiring electrode 83 drawn out from the gate main surface electrode 40a onto the interlayer insulating film 82 in the test region 30. The gate wiring electrode 83, like the plurality of first main surface electrodes 40, has a laminated structure including a first metal film 41 and a second metal film 42 stacked in this order from the first main surface 21 side. The gate wiring electrode 83 is formed in a strip shape extending along the periphery of the test region 30 so as to intersect (specifically orthogonally) with the ends of the plurality of trench gate structures 72 in a plan view. The gate wiring electrode 83 penetrates the interlayer insulating film 82 and is electrically connected to the plurality of trench gate structures 72.

[0108] The test semiconductor structure 2C includes the aforementioned insulating film 50 that covers a plurality of first main surface electrodes 40 in the test region 30. Similar to the first embodiment, the insulating film 50 has a laminated structure including an inorganic insulating film 53 and an organic insulating film 54 stacked in this order from the first main surface electrode 40 side. In this embodiment, the insulating film 50 covers the peripheral edges of the gate main surface electrode 40a and the source main surface electrode 40b, spaced inward from the periphery of the test region 30. The insulating film 50 covers the entire area of ​​the gate wiring electrode 83.

[0109] The insulating film 50 defines a plurality of pad openings 51 in the inner part of the inspection area 30 that expose the inner parts of the gate main surface electrode 40a and the source main surface electrode 40b, and defines a street opening 52 in the peripheral part of the inspection area 30 that exposes the interlayer insulating film 82. In this embodiment, the plurality of pad openings 51 include a gate pad opening 51a that exposes the inner part of the gate main surface electrode 40a, and a source pad opening 51b that exposes the inner part of the source main surface electrode 40b.

[0110] In this embodiment, the gate pad opening 51a is partitioned into a rectangular shape along the periphery of the gate main surface electrode 40a in a plan view. In this embodiment, the source pad opening 51b is formed into a polygonal shape along the periphery of the source main surface electrode 40b in a plan view. The street opening 52 is formed in the same manner as in the first embodiment.

[0111] The organic insulating film 54 may cover the inorganic insulating film 53 such that it exposes either or both of the inner and outer periphery of the inorganic insulating film 53. In this embodiment, the organic insulating film 54 exposes both the inner and outer periphery of the inorganic insulating film 53 and demarcates the inorganic insulating film 53 from the plurality of pad openings 51 and street openings 52. The organic insulating film 54 may cover the entire area of ​​the inorganic insulating film 53.

[0112] The test semiconductor structure 2C includes a plurality of the aforementioned protective electrodes 60 that each cover a plurality of first main surface electrodes 40 in the test region 30. The plurality of protective electrodes 60 include at least one of Ni film 61, Pd film 62, Au film 63, and Ag film, as in the first embodiment. In this embodiment, the plurality of protective electrodes 60 include a gate protective electrode 60a and a source protective electrode 60b.

[0113] The gate protection electrode 60a is formed on the gate main surface electrode 40a, spaced inward from the periphery of the gate main surface electrode 40a. The gate protection electrode 60a forms a current path to the gate electrode 75 via the gate main surface electrode 40a and the gate wiring electrode 83. In this embodiment, the gate protection electrode 60a is positioned within the gate pad opening 51a and covers the inner portion of the gate main surface electrode 40a.

[0114] The gate protection electrode 60a has a gate electrode surface located within the gate pad opening 51a and is not positioned outside the gate pad opening 51a. The gate electrode surface is the contact surface of the probe needle 13. The gate protection electrode 60a is formed in a planar shape that aligns with the gate pad opening 51a in a planar view (in this configuration, a rectangular shape along the periphery of the gate main surface electrode 40a). The gate protection electrode 60a has an area less than the area of ​​the gate main surface electrode 40a in a planar view.

[0115] The gate protection electrode 60a covers the gate main surface electrode 40a and the wall surface of the insulating film 50 within the gate pad opening 51a. Specifically, within the gate pad opening 51a, the gate protection electrode 60a overlaps the inner circumference of the inorganic insulating film 53 from above the gate main surface electrode 40a and covers the organic insulating film 54. The gate protection electrode 60a is formed with a gap from the opening end of the gate pad opening 51a toward the gate main surface electrode 40a, so as to expose a portion of the wall surface of the gate pad opening 51a. In other words, the gate protection electrode 60a is thinner than the insulating film 50.

[0116] The source protection electrode 60b is formed on the source main surface electrode 40b, spaced inward from the periphery of the source main surface electrode 40b. The source protection electrode 60b forms a current path between the functional device 31 and the source main surface electrode 40b and the second main surface 22. In this embodiment, the source protection electrode 60b is positioned within the source pad opening 51b and covers the inner portion of the source main surface electrode 40b.

[0117] The source protection electrode 60b has a source electrode surface located within the source pad opening 51b and is not positioned outside the source pad opening 51b. The source electrode surface is the contact surface of the probe needle 13. The source protection electrode 60b is formed in a planar shape (in this embodiment, a polygonal shape with a recess) that is aligned with the source pad opening 51b in a planar view. The source protection electrode 60b has an area less than the area of ​​the source main surface electrode 40b in a planar view.

[0118] The source protection electrode 60b covers the source main surface electrode 40b and the wall surface of the insulating film 50 within the source pad opening 51b. Specifically, within the source pad opening 51b, the source protection electrode 60b overlaps the inner circumference of the inorganic insulating film 53 from above the source main surface electrode 40b and covers the organic insulating film 54. The source protection electrode 60b is formed with a gap from the opening end of the source pad opening 51b toward the source main surface electrode 40b, so as to expose a portion of the wall surface of the source pad opening 51b. In other words, the source protection electrode 60b is thinner than the insulating film 50.

[0119] The test semiconductor structure 2C includes the aforementioned second main surface electrode 65 that covers the second main surface 22. In this embodiment, the second main surface electrode 65 forms a current path between each source protection electrode 60b and each functional device 31.

[0120] The process shown in Figures 4 to 5F also applies to the semiconductor structure 2C for inspection. In this case, the probe device 3 includes at least two probe units 7. Specifically, the at least two probe units 7 include at least one gate probe unit 7 and at least one source probe unit 7. The gate probe unit 7 includes a gate probe needle 13 that contacts the gate protection electrode 60a. The source probe unit 7 includes a source probe needle 13 that contacts the source protection electrode 60b.

[0121] In the inspection process of the mounting surface 8a, a gate signal is applied from the gate probe needle 13 to the gate protection electrode 60a, and a drain-source current as an inspection current I1 is applied between the mounting surface 8a and the source probe needle 13. The tester device 4 measures either or both of the voltage and resistance values ​​between the mounting surface 8a and the source probe needle 13 based on the energization results of the mounting surface 8a and the source probe needle 13, as in the first embodiment.

[0122] The semiconductor structure for manufacturing 2B (see Figure 5E), which is evaluated after the inspection process of the chuck stage 8 (mounting surface 8a), preferably has the same structure as the semiconductor structure for inspection 2C. That is, the semiconductor structure for manufacturing 2B preferably includes, like the semiconductor structure for inspection 2C, a semiconductor wafer 20 (wide bandgap semiconductor wafer), a first semiconductor region 25, a second semiconductor region 26, a functional device 31 (MISFET), a main surface insulating film 33, a first main surface electrode 40 (gate main surface electrode 40a and source main surface electrode 40b), an insulating film 50, a protective electrode 60 (gate protective electrode 60a and source protective electrode 60b), a second main surface electrode 65, a body region 70, a source region 71, a trench gate structure 72, a trench source structure 76, a contact region 80, a well region 81, an interlayer insulating film 82, and a gate wiring electrode 83. In the semiconductor structure for manufacturing 2B, the multiple inspection regions 30 are read as "multiple device regions (30)".

[0123] As described above, even when the semiconductor structure 2C for testing is applied to the semiconductor evaluation apparatus 1, the same effects and advantages as those described in the first embodiment are achieved.

[0124] The following are examples of other embodiments of the semiconductor evaluation apparatus 1. Figure 10 is a schematic diagram showing a second embodiment of the semiconductor evaluation apparatus 1 shown in Figure 1. In Figure 1, an example was shown in which the probe apparatus 3 includes a manipulator-type probe unit 7. However, as shown in Figure 10, the probe apparatus 3 may include a cantilever-type probe unit 7. In this embodiment, the probe unit 7 includes a card substrate 90, a support portion 91, at least one probe needle 13, and a fixing portion 92.

[0125] The card substrate 90 is made of a resin PCB (Printed Circuit Board). The card substrate 90 is positioned at a height that is vertically separated Z from the semiconductor structure 2 when the semiconductor structure 2 is placed on the mounting surface 8a of the chuck stage 8. In this embodiment, the card substrate 90 has a first surface 90a facing the mounting surface 8a (semiconductor structure 2) and a second surface 90b opposite to the first surface 90a, and is formed in an annular (e.g., circular or rectangular annular) plate shape with a through hole 90c in the center. The card substrate 90 also includes at least one via hole 90d and wiring 90e selectively routed to the first surface 90a and the second surface 90b via the via hole 90d.

[0126] The support portion 91 consists of an annular (e.g., circular or rectangular annular) insulating plate (e.g., a ceramic plate) having a through hole 91a in its center, and is positioned parallel to the first plate surface 90a on the side of the first plate surface 90a. The support portion 91 is positioned on the side of the first plate surface 90a, facing the through hole 90c, such that the through hole 91a communicates with the through hole 90c of the card substrate 90.

[0127] The probe needle 13 is positioned on the first board surface 90a side of the card substrate 90 so as to be supported by the support portion 91 and is electrically connected to the wiring 90e. In this embodiment, the probe needle 13 is formed in an L-shape having a first portion 13a extending along the first board surface 90a and a second portion 13b extending toward the mounting surface 8a. The first portion 13a has a base end that is inserted through the via hole 90d and connected to the wiring 90e. The first portion 13a extends from the via hole 90d toward the through hole 90c so as to cross the support portion 91. The second portion 13b is located on the side of the card substrate 90 facing the through hole 90c (through hole 91a of the support portion 91) and has a sharp needle tip that contacts the semiconductor structure 2.

[0128] The number of probe needles 13 is adjusted according to the number of electrodes (contact points) in the part of the semiconductor structure 2 to be inspected. If the part of the semiconductor structure 2 to be inspected has multiple electrodes arranged in an array, multiple probe needles 13 are attached in an array on the first plate surface 90a side corresponding to the multiple electrodes. If the part of the semiconductor structure 2 to be inspected has a single electrode, one or more probe needles 13 are attached on the first plate surface 90a side.

[0129] The fixing part 92 is made of an insulator (for example, resin) and fixes the probe needle 13 to the support part 91. Specifically, the fixing part 92 fixes the first portion 13a of the probe needle 13 to the support part 91.

[0130] The tester device 4, as in the previously described embodiment, is electrically connected to the mounting surface 8a and the probe needle 13, applies a predetermined electrical signal between the mounting surface 8a and the probe needle 13, and obtains the result of current flow between the mounting surface 8a and the probe needle 13. In this embodiment, the tester device 4 includes a tester body 93 and a tester head 94. The tester body 93 is the part that generates the electrical signal applied between the mounting surface 8a and the probe needle 13 and obtains the result of current flow between the mounting surface 8a and the probe needle 13.

[0131] The tester head 94 is detachably mounted to the probe device 3 and electrically connected to the tester body 93. The tester head 94 is mounted to the probe device 3 so as to face the mounting surface 8a with the probe unit 7 in between. The tester head 94 has at least one contact portion electrically connected to the card board 90 (wiring 90e) and is electrically connected to the probe needle 13 via the wiring 90e. The tester head 94 applies an electrical signal from the tester body 93 to the probe needle 13 and applies an electrical signal (energization result) from the probe needle 13 to the tester body 93. The tester head 94 may be configured to convert the electrical signals applied from the tester body 93 and / or the probe needle 13 into another electrical signal and output it.

[0132] When a cantilever-type probe unit 7 is applied to the semiconductor structure 2C for inspection according to the second embodiment, the probe unit 7 includes at least two probe needles 13. Specifically, the at least two probe needles 13 include at least one gate probe needle 13 that contacts the gate protection electrode 60a, and at least one source probe needle 13 that contacts the source protection electrode 60b. Thus, even when a cantilever-type probe unit 7 is used, the same effects as those achieved in the embodiments described above are achieved.

[0133] Figure 11 is a schematic diagram showing a third embodiment of the semiconductor evaluation apparatus 1 shown in Figure 1. In Figure 10, a cantilever-type probe unit 7 was shown. However, the probe apparatus 3 may also include a vertical-type probe unit 7, as shown in Figure 11. In this embodiment, the probe unit 7 includes a cardboard substrate 95, a support plate 96, a support portion 97, and at least one probe needle 13.

[0134] The card substrate 95 is made of a resin PCB. The card substrate 95 is positioned at a height that is perpendicular to the semiconductor structure 2 in the Z direction when the semiconductor structure 2 is placed on the mounting surface 8a of the chuck stage 8. In this embodiment, the card substrate 95 is formed in a disc shape having a first surface 95a facing the mounting surface 8a (semiconductor structure 2) and a second surface 95b opposite to the first surface 95a. The card substrate 95 includes at least one via hole 95c and wiring 95d selectively routed to the first surface 95a and the second surface 95b via the via hole 95c.

[0135] The support plate 96 is made of an insulating plate (for example, a ceramic plate) and is positioned parallel to the first plate surface 95a on the side of the first plate surface 95a. The support plate 96 has through holes 96a in the portion facing the via holes 95c of the card substrate 95. The support portion 91 is fixed to the card substrate 95 and supports the support plate 96 at a position spaced apart from the first plate surface 95a toward the mounting surface 8a.

[0136] In this embodiment, the probe needle 13 is formed in a straight, needle-like shape. The probe needle 13 is supported by the support portion 91 on the first plate surface 95a side in an upright position along the vertical direction Z. Specifically, the probe needle 13 is positioned in the insertion hole 96a of the support portion 91 such that a gap is formed between it and the wiring 95d. The probe needle 13 has a base end located on the first plate surface 95a side relative to the support plate 96, and a sharp needle tip located on the mounting surface 8a side relative to the support plate 96, and is movably held by the support plate 96.

[0137] The probe needle 13 has a retaining portion 98 to prevent it from falling out of the support plate 96. The retaining portion 98 may be provided in the gap between it and the wiring 95d. The retaining portion 98 may be configured to abut against a part of the support plate 96 (the second plate surface 95b). In this embodiment, the retaining portion 98 is provided at the base end of the probe needle 13 and is formed by a wide portion having a width greater than the diameter of the insertion hole 96a. The retaining portion 98 may be formed by the bent portion of the probe needle 13, or it may be formed by a member other than the probe needle 13.

[0138] An external force is applied to the probe needle 13 toward the card substrate 95 due to its contact with the semiconductor structure 2. In this case, the probe needle 13 moves toward the card substrate 95 and comes into contact with the wiring 95d. As a result, the probe needle 13 is electrically connected to the wiring 95d.

[0139] Of course, other conductive materials may be placed in the gap between the wiring 95d and the probe needle 13. These other conductive materials may be formed, for example, in the shape of a coil or a leaf spring. The probe needle 13 may also be directly attached to the card substrate 90. In this case, a portion of the probe needle 13 may be formed in the shape of a leaf spring. The tester device 4 includes a tester body 93 and a tester head 94, as in the second embodiment described above.

[0140] When a vertical probe unit 7 is applied to the semiconductor structure 2C for inspection according to the second embodiment, the probe unit 7 includes at least two probe needles 13. Specifically, the at least two probe needles 13 include at least one gate probe needle 13 that contacts the gate protection electrode 60a, and at least one source probe needle 13 that contacts the source protection electrode 60b. Thus, even when a vertical probe unit 7 is used, the same effects as those achieved in the embodiments described above are achieved.

[0141] The embodiments described above can be implemented in other forms. In the embodiments described above, examples were shown in which the probe unit 7 consists of a manipulator type, a cantilever type, or a vertical type. However, the form of the probe unit 7 is arbitrary as long as the probe unit 7 has a probe needle 13, and is not limited to any particular form.

[0142] In the embodiments described above, examples were shown in which a semiconductor wafer 20 containing SiC as an example of a wide-bandgap semiconductor was used. However, a semiconductor wafer 20 containing a wide-bandgap semiconductor other than SiC may also be used. Examples of wide-bandgap semiconductors other than SiC include diamond and GaN (gallium nitride).

[0143] In the embodiments described above, an example was shown in which the insulating film 50 has a laminated structure including an inorganic insulating film 53 and an organic insulating film 54 stacked in this order from the first main surface electrode 40 side. However, the insulating film 50 may have a single-layer structure consisting of an organic insulating film 54 and not including the inorganic insulating film 53.

[0144] In the embodiments described above, an example was shown in which the protective electrode 60 (including the gate protective electrode 60a and the source protective electrode 60b) rests on the inner circumference of the inorganic insulating film 53 and covers the organic insulating film 54. However, the protective electrode 60 (including the gate protective electrode 60a and the source protective electrode 60b) may also rest on the inner circumference of the inorganic insulating film 53 with a gap between it and the organic insulating film 54 so as not to come into contact with the organic insulating film 54.

[0145] In this case, the Ni film 61 may be positioned at a distance from the organic insulating film 54 and overlap the inner circumference of the inorganic insulating film 53 so as not to come into contact with the organic insulating film 54. The Pd film 62 may also cover the Ni film 61 in a film-like manner and have a portion that comes into contact with the inorganic insulating film 53. The Au film 63 may also cover the Pd film 62 in a film-like manner and have a portion that comes into contact with the inorganic insulating film 53. Of course, an organic insulating film 54 may be formed to cover the inner circumference of the inorganic insulating film 53, and a protective electrode 60 may be formed within the pad opening 51 (including the gate pad opening 51a and the source pad opening 51b) that comes into contact only with the organic insulating film 54.

[0146] In the embodiments described above, examples were shown in which the test semiconductor structure 2A, the manufacturing semiconductor structure 2B, and the test semiconductor structure 2C included the second main surface electrode 65. However, test semiconductor structures 2A, manufacturing semiconductor structure 2B, and test semiconductor structure 2C that do not include the second main surface electrode 65 may also be employed.

[0147] In the embodiments described above, examples were shown in which the functional device 31 includes either an SBD or a MISFET. However, the functional device 31 may include both an SBD and a MISFET. That is, both the SBD and the MISFET may be formed within the same inspection region 30. Of course, in the embodiments described above, the functional device 31 including an SBD and the functional device 31 including a MISFET may be formed in different inspection regions 30 on the same semiconductor wafer 20.

[0148] In the second embodiment described above, an example was described in which a trench gate type MISFET was formed as an example of a functional device 31. However, the functional device 31 may include a planar gate type MISFET instead of a trench gate type.

[0149] In the second embodiment described above, a p-type first semiconductor region 25 may be used instead of an n-type first semiconductor region 25. In this case, the functional device 31 includes an IGBT (Insulated Gate Bipolar Transistor) instead of a MISFET. The specific configuration in this case can be obtained by replacing the "source" of the MISFET with the "emitter" of the IGBT and the "drain" of the MISFET with the "collector" of the IGBT, as described above.

[0150] In the embodiments described above, a configuration in which the first conductivity type is n-type and the second conductivity type is p-type was described. However, in the embodiments described above, a configuration in which the first conductivity type is p-type and the second conductivity type is n-type may also be adopted. In this case, the specific configuration can be obtained by replacing the n-type region with a p-type region and the p-type region with an n-type region, as shown in the above description and attached drawings.

[0151] The following are examples of features extracted from this specification and drawings. The following provides a highly reliable semiconductor structure for testing.

[0152] [A1] A semiconductor structure for inspection, comprising: a semiconductor plate having a first main surface on one side and a second main surface on the other side; an inspection area provided on the first main surface; a main surface electrode having a first hardness and covering the first main surface in the inspection area; and a protective electrode having a second hardness exceeding the first hardness, covering the main surface electrode in the inspection area, and forming a current path between itself and the second main surface via the semiconductor plate.

[0153] [A2] The semiconductor structure for testing according to A1, wherein a plurality of inspection areas are provided on the first main surface, a plurality of main surface electrodes cover the first main surface in each of the inspection areas, and a plurality of protective electrodes cover the plurality of main surface electrodes in each of the inspection areas, and each of the current paths are formed with the second main surface.

[0154] [A3] The semiconductor structure for inspection according to A1 or A2, wherein a plurality of the inspection regions are arranged on the first main surface along a first direction and a second direction intersecting the first direction.

[0155] [A4] The semiconductor structure for testing according to A2 or A3, wherein 100 or more of the above-mentioned testing areas are provided on the first main surface.

[0156] [A5] The semiconductor plate is a test semiconductor structure according to any one of A1 to A4, comprising a wide bandgap semiconductor.

[0157] [A6] The semiconductor plate is a test semiconductor structure according to any one of A1 to A5, comprising SiC.

[0158] [A7] The inspection semiconductor structure according to any one of A1 to A6, wherein the protective electrode consists of a surface to which the probe needle will make contact and has a thickness exceeding the depth of the contact mark left by the probe needle.

[0159] [A8] The protective electrode has a thickness of 0.05 μm or more, and is an inspection semiconductor structure according to any one of A1 to A7.

[0160] [A9] The protective electrode has a thickness of 25 μm or less, and is an inspection semiconductor structure according to any one of A1 to A8.

[0161] [A10] The main surface electrode has a thickness of 1 μm or more, and is an inspection semiconductor structure according to any one of A1 to A9.

[0162] [A11] The main surface electrode has a thickness of 5.3 μm or less, and is an inspection semiconductor structure according to any one of A1 to A10.

[0163] [A12] The protective electrode is thicker than the main surface electrode, and is an inspection semiconductor structure according to any one of A1 to A11.

[0164] [A13] The inspection semiconductor structure according to any one of A1 to A12, wherein the main surface electrode is made of a metal film other than a plating film, and the protective electrode is made of a plating film.

[0165] [A14] The inspection semiconductor structure according to any one of A1 to A13, wherein the main surface electrode includes an Al-based metal film and the protective electrode includes a Ni film.

[0166] [A15] The semiconductor structure for testing according to A14, wherein the Ni film is thicker than the Al-based metal film.

[0167] [A16] The semiconductor structure for testing according to A14 or A15, wherein the Ni film has a thickness of 0.03 μm or more and 25 μm or less.

[0168] [A17] The protective electrode is a test semiconductor structure according to any one of A14 to A16, comprising an Au film laminated on the Ni film.

[0169] [A18] The semiconductor structure for testing described in A17, wherein the Au film is thinner than the Ni film.

[0170] [A19] The semiconductor structure for testing according to A17 or A18, wherein the Au film has a thickness of 0.01 μm or more and 0.2 μm or less.

[0171] [A20] The inspection semiconductor structure according to any one of A17 to A19, wherein the protective electrode includes a Pd film interposed between the Ni film and the Au film.

[0172] [A21] The Pd film is thinner than the Ni film, and is a test semiconductor structure as described in A20.

[0173] [A22] The semiconductor structure for testing according to A20 or A21, wherein the Pd film has a thickness of 0.01 μm or more and 0.2 μm or less.

[0174] [A23] The inspection semiconductor structure according to any one of A1 to A22, wherein the protective electrode has an area less than the area of ​​the main surface electrode in a plan view.

[0175] [A24] The inspection semiconductor structure according to any one of A1 to A23, further comprising an insulating film that covers the peripheral edge of the main surface electrode and has an opening that exposes the inner portion of the main surface electrode, wherein the protective electrode covers the main surface electrode within the opening.

[0176] [A25] The protective electrode is a semiconductor structure for testing described in A24, which is thinner than the insulating film.

[0177] [A26] The inspection semiconductor structure according to A25, wherein the protective electrode has an electrode surface located on the main surface electrode side with respect to the surface of the insulating film.

[0178] [A27] The inspection semiconductor structure according to any one of A24 to A26, wherein the protective electrode is formed at a distance from the opening end of the opening toward the main surface electrode so as to expose a part of the wall surface of the opening.

[0179] [A28] The semiconductor structure for testing according to any one of A24 to A27, wherein the insulating film includes an organic film, and the protective electrode is in contact with the organic film within the opening.

[0180] [A29] The semiconductor structure for testing according to A28, wherein the organic film has a thickness of 5 μm or more and 20 μm or less.

[0181] [A30] The protective electrode is a semiconductor structure for testing according to A28 or A29, which is thinner than the organic film.

[0182] [A31] The semiconductor structure for testing according to any one of A28 to A30, wherein the organic film comprises at least one of a polyimide film, a polyamide film, and a polybenzoxazole film.

[0183] [A32] The semiconductor structure for testing according to any one of A28 to A31, wherein the insulating film includes an inorganic film interposed between the main surface electrode and the organic film.

[0184] [A33] The semiconductor structure for testing according to A32, wherein the inorganic film has a thickness of 0.5 μm or more and 5 μm or less.

[0185] [A34] The protective electrode is a semiconductor structure for testing according to A32 or A33, which is thicker than the inorganic film.

[0186] [A35] The semiconductor structure for testing according to any one of A32 to A34, wherein the inorganic film is exposed from the organic film within the opening, and the protective electrode is in contact with the inorganic film and the organic film within the opening.

[0187] [A36] The semiconductor structure for inspection according to any one of A1 to A35, further comprising a functional device formed on the first main surface in the inspection area, wherein the main surface electrode is electrically connected to the functional device, and the protective electrode is electrically connected to the functional device via the main surface electrode, forming the current path through the functional device with respect to the second main surface.

[0188] [A37] The functional device is a test semiconductor structure according to A36, comprising at least one of a diode and a transistor.

[0189] [A38] The semiconductor structure for testing according to any one of A1 to A37, further comprising a second main surface electrode that covers the second main surface and forms a current path through the semiconductor plate between itself and the protective electrode.

[0190] [A39] The semiconductor structure for testing according to A38, wherein the second main surface electrode covers the entire area of ​​the second main surface.

[0191] [A40] A chuck stage inspection apparatus comprising: a chuck stage having a conductive mounting surface; a conductive probe needle to which an electrical signal is applied; and an inspection semiconductor structure according to any one of A1 to A39, wherein the second main surface is electrically connected to the mounting surface and the protective electrode is positioned on the mounting surface in a position in contact with the probe needle.

[0192] [A41] The chuck stage inspection apparatus according to A40, wherein the probe needle is configured to have an electric current applied to it and the aforementioned surface.

[0193] [A42] A chuck stage inspection apparatus comprising: a prober device including a conductive mounting surface and a conductive probe needle; a tester device electrically connected to the mounting surface and the probe needle and applying an electrical signal between the mounting surface and the probe needle; and an inspection semiconductor structure according to any one of A1 to A39, wherein the second main surface is electrically connected to the mounting surface and the protective electrode is positioned on the mounting surface in a position in contact with the probe needle.

[0194] [A43] The chuck stage inspection device according to A42, wherein the tester device obtains at least one of the voltage value and resistance value between the probe needle and the chuck stage.

[0195] [A44] A method for inspecting a chuck stage using a semiconductor evaluation apparatus, comprising a chuck stage having a conductive mounting surface and a conductive probe needle to which an electrical signal is applied between the mounting surface and the chuck stage, comprising the steps of: placing an inspection semiconductor structure according to any one of A1 to A39 on the mounting surface in a position in which the second main surface is electrically connected to the mounting surface; and bringing the probe needle into contact with the protective electrode, applying an electrical signal between the mounting surface and the probe needle via the inspection semiconductor structure, and inspecting the state of the mounting surface from the result of energizing the mounting surface and the probe needle.

[0196] [A45] A method for inspecting a chuck stage using a semiconductor evaluation apparatus, comprising a chuck stage having a conductive mounting surface, a prober device including a conductive probe needle, and a tester device electrically connected to the mounting surface and the probe needle, which applies an electrical signal between the mounting surface and the probe needle, the method comprising: placing an inspection semiconductor structure according to any one of A1 to A39 on the mounting surface in a position in which the second main surface is electrically connected to the mounting surface; and contacting the probe needle with the protective electrode, applying an electrical signal between the mounting surface and the probe needle via the inspection semiconductor structure, and inspecting the state of the mounting surface from the result of energizing the mounting surface and the probe needle.

[0197] [A46] A method for manufacturing a semiconductor device, comprising the steps of: after performing the inspection method for a chuck stage described in A44 or A45, arranging a semiconductor structure to be processed into a semiconductor device on the aforementioned surface so as to be electrically connected to the aforementioned surface; and contacting the semiconductor structure to be manufactured with a probe needle, applying an electrical signal between the aforementioned surface and the probe needle via the semiconductor structure to inspect the electrical characteristics of the semiconductor structure to be manufactured.

[0198] [A47] A method for manufacturing a semiconductor device using a semiconductor evaluation apparatus, comprising: a chuck stage having a conductive mounting surface; and a conductive probe needle to which an electrical signal is applied between the mounting surface and the chuck stage, comprising the steps of: placing an inspection semiconductor structure according to any one of A1 to A39 on the mounting surface in a position in which the second main surface is electrically connected to the mounting surface; and contacting the probe needle with the protective electrode, applying an electrical signal between the mounting surface and the probe needle via the inspection semiconductor structure, and inspecting the state of the mounting surface from the result of energization of the mounting surface and the probe needle.

[0199] [A48] A method for manufacturing a semiconductor device using a semiconductor evaluation apparatus, comprising: a prober device including a chuck stage having a conductive mounting surface and a conductive probe needle; and a tester device electrically connected to the mounting surface and the probe needle, which applies an electrical signal between the mounting surface and the probe needle, the method comprising: placing an inspection semiconductor structure according to any one of A1 to A39 on the mounting surface in a position in which the second main surface is electrically connected to the mounting surface; and contacting the probe needle with the protective electrode, applying an electrical signal between the mounting surface and the probe needle via the inspection semiconductor structure, and inspecting the state of the mounting surface from the energization result of the mounting surface and the probe needle.

[0200] Although embodiments have been described in detail, these are merely specific examples used to clarify the technical content, and the present invention should not be interpreted as being limited to these specific examples. The scope of the present invention is limited by the appended claims. [Explanation of symbols]

[0201] 1. Semiconductor evaluation equipment 2A Semiconductor structure for testing 2B Semiconductor structure for manufacturing 2C semiconductor structure for testing 3. Probe device 4 Tester device 8 Chuck Stage 8a Mounting surface 13 Probe needle 20 Semiconductor wafers 21 First Main Surface 22 Second Main Surface 30 Examination Areas 31 Functional Devices 40 First main surface electrode 40a Gate main surface electrode 40b Source main surface electrode 50 insulating film 51 Pad opening 51a Gate pad opening 51b Source pad opening 60 Protective electrodes 60a Gate protection electrode 60b Source protection electrode 61 Ni film 62 Pd film 63 Au film 65 Second main surface electrode X 1st direction Y Second direction

Claims

1. A semiconductor plate having a first main surface on one side and a second main surface on the other side, An inspection area provided on the first main surface, A main surface electrode having a first hardness and covering the first main surface in the inspection area, A semiconductor inspection structure for inspecting the mounting surface of a chuck stage for a semiconductor wafer, comprising: a protective electrode having a second hardness exceeding the first hardness, covering the entire exposed portion of the main surface electrode in the inspection area, and forming a current path between itself and the second main surface via the semiconductor plate.

2. Multiple inspection areas are provided on the first main surface, Multiple main surface electrodes each cover the first main surface in multiple inspection areas. The semiconductor structure for inspection according to claim 1, wherein a plurality of protective electrodes cover a plurality of main surface electrodes in a plurality of inspection areas, and each forms a current path between them and the second main surface.

3. The semiconductor structure for inspection according to claim 1 or 2, wherein a plurality of the inspection regions are arranged on the first main surface along a first direction and a second direction intersecting the first direction.

4. The semiconductor structure for inspection according to claim 2 or 3, wherein 100 or more of the inspection areas are provided on the first main surface.

5. The semiconductor plate comprises a wide-bandgap semiconductor, as described in any one of claims 1 to 4, for testing purposes.

6. The semiconductor plate comprises SiC, and the semiconductor structure for testing according to any one of claims 1 to 5.

7. The inspection semiconductor structure according to any one of claims 1 to 6, wherein the protective electrode consists of a surface that the probe needle contacts and has a thickness exceeding the depth of the contact mark left by the probe needle.

8. The main surface electrode is made of a metal film other than a plating film. The inspection semiconductor structure according to any one of claims 1 to 7, wherein the protective electrode is made of a plated film.

9. The main surface electrode includes an Al-based metal film. The protective electrode comprises a Ni film, and the inspection semiconductor structure is as described in any one of claims 1 to 8.

10. The inspection semiconductor structure according to claim 9, wherein the protective electrode has a laminated structure including an Au film laminated on the Ni film.

11. The inspection semiconductor structure according to claim 10, wherein the protective electrode includes a Pd film interposed between the Ni film and the Au film.

12. The inspection semiconductor structure according to any one of claims 1 to 11, wherein the protective electrode has an area less than the area of ​​the main surface electrode in a plan view.

13. The insulating film further includes an insulating film that covers the peripheral edge of the main surface electrode and has an opening that exposes the inner portion of the main surface electrode, The inspection semiconductor structure according to any one of claims 1 to 12, wherein the protective electrode covers the entire area of ​​the main surface electrode within the opening.

14. The inspection semiconductor structure according to claim 13, wherein the protective electrode is formed at a distance from the opening end of the opening toward the main surface electrode, such that a portion of the wall surface of the opening is exposed.

15. The inspection area further includes a functional device formed on the first main surface, The main surface electrode is electrically connected to the functional device. The semiconductor structure for testing according to any one of claims 1 to 14, wherein the protective electrode is electrically connected to the functional device via the main surface electrode and forms the current path through the functional device with respect to the second main surface.

16. The test semiconductor structure according to claim 15, wherein the functional device includes at least one of a diode and a transistor.

17. The semiconductor structure for testing according to any one of claims 1 to 16, further comprising a second main surface electrode that covers the second main surface and forms a current path through the semiconductor plate between itself and the protective electrode.

18. A chuck stage having a conductive mounting surface, A conductive probe needle to which an electrical signal is applied, A chuck stage inspection apparatus comprising a semiconductor inspection structure according to any one of claims 1 to 17, wherein the second main surface is electrically connected to the aforementioned mounting surface, and the protective electrode is positioned on the aforementioned mounting surface in a manner in contact with the probe needle.

19. The chuck stage inspection apparatus according to claim 18, wherein the probe needle is configured to apply an electric current between itself and the aforementioned surface.

20. A method for manufacturing a semiconductor device using a semiconductor evaluation apparatus, comprising a chuck stage having a conductive mounting surface and a conductive probe needle to which an electrical signal is applied between the mounting surface, A step of placing the inspection semiconductor structure according to any one of claims 1 to 17 on the aforementioned surface in a position in which the second main surface is electrically connected to the aforementioned surface, A method for manufacturing a semiconductor device, comprising the steps of: bringing the probe needle into contact with the protective electrode; applying an electrical signal between the aforementioned surface and the probe needle via the inspection semiconductor structure; and inspecting the state of the aforementioned surface from the result of energizing the aforementioned surface and the probe needle.

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