circuit

Abstract

To provide a VCSEL device with a lithographic aperture and integrated electrostatic discharge event protection.SOLUTION: A VCSEL device includes multiple layers forming a protection diode outside of a lithographic aperture area, the protection diode having a surface area that is greater than a surface area of the lithographic aperture.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001]

[0001] The disclosure generally relates to a vertical cavity surface emitting laser (VCSEL) equipped with electrostatic discharge (ESD) protection. [Background technology]

[0002]

[0002] Aspects of this disclosure relate to VCSELs with integrated ESD protection. Conventional solutions for VCSELs with ESD protection may have various problems. In this regard, conventional systems and methods for VCSELs with ESD protection may be costly, cumbersome, and / or inefficient.

[0003]

[0003] The limitations and drawbacks of conventional systems and methods will become apparent to those skilled in the art through a comparison of such approaches with some aspects of the methods and systems described in the remainder of this disclosure with reference to the drawings. [Overview of the Initiative]

[0004]

[0004] VCSELs with ESD protection are illustrated and / or described in relation to at least one of the figures and are more fully described in the claims.

[0005] These and other advantages, aspects and novel features of the present disclosure, as well as details of the illustrated embodiments, will be better understood from the following description and drawings. [Brief explanation of the drawing]

[0005]

[0006] The various features and advantages of this disclosure will be more readily apparent upon referring to the following detailed description in conjunction with the accompanying drawings, where similar reference numerals indicate similar structural elements. [Figure 1]

[0007] This figure shows an exemplary ESD protection circuit for an ESD-sensitive light-emitting diode. [Figure 2]

[0008] This figure shows a VCSEL equipped with an oxide perforation. [Figure 3]

[0009] This figure shows a VCSEL (Variable Cross Cell) equipped with a lithographic tunnel junction aperture and an integrated ESD protection diode function. [Figure 4]

[0010] Figure 3 is an equivalent circuit diagram illustrating the function of the VCSEL. [Figure 5]

[0011] This figure shows a VCSEL with a lithographic aperture defined by an opening in an n-blocking layer that has an integrated ESD protection diode function. [Figure 6]

[0012] Figure 5 is an equivalent circuit diagram illustrating the function of the VCSEL. [Modes for carrying out the invention]

[0006]

[0013] The following discussion provides various embodiments of semiconductor devices and methods for manufacturing semiconductor devices. Such embodiments are not limiting, and the appended claims should not be limited to the specific embodiments disclosed. In the following discussion, the terms “embodiments” and “for example” are not limiting.

[0007]

[0014] The figures illustrate general construction methods, and well-known features and technical descriptions and details may be omitted to avoid unnecessarily complicating this disclosure. Furthermore, elements in the drawings are not necessarily depicted to scale. For example, the dimensions of some elements in the drawings may be exaggerated relative to others to aid in understanding the embodiments considered in this disclosure. The same reference numeral in different figures refers to the same element.

[0008]

[0015] The term "or" means any one or more items in a list joined by "or". For example, "x or y" means any element in the set of three elements {(x), (y), (x,y)}. Another example is "x,y, or z" meaning any element in the set of seven elements {(x), (y), (z), (x,y), (x,z), (y,z), (x,y,z)}.

[0009]

[0016] The terms “comprises,” “comprising,” “includes,” and / or “including” are “open-ended” terms that specify the presence of the described feature but do not exclude the presence or addition of one or more other features.

[0010]

[0017] Terms such as “first,” “second,” etc., are used herein to describe various elements, but these elements should not be limited by these terms. These terms are used solely to distinguish one element from another. Thus, for example, the first element considered herein may also be called the second element without departing from the teachings herein.

[0011]

[0018] Unless otherwise specified, the term “coupled” can be used to describe two elements that are in direct contact with each other, or two elements that are indirectly connected by one or more other elements. For example, if element A is coupled to element B, element A may be in direct contact with element B, or it may be indirectly connected to element B by an intervening element C. Similarly, the terms “over” or “on” can be used to describe two elements that are in direct contact with each other, or two elements that are indirectly connected by one or more other elements.

[0012]

[0019] Referring now to FIG. 1, an exemplary ESD protection circuit is shown that includes a light emitting diode (LD) 10, a protection diode 20, a voltage source 30, an ESD current flow 50 with an associated ESD voltage 55, and a normal current flow 40 with an associated normal operating voltage 45.

[0013]

[0020] The light emitting diode 10 may be operable to emit light in response to an applied voltage / current. The light emitting diode 10 may be a vertical cavity surface emitting laser or VCSEL. A VCSEL is a type of semiconductor laser diode from which a laser beam is emitted vertically from the upper end face. VCSELs are used in various laser products.

[0014]

[0021] The ESD protection diode 20 may be coupled to the LD 10 as shown in FIG. 1. The voltage source 30 may represent a device operable to supply a fixed or variable voltage to the electrical circuit of FIG. 1. The depicted voltage source 30 may represent a source for the normal operating voltage 45 and normal current flow 40, as well as the ESD current flow 50 and ESD voltage 55.

[0015]

[0022] Due to its small aperture, a VCSEL may be sensitive to ESD events. That is, the LD 10 may be damaged if excessive voltage and / or current is applied thereto, for example, by the depicted voltage source 30. For an ESD-sensitive device such as the LD 10, the protection diode 20 may be in parallel with, but reverse-biased to, the ESD-sensitive laser diode 10 as shown. The protection diode 20 may be selected or designed to be highly resistive during normal operation so that substantially all current may flow through the ESD-sensitive laser diode 10. This is shown in FIG. 1 by the normal current flow 40 with an associated exemplary normal voltage 45. During normal operation, the positive The normal voltage 45 is lower than the (reverse) breakdown voltage VBR associated with the protection diode 20. When an electrostatic discharge occurs, the ESD voltage 55 may exceed the breakdown voltage VBR as illustrated by the ESD current flow 50, and the ESD current flow 50 may flow in the reverse direction across the protection diode 20. Correspondingly, the breakdown voltage VBR of the protection diode 20 is desirably higher than the normal operating voltage 45 and lower than a voltage that could damage the LD10. In this way, an ESD sensitive device, such as the LD10, can be protected from electrostatic discharge by the protection diode 20 coupled thereto in the reverse direction and in parallel, as illustrated in FIG. 1. According to normal diode operation, the forward breakdown voltage of the protection diode 20 may be substantially lower than the (reverse) breakdown voltage VBR. If an electrostatic discharge creates a voltage applied in the forward direction of the protection diode 20, the protection diode 20 shorts at a forward voltage substantially lower than the reverse breakdown voltage, preventing damage to the ESD sensitive device LD10, so the LD10 can be protected.

[0016]

[0023] FIG. 2 shows an exemplary cross-section of a VCSEL device 100 with an oxide aperture. An ohmic n contact layer 180, a substrate n-GaAs layer 170, an n-DBR layer 160, an active region 150, an oxide aperture layer 140, a p-DBR layer 130, a mesa layer 110, and an ohmic p contact layer 120 are shown. Further, an electron flow 190 and a hole flow 200 are shown. The cross-section of the VCSEL device 100 may be a cross-section of a cylindrical structure having, for example, a circular, elliptical, rectangular, or any other shaped cross-section.

[0017]

[0024] The VCSEL 100 can be fabricated, for example, using a lithographic semiconductor manufacturing process. The ohmic n contact 180 may be operable as an electrical coupling contact for a negative voltage terminal. Similarly, the ohmic p contact 120 may be operable as an electrical coupling contact for a positive voltage terminal.

[0018]

[0025] The p-DBR130 may be a p-type distributed Bragg reflector (DBR). The n-DBR160 may be an n-type distributed Bragg reflector. The p-DBR130 and n-DBR160 may be capable of operating as resonant mirrors for a laser. n-type may mean doping with impurities to supply additional electrons, and p-type may mean doping with impurities to supply additional holes.

[0019]

[0026] The oxide aperture 140 may be operable perpendicular to the active region 150 to allow the emission of light generated by the VCSEL 100. The oxide layer can confine the current flow (200 / 190) to the aperture region 140, as shown in Figure 2. The active region 150 can enable stimulated emission of light with an appropriate energy level so that energy injection can supply an excess of excited atoms between the resonator system which may be formed between the p-DBR 130 mirror and the n-DBR 160 mirror. The active region 150 may include a quantum well, quantum dash, or quantum dot.

[0020]

[0027] The substrate n-GaAs 170 may be an n-type gallium arsenide (GaAs) substrate layer. According to various embodiments of this patent, the substrate 170 may be any suitable material, including, but not limited to, indium phosphide (InP), gallium nitride (GaN), silicon (Si), and silicon carbide (SiC).

[0021]

[0028] Mesa 110 is an area on the semiconductor wafer where the semiconductor has not been etched away, resulting in the formation of a mesa 110 that rises above the surrounding area.

[0022]

[0029] In the context of an electrostatic discharge (ESD) event, a discharge current flow can occur through the area of ​​the oxide perforation 140, as illustrated by the hole flow 200 and electron flow 190 in Figure 2. Since the area of ​​aperture 140 is limited (compared to the area of ​​mesa 110), the discharge current density in the oxide perforation 140 area becomes high, potentially damaging the active region layer 150 of the VCSEL 100. Therefore, it may be advantageous to directly integrate a structure similar to the ESD protection diode 20 into the VCSEL, as illustrated in Figure 3.

[0023]

[0030] Figure 3 shows an exemplary tunnel junction configuration VCSEL with an integrated protection diode structure. Referring to Figure 3, a VCSEL 300 in a tunnel junction configuration is shown. This VCSEL may include a mesa 110, an ohmic p-contact 120, an ohmic n-contact 180, an n-DBR 160a, an active region 150, an n-DBR 160, and a substrate n-GaAs 170 layer. The same reference numerals refer to layers similar to those in Figure 2. The n-DBR 160a may be similar to the n-DBR 160. An electron flow 190 is shown. An electron discharge flow 350 is shown. Exemplary protection diode symbols 360 and tunnel diode symbol 380 are shown. The protection diode symbol 360 may represent an np junction diode formed by a p-type cavity 310 / pn blocking layer 320 and an n-DBR 160a. The symbol 380 for tunnel diode indicates a tunnel diode formed by a p-type cavity 310 / pn blocking layer 320 / tunnel junction layer 330 and an n-DBR 160a layer.

[0024]

[0031] Furthermore, a p-type cavity 310, a pn-blocking layer 320, and a tunnel junction layer 330 are shown. The pn-blocking layer 320 may be operable to block current flow during normal operation (i.e., lower voltages, for example, less than 5V). An n-type cavity 390 is also shown.

[0025]

[0032] The lithographic aperture VCSEL300 may rely on a conductive aperture for current and optical mode confinement (formed by the tunnel junction layer 330), while the surrounding region is fabricated to be non-conductive. This can be achieved by first growing the lower end n-DBR mirror 160, and then the n cavity 390, the active region 150 (containing quantum wells, quantum dashes or quantum dots), and the partial p cavity 310. The tunnel junction layer 330 is highly doped (e.g., >10) 19 cm -3 )p++ layer and highly doped (e.g., >10 19 cm -3 ) may include n++ layers. The aperture is defined in the tunnel junction layer 330. In order to form an aperture in the tunnel junction layer 330, the n++ layers (from which the tunnel junction layer 330 is formed) may be removed / etched outside the lithographic aperture, and the wafer may be n-type doped (e.g., 10 17 cm -3 Just 10 18 cm -3 During the generation, the remaining cavity is overgrown, with the upper end being an n-DBR mirror 160a. In this case, current flow and optical mode confinement may be provided by the tunnel junction. Outside the aperture formed by the tunnel junction layer 330, the current may be blocked for a pn junction formed by the pn blocking layer 320 / p-type cavity 310 and the n-DBR 160a which is in the opposite direction.

[0026]

[0033] In Figure 3, during normal operation, the voltage applied to the VCSEL 300 may be far below the breakdown voltage of the blocking pn junction layer, and therefore the current flow during operation is limited to the tunnel junction aperture 330. The blocking pn junction may be formed between the n-DBR 160a and the pn blocking layer 320 / p-type cavity 310. The current flow is indicated by the electron flow 190 with a dashed arrow. In the event of electrostatic discharge, the voltage exceeds the breakdown voltage of the pn blocking layer (n-DBR 160a and pn blocking layer 320 / p-type cavity 310), and Therefore, the electrostatic discharge current 350 (illustrated by a solid arrow) can flow almost entirely around the tunnel junction 330 because the available conductive area is much larger during diode breakdown. In this case, the current density in the active region beneath the tunnel junction layer 330 may decrease accordingly. According to various embodiments of this patent, the layers formed within the VCSEL 300 by the mesa 110 and the lower layers allow for the formation of protection diodes 360 and 370 (not symbolically illustrated, see also Figure 4). The protection diodes may be formed between the n-DBR 160a and the pn blocking layer 320 / p-type cavity 310.

[0027]

[0034] To make the ESD protection efficient, the current blocking p-n junction area may be as large as practically possible since it is limited by the mesa 110 surface area. In this case, the ESD current may be distributed across the entire corresponding mesa 110 surface area, resulting in a reduced current density and thus a lower likelihood of damage. The breakdown voltage of the p-n blocking layer 320 is advantageously above 5V. The breakdown voltage can be adjusted by appropriate selection of the doping and thickness of the p-type layer (p-n blocking layer 320 / p-type cavity 310) and the n-type layer (n-DBR160a). In some examples, an additional layer may be present on the p-n blocking layer 320. Also, in some examples, the n-DBR160a may include additional layers with different dopings to form a non-uniformly doped n-DBR160a. Thus, the lower half of the cavity under the lower end n-DBR160 and the active region 150 may be n-doped. In the case of the n-p-n blocking configuration shown in FIG. 3 (from n-DBR160a, p-n blocking layer 320 / p-type cavity 310 / active region 150, and n-DBR160), the second half of the cavity above the active region 150 may be p-doped and the upper end n-DBR160a may be n-doped. The total thickness of the p-doped layer is preferably >50nm and the doping may be, for example, between 10 17 cm -3 and <10 19 cm -3 is desirable. The doping in the n-DBR160a may be <10 19 cm -3 to reduce the quantum tunneling of carriers between the p-doped and n-doped layers, which can result in inefficient current blocking. On the other hand, the breakdown voltage of the n-p-n ESD protection diode (formed by n-DBR160a, p-n blocking layer 320 / p-type cavity 310 / active region 150 and n-DBR160) may be selected to be <50V to avoid potential damage to the lithographic aperture (in the tunnel junction layer 330) in the case of an ESD event and before the ESD protection diode 360 opens in the reverse mode.

[0028]

[0035] Furthermore, the use of the n-DBR160a mirror at the top of the VCSEL300 results in improved electrical conductivity compared to the p-DBR130 as illustrated in Figure 2 for the VCSEL100 with oxide percha. This improved electrical conductivity may reduce the heat generated by ESD events near the sensitive area of ​​the VCSEL300, thus providing further protection.

[0029]

[0036] Figure 4 shows an equivalent circuit diagram for the VCSEL structure in Figure 3, illustrating the diode arrangement formed by the layers in Figure 3. A voltage / current source 30, ESD voltage 55, normal operating voltage 45, ESD current 50, normal operating current 40, protection diodes 360 and 370, tunnel diode 380, and light-emitting diode 10 are shown. The same reference numerals are similar to the elements in the previous figure.

[0030]

[0037] The symbol 360 for protection diode represents a pn junction diode formed by a p-type cavity 310 / pn blocking layer 320 and an n-DBR 160a. The symbol 380 for tunnel diode represents a tunnel diode that may be formed by a p-type cavity 310 / pn blocking layer 320 / tunnel junction layer 330 and an n-DBR 160a layer. This shows an diode. The protection diode 370 can be represented by the pn junction formed by the p cavity 320 / active region 150 and the n-DBR 160 (not shown by symbols in Figure 3).

[0031]

[0038] Under normal operation, the operating voltage 45 can be below the breakdown voltage VBR of the protection diode 360 ​​(or the reverse diode 370, not shown). The normal operating current 40 can effectively flow only through the tunnel diode 380 and LD10. When an electrostatic discharge event occurs and the ESD voltage 55 exceeds the breakdown voltage VBR, the protection diode 360 ​​becomes conductive, and the ESD current 50 can mostly flow through the protection diodes 360 and 370. Therefore, in the event of an ESD event, the protection diodes 360 and 370 are effectively short-circuited, thus protecting the tunnel diode 380 and LD10 from excessive ESD voltage / current.

[0032]

[0039] Figure 5 shows a VCSEL diode based on a pnp current blocking configuration with an integrated ESD protection diode. Figure 5 shows a VCSEL 500 including a mesa 110, an ohmic p-contact 120, a p-DBR 130, an n-blocking layer 510, a p-type cavity 310, an active region 150, an n-DBR 160, an n-GaAs substrate 170, and an ohmic n-contact 180. Furthermore, electron flow 190 and hole flow 200 are shown. A symbolic protection diode 360 ​​is shown, such as that formed by the p-DBR 130 layer, the n-blocking layer 510, and the p-type cavity 310. An n-type cavity 390 is also shown. The same reference numerals refer to elements similar to those in the previous figure.

[0033]

[0040] As shown in Figure 5, ESD protection can also be introduced in the lithographic aperture using a current-n-blocking layer 510. In the VCSEL 500, the n-doped current-blocking layer 510 can be grown during the first epitaxial step. This layer 510 may become part of the illustrated ESD protection diode 360. During the wafer manufacturing process, the lithographic aperture can be defined by etching through the n-doped layer 510, as shown in Figure 5. After the lithographic aperture is defined, the wafer on the n-blocking layer 510 may have an overgrown upper-end p-doped p-DBR 130 mirror. Therefore, in the region of the lithographic aperture, the n-doped layer 510 may be etched to allow current to flow directly from the p-doped p-type cavity 310 to the p-doped p-DBR 130 mirror. The lithographic aperture can also provide optical mode confinement for the VCSEL 500.

[0034]

[0041] In the embodiment of the present patent shown in Figure 5, during normal operation, the voltage applied to the VCSEL 500 is below the breakdown voltage of the n-blocking layer 510, so the normal current flow is restricted to the aperture opened within the pnp layer (indicated by the yellow dashed arrow). When an ESD event occurs, higher voltages may exceed the breakdown voltage of the n-blocking layer 510, and therefore ESD current (red solid arrow) may flow outside the aperture. Since the area of ​​the n-blocking layer 510 around the aperture is usually significantly larger than the aperture area itself, the ESD current is effectively defined by the mesa cross-sectional area and thus distributed over a much larger surface area. This feature is illustrated in Figure 6.

[0035]

[0042] Figure 6 shows the equivalent circuit diagram of the VCSEL500. The voltage / current source 30, ESD voltage 55, normal operating voltage 45, ESD current flow 50, normal operating current 40, protection diodes 360 and 370, and light-emitting diode 10 are shown. The same reference numbers refer to similar elements shown in other figures.

[0036]

[0043] During normal operation, i.e., when the operating voltage 45 is below the breakdown voltage VBR, the protection diodes 360 and 370 block the current flow, allowing the normal current 40 to flow through LD10. In this case, the current flows through the aperture region, as illustrated by the dashed arrows in Figure 5. If an ESD event occurs and the ESD voltage 55 may exceed the breakdown voltage VBR, the protection diodes 360 and 370 effectively short-circuit, allowing the ESD current 50 to flow through the protection diodes 360 and 370. This protects LD10 from current and voltage spikes that could damage it.

[0037]

[0044] Therefore, the mesa 110 cross-sectional area may be selected to be as large as practically possible to minimize the ESD event current density through the aperture and thus protect the VCSEL 500. In other words, the n-blocking layer 510 surface area may be increased.

[0038]

[0045] According to various embodiments of this patent, the breakdown voltage of the n-blocking layer 510 can be preferably greater than 5V by selecting, for example, the desired doping and thickness of the p-type and n-type layers in Figure 5.

[0039]

[0046] In the pnp blocking diode configuration shown in Figure 5, formed by a p-type cavity 310 above the active region 150, an n-blocking layer 510, and a p-DBR 130 mirror, the thickness of the n-blocking layer 510 may be >50 nm, and the doping is 10 17 cm -3 and 10 19 cm -3 It may be within the range of <10. Doping in the p-DBR layer 130 is <10 19 cm -3This may also be the case. Such doping levels are advantageous in preventing quantum tunneling of carriers between the n-doped and p-doped layers, which can result in inefficient current blocking. The breakdown voltage VBR of the pn-pESD protection diodes 360, 370 may be designed to be <50V to prevent damage to the lithographic aperture in the event of an ESD event.

[0040]

[0047] The structures disclosed in Figures 3 and 5 can be manufactured, for example, using a two-step epitaxy process having an intermediate lithographic step.

[0048] This disclosure includes references to specific embodiments, but it will be understood by those skilled in the art that various modifications are possible and that equivalents can be substituted without departing from the scope of the disclosure. Modifications to the disclosed embodiments may also be made without departing from the scope of the disclosure. Therefore, this disclosure is not limited to the disclosed embodiments, and is intended to include all embodiments included in the appended claims. [Explanation of Symbols]

[0041] 10 Laser Diodes 20 Protection diodes 30 Voltage / Current Sources 40 normal operating current 45 Normal operating voltage 50 ESD current 100 VCSEL 110 Mesa 120 Ohmic P-contact 130 p-DBR 140 Oxide percha 150 active area 160 n-DBR 160a n-DBR 170 substrate n-GaAs 180 Ohmic N-contact 190 Electronic Flow 200 Hole Flow 300 VCSEL 310 p-type cavity 320 pn blocking layer 330 Tunnel junction layer 350 Electron Discharge Flow 360 protection diodes 370 Protection Diode 380 Tunnel Diodes 390 n-type cavity 510 n blocking layer VBR Breakdown Voltage DBR (Distributed Bragg Reflector)

Claims

1. A light-emitting diode (LED) and A protection diode is coupled in parallel with the LED in operation, wherein the protection diode and the LED are configured in opposite directions. A voltage source configured to supply an operating voltage and an electrostatic discharge (ESD) voltage, wherein during an ESD event, the ESD voltage exceeds the breakdown voltage of the protection diode, and the ESD current flows in the reverse direction through the protection diode. A circuit comprising an LED which is a vertical-cavity surface-emitting laser (VCSEL), the VCSEL which is configured with a tunnel junction comprising a highly doped p++ layer and a highly doped n++ layer.

2. The circuit according to claim 1, wherein the aperture of the tunnel junction confines the optical modes of the VCSEL.

3. Light-emitting diode (LED) and A protection diode is coupled in parallel with the LED in operation, wherein the protection diode and the LED are configured in opposite directions. A voltage source configured to supply an operating voltage and an electrostatic discharge (ESD) voltage, wherein during an ESD event, the ESD voltage exceeds the breakdown voltage of the protection diode, and the ESD current flows in the reverse direction through the protection diode. A circuit comprising an LED which is a vertical cavity surface-emitting laser (VCSEL), and a protection diode which is integrated into the structure of the VCSEL as part of a tunnel junction configuration.

4. Light-emitting diode (LED) and A protection diode is coupled in parallel with the LED in operation, wherein the protection diode and the LED are configured in opposite directions. A voltage source configured to supply an operating voltage and an electrostatic discharge (ESD) voltage, wherein during an ESD event, the ESD voltage exceeds the breakdown voltage of the protection diode, and the ESD current flows in the reverse direction through the protection diode. A circuit comprising a protection diode wherein the forward breakdown voltage of the protection diode is lower than the reverse breakdown voltage of the protection diode.

5. Light-emitting diode (LED) and A protection diode is coupled in parallel with the LED in operation, wherein the protection diode and the LED are configured in opposite directions. A voltage source configured to supply an operating voltage and an electrostatic discharge (ESD) voltage, wherein during an ESD event, the ESD voltage exceeds the breakdown voltage of the protection diode, and the ESD current flows in the reverse direction through the protection diode. A circuit comprising a protection diode which is a p-n junction diode formed between a p-type cavity and an n-type distributed Bragg reflector (DBR) layer.

6. Light-emitting diode (LED) and A protection diode is coupled in parallel with the LED in operation, wherein the protection diode and the LED are configured in opposite directions. A voltage source configured to supply an operating voltage and an electrostatic discharge (ESD) voltage, wherein during an ESD event, the ESD voltage exceeds the breakdown voltage of the protection diode, and the ESD current flows in the reverse direction through the protection diode. A circuit comprising a protection diode formed between a p-n blocking layer and an n-DBR layer.

7. The circuit according to claim 6, wherein the breakdown voltage of the protection diode is adjustable by selecting the doping and thickness of one or both of the p-type and n-type layers.

8. A circuit according to any one of claims 1 to 3, wherein the VCSEL includes an n-blocking layer configured to block current flow during normal operation and conduct the ESD current during the ESD event.

9. A circuit according to any one of claims 1 to 3, wherein the VCSEL includes a substrate, an active region, a distributed Bragg reflector (DBR), and an oxide percha for confining the current flow.

10. The circuit according to claim 9, wherein the active region includes one or more of a quantum well, a quantum dot, and a quantum dash.

11. A circuit according to any one of claims 1 to 7, wherein the breakdown voltage of the protection diode is higher than the operating voltage and lower than the voltage that damages the LED.

12. A circuit according to any one of claims 1 to 7, wherein the flow of the ESD current during the ESD event is distributed to the surface region of the mesa structure.

13. The circuit according to claim 9, wherein the flow of the ESD current bypasses the active region of the LED during the ESD event.

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