Imaging device

Abstract

To provide a solid-state imaging apparatus with good productivity and improved dynamic range.SOLUTION: An imaging apparatus includes a photoelectric conversion element having an i-type semiconductor layer, a functional element, and a wiring, and an area in which the i-type semiconductor layer overlaps the functional element and the wiring in plan view is preferably 35% or less, more preferably 15% or less, and further preferably 10% or less of the area of the i-type semiconductor layer in plan view. A plurality of photoelectric conversion elements are provided in the same semiconductor layer, and therefore, a step of separating photoelectric conversion elements can be omitted. Each of the i-type semiconductor layers included in the plurality of photoelectric conversion elements is separated by a p-type semiconductor layer or an n-type semiconductor layer.SELECTED DRAWING: Figure 3

Description

Technical Field

[0001] One aspect of the present invention relates to an imaging device. Specifically, it relates to an imaging device provided with a plurality of pixels having photo sensors. Furthermore, it relates to an electronic device having the imaging device. Note that one aspect of the present invention is not limited to the above technical field. For example, one aspect of the present invention relates to an object, a method, or a manufacturing method. Or, the present invention relates to a process, a machine, a manufacture, or a composition of matter. Or, one aspect of the present invention relates to a storage device, a processor, their driving methods, or their manufacturing methods.

[0002] In this specification and the like, the semiconductor device refers to all things that can function by utilizing semiconductor characteristics. Therefore, semiconductor elements such as transistors and diodes and semiconductor circuits are semiconductor devices. Also, display devices, light-emitting devices, lighting devices, electro-optical devices, imaging devices, and electronic devices may include semiconductor elements and semiconductor circuits. Therefore, display devices, light-emitting devices, lighting devices, electro-optical devices, imaging devices, and electronic devices may also have semiconductor devices.

[0003]

[0004]

Background Art

[0004] Imaging devices are standardly incorporated into mobile phones and are becoming widespread (for example, Patent Document 1). In particular, CMOS image sensors have characteristics such as low cost, high resolution, and low power consumption compared to CCD image sensors, and most imaging devices are composed of CMOS image sensors.

Prior Art Documents

[0005]

Patent Documents

[0005] [Patent Document 1] U.S. Patent No. 7,046,282 [Summary of the Invention] [Problems to be Solved by the Invention]

[0006] In an imaging device using a CMOS image sensor, in order to enable imaging in various environments an improvement in dynamic range is required.

[0007] Also, in evaluating the performance of an imaging device, low power consumption is also an important performance [[ID=2X]] requirement. Especially in the case of portable electronic devices such as mobile phones, if the power consumption of the imaging device is high the continuous usage time will be shortened.

[0008] One aspect of the present invention is to provide an imaging device with an improved dynamic range, etc. as one of the problems. Or, one aspect of the present invention is to provide an imaging device with good quality of the captured image, etc. as one of the problems. Or, one aspect of the present invention is to provide an imaging device with low power consumption as one of the problems. Or, one aspect of the present invention is to provide an imaging device with good productivity as one of the problems. Or, one aspect of the present invention is to provide a novel imaging device or a novel semiconductor device, etc. as one of the problems. Or, one aspect of the present invention is to provide a novel imaging device or a novel semiconductor device, etc. as one of the problems.

[0009] Note that the description of these problems does not prevent the existence of other problems. Note that one aspect of the present invention is not required to solve all of these problems. Note that other problems will become apparent from the descriptions in the specification, drawings, claims, etc., and it is possible to extract these other problems from the descriptions in the specification, drawings, claims, etc. will become apparent from the descriptions in the specification, drawings, claims, etc., and it is possible to extract these other problems from the descriptions in the specification, drawings, claims, etc. [Means for solving the problem]

[0010] One aspect of the present invention comprises a photoelectric conversion element, first to fourth transistors, a capacitive element, and first The photoelectric conversion element has a to seventh wiring, and the photoelectric conversion element has an n-type semiconductor and a p-type semiconductor, Wiring 1 is electrically connected to either an n-type semiconductor or a p-type semiconductor, and the n-type semiconductor or The other end of the p-type semiconductor is electrically connected to either the source or the drain of the first transistor. The gate of the first transistor is electrically connected to the second wiring, and the first transistor The source or drain of the transistor is electrically connected to the first node, and the other is connected to the second transistor. Either the source or drain of the transistor is electrically connected to the third wiring, and the second transistor The source or drain of the other is electrically connected to the first node and the second transistor The gate is electrically connected to the fourth wiring, and one electrode of the capacitive element is electrically connected to the first node. The other electrode of the capacitive element is electrically connected to the first wiring, and the third transient The gate of the transistor is electrically connected to the first node, and the source or gate of the third transistor is connected to the first node. One end of the rain is electrically connected to the fifth wire, and the source or drain of the third transistor. The other end of the input is electrically connected to either the source or the drain of the fourth transistor. The source or drain of the fourth transistor, the other of which is electrically connected to the sixth wiring, The gate of the fourth transistor is electrically connected to the seventh wiring in the imaging device.

[0011] The photoelectric conversion element has an i-type semiconductor, and in a planar view, it has the first to fourth transistors. The area where each of them and the type i semiconductor overlaps, the area where the capacitive element and the type i semiconductor overlap, and The total area where each of the first to seventh wirings and the i-type semiconductor overlaps is equal to the area where the i-type semiconductor overlaps. It is preferable that it covers 35% or less of the body's surface area.

[0012] The first to fourth transistors use an oxide semiconductor as the semiconductor in which the channel is formed. This is preferable.

[0013] Furthermore, the semiconductors used in the first to fourth transistors are i-type semiconductors, which are the type of semiconductors found in photoelectric conversion elements. It may have a different restricted zone width.

[0014] Alternatively, one aspect of the present invention relates to an imaging device having at least first and second photoelectric conversion elements. The first and second photoelectric conversion elements have an i-type semiconductor, and the first photoelectric conversion element has The i-type semiconductor and the i-type semiconductor in the second photoelectric conversion element are either an n-type or p-type semiconductor. This imaging device is characterized by being adjacent via a barrier. [Effects of the Invention]

[0015] According to one aspect of the present invention, it is possible to provide an imaging device with improved dynamic range. It is possible to provide an imaging device or the like that improves the quality of the captured images. Alternatively, an imaging device with a short imaging interval can be provided. Or, a device with low power consumption can be provided. We can provide imaging devices, etc. Or, we can provide imaging devices, etc. with good productivity. One of the objectives is to provide a novel imaging device or a novel semiconductor device, etc. It is possible.

[0016] Furthermore, the description of these effects does not preclude the existence of other effects. The embodiment does not necessarily have to have all of these effects. Furthermore, other effects are... This will become clear from the description in the specification, drawings, claims, etc., and the specification, drawings Furthermore, it is possible to extract other effects from the descriptions in the claims and other documents. [Brief explanation of the drawing]

[0017] [Figure 1] A diagram illustrating an example configuration of an imaging device according to one embodiment of the present invention. [Figure 2] A diagram illustrating an example of peripheral circuit configuration. [Figure 3] A diagram illustrating an example of pixel configuration. [Figure 4] Planar and pixel circuit diagrams of the pixel driving circuit. [Figure 5] A perspective view illustrating an example of pixel configuration. [Figure 6] A diagram showing an example of pixels arranged in a matrix. [Figure 7] A diagram illustrating an example of a circuit configuration for pixels arranged in a matrix. [Figure 8] A diagram showing an example of a matrix arrangement of photoelectric conversion elements. [Figure 9] A diagram illustrating an example of pixel configuration. [Figure 10] A diagram illustrating an example of pixel configuration. [Figure 11] A diagram illustrating an example of the configuration of an imaging device. [Figure 12] A diagram illustrating an example of a transistor. [Figure 13] A diagram illustrating the energy band structure. [Figure 14] A diagram illustrating an example of a transistor. [Figure 15] A diagram illustrating an example of a circuit configuration. [Figure 16] A diagram illustrating an example of a circuit configuration. [Figure 17] A diagram illustrating an example of a circuit configuration. [Figure 18] A diagram illustrating one form of transistor. [Figure 19] A diagram illustrating one form of transistor. [Figure 20]A diagram illustrating one form of transistor. [Figure 21] A diagram illustrating one form of transistor. [Figure 22] A diagram illustrating one form of transistor. [Figure 23] A diagram illustrating one form of a capacitive element. [Figure 24] A diagram illustrating an electronic device according to one aspect of the present invention. [Modes for carrying out the invention]

[0018] The embodiments of the present invention will be described in detail below with reference to the drawings. However, the present invention is... Not limited to the following description, the form and details can be modified in various ways, as any person skilled in the art would know. This is easily understood. Furthermore, the present invention shall be interpreted as being limited to the contents of the embodiments described below. It is not the case that the same part or the same Parts with similar functions are given the same code, and explanations of their repetitions may be omitted. .

[0019] Furthermore, in this specification, the terms "electrode" and "wiring" do not limit the functionality of these components. It is not fixed. For example, "electrode" can be used as part of "wiring". The reverse is also true. Furthermore, the terms "electrode" and "wiring" can refer to multiple "electrodes" and "wiring". This also includes cases where the "lines" are formed as a single unit.

[0020] Furthermore, if it is explicitly stated in this specification, etc., that X and Y are connected. This refers to the case where X and Y are electrically connected, and the case where X and Y are functionally connected. The cases in which X and Y are directly connected are disclosed in this specification, etc. Therefore, the connection relationships are not limited to predetermined relationships, such as those shown in the diagram or text. Connections other than those shown in the diagram or text are also included as those described in the diagram or text. ru.

[0021] Here, X and Y are the object (e.g., device, element, circuit, wiring, electrode, terminal, conductive film, layer). (etc.)

[0022] An example of a case where X and Y are directly connected is an electrical connection between X and Y. Elements that perform this function (for example, switches, transistors, capacitive elements, inductors, resistive elements, etc.) If an ion, display element, light-emitting element, load, etc. is not connected between X and Y Yes, elements that enable electrical connection between X and Y (e.g., switches, transistors, capacitors) Without using (quantitative elements, inductors, resistors, diodes, display elements, light-emitting elements, loads, etc.) This is the case when X and Y are connected.

[0023] One example of a case where X and Y are electrically connected is when the electrical connection between X and Y is possible. Elements that perform this function (for example, switches, transistors, capacitive elements, inductors, resistive elements, etc.) One or more elements (such as ions, display elements, light-emitting elements, and loads) are connected between X and Y. This is possible. Furthermore, the switch has a function that allows it to be controlled to be on or off. In other words, A switch can be either conductive (on) or non-conductive (off), allowing current to flow. It has a function to control whether or not current flows. Alternatively, the switch selects the path through which the current flows. It has a function to switch between them. Note that if X and Y are electrically connected, X This includes cases where and Y are directly connected.

[0024] One example of a functional connection between X and Y is enabling a functional connection between X and Y. Circuits that perform this function (for example, logic circuits (inverters, NAND gates, NOR gates, etc.), signal transformers) Conversion circuits (DA conversion circuits, AD conversion circuits, gamma correction circuits, etc.), potential level conversion circuits (electric (Source circuits (boost circuits, buck circuits, etc.), level shifter circuits that change the potential level of a signal, etc.) Voltage source, current source, switching circuit, amplification circuit (which can increase signal amplitude or current amount, etc.) Circuits, operational amplifiers, differential amplifier circuits, source follower circuits, buffer circuits, etc., signal generation One or more circuits (such as memory circuits and control circuits) can be connected between X and Y. For example, even if another circuit is placed between X and Y, the signal output from A If the signal is transmitted to B, then X and Y are assumed to be functionally connected. When X and Y are functionally connected, the situation is different from when X and Y are directly connected. This includes cases where and are electrically connected.

[0025] Furthermore, if it is explicitly stated that X and Y are electrically connected, then X and Y When X and Y are electrically connected (that is, when there is another element or circuit between X and Y) (when connected by) and when X and Y are functionally connected (i.e., X and Y and (When they are functionally connected with another circuit in between) and when X and Y are directly connected In the case where (that is, when X and Y are connected without another element or circuit in between) This shall be disclosed in this specification, etc. That is, it shall be clearly stated that they are electrically connected. Where explicitly stated, it is simply stated that it is connected. Similar information is disclosed in this specification, etc.

[0026] For example, if the source (or first terminal, etc.) of the transistor is connected via Z1 (or via (In short), electrically connected to X, the drain (or second terminal, etc.) of the transistor is connected to Z. If Y is electrically connected via (or without) 2, or if the transistor source (or the first terminal, etc.) is directly connected to a part of Z1, and another part of Z1 is directly connected to X. They are directly connected, with the transistor's drain (or second terminal, etc.) directly connected to a portion of Z2. If it is connected to and another part of Z2 is directly connected to Y, it can be expressed as follows: It is possible to do so.

[0027] For example, "X and Y and the source (or first terminal, etc.) and drain (or second terminal) of the transistor." The terminals (such as the X terminal) are electrically connected to each other, and X is the source (or the X terminal) of the transistor. The electrical connections are in the following order: terminal 1, the drain of the transistor (or terminal 2, etc.), and Y. It can be expressed as "It is connected." Or, "The source (or the source) of the transistor." Terminal 1 (or terminal 2) is electrically connected to X, and the drain (or terminal 2) of the transistor is connected to X. (d) is electrically connected to Y, X is the source of the transistor (or the first terminal, etc.), and the transistor The drain (or second terminal, etc.) of the converter, Y, is electrically connected in this order. It can be expressed as "X is the source (or first terminal) of the transistor." Alternatively, "X is the source (or first terminal) of the transistor." Y is electrically connected to X via the drain (or second terminal, etc.) and X, the transistor The source of the transistor (or the first terminal, etc.), the drain of the transistor (or the second terminal, etc.) ), Y is provided in this connection order. By using a specific method of expression to define the order of connections in the circuit configuration, Distinguish between the source (or first terminal, etc.) and drain (or second terminal, etc.) of the zista. This allows us to determine the technical scope.

[0028] Alternatively, another way to express it is, for example, "the source (or first terminal, etc.) of the transistor." It is electrically connected to X via at least a first connection path, and the first connection path is the It does not have a second connection path, and the second connection path is via a transistor, The source (or first terminal, etc.) and the drain (or second terminal, etc.) of the transistor The path between them, the first connection path is the path through Z1, and the drain of the transistor (or a second terminal, etc.) is electrically connected to Y via at least a third connection path. The third connection path does not have the second connection path, and the third connection path is via Z2 It can be expressed as "the path." Or, "the source of the transistor (or the first The terminals, etc., are electrically connected to X via Z1 by at least a first connection path. Therefore, the first connection path does not have the second connection path, and the second connection path is a transit It has a connection path via a terminal, and the transistor's drain (or second terminal, etc.) is less Both are electrically connected to Y via Z2 through a third connection path, and the third connection path is It can be expressed as, "It does not have a second connection path." Or, "transistor The source (or first terminal, etc.) is connected to Z1 via at least the first electrical path. And, electrically connected to X, the first electrical path does not have a second electrical path, and The electrical path of 2 runs from the source (or first terminal, etc.) of the transistor to the terminal of the transistor. It is an electrical path to the drain (or second terminal, etc.) of the transistor, and the drain (or second terminal, etc.) Terminal 2 (and so on) is electrically connected to Y via Z2 by at least a third electrical path. The third connection path does not have a fourth connection path, and the fourth electrical path is From the drain of the transistor (or the second terminal, etc.) to the source of the transistor (or the first terminal) It can be expressed as "an electrical path to (a child, etc.)." Similar expressions can be used in these examples. By using the law to define the connection paths in the circuit configuration, the transistor's The technology distinguishes between the drain (or first terminal, etc.) and the drain (or second terminal, etc.). The target range can be determined.

[0029] Note that these methods of expression are just examples and are not limited to these methods. Here, X Y, Z1, and Z2 are the objects (e.g., devices, elements, circuits, wiring, electrodes, terminals, conductive films, etc.) Let's assume it is a layer, etc.

[0030] Note that, in circuit diagrams, independent components are shown as being electrically connected to each other. Even in such cases, one component may possess the functions of multiple components. For example, if part of the wiring also functions as an electrode, one conductive film will perform the function of the wiring, and It possesses the functions of both components of the electrode's function. Therefore, the electrode in this specification A conductive connection is a situation where a single conductive film combines the functions of multiple components. Combined forms are also included in that category.

[0031] Furthermore, in this specification, transistors can be formed using various substrates. The type of substrate is not limited to a specific one. One example of such a substrate is a semiconductor. Substrates (e.g., single crystal substrates or silicon substrates), SOI substrates, glass substrates, quartz substrates, We have plastic substrates, metal substrates, stainless steel substrates, and stainless steel foil. Substrates, tungsten substrates, substrates having tungsten foil, flexible substrates, laminated Examples include laminated films, paper containing fibrous materials, or base films. One of the glass substrates. Examples include barium borosilicate glass, aluminoborosilicate glass, or soda fountains. Examples include glass. One example of a flexible substrate is polyethylene terephthalate (PET). ), represented by polyethylene naphthalate (PEN) and polyethersulfone (PES) These include flexible plastics or synthetic resins such as acrylic. Examples of films include vinyl such as polyvinyl fluoride or polyvinyl chloride, and polypropylene. Examples include polyester and other materials. Examples of base films include polyester and polyamine. These include materials such as polyimides, inorganic vapor-deposited films, and paper. In particular, semiconductor substrates and single crystals. By manufacturing transistors using substrates, or SOI substrates, characteristics, size, etc. A transistor with minimal variation in size or shape, high current capacity, and small size. It is possible to manufacture such transistors. When a circuit is constructed using such transistors, the circuit's low This allows for reduced power consumption or increased circuit integration.

[0032] Furthermore, a transistor is formed using one substrate, and then the transistor is transferred to another substrate. Alternatively, the transistor may be placed on a different substrate. An example of a substrate on which the transistor is relocated. In addition to the substrates on which the aforementioned transistors can be formed, paper substrates, cellophane Substrates: stone substrates, wood substrates, fabric substrates (natural fibers (silk, cotton, linen), synthetic fibers (nylon, Polyurethane, polyester) or regenerated fibers (acetate, cupro, rayon, recycled) These include raw polyester, leather substrates, or rubber substrates. By using this method, it is possible to form transistors with good characteristics and transistors with low power consumption. This allows for the manufacture of durable devices, improved heat resistance, weight reduction, and thinner designs.

[0033] Furthermore, the position, size, and scope of each component shown in the drawings, etc., are intended to facilitate understanding of the invention. Therefore, it may not represent the actual location, size, or range. For this reason, disclosure is required. The invention is not necessarily limited to the location, size, scope, etc. disclosed in the drawings, etc. For example. In the actual manufacturing process, the resist mask may be unintentionally damaged by processes such as etching. While this may result in a reduction in value, it is sometimes omitted for the sake of easier understanding.

[0034] Furthermore, especially in the top view (also called the "plan view"), in order to make the drawing easier to understand, Descriptions of some components may be omitted. Also, descriptions of some hidden lines, etc., may be omitted. There is a match.

[0035] In this specification, the terms "above" and "below" refer to the relative positions of the constituent elements, specifically whether they are directly above or below. It is not limited to being below and in direct contact. For example, "electrode on insulating layer A" If the expression is "B", then it is not necessary for electrode B to be formed in direct contact with insulating layer A. Cases containing other components between marginal layer A and electrode B are not excluded.

[0036] Furthermore, the source and drain functions may differ when using transistors with different polarities, or when rotating In circuit operation, the direction of the current changes, and depending on the operating conditions, they can be swapped. Therefore, it is difficult to determine which is the source and which is the drain. In this specification, the terms source and drain may be used interchangeably. Let's assume that.

[0037] Furthermore, in this specification, "parallel" means that two straight lines are at an angle of -10° or more and 10° or less. This refers to the state in which something is positioned. Therefore, it also includes cases where the angle is between -5° and 5°. Also, "abbreviated "Parallel" refers to a state where two straight lines are positioned at an angle between -30° and 30°. Furthermore, "perpendicular" and "orthogonal" refer to two lines positioned at an angle of 80° to 100°. This refers to a state in which it is in a certain position. Therefore, it also includes cases where the angle is between 85° and 95°. "Straight" refers to a state in which two straight lines are positioned at an angle between 60° and 120°.

[0038] Furthermore, voltage is defined by a certain potential and a reference potential (for example, ground potential (GND potential) or source potential). It often refers to the potential difference between a voltage and a potential. Therefore, it is possible to rephrase voltage as potential. be.

[0039] Furthermore, semiconductor impurities refer to components other than the main components that make up the semiconductor, for example, concentration. Elements present in less than 0.1 atomic percent are considered impurities. The presence of impurities can, for example, lead to... The conductor's DOS (Density of State) increases, and carrier mobility In some cases, the quality may decrease, or the crystallinity may decrease. In the case of semiconductors, impurities that alter the properties of semiconductors include, for example, Group 1 elements and Group 2 elements. These include elements, Group 13 elements, Group 14 elements, Group 15 elements, and transition metals other than the main components. In particular, for example, hydrogen (also found in water), lithium, sodium, silicon, boron, ri These include hydrogen, carbon, and nitrogen. In the case of oxide semiconductors, for example, the inclusion of impurities such as hydrogen can cause problems. This can lead to the formation of oxygen vacancies. Furthermore, if the semiconductor is a silicon film, the semiconductor properties... Impurities that alter the composition include, for example, oxygen, Group 1 elements excluding hydrogen, Group 2 elements, and Group 1 elements. These include Group 3 elements and Group 15 elements.

[0040] Furthermore, in this specification, ordinal numbers such as "the first," "the second," etc., are used to avoid confusion of constituent elements. This is for visual inspection only and does not indicate any order or ranking, such as process order or layering order. Furthermore, even if an ordinal number is not attached to a term in this specification, the confusion of its constituent elements may occur. To avoid this, ordinal numbers may be added to the claims. Also, in this specification, etc. Even if a term is given an ordinal number in the patent claim, if a different ordinal number is used in the patent claim Ordinal numbers may be attached. Also, even if a term is used with an ordinal number in this specification, Ordinal numbers may be omitted in patent claims and other documents.

[0041] Note that "channel length" refers to, for example, the length of the semiconductor (or transistor) in the top view of a transistor. When the transistor is ON, the part of the semiconductor through which current flows and the gate electrode overlap. In the region where a region or channel is formed, the source (source region or source electrode) This refers to the distance between the drain (drain region or drain electrode). In a transistor, the channel length is not necessarily the same across all regions. That is, The channel length of a single transistor may not be fixed to a single value. Therefore, The detailed explanation states that the channel length is any one value, the maximum value, in the region where the channel is formed. , or the minimum value or the average value.

[0042] Furthermore, "channel width" refers to, for example, the half-length of a semiconductor (or transistor) when it is turned on. A region or channel is formed where the part of the conductor through which current flows overlaps with the gate electrode. This refers to the length of the portion where the source and drain face each other in the region. In a transistor, the channel width is not necessarily the same across all regions. In other words, the channel width of a single transistor may not be fixed to a single value. In this specification, the channel width is any one value in the region where the channel is formed. This represents the maximum value, minimum value, or average value.

[0043] Furthermore, depending on the transistor structure, the channel may actually be formed in the region where the channel is formed. The channel width (hereinafter referred to as the effective channel width) and the top view of the transistor are shown. The channel width (hereinafter referred to as the apparent channel width) may differ from the actual channel width. For example, In transistors with a three-dimensional structure, the effective channel width is shown in the top view of the transistor. The apparent channel width shown in [the relevant section] becomes larger, and its effect can no longer be ignored. In some cases, such as in transistors with a fine and three-dimensional structure, the upper surface of the semiconductor may be The ratio of channel regions formed on the side surface of the semiconductor to the ratio of channel regions formed In some cases, the apparent channel width shown in the top view may become larger. However, the effective channel width actually formed is larger.

[0044] By the way, in transistors with a three-dimensional structure, the effective channel width is measured Estimation can be difficult in some cases. For example, estimating the effective channel width from the design value. In order to do this, it is necessary to assume that the shape of the semiconductor is known. If this information is not precisely known, it is difficult to accurately measure the effective channel width.

[0045] Therefore, in this specification, in the top view of a transistor, the semiconductor and the gate electrode overlap. The apparent channel is the length of the portion in the region where the source and drain face each other. Channel width is defined as "Surrounded Channel Width (SCW)". It is sometimes referred to as "channel width." Also, in this specification, when simply referred to as channel width, This may refer to the enclosed channel width or the apparent channel width. Or, this detail In some documents, when simply referred to as "channel width," it may refer to the effective channel width. Oh, channel length, channel width, effective channel width, apparent channel width, enclosure channel Channel width and other parameters can be determined by acquiring cross-sectional TEM images and analyzing those images. The value can be determined.

[0046] Furthermore, the field-effect mobility of the transistor and the current value per channel width are calculated to determine this. In some cases, the calculation may be performed using the enclosed channel width. In that case, the effective channel The values ​​may differ from those obtained when calculating using the channel width.

[0047] Furthermore, in this specification, etc., the high power supply potential VDD (hereinafter simply referred to as "VDD" or "H potential") (Also known as) refers to a power supply potential that is higher than the low power supply potential VSS. VSS (hereinafter also simply referred to as "VSS" or "L potential") is the potential of the high power supply potential VDD. It also shows a low potential power supply potential. Furthermore, the ground potential can be used as VDD or VSS. Yes, it is possible. For example, if VDD is at ground potential, then VSS is at a lower potential than ground potential, and V If SS is at ground potential, then VDD is at a higher potential than ground potential.

[0048] (Embodiment 1) In this embodiment, an imaging device according to one aspect of the present invention will be described with reference to the drawings.

[0049] <Example of configuration of imaging device 100> Figure 1(A) is a plan view showing an example of the configuration of an imaging device 100 according to one embodiment of the present invention. 100 consists of a pixel section 110, a first circuit 260, a second circuit 270, a third circuit 280, It also has a fourth circuit 290. The pixel section 110 has p rows and q columns (where p and q are natural numbers greater than or equal to 2). The first circuit 26 has multiple pixels 111 (image sensor) arranged in a matrix. Circuits 0 to 4 290 are connected to multiple pixels 111 and drive multiple pixels 111. It has the function of supplying signals. In this specification, the first circuit 260 to the Circuit 4, such as 290, is sometimes referred to as a "peripheral circuit" or "drive circuit." For example, Circuit 260 in section 1 can be considered part of the peripheral circuitry.

[0050] For example, the first circuit 260 or the fourth circuit 290 receives the analog output from the pixel 111. It has the function of processing signals. For example, as shown in Figure 2, the first circuit 260 has the function of processing signals. A control circuit 261, a column drive circuit 262, an output circuit 263, etc. may also be provided.

[0051] Furthermore, the signal processing circuit 261 shown in Figure 2 has circuits 264 provided in each column. The 264 has functions for signal processing such as noise reduction and analog-to-digital conversion. This is possible. The circuit 264 shown in Figure 2 has the function of analog-to-digital conversion. Signal processing Circuit 261 can function as a column-parallel (column-type) analog-to-digital converter. can.

[0052] Circuit 264 has a comparator 264a and a counter circuit 264b. Comparator 2 64a receives analog signals from wiring 123 provided in each row, and wiring 267 It has the function of comparing the potential of the input reference potential signal (e.g., ramp wave signal). Counter circuit 264b receives the clock signal from wiring 268. Counter circuit 26 4b measures the period during which the first value is output by the comparison operation of comparator 264a. It also has the function of storing the measurement result as an N-bit digital value.

[0053] The column drive circuit 262 is also called a column selection circuit, horizontal drive circuit, etc. The column drive circuit 262 is A selection signal is generated to select the column from which to read the signal. The column drive circuit 262 is a shift register It can be composed of the following. The column drive circuit 262 sequentially selects columns, and the selected column The signal output from circuit 264 is input to output circuit 263 via wiring 269. Wiring 269 can function as a horizontal transfer line.

[0054] The signal input to the output circuit 263 is processed by the output circuit 263 and then sent to the outside of the imaging device 100. The output is sent to the section. The output circuit 263 can be configured as, for example, a buffer circuit. The output circuit 263 can control the timing of outputting a signal to the outside of the imaging device 100. They may possess the ability.

[0055] Also, for example, the second circuit 270 or the third circuit 280 reads out the pixel 111 It has the function of generating and outputting a selection signal to select the second circuit 270 or the Circuit 280 in section 3 is sometimes referred to as a row selection circuit or a vertical drive circuit.

[0056] The peripheral circuitry includes at least logic circuits, switches, buffers, amplification circuits, or conversion circuits. It has one. Transistors and the like used in the peripheral circuit form the photoelectric conversion element 136 described later. It may also be formed using other parts of the semiconductor that make up the structure. Furthermore, transistors used in peripheral circuits. These may be formed using other parts of the semiconductor that forms the pixel driving circuit 112, which will be described later. Furthermore, transistors used in peripheral circuits are combined with these transistors. It may also be used in this manner. Furthermore, some or all of the peripheral circuits may be implemented using semiconductor devices such as ICs. good.

[0057] Furthermore, the peripheral circuits omit at least one of the first to fourth circuits 260. It may be omitted. For example, the function of either the first circuit 260 or the fourth circuit 290 may be the first In addition to the other of circuit 260 or the fourth circuit 290, the first circuit 260 or the fourth One of the circuits 290 may be omitted. Also, for example, a second circuit 270 or a third circuit By adding one function of 280 to the other of the second circuit 270 or the third circuit 280, Either the second circuit 270 or the third circuit 280 may be omitted. Also, for example, the first The function of another circuit is added to any one of circuits 260 to the fourth circuit 290, and the first Circuits 260 through the fourth circuit 290 may be omitted, except for one of them.

[0058] Furthermore, as shown in Figure 1(B), in the pixel section 110 of the imaging device 100, pixel 11 1 may be tilted and placed diagonally. By tilting and placing pixel 111, the row direction and The pixel spacing (pitch) in the row direction can be shortened. This allows the imaging device 100 to The quality of the captured images can be further improved.

[0059] [Example configuration of pixel 111] An example of the configuration of pixel 111 will be explained using Figures 3 to 5. Pixel 111 is a transient 131 transistor, 132 transistor, 133 transistor, 134 transistor, capacitive element It has functional elements such as 135 and a photoelectric conversion element 136. It also constitutes the pixel 111. The pixel driving circuit 11 is a circuit composed of functional elements other than the photoelectric conversion element 136. This is referred to as 2. The pixel driving circuit 112 is electrically connected to the photoelectric conversion element 136. The drive circuit 112 has a function to generate an analog signal according to the amount of light received by the photoelectric conversion element 136. To possess.

[0060] Figure 3(A) is a plan view of pixel 111. Figure 3(B) is a plan view of photoelectric conversion element 136. Figure 4(A) is a plan view of the pixel driving circuit 112. Figure 4(B) is a plan view of the pixel 111 This is the circuit diagram. Figure 5 is a perspective view illustrating the configuration of pixel 111. Pixel 111 is a light The pixel driving circuit 112 is located on the power conversion element 136.

[0061] The photoelectric conversion element 136 comprises a p-type semiconductor 221, an i-type semiconductor 222, and an n-type semiconductor 223. The photoelectric conversion element 136 has, in a plan view, a p-type semiconductor 221 and an n-type semiconductor 22 An i-type semiconductor 222 is sandwiched between 3. The photoelectric conversion element 136 is an i-type semiconductor It is also possible to construct it using a p-type semiconductor 221 and an n-type semiconductor 223 without providing a conductor 222, By providing the i-type semiconductor 222 on the photoelectric conversion element 136, the light reception sensitivity can be increased.

[0062] Ideally, intrinsic semiconductors (type i semiconductors) should be free of impurities and have a Fermi level that is not affected. Although it is a semiconductor located almost in the center of the band, in this specification, etc., it is an impurity that serves as a donor or An acceptor impurity is added so that the Fermi level is located approximately in the center of the band gap. Semiconductors that have been modified are also included in intrinsic semiconductors. In addition, impurities that act as donors or impurities that act as acceptors are also included. Even if a semiconductor contains pure substances, if it is in a state where it can function as an intrinsic semiconductor, Semiconductors are classified as intrinsic semiconductors.

[0063] The p-type semiconductor 221 and the n-type semiconductor 223 are formed in a comb-like shape in a plan view, and the i-type semiconductor It is preferable to form them so that they interlock via body 222. p-type semiconductor 221 and n-type By making semiconductor 223 comb-shaped, the distance between the p-type semiconductor 221 and the n-type semiconductor 223 is such that they face each other. The distance D can be increased. Note that the distance D is the distance between the p-type semiconductor 221 and the n-type semiconductor in a plan view. It can also be said that this is the length of the line passing through the center of the i-type semiconductor 222 sandwiched between semiconductors 223. By doing so, the detection sensitivity of the photoelectric conversion element 136 can be increased. A highly sensitive imaging device 100 can be provided. In Figure 3(B), the position at distance D is indicated by a dashed line. This is shown. Also, when visible light is detected at pixel 111, the p-type semiconductor 221 in planar view is The distance E (width of the i-type semiconductor 222) to the n-type semiconductor 223 is set to 800 nm or more. This is preferable (see Figure 3(B)).

[0064] Either the source or drain of transistor 131 is electrically connected to wiring 123, The other side of the source or drain of transistor 132 is electrically connected to either the source or drain of transistor 132. They are connected. The gate of transistor 131 is electrically connected to wiring 125. The source or drain of transistor 132 is electrically connected to wiring 124. The gate of transistor 132 is electrically connected to node 152. Either the source or drain of 133 is electrically connected to the wiring 122, and the source or drain The other end of the rain is electrically connected to node 152. The gate of transistor 133 is It is electrically connected to wiring 126. One of the source or drains of transistor 134. One end is electrically connected to node 151, and the other end, either source or drain, is electrically connected to node 152. They are electrically connected. The gate of transistor 134 is electrically connected to wiring 127. One electrode (for example, the cathode) of the photoelectric conversion element 136 (photodiode) is Node 151 is electrically connected, and the other electrode (e.g., anode) is electrically connected to wiring 121. They are connected to each other (see Figures 4(A) and 4(B)).

[0065] Node 152 functions as a charge storage unit. Transistor 134 is a photoelectric conversion element 1 It functions as a transfer transistor to transfer charge to node 152 according to the amount of light received by node 36. Yes, it is possible. Also, transistor 133 resets the potential of node 152. It can function as a transistor. Also, transistor 132 is stored at node 152. It can function as an amplifying transistor that amplifies electric charge. Also, transistor 13 1 is a readout transistor for reading the signal amplified by transistor 132. It can function.

[0066] The analog signal generated by the photoelectric conversion element 136 and the pixel driving circuit 112 is routed through wiring 123. It is supplied to. Also, for example, wiring 121 has the function of supplying potential VPD. Wiring 122 has the function of supplying the potential VRS. For example, wiring 124 has the potential VPI It has a supplying function. For example, wiring 125 has the function of supplying potential SEL. For example, wiring 126 has the function of supplying potential PR. Wiring 127 supplies potential TX. It has a supplying function. For example, wiring 128 has the function of supplying potential VPI.

[0067] Furthermore, in this embodiment, the wiring 121 is arranged in a mesh pattern so as to surround the outer periphery of the pixel 111. The wiring 121 is electrically connected to the p-type semiconductor 221. By providing this, the potential variation of the wiring 121 within the pixel section 110 is reduced, and the imaging device 100 This stabilizes the operation and improves the reliability of the imaging device 100. Also, transistor 1 Connect either the source or drain of 34 electrically to the wiring 129, and connect the wiring 129 to an n-type semiconductor It may also be electrically connected to conductor 223 (see Figure 5). Also, the source of transistor 131 Alternatively, electrically connect one of the drains to wiring 141, and electrically connect wiring 141 to wiring 123. It may also be connected to the source or drain of transistor 132. It may also be electrically connected to 2, and wiring 142 may be electrically connected to wiring 124. Connect either the source or drain of the generator 133 electrically to the wiring 143, and wiring 143 It may also be electrically connected to wiring 122. Alternatively, the other electrode of the capacitive element 135 may be connected to wiring 14 Connect 4 electrically, connect wiring 144 electrically to wiring 145, and connect wiring 145 to wiring 12 It may be electrically connected to 1. In this embodiment, it crosses the wiring 124 and is electrically This shows an example of providing wiring 128 for electrical connection. By providing wiring 128, the pixel section Reduce the potential variation of the wiring 124 within 110, stabilize the operation of the imaging device 100, and capture The reliability of the device 100 can be improved. Furthermore, the capacitor element 135 is a transistor. Parasitic capacity may be used.

[0068] Furthermore, the functional elements and wiring (electrodes) constituting the pixel 111 are made of p-type semiconductor 221 as much as possible. Formed on the n-type semiconductor 223 and, as far as possible, not overlapping with the i-type semiconductor 222. It is preferable to do so. Specifically, the i-type semiconductor 222 and the functional element in a plan view The area where the wiring overlaps is preferably 35% or less of the area of ​​the i-type semiconductor 222 in a plan view. More preferably, it should be 20% or less, and even more preferably 10% or less. In other words, In a planar view, the ratio of the area that can actually receive light to the total area of ​​the i-type semiconductor 222 ( The "effective aperture ratio" (also called the "effective aperture ratio") is preferably 65% ​​or more, more preferably 80% or more, and further Preferably, it should be 90% or more. By increasing the effective aperture ratio, the exposed area of ​​the i-type semiconductor 222 is By increasing this, the detection sensitivity of the imaging device 100 can be improved. Also, the imaging device 100 This can increase the dynamic range.

[0069] Figures 6 and 7 show examples of arranging multiple pixels 111 in a matrix. Figure 6 shows pixel 11 An example is shown where 1 is arranged in a matrix of 3 rows (n to n+2 rows) and 2 columns (m and m+1 columns). This is a plan view. Figure 7 is a circuit diagram corresponding to Figure 6. In Figures 6 and 7, the m row and m+ An example of mirror symmetry achieved by swapping the left and right sides of a pixel configuration of 111 pixels in one column (for example, odd-numbered and even-numbered columns). It is showing.

[0070] Furthermore, the nth line of wiring 128 is electrically connected to wiring 124 which has the function of supplying potential VPI. Connect the (n+1)th line of wiring 128 to wiring 122 which has the function of supplying potential VRS. They are electrically connected. In this way, wiring 122 or wiring 128 is electrically connected to wiring 128. By changing the 124 wiring at regular intervals, the potentials VPI and VRS within the pixel section 110 are This reduces potential variation, stabilizes the operation of the imaging device 100, and improves the reliability of the imaging device 100. It is possible to do so.

[0071] Figure 8 shows the photoelectric conversion element 136 of the pixel 111 arranged in 3 rows (n to n+2 rows) and 2 columns (m and This is a plan view showing an example of arrangement in a matrix of (x + m) columns. The photoelectric conversion element 136 is A semiconductor layer can be formed without separating each pixel 111. Specifically, the pixel portion A semiconductor layer is formed throughout the 110, and then the following methods are used: ion implantation, ion doping, etc. Within the semiconductor layer, p-type semiconductor 221, n-type semiconductor 223, and i-type semiconductor 222 function as a single unit. A region can be formed. In addition, an i-type semiconductor 222 is used for each pixel, and a p-type semiconductor 221 is used. By enclosing it in this way, electrical interference with the i-type semiconductor 222 between adjacent pixels can be prevented. Since it is not necessary to separate the semiconductor layers constituting the power conversion element 136 for each pixel, the photoelectric conversion element 136 can be efficiently placed within the pixel 111. Therefore, the light-receiving sensor of the imaging device 100 The degree can be increased.

[0072] Furthermore, the p-type semiconductor 221 may be used as part of the wiring that supplies power. By using the conductor 221 as part of the wiring that supplies power, the power supply within the pixel section 110 This can reduce variations in the source potential. You may substitute them for each other.

[0073] [Color filters, etc.] The image capture device 100 uses its pixels 111 as sub-pixels, and each of the multiple pixels 111 is used By providing filters (color filters) that transmit light in different wavelength ranges, a color image can be displayed. Information necessary to realize the objective can be obtained.

[0074] Figure 9(E) is a plan view showing an example of pixels 111 for acquiring a color image. Figure 9 (E) is a pixel 111 (hereinafter, a color filter that transmits the red (R) wavelength range) provided with it. (Also known as "Pixel 111R"), it is equipped with a color filter that transmits the green (G) wavelength range. Pixel 111 (hereinafter also referred to as "pixel 111G") and color that transmits the blue (B) wavelength range It has a pixel 111 (hereinafter also referred to as "pixel 111B") which is equipped with a filter. Pixels 11R, 111G, and 111B are combined and function as a single pixel 113.

[0075] Note that the color filters used for pixel 111 are limited to red (R), green (G), and blue (B). As shown in Figure 9(A), cyan (C), yellow (Y), and magenta (M) light are used, respectively. A color filter that transmits light may be used. Three different wavelength ranges may be used for one pixel 113. By providing light-detecting pixels 111, a full-color image can be acquired.

[0076] Figure 9(B) shows color filters that transmit red (R), green (G), and blue (B) light, respectively. In addition to the pixel 111 which is provided, a color filter that transmits yellow (Y) light is provided. An example is shown of a pixel 113 having pixel 111. Figure 9(C) shows cyan (C) and A color filter that transmits yellow (Y) and magenta (M) light is added to pixel 111. Furthermore, a pixel 111 having a color filter that transmits blue (B) light. Example 3 is shown. A single pixel 113 detects light in four different wavelength ranges. By implementing this feature, the color reproduction accuracy of the acquired images can be further improved.

[0077] Also, for example, the pixel ratio of pixel 111R, pixel 111G, and pixel 111B (or receiving The light area ratio does not necessarily have to be 1:1:1. As shown in Figure 9(D), the number of pixels A Bayer array with a ratio (light-receiving area ratio) of red:green:blue = 1:2:1 may also be used. The pixel ratio (light-receiving area ratio) may also be set to red:green:blue = 1:6:1.

[0078] Note that while one pixel 111 may be provided in pixel 113, two or more are preferable. For example, By providing two or more pixels 111 that detect the same wavelength range, redundancy is increased, and the imaging device 10 This can improve the reliability of the value of zero.

[0079] Furthermore, as a filter, it absorbs or reflects light with wavelengths below the wavelength of visible light, thus blocking infrared light. By using an IR (Infrared) filter that transmits infrared light, infrared light can be detected. The imaging device 100 can be realized. In addition, wavelengths greater than the wavelength of visible light can be used as a filter. UV (Ultra Viol) absorbs or reflects light containing ultraviolet light and transmits ultraviolet light. By using an (et) filter, an imaging device 100 that detects ultraviolet light can be realized. Furthermore, a scintillator that converts radiation into ultraviolet or visible light is used as a filter. Therefore, the imaging device 100 can also function as a radiation detector that detects X-rays, gamma rays, etc. can.

[0080] Additionally, filter 602 is an ND (ND: Neutral Density) filter. When a (light-reducing filter) is used, a large amount of light is incident on the photoelectric conversion element (light-receiving element). This can prevent the phenomenon of output saturation that sometimes occurs (hereinafter also referred to as "output saturation"). By using a combination of ND filters with different light reduction amounts, the dynamic range of the imaging device can be adjusted. The range can be enlarged.

[0081] In addition to the filter mentioned above, a lens may also be provided at pixel 113. Here, Figure 10 An example of the arrangement of pixel 113, filter 602, and lens 600 will be explained using a cross-sectional diagram. By providing the 600, incident light can be efficiently received by the photoelectric conversion element. Specifically, as shown in Figure 10(A), a lens 600 and a filter 6 are formed on the pixel 113. 02 (filter 602R, filter 602G, filter 602B), and pixel driving circuit 1 The structure can be configured to allow light 660 to be incident on the photoelectric conversion element 136 through 12, etc.

[0082] However, as shown in the area enclosed by the dashed line, a portion of the light 660 indicated by the arrow is connected to the wiring layer 604 Light may be partially blocked by the light. Therefore, as shown in Figure 10(B), light Lens 600 and filter 602 are formed on the side of the photoelectric conversion element 136, so that the incident light is converted into a photoelectric conversion element A structure may be used to efficiently receive light in the child 136. Light 660 from the photoelectric conversion element 136 side By allowing light to enter, an imaging device 100 with high detection sensitivity can be provided.

[0083] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments. That is the case.

[0084] (Embodiment 2) In this embodiment, the imaging device 100 shown in the above embodiment is a type of solid-state image sensor. An example of a configuration using a CMOS image sensor will be explained using Figures 11 to 15. The pixel region 251 shown in Figure 11 is a cross-section of a part of the pixels 111 of the imaging device 100. This is a diagram. The peripheral circuit region 252 shown in Figure 11 is part of the peripheral circuitry of the imaging device 100. This is a cross-sectional view. Figure 12(A) shows an enlarged view of the transistor 134 shown in Figure 11. Furthermore, an enlarged view of the capacitive element 135 shown in Figure 11 is shown in Figure 12(B). Also, as shown in Figure 11 An enlarged view of transistor 281 is shown in Figure 14(A). Also, the transistor shown in Figure 11 An enlarged view of 282 is shown in Figure 14(B).

[0085] The imaging device 100 illustrated in this embodiment has an insulating layer 102 on a substrate 101, and the insulating layer The photoelectric conversion element 136 has a pin-type junction formed on 102. As explained, the photoelectric conversion element 136 consists of a p-type semiconductor 221, an i-type semiconductor 222, and n It has a type semiconductor 223.

[0086] The substrate 101 can be a glass substrate, a quartz substrate, a sapphire substrate, a ceramic substrate, or a metal substrate. A plate, semiconductor substrate, etc., can be used. Furthermore, a durable material that can withstand the processing temperature of this embodiment is also used. A heat-resistant plastic substrate may be used. An example of such a substrate is a semiconductor substrate. For example, single crystal substrates or silicon substrates), SOI (SOI: Silicon on Ins ulator) substrates, glass substrates, quartz substrates, plastic substrates, metal substrates, stainless steel • Steel substrate, substrate with stainless steel foil, tungsten substrate, tungsten Examples include substrates with 10 foil. An example of a glass substrate is barium rhodium. Examples include acidic glass, aluminoborosilicate glass, or soda-lime glass.

[0087] Furthermore, after the formation of the photoelectric conversion element 136 and the pixel driving circuit 112, mechanical polishing and etching are performed. The substrate 101 may be removed using a method such as the G method. If a material that can transmit the light to be detected is used, light is input to the photoelectric conversion element 136 from the substrate 101 side. It can be shot.

[0088] The insulating layer 102 is made of aluminum oxide, magnesium oxide, silicon oxide, and silicon oxide nitride. N, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, ranium oxide Oxide materials such as tungsten, neodymium oxide, hafnium oxide, and tantalum oxide, and silica nitride Nitride materials such as silicon nitride, aluminum nitride, and aluminum nitride. This can be formed in a single layer or multiple layers. The insulating layer 102 can be formed by sputtering or CV It can be formed using methods such as D method, thermal oxidation method, coating method, and printing method.

[0089] The formation of the p-type semiconductor 221, i-type semiconductor 222, and n-type semiconductor 223 is, for example, an insulating After forming island-shaped i-type semiconductors 222 on layer 102, a mask is placed on top of the i-type semiconductors 222. This can be achieved by forming and selectively introducing impurity elements into a portion of the i-type semiconductor 222. The introduction of elements can be carried out, for example, using methods such as ion implantation or ion doping. After introducing the impurity elements, remove the mask.

[0090] The p-type semiconductor 221, i-type semiconductor 222, and n-type semiconductor 223 are single-crystal semiconductors, multi-crystalline Crystalline semiconductors, microcrystalline semiconductors, nanocrystalline semiconductors, semi-amorphous semiconductors, amorphous semiconductors It can be formed using materials such as amorphous silicon or microcrystalline germanium. These can be used. In addition, compound semiconductors such as silicon carbide and gallium arsenide can be used. It is possible.

[0091] Materials for forming p-type semiconductor 221, i-type semiconductor 222, and n-type semiconductor 223 When using silicon, for example, a group 13 element can be used as the p-type impurity element. This can be done. In addition, as n-type impurity elements, for example, elements from Group 15 can be used. ru.

[0092] Furthermore, for example, when the above semiconductor is formed by SOI, the insulating layer 102 is a BOX layer (BO X: Buried Oxide) may also be used.

[0093] Furthermore, the imaging device 100 shown in this embodiment includes a p-type semiconductor 221, an i-type semiconductor 222, and It has an insulating layer 103 and an insulating layer 104 on the p-type semiconductor 221. The insulating layer 103 and the insulating layer 104 can be formed by the same materials and methods as the insulating layer 102. Note that either the insulating layer 103 or the insulating layer 104 may be omitted, or insulating layers may be further stacked.

[0094] In addition, the imaging device 100 shown in this embodiment forms an insulating layer 105 having a flat surface on the insulating layer 104. The insulating layer 105 can be formed by the same materials and methods as the insulating layer 102. Also, as the insulating layer 105, a low dielectric constant material (low-k material), a siloxane-based resin, PSG (phosphosilicate glass), BPSG (borophosphosilicate glass), etc. may be used. Also, a chemical mechanical polishing (CMP: Chemical Mechanical Polishing) treatment (hereinafter also referred to as "CMP treatment") may be performed on the surface of the insulating layer 105. By performing the CMP treatment, the unevenness on the sample surface can be reduced, and the coating properties of the insulating layer and the conductive layer formed thereafter can be improved.

[0095] Also, an opening​​​​​​​​​​​​​​It can be covered with a (layer). In this case, it may be referred to as a contact plug including a barrier film. Note that there are no particular restrictions on the number and arrangement of the openings 224 and 225. Therefore, an imaging device with a high degree of layout freedom can be realized.

[0096] Also, wiring 121 and wiring 129 are formed on the insulating layer 105. Wiring 121 is electrically connected to the p-type semiconductor 221 through the contact plug 106 at the opening 224. [[ID=...]] Also, wiring 129 is electrically connected to the n-type semiconductor 223 through the contact plug 106 at the opening 225.

[0097] Also, an insulating layer 107 is formed covering the wiring 121 and the wiring 129. The insulating layer 10 7 can be formed by the same material and method as the insulating layer 105. Also, a CMP process may be performed on the surface of the insulating layer 10 7. By performing the CMP process, the unevenness on the sample surface can be reduced, and the coating property of the insulating layer and the conductive layer formed later can be improved.

[0098] The wiring 121 and the wiring 129 can be used as a single-layer structure or a laminated structure of a single metal composed of aluminum, titanium, chromium, nickel, copper, yttrium, zirconium, molybdenum, manganese, silver, tantalum, or tungsten, or an alloy having this as a main component. For example, a single-layer structure of a copper film containing manganese, a two-layer structure in which an aluminum film is laminated on a titanium film, a two-layer structure in which an aluminum film is laminated on a tungsten film, a two-layer structure in which a copper film is laminated on a copper-magnesium-aluminum alloy film, a two-layer structure in which a copper film is laminated on a titanium film, a two-layer structure in which a copper film is laminated on a tungsten film, a titanium film or a titanium nitride film, and a two-layer structure in which a copper film is laminated on a copper-magnesium-aluminum alloy film, a two-layer structure in which a copper film is laminated on a titanium film, a two-layer structure in which a copper film is laminated on a tungsten film, a two-layer structure of a titanium film or a titanium nitride film and a two-layer structure in which a copper film is laminated on a tungsten film, a titanium film or a titanium nitride film, and An aluminum film or copper film is laminated on top of the titanium film or titanium nitride film, and further A three-layer structure formed by forming a titanium film or titanium nitride film on top of that, or a molybdenum film or molybdenum nitride film. A molybdenum film, and an aluminum film or a molybdenum nitride film layered on top of the molybdenum film or molybdenum nitride film. A three-layer structure in which copper films are stacked, and then a molybdenum film or molybdenum nitride film is formed on top of them. A three-layer structure in which a copper film is laminated on a tungsten film, and then another tungsten film is formed on top of that. These include titanium, tantalum, tungsten, molybdenum, and chromium alloys. A film of elements selected from chromium, neodymium, and scandium, or an alloy film of a combination of multiple elements, Alternatively, a nitride film may be used.

[0099] Furthermore, indium tin oxide, zinc oxide, indium oxides including tungsten oxide, and acid Indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, oxide Titanium-containing indium tin oxide, indium zinc oxide, and indium with added silicon dioxide Conductive materials containing oxygen, such as um-tin oxide, and nitrogen-containing materials, such as titanium nitride and tantalum nitride. Conductive materials may be used. In addition, materials containing the aforementioned metal elements and conductive materials containing oxygen may be used. It is also possible to create a laminated structure by combining materials. Furthermore, the aforementioned materials containing metal elements, A layered structure can also be formed by combining conductive materials containing nitrogen. Furthermore, the aforementioned metals... The product of a combination of elemental materials, oxygen-containing conductive materials, and nitrogen-containing conductive materials It can also be structured in layers.

[0100] Transistor 134, transistor 289, and capacitive element 135 are insulated from insulating layer 108 and It is formed on the insulating layer 107 via the edge layer 109. Although not shown in Figure 11, Transistors 131, 132, 133, etc. are also formed on the insulating layer 107 via the insulating layers 108 and 109. In this embodiment, transistors 134 and 289 are exemplified as top-gate-structured transitors, but they may also be bottom-gate-structured transitors. The same applies to other transitors not shown in FIG. 11.

[0101] In addition, as the above transitor, an inverse staggered type transitor or a forward staggered type transitor can also be used. Also, it is possible to use a dual-gate type transitor in which the semiconductor layer in which the channel is formed is sandwiched between two gate electrodes. Further, it is not limited to a single-gate structure transitor, and it may be a multi-gate type transitor having a plurality of channel formation regions, for example, a double-gate type transitor.

[0102] In addition, as the above transitor, various configurations of transitors such as a planar type, a FIN type (fin type), and a TRI-GATE type (tri-gate type) can be used.

[0103] The above transitors may each have the same structure or different structures. The size of the transitor (for example, channel length and channel width) etc. may be appropriately adjusted for each transitor. When all of the plurality of transitors included in the imaging device 100 have the same structure, each transitor can be manufactured simultaneously in the same process.

[0104] Transistor 134 includes an electrode 243 that can function as a gate electrode and a source electrode An electrode 244 which can function as either a pole or a drain electrode, and a source electrode The electrode 245 can function as the other side of the drain electrode, and the gate insulating layer is a machine It has a functional insulating layer 117 and a semiconductor layer 242.

[0105] In Figure 11, the other of the source electrode or drain electrode of transistor 134 is shown. The electrode 245 can function as one of the electrodes of the capacitive element 135, Both are formed using electrode 245. However, one aspect of the present invention is not limited thereto. i. An electrode that functions as the other of the source electrode or drain electrode of transistor 134, The electrodes that can function as one of the electrodes of the capacitive element 135 are each different electrodes. It may be formed using this method.

[0106] Furthermore, the capacitive element 135 is an electrode that can function as one of the electrodes of the capacitive element 135. 245 and electrode 273, which can function as the other electrode, are connected to the insulating layer 277 and semiconductor It has a configuration in which the body layers 272c overlap. Also, electrode 273 is formed simultaneously with electrode 243. This can be achieved. Furthermore, the insulating layer 277 and the semiconductor layer 272c function as dielectrics. It is possible. Furthermore, the insulating layer 277 can be formed at the same time as the insulating layer 177. Also, semiconductor Layer 272c can be formed simultaneously with the semiconductor layer 242c. One of the conductor layers 272c may be omitted.

[0107] The insulating layer 108 prevents the diffusion of impurities such as oxygen, hydrogen, water, alkali metals, and alkaline earth metals. It is preferable to form it using an insulating film that has a protective function. As the insulating film, silica Cone, silicon nitride, silicon nitride, silicon oxide nitride, gallium oxide, hafni oxide Examples include yttrium oxide, aluminum oxide, and aluminum oxide / nitride. As insulating films, silicon nitride, gallium oxide, hafnium oxide, yttrium oxide, oxide By using aluminum, impurities diffusing from the photoelectric conversion element 136 side are contained within the semiconductor layer. This can prevent the material from reaching 242. Furthermore, the insulating layer 108 is sputtered. It can be formed by methods such as CVD, vapor deposition, and thermal oxidation. The insulating layer 108 is These materials can be used in a single layer or in a laminated configuration.

[0108] The insulating layer 109 can be formed using the same materials and methods as the insulating layer 102. When an oxide semiconductor is used as the conductive layer 242, the insulating layer 108 must satisfy a stoichiometric composition. It is preferable to form it using an insulating layer that contains more oxygen than oxygen. In an insulating layer containing more oxygen than it can fill, some of the oxygen will be released upon heating. An insulating layer containing more oxygen than that satisfying the theoretical composition will have a surface temperature of 100°C or higher. TDS analysis performed by heat treatment at 0°C or below, preferably between 100°C and 500°C. The amount of oxygen removed, converted to oxygen atoms, is 1.0 × 10⁻⁶. 18 atoms / cm 3 The above is preferred Or 3.0 x 10 20 atoms / cm 3 The above is the insulating layer.

[0109] Furthermore, an insulating layer containing more oxygen than that satisfying the stoichiometric composition is an insulating layer that has oxygen added to it. It can also be formed by adding oxygen. The oxygen addition process is carried out under an oxygen atmosphere. This is done using heat treatment, ion implantation equipment, ion doping equipment, or plasma treatment equipment. It is possible. As for the gas used to add oxygen, 16 O2 or 18 Acids such as O2 Elementary gases, nitrous oxide gas, or ozone gas can be used. The process of adding oxygen is also called "oxygen doping."

[0110] The semiconductor layers of transistors such as transistor 134 and transistor 289 are single-crystal semiconductors and polycrystalline semiconductors. Using microcrystalline semiconductors, nanocrystalline semiconductors, semi-amorphous semiconductors, amorphous semiconductors, etc. It can be formed by using materials such as amorphous silicon or microcrystalline germanium. It is possible to do so with silicon carbide, gallium arsenide, oxide semiconductors, nitride semiconductors, etc. Compound semiconductors, organic semiconductors, and the like can be used.

[0111] In this embodiment, an example in which an oxide semiconductor is used as the semiconductor layer 242 will be described. In this embodiment, the semiconductor layer 242 is made up of semiconductor layer 242a, semiconductor layer 242b, and We will now explain the case where the semiconductor layer 242c is stacked.

[0112] Semiconductor layer 242a, semiconductor layer 242b, and semiconductor layer 242c are made of In or Ga Formed from a material containing one or both of the following: Typically, In-Ga oxide (In and Ga (Oxides containing), In-Zn oxide (Oxides containing In and Zn), In-M-Zn oxide ( An oxide containing In, element M, and Zn. Element M can be Al, Ti, Ga, Y, Zr, La, One or more elements selected from Ce, Nd, or Hf, with a stronger bond to oxygen than In. It is a metallic element.

[0113] Semiconductor layer 242a and semiconductor layer 242c are composed of metal elements that make up semiconductor layer 242b It is preferable that it be formed from a material containing one or more of the same metallic elements. When the material is used, the interface between semiconductor layer 242a and semiconductor layer 242b, and the semiconductor layer This makes it less likely for interface states to form at the interface between 242c and the semiconductor layer 242b. Therefore, carrier scattering and trapping at the interface are less likely to occur, and the field-effect mobility of the transistor is reduced. This makes it possible to improve the performance. Furthermore, it reduces variations in the transistor threshold voltage. This makes it possible to realize semiconductor devices with good electrical characteristics. This is the result.

[0114] The thickness of semiconductor layer 242a and semiconductor layer 242c is preferably between 3 nm and 100 nm. The thickness shall be between 3 nm and 50 nm. Also, the thickness of semiconductor layer 242b shall be between 3 nm and 20 nm. 0 nm or less, preferably 3 nm to 100 nm, more preferably 3 nm to 50 nm Let m be less than or equal to m.

[0115] Furthermore, semiconductor layer 242b is In-M-Zn oxide, and semiconductor layer 242a and semiconductor When layer 242c is also an In-M-Zn oxide, semiconductor layer 242a and semiconductor layer 242 c is In:M:Zn=x1:y1:z1 [atomic ratio], and semiconductor layer 242b is In:M:Z If n = x²:y²:z² [atomic ratio], then y1 / x1 will be greater than y² / x². Semiconductor layer 242a, semiconductor layer 242c, and semiconductor layer 242b are selected accordingly. Alternatively, the semiconductor layer 242a is configured such that y1 / x1 is 1.5 times or more larger than y2 / x2. Select semiconductor layer 242c and semiconductor layer 242b. More preferably, y1 / x Semiconductor layer 242a, semiconductor layer 242c, such that 1 is more than twice as large as y² / x². And semiconductor layer 242b is selected. More preferably, y1 / x1 is 3 than y2 / x2. Semiconductor layers 242a, 242c, and 242b are made to be more than twice as large. Select. At this time, if y1 is greater than or equal to x1 in semiconductor layer 242b, then a transistor This is preferable because it provides stable electrical characteristics. However, when y1 is 3 times or more x1 Therefore, the field-effect mobility of the transistor decreases, so y1 is less than 3 times x1. Preferred. By having the semiconductor layer 242a and semiconductor layer 242c in the above configuration, Body layer 242a and semiconductor layer 242c are less prone to oxygen vacancies than semiconductor layer 242b. It can be made into layers.

[0116] Furthermore, when semiconductor layer 242a and semiconductor layer 242c are In-M-Zn oxide, I The content of n and element M is preferably less than 50 atomic% for In and 50 atomic% for element M. mic% or more, more preferably In is less than 25 atomic%, and element M is 75 atomic The concentration shall be ic% or higher. Also, when semiconductor layer 242b is In-M-Zn oxide, In and The content of element M is preferably 25 atomic% or more of In and 75 atomic% of element M. Less than %, more preferably In is 34 atomic% or more, and element M is 66 atomic% Less than.

[0117] For example, a semiconductor layer 242a containing In or Ga, and a semiconductor layer containing In or Ga As 242c, In:Ga:Zn = 1:3:2, 1:3:4, 1:3:6, 1:6:4, Alternatively, In-Ga-Zn oxide formed using a target with an atomic ratio such as 1:9:6. Or, an In-Ga oxide formed using a target with an atomic ratio such as In:Ga = 1:9 Or, gallium oxide or the like can be used. Also, as the semiconductor layer 242b, In:Ga :Zn = 3:1:2, 1:1:1, 5:5:6, or 4:2:4.1 and other atomic ratio targets can be used to form an In-Ga-Zn oxide. Note that the atomic ratios of the semiconductor layer 242a and the semiconductor layer 242b each include fluctuations of plus or minus 20% of the above atomic ratio as an error.

[0118] In order to impart stable electrical characteristics to the transistor using the semiconductor layer 242b, impurities and oxygen deficiencies in the semiconductor layer 242b are reduced to achieve high purity intrinsicization, and the semiconductor layer 242b is preferably made into an oxide semiconductor layer that can be regarded as intrinsic or substantially intrinsic. Also, at least the channel formation region in the semiconductor layer 242b is preferably made into a semiconductor layer that can be regarded as intrinsic or substantially intrinsic.

[0119] Note that an oxide semiconductor layer that can be regarded as substantially intrinsic means an oxide semiconductor layer in which the carrier density is , less than 1×10 17 / cm 3 , less than 1×10 15 / cm 3 , or less than 1×10 13 / cm 3

[0120] [Energy Band Structure of Oxide Semiconductor] Here, the functions and effects of the semiconductor layer 242 composed of the semiconductor layer 242a, the semiconductor layer 242b, and the semiconductor layer 242c stacked will be described using the energy band structure diagram shown in FIG. 13. FIG. 13 shows the energy band structure of the site indicated by the one-dot chain line C1-C2 in FIG. 12(A). ​ This is an energy band structure diagram. Figure 13 shows the energy of the channel formation region of transistor 134. It shows a gyroband structure.

[0121] In Figure 13, Ec382, Ec383a, Ec383b, Ec383c, and Ec386 are... Each of these consists of an insulating layer 109, a semiconductor layer 242a, a semiconductor layer 242b, a semiconductor layer 242c, and an insulating layer. This shows the energy at the lower end of the conduction band in layer 117.

[0122] Here, the difference between the energy of the vacuum level and the energy of the lower end of the conduction band (also called "electron affinity") is true The difference between the energy of the empty level and the energy of the upper end of the valence band (also called the ionization potential) This is the value after subtracting the energy gap. Note that the energy gap is measured using a spectroscopic ellipsometer. Measurement can be performed using the HORIBA JOBIN YVON UT-300. The energy difference between the vacant level and the upper end of the valence band is determined by ultraviolet photoelectron spectroscopy (UPS). iolet Photoelectron Spectroscopy (PHI Corporation) It can be measured using VersaProbe.

[0123] Furthermore, In-G was formed using a target with an atomic ratio of In:Ga:Zn=1:3:2. The energy gap of α-Zn oxide is approximately 3.5 eV, and the electron affinity is approximately 4.5 eV. Furthermore, In- formed using a target with an atomic ratio of In:Ga:Zn=1:3:4 The energy gap of Ga-Zn oxide is approximately 3.4 eV, and the electron affinity is approximately 4.5 eV. Furthermore, In formed using a target with an atomic ratio of In:Ga:Zn=1:3:6 The energy gap of Ga-Zn oxide is approximately 3.3 eV, and the electron affinity is approximately 4.5 eV. Yes. Also, I formed using a target with an atomic ratio of In:Ga:Zn=1:6:2 The energy gap of n-Ga-Zn oxide is approximately 3.9 eV, and its electron affinity is approximately 4.3 eV. Furthermore, a target with an atomic ratio of In:Ga:Zn=1:6:8 was formed. The energy gap of In-Ga-Zn oxide is approximately 3.5 eV, and its electron affinity is approximately 4.4 eV. It is V. Furthermore, it is formed using a target with an atomic ratio of In:Ga:Zn = 1:6:10. The energy gap of the resulting In-Ga-Zn oxide is approximately 3.5 eV, and its electron affinity is approximately 4. It is 5 eV. Also, using a target with an atomic ratio of In:Ga:Zn=1:1:1, the shape The resulting In-Ga-Zn oxide has an energy gap of approximately 3.2 eV and an electron affinity of approximately 4 It is 0.7eV. Also, using a target with an atomic ratio of In:Ga:Zn=3:1:2 The energy gap of the formed In-Ga-Zn oxide is approximately 2.8 eV, and the electron affinity is approximately It is 5.0 eV.

[0124] Since insulating layer 109 and insulating layer 117 are insulators, Ec382 and Ec386 are Ec38 It is closer to the vacuum level (lower electron affinity) than 3a, Ec383b, and Ec383c. .

[0125] Furthermore, Ec383a is closer to the vacuum level than Ec383b. Specifically, Ec383a This is 0.05eV or more, 0.07eV or more, 0.1eV or more, or 0 eV higher than Ec383b. 0.15eV or greater, and 2eV or less, 1eV or less, 0.5eV or less, or 0.4eV or less (true) It is preferable to be close to the empty level.

[0126] Furthermore, Ec383c is closer to the vacuum level than Ec383b. Specifically, Ec383c This is 0.05eV or more, 0.07eV or more, 0.1eV or more, or 0 eV higher than Ec383b. 0.15eV or greater, and 2eV or less, 1eV or less, 0.5eV or less, or 0.4eV or less (true) It is preferable to be close to the empty level.

[0127] Furthermore, near the interface between semiconductor layer 242a and semiconductor layer 242b, and with semiconductor layer 242b Near the interface with the semiconductor layer 242c, a mixed region is formed, and therefore the energy at the lower end of the conduction band - changes continuously. That is, at these interfaces, there are either no levels or very few levels. stomach.

[0128] Therefore, in the laminated structure having the energy band structure, electrons are in the semiconductor layer 242b The movement will mainly occur at the interface between the semiconductor layer 242a and the insulating layer 107. Alternatively, even if an energy level exists at the interface between the semiconductor layer 242c and the insulating layer 117, the said energy level This has almost no effect on electron movement. Also, the boundary between semiconductor layer 242a and semiconductor layer 242b There are no energy levels present on the surface, and at the interface between semiconductor layer 242c and semiconductor layer 242b, or almost none. Therefore, it does not hinder electron movement in that region. The transistor 134, which has a layered structure of conductors, can achieve high field-effect mobility. Cut.

[0129] Furthermore, as shown in Figure 13, the interface between semiconductor layer 242a and insulating layer 109, and semiconductor layer 2 Near the interface between 42c and the insulating layer 117, trap levels 390 are formed due to impurities and defects. Although this can be achieved, the presence of semiconductor layer 242a and semiconductor layer 242c makes it difficult to conduct semiconductors. This allows for the separation of body layer 242b from the trap level.

[0130] In particular, the transistor 134 illustrated in this embodiment has the upper and side surfaces of the semiconductor layer 242b It is formed in contact with semiconductor layer 242c, and the lower surface of semiconductor layer 242b is in contact with semiconductor layer 242a. In this way, the semiconductor layer 242b is covered by semiconductor layers 242a and 242c. By doing so, the influence of the trap order mentioned above can be further reduced.

[0131] However, in the case where the energy difference between Ec383a or Ec383c and Ec383b is small In addition, electrons in semiconductor layer 242b may exceed the energy difference and reach the trap level. . When electrons are trapped in the trap level, a negative fixed charge is generated at the interface of the insulating layer. The transistor's threshold voltage shifts in the positive direction.

[0132] Therefore, the energy difference between Ec383a and Ec383c and Ec383b is... If each is set to 0.1 eV or higher, preferably 0.15 eV or higher, the threshold voltage of the transistor Because the pressure fluctuations are reduced and the electrical characteristics of the transistor can be improved, It seems so.

[0133] Furthermore, the band gap of semiconductor layer 242a and semiconductor layer 242c is... A band gap wider than b is preferable.

[0134] According to one aspect of the present invention, it is possible to realize a transistor with less variation in electrical characteristics. Therefore, it is possible to realize a semiconductor device with less variation in electrical characteristics. This invention According to one embodiment, a transistor with good reliability can be realized. This makes it possible to realize a semiconductor device with good performance.

[0135] Furthermore, since oxide semiconductors have a band gap of 2 eV or more, channels are formed in semiconductors. Transistors using oxide semiconductors in their body layers can achieve extremely low off-currents. Specifically, the off-current per 1 μm of channel width is 1 × 10⁻¹⁶ at room temperature. -20 A Full, preferably 1 × 10 -22 Less than A, more preferably 1 × 10 -24 Let it be less than A This is possible. In other words, the on / off ratio can be set to between 20 and 150 digits.

[0136] According to one aspect of the present invention, a transistor with low power consumption can be realized. This makes it possible to realize imaging devices and semiconductor devices with low power consumption.

[0137] Also, transistors that use oxide semiconductors in the semiconductor layer (also called "OS transistors") Because the off-current is extremely low, the OS transistors are connected to transistors 133 and 134. By using a zista, the capacitance element 135 can be made smaller. Alternatively, the capacitance element 1 By omitting 35, parasitic capacitances such as those of transistors can be used instead of the capacitive element 135. Therefore, the light-receiving area of ​​the photoelectric conversion element 136 can be increased.

[0138] According to one aspect of the present invention, it is possible to realize imaging devices and semiconductor devices with high light-receiving sensitivity. Furthermore, according to one aspect of the present invention, an imaging device or semiconductor device with a wide dynamic range can be realized. It can be expressed.

[0139] Furthermore, because oxide semiconductors have a wide band gap, semiconductor devices using oxide semiconductors are used The operating temperature range of the environment in which it can be used is wide. According to one aspect of the present invention, an imaging device with a wide operating temperature range. This enables the realization of semiconductor devices.

[0140] Note that the above-mentioned three-layer structure is just one example. For example, semiconductor layer 242a or semiconductor layer 242c It is also acceptable to have a two-layer structure in which one of the two layers is not formed.

[0141] [About oxide semiconductors] Here, we will explain in detail the oxide semiconductor film applicable to semiconductor layer 242.

[0142] Oxide semiconductor films are broadly classified into non-single-crystal oxide semiconductor films and single-crystal oxide semiconductor films. A single-crystal oxide semiconductor film is a CAAC-OS (C Axis Aligned Crystals Polycrystalline oxide semiconductor film This refers to microcrystalline oxide semiconductor films, amorphous oxide semiconductor films, etc.

[0143] First, let's explain the CAAC-OS membrane.

[0144] CAAC-OS film is an oxide semiconductor film having multiple c-axis oriented crystalline regions.

[0145] Transmission Electron Microscope (TEM) A composite analysis image of the CAAC-OS film's bright-field image and diffraction pattern (using a scope) Also known as a high-resolution TEM image, multiple crystalline regions can be identified by observing it. On the other hand, high-resolution TEM images also clearly show the boundaries between crystalline parts, i.e., grain boundaries. Also called boundary.) It is not possible to confirm. Therefore, the CAAC-OS membrane is This means that a decrease in electron mobility due to grain boundaries is less likely to occur.

[0146] When observing a high-resolution TEM image of the cross-section of the CAAC-OS film from a direction approximately parallel to the sample surface, In the crystalline region, it can be confirmed that the metal atoms are arranged in layers. Each layer of metal atoms is: The surface (also called the film-forming surface) or the top surface of the CAAC-OS film reflects the unevenness of the surface on which the film is formed. It has a specific shape and is arranged parallel to the surface or top surface of the CAAC-OS film to be formed.

[0147] On the other hand, a high-resolution TEM image of the CAAC-OS film plane was observed from a direction approximately perpendicular to the sample surface. This confirms that in the crystalline region, the metal atoms are arranged in a triangular or hexagonal shape. However, no regularity is observed in the arrangement of metal atoms between different crystalline regions.

[0148] X-ray diffraction (XRD) applied to the CAAC-OS film. When structural analysis is performed using this method, for example, a CAAC-OS film having InGaZnO4 crystals is found. In the out-of-plane analysis, the diffraction angle (2θ) shows a peak near 31°. This peak may appear. This peak is attributed to the (009) plane of the InGaZnO4 crystal. Therefore, the crystals of the CAAC-OS film have c-axis orientation, and the c-axis is approximately aligned with the surface to be formed or the upper surface. It can be confirmed that it is facing vertically.

[0149] Furthermore, the out-of-plane method for CAAC-OS films containing InGaZnO4 crystals. Analysis revealed that in addition to a peak near 2θ = 31°, a peak also appeared near 2θ = 36°. In some cases, this may occur. Peaks near 36° 2θ indicate c-axis orientation in a portion of the CAAC-OS film. This indicates that it contains crystals that do not have [the specified characteristic]. The CAAC-OS film has 2θ near 31°. It is preferable that a peak is observed, and that no peak is observed near 36° for 2θ.

[0150] CAAC-OS films are oxide semiconductor films with low impurity concentrations. The impurities include hydrogen, carbon, These are elements other than silicon and transition metal elements, which are the main components of oxide semiconductor films. In particular, silicon Elements such as ions, which have a stronger bonding force with oxygen than the metal elements that make up oxide semiconductor films, By removing oxygen from the material semiconductor film, the atomic arrangement of the oxide semiconductor film is disrupted, reducing its crystallinity. This is a contributing factor. Also, heavy metals such as iron and nickel, argon, and carbon dioxide have a certain atomic radius. Because of its large molecular radius, when it is contained within an oxide semiconductor film, the oxide semiconductor film This disrupts the atomic arrangement and reduces crystallinity. Furthermore, these impurities are present in oxide semiconductor films. Objects can sometimes act as carrier traps or carrier sources.

[0151] Furthermore, CAAC-OS films are oxide semiconductor films with a low defect level density. For example, oxide Oxygen vacancies in semiconductor films can act as carrier traps or capture hydrogen. It can be a source of carrier activity.

[0152] A low impurity concentration and low defect level density (few oxygen vacancies) is referred to as high-purity intrinsic or This is essentially called high-purity intrinsic. High-purity intrinsic or substantially high-purity intrinsic oxide semiconductor film Because there are fewer carrier sources, the carrier density can be kept low. Therefore, The transistor using this oxide semiconductor film exhibits an electrical characteristic in which the threshold voltage becomes negative. Also called normally-on.) It rarely becomes high-purity intrinsic or substantially high-purity. Highly intrinsic oxide semiconductor films have few carrier traps. Transistors using body membranes exhibit less variation in electrical characteristics and are highly reliable. Furthermore, the charge trapped in the carrier trap of the oxide semiconductor film requires time to be released. It can remain dormant for a long time, behaving almost like a fixed charge. Therefore, the impurity concentration Transistors using oxide semiconductor films with high defect level density have unstable electrical properties. This can happen.

[0153] Furthermore, transistors using CAAC-OS films exhibit electrical characteristics under irradiation with visible light and ultraviolet light. The fluctuations are small.

[0154] Next, we will explain microcrystalline oxide semiconductor films.

[0155] Microcrystalline oxide semiconductor films have areas where crystalline regions can be confirmed in high-resolution TEM images. It has regions where a clear crystalline structure cannot be observed, and regions where a clear crystalline structure cannot be identified. Microcrystalline oxide semiconductor film The crystalline portion contained therein is between 1 nm and 100 nm in size, or between 1 nm and 10 nm in size. This is often the case. In particular, the minute particles are between 1 nm and 10 nm, or between 1 nm and 3 nm. An oxide semiconductor film having nanocrystals (nc) which are crystalline, -OS(nanocrystalline oxide semiconductor) It is called a film. Furthermore, nc-OS films, for example, clearly show grain boundaries in high-resolution TEM images. There may be cases where it cannot be recognized.

[0156] nc-OS films are used in minute regions (for example, regions between 1 nm and 10 nm, especially regions larger than 1 nm). The atomic arrangement has periodicity in the region of 3 nm or less. Also, the nc-OS film is different No regularity in crystal orientation is observed between the crystalline regions. Therefore, no orientation is observed throughout the entire film. Therefore, depending on the analytical method, nc-OS films may be indistinguishable from amorphous oxide semiconductor films. There are cases where this is not possible. For example, when using X-rays with a diameter larger than that of the crystalline region on an nc-OS film, XR When structural analysis is performed using instrument D, the out-of-plane method shows that the crystal plane No peaks indicating this are detected. Also, for the nc-OS film, probes larger than the crystalline region are detected. Electron diffraction (also called limited-area electron diffraction) using an electron beam with a diameter (e.g., 50 nm or more) When this is done, a diffraction pattern resembling a halo pattern is observed. On the other hand, for nc-OS films... Nanobeam electron beams with a probe diameter close to or smaller than the size of the crystal region are used. When diffraction is performed, spots are observed. Furthermore, nanobeam electron diffraction is performed on nc-OS films. When this is done, a region of high brightness may be observed in a circular (ring-shaped) pattern. Also, When nanobeam electron diffraction is performed on an nc-OS film, multiple spots are observed within a ring-shaped region. It may be observed.

[0157] nc-OS films are oxide semiconductor films with higher orderliness than amorphous oxide semiconductor films. Therefore, nc-OS films have a lower defect level density than amorphous oxide semiconductor films. However, In nc-OS films, no regularity is observed in the crystal orientation between different crystalline regions. Therefore, nc-O The S film has a higher defect level density compared to the CAAC-OS film.

[0158] Next, we will explain amorphous oxide semiconductor films.

[0159] Amorphous oxide semiconductor films have an irregular atomic arrangement within the film and do not contain crystalline regions. These are physical semiconductor films. One example is an oxide semiconductor film that has an amorphous state, such as quartz.

[0160] In amorphous oxide semiconductor films, crystalline regions cannot be observed in high-resolution TEM images.

[0161] When structural analysis of amorphous oxide semiconductor films is performed using an XRD device, out-of-p Analysis using the Lane method did not detect any peaks indicating crystal planes. Furthermore, amorphous oxide semi-crystalline materials were found. When electron diffraction is performed on a conductive film, a halo pattern is observed. Furthermore, amorphous oxide semiconductors... When nanobeam electron diffraction is performed on a conductive film, no spots are observed, and a halo pattern is not seen. It is observed.

[0162] Furthermore, oxide semiconductor films exhibit physical properties between nc-OS films and amorphous oxide semiconductor films. It may have such a structure. Oxide semiconductor films having such a structure are particularly amorphous-like oxide Amorphous-like Oxide Semiconductor (OS) It is called a conductor film.

[0163] In a-like OS films, porosity (also called voids) is observed in high-resolution TEM images. In some cases, the crystalline portion can be clearly identified in high-resolution TEM images. It has regions and regions where the crystalline portion cannot be observed. The a-like OS film is Crystallization occurs and crystalline growth is observed even with minute electron irradiation, such as that seen by TEM. This can sometimes occur. On the other hand, with a high-quality nc-OS film, even trace amounts of electricity, such as those observed by TEM, are not detected. Crystallization due to subirradiation is hardly observed.

[0164] Furthermore, the size of the crystalline portion of a-like OS films and nc-OS films was measured using high-resolution T This can be done using EM imaging. For example, the crystal of InGaZnO4 has a layered structure, The unit cell of the InGaZnO4 crystal has two Ga-Zn-O layers between the In-O layers. It has three In-O layers and six Ga-Zn-O layers, for a total of nine layers arranged in the c-axis direction. It has a structure that is layered in a staggered manner. Therefore, the spacing between these adjacent layers is the (009) plane. It is approximately the same as the lattice plane spacing (also called the d-value), and its value, as determined by crystal structure analysis, is 0.29 nm. Therefore, we are focusing on the grid lines in high-resolution TEM images, and the spacing of the grid lines. In areas where the wavelength is between 0.28 nm and 0.30 nm, each lattice fringe is InG This corresponds to the ab-plane of the aZnO4 crystal.

[0165] Furthermore, oxide semiconductor films may have different densities depending on their structure. For example, a certain oxide semiconductor If the composition of the body membrane is known, then by comparing it with the density of a single crystal with the same composition, The structure of the oxide semiconductor film can be estimated. For example, with respect to the density of a single crystal, a- The density of the OS film is between 78.6% and 92.3%. Also, for example, single crystal Compared to the density of the nc-OS film and the CAAC-OS film, the density of the nc-OS film is 92.3% or higher. It will be less than 0%. Furthermore, an oxide semiconductor film with a density of less than 78% of the density of a single crystal is... The process of forming the film itself is difficult.

[0166] The above will be explained using a concrete example. For example, In:Ga:Zn=1:1:1[atom In an oxide semiconductor film satisfying the [number ratio], a single crystal InGaZnO4 having a rhombohedral structure. The density is 6.357 g / cm³ 3 Therefore, for example, In:Ga:Zn=1:1:1 In an oxide semiconductor film satisfying the [atomic ratio], the density of the a-like OS film is 5.0 g. / cm 3 More than 5.9g / cm 3 It becomes less than. Also, for example, In:Ga:Zn=1:1: In an oxide semiconductor film satisfying 1 [atomic ratio], the density of the nc-OS film and CAAC- The density of the OS film is 5.9 g / cm³. 3 More than 6.3g / cm 3 It will be less than.

[0167] Note that single crystals with the same composition may not exist. In that case, crystals with different compositions in arbitrary proportions may be found. By combining single crystals, it is possible to calculate the density corresponding to a single crystal with a desired composition. Yes, it is possible. The density of a single crystal of the desired composition depends on the ratio of single crystals with different compositions combined. The density can be calculated using a weighted average. However, the density should be calculated using as few types of single crystals as possible. It is preferable to calculate by combining the two factors.

[0168] Furthermore, oxide semiconductor films include, for example, amorphous oxide semiconductor films, a-like OS films, and microcrystalline films. The film may be a multilayer film having two or more types of crystalline oxide semiconductor films and CAAC-OS films.

[0169] By the way, even if the oxide semiconductor film is a CAAC-OS film, it may be partially an nc-OS film. Similar diffraction patterns may be observed in the CAAC-OS film. No indicates the percentage of the region where the diffraction pattern of the CAAC-OS film is observed within a certain range (C It can sometimes be expressed as (also called AAC conversion rate). For example, a good CAAC-OS For membranes, the CAAC conversion rate should be 50% or more, preferably 80% or more, and more preferably 9%. The diffraction pattern is 0% or more, more preferably 95% or more. The region in which the 'c' is observed is referred to as the non-CAAC rate.

[0170] Oxide semiconductor applicable to semiconductor layer 242a, semiconductor layer 242b, and semiconductor layer 108c One example of a body is an oxide containing indium. Oxides include, for example, The presence of iondium increases carrier mobility (electron mobility). Also, oxide semiconductors... It is preferable that it contains element M. Element M is preferably aluminum, gallium, or yttrium. This can be represented as mu or tin, etc. Other elements that can be applied to element M include boron, silicone, etc. Titanium, iron, nickel, germanium, yttrium, zirconium, molybdenum, Lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium There are such cases. However, in some cases, it is acceptable to combine multiple of the aforementioned elements as element M. Element M is, for example, an element with a high bond energy with oxygen. Element M is, for example, an acid It is an element that has the function of increasing the energy gap of oxides. Also, oxide semiconductors It is preferable that the oxide contains zinc. When the oxide contains zinc, for example, the oxide becomes easier to crystallize. .

[0171] However, oxide semiconductors are not limited to oxides containing indium. For example, zinc tin oxide, gallium tin oxide, or gallium oxide would also be acceptable.

[0172] Furthermore, oxide semiconductors use oxides with a large energy gap. The energy gap is, for example, between 2.5 eV and 4.2 eV, preferably 2.8 eV or more. The voltage should be 3.8 eV or less, and more preferably 3 eV to 3.5 eV.

[0173] The following section explains the effects of impurities in oxide semiconductors. To stabilize its electrical properties, the impurity concentration in the oxide semiconductor is reduced, and the carrier density is low. It is effective to improve the degree of oxidation and increase the purity. The carrier density of oxide semiconductors is 1 × 10 17 pieces / cm 3 Less than 1 × 10 15 pieces / cm 3 Less than, or 1 × 10⁻⁶ 13 pieces / cm 3 It shall be less than. In order to reduce the impurity concentration in oxide semiconductors, the impurity concentration in adjacent films shall be reduced. It is preferable to reduce the degree as well.

[0174] For example, silicon in oxide semiconductors can act as a carrier trap or carrier source. Yes. Therefore, the silicon concentration in oxide semiconductors is determined by secondary ion mass spectrometry (SIMS). In Secondary Ion Mass Spectrometry, 1×1 0 19 atoms / cm 3 Less than 5 × 10 18 atoms / cm 3 less than, further Preferably 2 × 10 18 atoms / cm 3 Less than.

[0175] Furthermore, the presence of hydrogen in oxide semiconductors can increase carrier density. The hydrogen concentration of oxide semiconductors is 2 × 10⁻⁶ in SIMS. 20 atoms / cm 3 below, Preferably 5 × 10 19 atoms / cm 3 More preferably 1 × 10 19 Atom s / cm 3 More preferably 5 × 10 18 atoms / cm 3 The following applies. Also, The presence of nitrogen in oxide semiconductors can increase carrier density. The nitrogen concentration of a semiconductor material is 5 × 10⁻⁶ in SIMS. 19 atoms / cm 3 Less than preferred Or 5x10 18 atoms / cm 3 More preferably 1 × 10 18 atom / cm 3 More preferably 5 × 10 17 atoms / cm 3 The following applies:

[0176] Furthermore, in order to reduce the hydrogen concentration of the oxide semiconductor, the insulating layer 109 in contact with the semiconductor layer 242 It is preferable to reduce the hydrogen concentration in the insulating layer 109 and insulating layer 117. The hydrogen concentration in SIMS is 2 × 10⁻⁶. 20 atoms / cm 3 The following is preferably 5× 10 19 atoms / cm 3 More preferably 1 × 10 19 atoms / cm 3 below More preferably 5 × 10 18 atoms / cm 3 The following applies. Also, oxide semiconductors To reduce nitrogen concentration, it is preferable to reduce the nitrogen concentration in insulating layer 109 and insulating layer 117. It seems that the nitrogen concentration in insulating layer 109 and insulating layer 117 is 5 × 10 in SIMS. 1 9 atoms / cm 3 Less than 5 × 10 18 atoms / cm 3 The following are more preferred Or 1 x 10 18 atoms / cm 3 More preferably 5 × 10 17 atoms / cm 3 The following applies:

[0177] In this embodiment, first, a semiconductor layer 242a is formed on the insulating layer 109, and the semiconductor layer 242 A semiconductor layer 242b is formed on a.

[0178] Furthermore, it is preferable to use the sputtering method for depositing the oxide semiconductor layer. Ring sputtering methods include RF sputtering, DC sputtering, and AC sputtering. Methods such as the following can be used. DC sputtering method or AC sputtering method, R This method allows for more uniform film deposition than the F sputtering method.

[0179] In this embodiment, the semiconductor layer 242a is an In-Ga-Zn oxide target (In Using Ga:Zn=1:3:2, a 20nm thick In-G layer was created by sputtering. α-Zn oxide is formed. The constituent elements and composition applicable to semiconductor layer 242a are as follows: This is not the only example.

[0180] Alternatively, oxygen doping may be performed after the formation of the semiconductor layer 242a.

[0181] Next, a semiconductor layer 242b is formed on the semiconductor layer 242a. In this embodiment, Layer 242b is an In-Ga-Zn oxide target (In:Ga:Zn=1:1:1 Using this method, a 30nm thick InGa-Zn oxide is formed by sputtering. Furthermore, the constituent elements and composition applicable to semiconductor layer 242b are not limited to those listed above. stomach.

[0182] Alternatively, oxygen doping may be performed after the formation of the semiconductor layer 242b.

[0183] Next, impurities such as water or hydrogen contained in semiconductor layer 242a and semiconductor layer 242b To further reduce and increase the purity of semiconductor layer 242a and semiconductor layer 242b, Heat treatment may be performed.

[0184] For example, under a reduced pressure atmosphere, under an inert atmosphere such as nitrogen or a noble gas, under an oxidizing atmosphere, or in an ultra-dry atmosphere. Dry air (measured using a CRDS (Cavity Ring-Down Laser Spectroscopy) type dew point meter) In that case, the moisture content is 20 ppm or less (dew point equivalent to -55°C), preferably 1 ppm or less. Preferably in an atmosphere of 10 ppb or less (air), semiconductor layer 242a and semiconductor layer 242 b is subjected to heat treatment. Note that an oxidizing atmosphere is an oxidizing atmosphere such as oxygen, ozone, or oxygen nitride. This refers to an atmosphere containing 10 ppm or more of an oxidizing gas. Furthermore, an inert atmosphere is defined as the aforementioned oxidizing atmosphere. This refers to an atmosphere where the gas concentration is less than 10 ppm, and which is also filled with nitrogen or a noble gas.

[0185] Furthermore, by performing heat treatment, impurities are released, and at the same time, oxygen contained in the insulating layer 109 is removed. The semiconductor layer 242a and semiconductor layer 242b are diffused, and the semiconductor layer 242a and semiconductor layer The oxygen deficiency of 242b can be reduced. The material is then heat-treated in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. It is also permissible to do so. Furthermore, the heat treatment may be performed at any time after the formation of the semiconductor layer 242b. For example, heat treatment may be performed after selective etching of the semiconductor layer 242b.

[0186] The heat treatment should be carried out at a temperature of 250°C to 650°C, preferably 300°C to 500°C. Good. The processing time should be within 24 hours. Heating for more than 24 hours will lead to a decrease in productivity. Therefore, it is undesirable.

[0187] Next, a resist mask is formed on the semiconductor layer 242b, and the resist mask is used to form a semiconductor A portion of the body layer 242a and the semiconductor layer 242b is selectively etched. At this time, the insulating layer In some cases, a portion of 109 may be etched, forming a protrusion on the insulating layer 109.

[0188] Etching of semiconductor layer 242a and semiconductor layer 242b can be done by dry etching or The etching method can be used, or both methods can be used. After etching is complete, remove the resist mask. Remove.

[0189] Furthermore, transistor 134 is located on semiconductor layer 242b, in contact with a portion of semiconductor layer 242b. , and electrodes 244 and 245 (the same layer as these). Other electrodes or wiring formed therein are formed of the same material and in the same manner as wiring 121. It is possible.

[0190] Furthermore, transistor 134 has a semiconductor layer 242b, electrode 244, and electrode 245. It has a conductive layer 242c. The semiconductor layer 242c is a semiconductor layer 242b, an electrode 244, and It makes contact with a portion of each electrode 245.

[0191] In this embodiment, the semiconductor layer 242c is made of an In-Ga-Zn oxide target (In:G The semiconductor layer 24 is formed by sputtering using a:Zn=1:3:2. The constituent elements and compositions applicable to 2c are not limited to these. For example, semiconductor layer Gallium oxide may be used as 242c. Alternatively, the semiconductor layer 242c may be oxygen-doped. You may do so.

[0192] Furthermore, transistor 241 has an insulating layer 117 on semiconductor layer 242c. Layer 7 can function as a gate insulating layer. Insulating layer 117 is similar to insulating layer 102. It can be formed by materials and methods. Furthermore, even if the insulating layer 117 is subjected to oxygen doping treatment... good.

[0193] After the formation of the semiconductor layer 242c and the insulating layer 117, a mask is formed on the insulating layer 117. A portion of the body layer 242c and the insulating layer 117 is selectively etched to form island-shaped semiconductor layers 24 2c and island-shaped insulating layers 117 may also be used.

[0194] Furthermore, transistor 134 has an electrode 243 on the insulating layer 117. Electrode 243 (this Other electrodes or wiring formed in the same layer as the wiring 121 are made of the same material as the wiring 121 and It can be formed by this method.

[0195] In this embodiment, an example is shown in which electrode 243 is a stack of electrode 243a and electrode 243b. For example, electrode 243a is formed from tantalum nitride and electrode 243b is formed from copper. 243a acts as a barrier layer, preventing the diffusion of copper elements. Therefore, reliability This enables the creation of high-performance semiconductor devices.

[0196] Furthermore, the transistor 241 has an insulating layer 118 covering the electrode 243. The insulating layer 118 is It can be formed using the same materials and methods as the insulating layer 102. In addition, acid can be applied to the insulating layer 118. Plain doping may be performed. Alternatively, CMP treatment may be performed on the surface of the insulating layer 118.

[0197] Furthermore, an insulating layer 119 is provided on the insulating layer 118. The insulating layer 119 is similar to the insulating layer 105. It can be formed by materials and methods. Alternatively, the surface of the insulating layer 119 can be subjected to CMP treatment. Alternatively, CMP treatment can be performed to reduce surface irregularities on the sample, and the insulation formed thereafter will be reduced. The covering properties of the layers and conductive layers can be improved. Also, the insulating layer 119 and the insulating layer 118 An opening is formed in the part. A contact plug is also formed in the opening.

[0198] Furthermore, wiring 127 and wiring 144 (formed in the same layer as these) are placed on top of the insulating layer 119. Other electrodes or wiring are formed. Wiring 144 is formed with insulating layer 119 and insulating layer An opening in 118 is electrically connected to electrode 273 via a contact plug. Furthermore, the wiring 127 is connected to the openings provided in the insulating layer 119 and the insulating layer 118. It is electrically connected to electrode 243 via a contact plug.

[0199] Furthermore, the imaging device 100 has wiring 127 and wiring 144 (and other wirings formed in the same layer as these). The electrodes or wiring (including) are covered by an insulating layer 115. The insulating layer 115 is an insulating layer 10 It can be formed using the same materials and methods as in 5. Furthermore, CMP treatment can be applied to the surface of the insulating layer 115. The following treatment may be performed. By performing CMP treatment, the surface irregularities of the sample are reduced, and the following formation This can improve the coverage of the insulating layer and conductive layer. In addition, openings can be made in a part of the insulating layer 115. It is formed.

[0200] Furthermore, on top of the insulating layer 115, there are wires 122, 123, and 266 (the same layer as these). (including other electrodes or wiring formed by) is formed.

[0201] Note that wiring 122, wiring 123, and wiring 266 (other electrodes formed in the same layer as these) (or including wiring) each has an opening and contact plug formed in the insulating layer Through this, it can be electrically connected to wiring or electrodes of other layers.

[0202] Furthermore, the wiring 122, wiring 123, and wiring 266 are covered by an insulating layer 116. Layer 116 can be formed using the same materials and methods as the insulating layer 105. 116 The surface may be treated with CMP.

[0203] As an example of a transistor that makes up the peripheral circuit, the transistor 281 shown in Figure 11 is expanded A large cross-sectional view is shown in Figure 14(A). Also shown is an enlarged cross-sectional view of transistor 282 shown in Figure 11. This is shown in Figure 14(B). In this embodiment, as an example, transistor 281 is p-channel When transistor 282 is an n-channel type transistor, I will explain.

[0204] Transistor 281 consists of an i-type semiconductor 283, a p-type semiconductor 285, and an insulating film. It has a marginal layer 286, an electrode 287, and a side wall 288. Also, the side wall 288 in the i-type semiconductor 283 The region overlapping with this has a low-concentration p-type impurity region 284.

[0205] The i-type semiconductor 283 in transistor 281 is the same i-type semiconductor in photoelectric conversion element 136. It can be formed simultaneously with body 222 in the same process. Also, transistor 281 has The p-type semiconductor 285 is produced simultaneously with the p-type semiconductor 221 of the photoelectric conversion element 136 in the same process. It can be formed.

[0206] The insulating layer 286 can function as a gate insulating layer. Also, the electrode 287 can function as a gate electrode. It is possible. The low-concentration p-type impurity region 284 is formed after the electrode 287 is formed and before the side wall 288 is formed. It can be formed by introducing impurity elements using electrode 287 as a mask. In other words, the low-concentration p-type impurity region 284 can be formed by a self-alignment method. Furthermore, the low-concentration p-type impurity region 284 has the same conductivity type as the p-type semiconductor 285, and the conductivity type is assigned. The concentration of impurities is lower than that of p-type semiconductor 285.

[0207] Transistor 282 has a similar configuration to transistor 281, but with a low concentration of p-type impurities. Instead of region 284 and p-type semiconductor 285, low-concentration n-type impurity region 294 and n-type semiconductor 295 They differ in that they possess the following characteristics.

[0208] Furthermore, the n-type semiconductor 295 in transistor 282 is the n-type semiconductor in photoelectric conversion element 136. It can be formed simultaneously with the semiconductor 223 in the same process. Also, transistor 281 and Similarly, the low-concentration n-type impurity region 294 can be formed by a self-alignment method. Oh, the low-concentration n-type impurity region 294 has the same conductivity type as the n-type semiconductor 295, thus conferring the conductivity type. The concentration of impurities is lower than that of n-type semiconductor 295.

[0209] Furthermore, the various films disclosed in this specification, such as metal films, semiconductor films, and inorganic insulating films, are produced by sputtering. It can be formed by the ring method or plasma CVD method, but other methods, such as thermal CVD, can also be used. It may also be formed by the D (Chemical Vapor Deposition) method. An example of a thermal CVD method is MOCVD (Metal Organic Chemical V). Apor Deposition (APOR Deposition) and ALD (Atomic Layer Deposition) You can also use the ition method.

[0210] Thermal CVD is a film deposition method that does not use plasma, so defects are generated by plasma damage. It has the advantage of not being affected.

[0211] In the thermal CVD method, the raw material gas and oxidizer are simultaneously introduced into the chamber, and the chamber pressure is reduced to atmospheric pressure. Alternatively, the film is formed by reacting the material near or on the substrate under reduced pressure, causing it to deposit on the substrate. That's fine.

[0212] Furthermore, the ALD method involves maintaining atmospheric pressure or reduced pressure inside the chamber, and sequentially supplying the raw material gases for the reaction. The gas can then be introduced into the chamber, and the film deposition process may be carried out by repeating this gas introduction sequence. For example, by switching between each switching valve (also called a high-speed valve), you can create two or more types. The raw material gases are supplied to the chamber in order, and the first raw material gas is supplied in order to prevent the mixing of multiple types of raw material gases. An inert gas (such as argon or nitrogen) is introduced simultaneously with or after the refrigerant gas, Introducing the raw material gas (2). Note that if an inert gas is introduced simultaneously, the inert gas should be... It becomes a carrier gas, and when introducing the second raw material gas, an inert gas may also be introduced at the same time. Also, instead of introducing an inert gas, the first raw material gas is discharged by vacuum evacuation. A second raw material gas may be introduced. The first raw material gas is adsorbed onto the surface of the substrate to form the first layer. The film is formed and reacts with a second raw material gas introduced later, so that the second layer is laminated on top of the first layer. A thin film is formed. This process is repeated multiple times while controlling the gas introduction sequence until the desired thickness is reached. By doing so, a thin film with excellent step coverage can be formed. The thickness of the thin film is determined by the order of gas introduction. Because it can be adjusted by the number of times the process is repeated, precise film thickness adjustment is possible. Suitable for fabricating thin FETs (Field Effect Transistors) It is.

[0213] Thermal CVD methods such as MOCVD and ALD are disclosed in the embodiments described above. It can form various films such as metal films, semiconductor films, and inorganic insulating films, for example, In-Ga When forming a -Zn-O film, trimethylindium, trimethylgallium, and Zn-O are used. Methylzinc is used. The chemical formula for trimethylindium is In(CH3)3. Furthermore, the chemical formula for trimethylgallium is Ga(CH3)3. Also, dimethylzinc... The chemical formula is Zn(CH3)2. Furthermore, it is not limited to these combinations, but also includes trim Triethylgallium (chemical formula Ga(C2H5)3) can also be used instead of tylgallium. It is also possible to use diethylzinc (chemical formula Zn(C2H5)2) instead of dimethylzinc. can.

[0214] For example, when forming a hafnium oxide film using a film deposition apparatus that utilizes ALD, the solvent and A liquid containing a hafnium precursor compound (hafnium alkoxide solution, typically tetrak The raw material gas is vaporized dimethylamide hafnium (TDMAH), and the oxidizing agent is O Two types of gases, O3, are used. Furthermore, the chemical reaction of tetrakisdimethylamidehafnium... The chemical formula is Hf[N(CH3)2]4. Other material liquids include tetrakis(eth Examples include methylamide (hafnium).

[0215] For example, when forming an aluminum oxide film using a film deposition apparatus that utilizes ALD, the solvent And a liquid containing an aluminum precursor compound (such as trimethylaluminum (TMA)) Two types of gases are used: a converted raw material gas and H2O as an oxidizing agent. The chemical formula for luminium is Al(CH3)3. Other materials include Tris(Di Methylamide) Aluminum, Triisobutylaluminum, Aluminum Tris(2, Examples include 2,6,6-tetramethyl-3,5-heptanedione).

[0216] For example, when forming a silicon oxide film using a film deposition apparatus that utilizes ALD, hexa Rolodisilane is adsorbed onto the film-forming surface, and chlorine contained in the adsorbed material is removed, causing an oxidizing gas (O2) A radical (nitrous oxide) is supplied and reacted with the adsorbed material.

[0217] For example, when depositing a tungsten film using a film deposition apparatus that utilizes ALD, WF6 gas The initial tungsten film is formed by sequentially introducing S and B2H6 gas, and then WF6 A tungsten film is formed by sequentially introducing gas and H2 gas. Note that B2H6 gas is also used. SiH4 gas may be used instead.

[0218] For example, oxide semiconductor films, such as In-Ga-Zn-O, can be deposited using an ALD (Advanced Laser Deposition) system. When forming a film, In(CH3)3 gas and O3 gas are introduced sequentially and repeatedly. An O layer is formed, and then Ga(CH3)3 gas and O3 gas are repeatedly introduced in sequence to form GaO A layer is formed, and then Zn(CH3)2 gas and O3 gas are repeatedly introduced sequentially to form ZnO Layers are formed. Note that the order of these layers is not limited to this example. Also, using these gases This forms mixed compound layers such as In-Ga-O layers, In-Zn-O layers, and Ga-Zn-O layers. It is also acceptable to use H3 gas instead of Ar by bubbling an inert gas such as Ar with water. While 2O gas may be used, it is preferable to use O3 gas that does not contain H. Also, In( In(C2H5)3 gas may be used instead of CH3)3 gas. Also, Ga(CH3 Ga(C2H5)3 gas may be used instead of )3 gas. Also, In(CH3)3 gas Alternatively, In(C2H5)3 gas may be used instead of Zn(CH3)2 gas. It's okay to be there.

[0219] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments. That is the case.

[0220] (Embodiment 3) Peripheral circuits and pixel circuits include OR circuits, AND circuits, NAND circuits, and NOR circuits, etc. Logic circuits, inverter circuits, buffer circuits, shift register circuits, flip-flop circuits Circuits, encoder circuits, decoder circuits, amplification circuits, analog switch circuits, integrating circuits, differential Circuits and memory elements can be provided as appropriate.

[0221] In this embodiment, Figures 15(A) to 15(E) are used to describe the peripheral circuit and the pixel circuit. An example of a CMOS circuit that can be used is shown in Figures 15(A) to 15(E). In the circuit diagram, to clearly indicate that it is a transistor using an oxide semiconductor, The circuit symbol for transistors using semiconductors is marked with "OS".

[0222] The CMOS circuit shown in Figure 15(A) consists of a p-channel type transistor 281 and an n-channel type Two transistors 282 are connected in series, and their gates are connected, resulting in what is known as an I This shows an example of a converter circuit configuration.

[0223] The CMOS circuit shown in Figure 15(B) consists of a p-channel type transistor 281 and an n-channel type This shows an example of a so-called analog switch circuit configuration in which transistor 282 is connected in parallel. It is.

[0224] The circuit shown in Figure 15(C) is the source or drain of an n-channel transistor 289. One end is connected to the gate of a p-channel transistor and one electrode of the capacitive element 257. The following shows an example of the configuration of a so-called memory element. Furthermore, the circuit shown in Figure 15(D) is... Either the source or drain of the n-channel transistor 289 is connected to the capacitive element 257. This shows an example configuration of a so-called memory element connected to one of the electrodes.

[0225] The circuits shown in Figures 15(C) and 15(D) have a source or drain for transistor 289. The charge input from the other side of the transistor can be held at node 256. By using an oxide semiconductor transistor in 289, node 25 can be used over a long period of time. It can hold a charge of 6. Also, transistor 281 forms a channel. A transistor using an oxide semiconductor for the semiconductor layer may also be used.

[0226] The circuit shown in Figure 15(E) illustrates an example of the configuration of a light sensor. In Figure 15(E), The source or One end of the drain is electrically connected to the photodiode 291, and the other end of the transistor 292 is connected to the photodiode 291. The other end of the drain or the other end of the drain is electrically connected to the gate of transistor 293 via node 254. It is connected to a transistor that uses an oxide semiconductor in the semiconductor layer where the channel is formed. 292 can make the off-current extremely small, so it is determined according to the amount of light received. The potential of node 254 is less likely to fluctuate. Therefore, an imaging device that is less susceptible to noise can be used. This can be achieved. Furthermore, it is possible to create an imaging device with high linearity.

[0227] Furthermore, the peripheral circuits include the shift register circuit 1800 and buffer circuit 19 shown in Figure 16(A). A circuit combining 00 may be provided. Additionally, a shift as shown in Figure 16(B) may be added to the peripheral circuitry. The register circuit 1810, buffer circuit 1910, and analog switch circuit 2100 are combined. A combined circuit may be provided. Each vertical output line 2110 is connected to an analog switch circuit 2100. This is selected, and the output signal is output to output line 2200. The analog switch circuit 2100 is The shift register circuit 1810 and the buffer circuit 1910 can be selected sequentially.

[0228] Furthermore, in the circuit diagram shown in the above embodiment, the wiring 137(OUT) is shown in Figure 17(A), An integrating circuit as shown in Figures 17(B) and 17(C) may be connected to the said circuit. Therefore, the signal-to-noise ratio of the readout signal can be increased, and weaker light can be detected. This means that the sensitivity of the imaging device can be increased.

[0229] Figure 17(A) shows an integration circuit using an operational amplifier (also called an op-amp). The inverting input terminal of the width circuit is connected to wiring 137 via a resistor R. The non-inverting input terminal is connected to ground potential. The output terminal of the operational amplifier circuit is connected via a capacitive element C. It is then connected to the inverting input terminal of the operational amplifier circuit.

[0230] Figure 17(B) shows an integral circuit using an operational amplifier circuit with a different configuration than that of Figure 17(A). The inverting input terminal of the operational amplifier circuit is connected via a resistor R and a capacitor C1 to wiring 137 (OUT The non-inverting input terminal of the operational amplifier circuit is connected to ground potential. The output terminal of the circuit is connected to the inverting input terminal of the operational amplifier circuit via the capacitive element C2.

[0231] Figure 17(C) uses an operational amplifier circuit with a different configuration than those in Figures 17(A) and 17(B). This is an integrating circuit. The non-inverting input terminal of the operational amplifier circuit is connected to wiring 137 via a resistor R. The inverting input terminal of the operational amplifier is connected to the inverting input terminal of the operational amplifier. Furthermore, the resistive element R and the capacitive element C constitute a CR integral circuit. Also, the operational amplifier circuit is... Configure a Nity Gain buffer.

[0232] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments. That is the case.

[0233] (Embodiment 4) In this embodiment, it can be used as a replacement for the transistor shown in the above embodiment. Examples of transistor configurations will be explained using Figures 18 to 22.

[0234] [Bottom-gate transistor] The transistor 410 shown in Figure 18(A1) is a type of bottom-gate transistor. It is a channel-protected transistor. Transistor 410 is on the insulating layer 109 It has an electrode 246 that can function as a gate electrode. Furthermore, an insulating layer 117 is provided on the electrode 246. It has a semiconductor layer 242 in between. The electrode 246 is formed using the same material and method as the wiring 121. It is possible.

[0235] Furthermore, transistor 410 has a channel protection layer on the channel formation region of semiconductor layer 242. It has an insulating layer 209 that can function as an insulating layer. The insulating layer 209 is made of the same material as the insulating layer 117. It can be formed by the method. Part of electrode 244 and part of electrode 249 are It is formed on the insulating layer 209.

[0236] By providing an insulating layer 209 on the channel formation region, electrodes 244 and 249 are formed. This prevents the exposure of the semiconductor layer 242 that sometimes occurs. Therefore, the electrodes 244 and 2 When forming 49, thinning of the semiconductor layer 242 can be prevented. According to one aspect of the present invention, This makes it possible to create transistors with good electrical characteristics.

[0237] The transistor 411 shown in Figure 18(A2) has a back gate electrode on the insulating layer 118. It differs from the transistor 410 in that it has a functional electrode 213. The electrode 213 is wired It can be formed using the same materials and methods as 121.

[0238] Generally, the back gate electrode is formed from a conductive layer, and the gate electrode and back gate electrode form a semiconductor. It is positioned so as to sandwich the channel formation region of the layer. Therefore, the back gate electrode is the gate electrode It can function similarly to a pole. The potential of the buck gate electrode is the same potential as the gate electrode. It may be set to GND potential or any other potential. Also, the potential of the buck gate electrode. By changing this independently of the gate electrode, the threshold voltage of the transistor can be changed. It can be transformed.

[0239] Both electrodes 246 and 213 can function as gate electrodes. The insulating layer 117, insulating layer 209, and insulating layer 118 function as gate insulating layers. It is possible.

[0240] Note that when one of the electrodes 246 or 213 is referred to as the "gate electrode," the other is referred to as the "battery electrode." It is sometimes called a "gate electrode." For example, in transistor 411, electrode 213 is When referring to a "gate electrode," electrode 246 is sometimes called a "back gate electrode." When electrode 213 is used as the "gate electrode", transistor 411 is the top gate. It can be considered a type of transistor. Also, electrodes 246 and 213 Sometimes one of them is called the "first gate electrode" and the other is called the "second gate electrode." be.

[0241] By providing electrodes 246 and 213 with the semiconductor layer 242 in between, further, electrode 24 By setting electrode 6 and electrode 213 to the same potential, the carrier flow region in semiconductor layer 242 As the region becomes larger in the film thickness direction, the amount of carrier movement increases. As a result, As the on-current of the transistor 411 increases, the field-effect mobility also increases.

[0242] Therefore, transistor 411 has a large on-current relative to its occupied area. It is a transistor. In other words, the area occupied by transistor 411 is relative to the required on-current. It can be made smaller. According to one aspect of the present invention, the area occupied by the transistor can be reduced. Therefore, according to one aspect of the present invention, a semiconductor device with a high degree of integration can be realized. It is possible.

[0243] Furthermore, since the gate electrode and back gate electrode are formed of conductive layers, outside the transistor... Function to prevent the generated electric field from acting on the semiconductor layer in which the channel is formed (especially static electricity) It has an electric field shielding function against such things. By forming this structure and covering the semiconductor layer with a back gate electrode, the electric field shielding function can be enhanced. .

[0244] Furthermore, electrodes 246 and 213 each have the function of shielding against external electric fields. Therefore, the charge of charged particles etc. that are generated on the insulating layer 109 side or above the electrode 213 is transferred to the semiconductor layer 2 It does not affect the 42 channel formation regions. As a result, stress tests (e.g., negative gate) Applying an electric charge - GBT (Gate Bias-Temperature) stress test The degradation of ) is suppressed, and the rise voltage of the on-current at different drain voltages is also reduced. This can suppress fluctuations. This effect is due to the fact that electrodes 246 and 213 are the same It occurs at different potentials or in different positions.

[0245] Note that the BT stress test is a type of accelerated stress test, and it tests the transient effects that occur due to long-term use. Changes in the characteristics of the sta (i.e., changes over time) can be evaluated in a short time. In particular, BT The amount of variation in the transistor's threshold voltage before and after stress testing is used to investigate reliability. This is an important indicator. The smaller the fluctuation in threshold voltage before and after the BT stress test, the better. It can be said that it is a highly reliable transistor.

[0246] Furthermore, it has electrodes 246 and 213, and electrodes 246 and 213 are at the same potential. This reduces the fluctuation in the threshold voltage. Therefore, in multiple transistors... The variation in electrical characteristics is also reduced at the same time.

[0247] Furthermore, a transistor with a back gate electrode is a +GBT transistor where a positive charge is applied to the gate. The threshold voltage fluctuations before and after stress testing are also observed in transients without back gate electrodes. It's smaller than a star.

[0248] Furthermore, when light is incident from the back gate electrode side, the back gate electrode has light-shielding properties. By forming it with a conductive film, it prevents light from entering the semiconductor layer from the back gate electrode side. This prevents photodegradation of the semiconductor layer and shifts the threshold voltage of the transistor. This prevents deterioration of electrical properties, such as those mentioned above.

[0249] According to one aspect of the present invention, a transistor with good reliability can be realized. Furthermore, This enables the creation of highly reliable semiconductor devices.

[0250] The transistor 420 shown in Figure 18(B1) is a type of bottom-gate transistor. It is a channel-protected transistor. Transistor 420 is a channel-protected transistor. It has a structure almost identical to 0, but differs in that the insulating layer 209 covers the semiconductor layer 242. In addition, an opening is formed by selectively removing a portion of the insulating layer 209 that overlaps with the semiconductor layer 242. At the opening, the semiconductor layer 242 and the electrode 244 are electrically connected. In the opening formed by selectively removing a portion of the insulating layer 209 that overlaps with 42, the semiconductor layer 242 and electrode 249 are electrically connected. The insulating layer 209 overlaps with the channel formation region. This region can function as a channel protection layer.

[0251] The transistor 421 shown in Figure 18(B2) has a back gate electrode on the insulating layer 118. It differs from the transistor 420 in that it has a functional electrode 213.

[0252] By providing the insulating layer 209, the semiconductor layer 2 generated during the formation of electrodes 244 and 249 Exposure of 42 can be prevented. Therefore, when forming electrodes 244 and 249, the semiconductor This prevents the thinning of layer 242.

[0253] Furthermore, transistors 420 and 421 are transistors 410 and 421. The distance between electrode 244 and electrode 246, and between electrode 249 and electrode 246, is greater than that of the radiator 411. The distance between them increases. Therefore, the parasitic capacitance between electrode 244 and electrode 246 is reduced. This can be done. Furthermore, it can reduce the parasitic capacitance that occurs between electrode 249 and electrode 246. This is possible. According to one aspect of the present invention, a transistor with good electrical characteristics can be realized.

[0254] [Top-gate transistor] The transistor 430 shown in Figure 19(A1) is a type of top-gate transistor. The transistor 430 has a semiconductor layer 242 on top of an insulating layer 109, and semiconductor layer 2 42 and an electrode 244 in contact with a part of the semiconductor layer 242 and on the insulating layer 109 and semiconductor layer It has an electrode 249 that is in contact with a part of 242, and the semiconductor layer 242, electrode 244, and electrode 24 The 9 has an insulating layer 117, and the insulating layer 117 has an electrode 246.

[0255] Transistor 430 has electrodes 246 and 244, and electrodes 246 and 2 Because 49 does not overlap, parasitic capacitance occurs between electrode 246 and electrode 244, and the electrode The parasitic capacitance between electrode 246 and electrode 249 can be reduced. Also, electrode 24 After forming 6, the impurity element 255 is removed from the semiconductor layer 242 using electrode 246 as a mask. By introducing it, impurity regions are self-aligned within semiconductor layer 242. This can be formed (see Figure 19(A3)). According to one aspect of the present invention, the electrical characteristics This allows for the creation of high-quality transistors.

[0256] Furthermore, the introduction of impurity element 255 is performed using an ion implanter, ion doping device, or plasma This can be done using a processing unit.

[0257] As impurity element 255, for example, at least one of the elements from Group 13 or Group 15 is included. Another type of element can be used. Also, when an oxide semiconductor is used for the semiconductor layer 242 The mixture contains at least one of the following impurity elements: noble gases, hydrogen, and nitrogen. It is also possible to use elements.

[0258] The transistor 431 shown in Figure 19(A2) has an electrode 213 and an insulating layer 217. This is different from transistor 430. Transistor 431 is formed on the insulating layer 109 It has an electrode 213 and an insulating layer 217 formed on the electrode 213. As mentioned above, Electrode 213 can function as a back gate electrode. Therefore, the insulating layer 217 is It can function as a gate insulating layer. The insulating layer 217 is made of the same material as the insulating layer 205. It can be formed by the and methods.

[0259] Similar to transistor 411, transistor 431 has a large on-current relative to its occupied area. This is a transistor having the following characteristics: That is, for the required on-current, transistor 4 The occupied area of ​​31 can be reduced. According to one aspect of the present invention, the occupancy area of ​​the transistor The surface area can be reduced. Therefore, according to one aspect of the present invention, a semiconductor with a high degree of integration A physical device can be realized.

[0260] The transistor 440 shown in Figure 19(B1) is a top-gate type transistor. The transistor 440 has electrodes 244 and 249 formed on a semiconductor layer 2 The point where 42 is formed differs from transistor 430. Also, the example shown in Figure 19(B2) The transistor 441 has electrodes 213 and an insulating layer 217, which is the same as transistor 440. This differs from the above. In transistors 440 and 441, one of the semiconductor layers 242 The portion is formed on electrode 244, and the other portion of the semiconductor layer 242 is formed on electrode 249.

[0261] Similar to transistor 411, transistor 441 has a large on-current relative to its occupied area. This is a transistor having the following characteristics: That is, for the required on-current, transistor 4 The occupied area of ​​41 can be reduced. According to one aspect of the present invention, the occupancy area of ​​the transistor The surface area can be reduced. Therefore, according to one aspect of the present invention, a semiconductor with a high degree of integration A physical device can be realized.

[0262] Transistors 440 and 441 also form electrodes 246 after the electrode 24 By using 6 as a mask to introduce impurity element 255 into semiconductor layer 242, the semiconductor layer A self-aligned impurity region can be formed in 242. According to one aspect of the present invention, A transistor with good electrical characteristics can be realized. Furthermore, according to one aspect of the present invention This enables the realization of highly integrated semiconductor devices.

[0263] [S-channel transistor] The transistor 450 illustrated in Figure 20 has the top and side surfaces of semiconductor layer 242b as semiconductor layer 2 It has a structure covered with 42c. Figure 20(A) is a top view of transistor 450. 20(B) is a cross-sectional view of the area indicated by the dashed line X1-X2 in Figure 20(A) (channel This is a cross-sectional view in the longitudinal direction. Figure 20(C) is shown by the dashed line Y1-Y2 in Figure 20(A). This is a cross-sectional view of the area (cross-sectional view in the channel width direction).

[0264] By providing a semiconductor layer 242b on a protrusion provided on the insulating layer 109, the semiconductor layer 242 The side of b can be completely covered with electrode 243. That is, transistor 450 is electric The structure has the ability to electrically surround the semiconductor layer 242b with the electric field of pole 243. In this way, the electric field of the conductive film electrically... The structure of the surrounding transistors is called a surrounded channel (S-Chan). It is called a nel structure. Also, a transistor having an s-channel structure is called a sc It is also called a "channel transistor" or "S-channel transistor".

[0265] In the s-channel structure, channels are formed throughout the entire (bulk) semiconductor layer 242b. In some cases, this occurs. In an s-channel structure, the drain current of the transistor is increased. This allows for obtaining an even larger on-current. Also, the electric field of electrode 243 This allows for the depletion of the entire channel formation region formed in the semiconductor layer 242b. Therefore, in an s-channel structure, the off-current of the transistor can be further reduced. It is possible.

[0266] Furthermore, by increasing the height of the protrusions of the insulating layer 109 and reducing the channel width, s-cha The nnel structure can further enhance the effects of increasing on-current and reducing off-current. It is possible to remove the exposed semiconductor layer 242a when forming the semiconductor layer 242b. In this case, the sides of semiconductor layer 242a and semiconductor layer 242b may be aligned.

[0267] Furthermore, as shown in Figure 21, transistor 451 has an insulating layer below the semiconductor layer 242. Electrode 213 may be provided. Figure 21(A) is a top view of transistor 451. Figure 21(B) is a cross-sectional view of the area indicated by the dashed line X1-X2 in Figure 21(A). Figure 21(C) is a cross-sectional view of the area indicated by the dashed line Y1-Y2 in Figure 21(A).

[0268] Furthermore, as shown in Figure 22, a layer 214 is provided above the electrode 243, as in the transistor 452. This is also fine. Figure 22(A) is a top view of transistor 452. Figure 22(B) is Figure 22( A) This is a cross-sectional view of the area indicated by the dashed line between X1 and X2. Figure 22(C) is a cross-sectional view of Figure 22( A) This is a cross-sectional view of the area indicated by the dashed line between Y1 and Y2.

[0269] In Figure 22, layer 214 is provided on the insulating layer 119, but it may also be provided on the insulating layer 118. By forming layer 214 with a light-shielding material, the characteristics of the transistor under light irradiation are controlled. This prevents fluctuations and a decrease in reliability. Furthermore, layer 214 is at least semiconductor layer 2 By forming it larger than 42b and covering the semiconductor layer 242b with layer 214, the above effect is enhanced. It can be made using organic materials, inorganic materials, or metallic materials. This is possible. Also, if layer 214 is made of a conductive material, a voltage can be supplied to layer 214. Alternatively, it may be in an electrically floating state.

[0270] Furthermore, the capacitive element 135 shown in the above embodiment causes the transistor 134 to be in the OFF state. Electrode 245 becomes floating, and is less susceptible to ambient potential fluctuations such as noise. The amount decreases. In other words, when transistor 134 is in the off state, the surrounding electric field such as noise decreases. Due to this influence, the potential of electrode 245, which can function as node 152, may fluctuate.

[0271] As shown in the cross-sectional view of Figure 23, electrode 212 is provided below electrode 245 via an insulating layer. This makes it possible to suppress potential fluctuations in electrode 245, which can function as node 152. The electrode 212 can be formed using the same materials and methods as the wiring 121.

[0272] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments. That is the case.

[0273] (Embodiment 5) This embodiment describes an example of an electronic device using an imaging device according to one aspect of the present invention. do.

[0274] An electronic device using an imaging device according to one aspect of the present invention includes a display device such as a television or monitor. Lighting fixtures, desktop or notebook personal computers, word processors It is stored on recording media such as DVDs (Digital Versatile Discs). Image playback devices that play still images or videos, portable CD players, radios, tape recorders Coda, headphone stereo, stereo, navigation system, desk clock, wall clock Totals, cordless phone handsets, transceivers, mobile phones, car phones, portable game consoles, tablets Let-type terminals, large game machines such as pachinko machines, calculators, personal digital assistants, electronic organizers, and e-books. Registration, electronic translators, voice input devices, video cameras, digital still cameras, electric shavers, High-frequency heating devices such as microwave ovens, electric rice cookers, electric washing machines, electric vacuum cleaners, water heaters, electric fans Hair dryers, air conditioners, humidifiers, dehumidifiers and other air conditioning equipment, dishwashers, food Dryer, clothes dryer, futon dryer, electric refrigerator, electric freezer, electric refrigerator-freezer, DNA Storage freezers, flashlights, tools such as chainsaws, smoke detectors, medical equipment such as dialysis machines, F Fax machines, printers, multifunction printers, automated teller machines (ATMs), vending machines Examples include machinery, etc. Furthermore, guide lights, traffic lights, conveyor belts, elevators, escalators Data, industrial robots, power storage systems, power leveling and storage for smart grids Industrial equipment such as electrical devices are examples. Also, fuel-powered engines and non-aqueous secondary batteries Mobile devices propelled by electric motors using electricity are also included in the category of electronic equipment. Examples of the above-mentioned mobile devices include electric vehicles (EVs) and vehicles that combine internal combustion engines and electric motors. Hybrid vehicles (HEV), plug-in hybrid vehicles (PHEV), and their tires and wheels Tracked vehicles that have been converted to tracks, motorized bicycles including electric assist bicycles, motorcycles, Electric wheelchairs, golf carts, small or large vessels, submarines, helicopters, aircraft, location Examples include spacecraft, artificial satellites, space probes and planetary probes, and spaceships.

[0275] Figure 24(A) shows a video camera, comprising a first housing 941, a second housing 942, a display unit 943, It has an operation key 944, a lens 945, a connecting part 946, etc. Operation key 944 and lens 945 is provided in the first housing 941, and the display unit 943 is provided in the second housing 942. And the first housing 941 and the second housing 942 are connected by a connecting part 946. The angle between the first housing 941 and the second housing 942 can be changed by the connecting part 946. The video on the display unit 943 is connected to the first housing 941 and the second housing 94 in the connection unit 946. It may also be configured to switch according to the angle between 2 and 3. The present invention may include an imaging device according to one embodiment of the present invention.

[0276] Figure 24(B) is a mobile phone, and the housing 951 contains a display unit 952, a microphone 957, and a speaker. It has -954, camera 959, input / output terminal 956, operation buttons 955, etc. Camera An imaging device according to one aspect of the present invention can be used for 959.

[0277] Figure 24(C) shows a digital camera, consisting of a housing 921, a shutter button 922, and a microphone 9 23. It has a light-emitting part 927, a lens 925, etc. The light-emitting part is located at the focal point of the lens 925. An imaging device of one aspect can be provided.

[0278] Figure 24(D) shows a portable game console, consisting of a casing 901, casing 902, display unit 903, and display unit. 904, Microphone 905, Speaker 906, Control keys 907, Stylus 908, Camera It has 909, etc. Note that the portable game console shown in Figure 23(A) has two display units 903 It has a display unit 904, but the number of display units that a portable game console has is not limited to this. It is not possible. Camera 909 can use an imaging device according to one aspect of the present invention.

[0279] Figure 24(E) shows a wristwatch-type information terminal, comprising a housing 931, a display unit 932, and a wristband 9 33. It has a camera 939, etc. The display unit 932 may be a touch panel. An imaging device according to one embodiment of the present invention can be used in the Ra909.

[0280] Figure 24(F) shows a portable data terminal, which includes a first housing 911, a display unit 912, a camera 919, etc. It has a touch panel function on the display unit 912, which allows for information input and output. The camera 909 can use an imaging device according to one embodiment of the present invention.

[0281] Furthermore, the present invention is not limited to the electronic devices described above, as long as it includes an imaging device according to one embodiment of the present invention. Needless to say, that's not possible.

[0282] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments. That is the case. [Explanation of symbols]

[0283] 100 Imaging device 101 circuit board 102 Insulating layer 103 Insulating layer 104 Insulating layer 105 Insulating layer 106 Contact Plug 107 Insulating layer 108 Insulating layer 109 Insulating layer 110 pixel section 111 pixels 112 Pixel Driving Circuit 113 pixels 115 Insulating layer 116 Insulating layer 117 Insulating layer 118 Insulating layer 119 Insulating layer 121 Wiring 122 Wiring 123 Wiring 124 Wiring 125 Wiring 126 Wiring 127 Wiring 128 Wiring 129 Wiring 131 transistors 132 transistors 133 transistors 134 transistors 135 Capacitive element 136 Photoelectric conversion element 137 Wiring 141 Wiring 142 Wiring 143 Wiring 144 Wiring 145 Wiring 151 nodes 152 nodes 177 Insulating layer 205 Insulating layer 209 Insulating layer 212 Electrode 213 Electrode 214 layers 217 Insulating layer 221 p-type semiconductor 222 i-type semiconductor 223 n-type semiconductor 224 Aperture 225 Aperture 241 transistors 242 Semiconductor layer 243 Electrode 244 electrode 245 Electrode 246 Electrode 249 Electrode 251 pixel area 252 Peripheral circuit area 254 nodes 255 Impurity Elements 256 nodes 257 Capacitive elements 260 circuits 261 Signal Processing Circuit 262-row drive circuit 263 Output Circuit 264 circuits 266 Wiring 267 Wiring 268 Wiring 269 ​​Wiring 270 circuits 273 Electrode 277 Insulating layer 280 circuits 281 transistors 282 transistors 283 i-type semiconductor 284 Low concentration p-type impurity region 285 p-type semiconductor 286 Insulating layer 287 Electrode 288 Side wall 289 transistors 290 circuits 291 Photodiode 292 transistors 293 Transistors 294 Low concentration n-type impurity region 295 n-type semiconductor 382 Ec 386 Ec 390 Trap Level 410 transistors 411 transistors 420 transistors 421 Transistors 430 transistors 431 transistors 440 transistors 441 transistors 450 transistors 451 transistors 452 transistors 600 lens 602 Filter 604 Wiring layer 660 light 901 cabinet 902 cabinet 903 Display section 904 Display section 905 Microphone 906 Speakers 907 Operation Keys 908 Stylus 909 Camera 911 cabinet 912 Display section 919 Camera 921 cabinet 922 Shutter button 923 Mike 925 lens 927 Light-emitting part 931 cabinet 932 Display section 933 Wristband 939 Camera 941 cabinet 942 cabinets 943 Display section 944 Operation Keys 945 lens 946 Connection part 951 cabinet 952 Display section 954 Speakers 955 Buttons 956 Input / output terminal 957 Mike 959 Camera 1800 Shift Register Circuit 1810 Shift Register Circuit 1900 Buffer Circuit 1910 Buffer Circuit 2100 Analog Switch Circuit 2110 Vertical output line 2200 output line 10⁸c semiconductor layer 111B pixels 111G pixels 111R pixels 242a Semiconductor layer 242b Semiconductor layer 242c semiconductor layer 243a electrode 243b Electrode 264a Comparator 264b Counter circuit 272c semiconductor layer 383a Ec 383b Ec 383c Ec 602B filter 602G filter 602R filter

Claims

1. A mesh-like wiring layer having multiple openings, A conductive layer is electrically connected to the wiring layer via a contact plug and functions as one of the capacitive electrodes, A photodiode into which light is incident, through a microlens array, a color filter, and one of the multiple apertures, A transfer transistor in which either the source or drain is electrically connected to the photodiode, An amplifying transistor whose gate is electrically connected to the other of the source or drain of the transfer transistor, A readout transistor in which either the source or drain is electrically connected to either the source or drain of the amplification transistor, An imaging apparatus having a reset transistor whose source or drain is electrically connected to the gate of the amplification transistor, The first wiring, electrically connected to the source or drain of the amplification transistor, has a first region extending in a first direction. The first region has a portion of the mesh wiring layer that corresponds to one of the sides of the opening along the first direction and a region that overlaps along the first direction. The second wiring, electrically connected to the other of the source or drain of the reset transistor, has a second region extending in the first direction. The second region has a portion of the mesh wiring layer that corresponds to the other side of the first opening along the first direction and a region that overlaps along the first direction. A third wire is provided which is electrically connected to the other of the source or drain of the readout transistor. A first gate wire is provided which is electrically connected to the gate of the transfer transistor. A second gate wire is provided which is electrically connected to the gate of the reset transistor. A third gate wire is provided which is electrically connected to the gate of the readout transistor. An insulating layer is provided in contact with the first gate wire, the second gate wire, and the third gate wire. The imaging device is provided with the first wiring, the second wiring, and the third wiring in contact with the insulating layer.

2. A mesh-like wiring layer having multiple openings, A conductive layer is electrically connected to the wiring layer via a contact plug and functions as one of the capacitive electrodes, A photodiode into which light is incident, through a microlens array, a color filter, and one of the multiple apertures, A transfer transistor in which either the source or drain is electrically connected to the photodiode, An amplifying transistor whose gate is electrically connected to the other of the source or drain of the transfer transistor, A readout transistor in which either the source or drain is electrically connected to either the source or drain of the amplification transistor, An imaging apparatus having a reset transistor whose source or drain is electrically connected to the gate of the amplification transistor, The first wiring, electrically connected to the source or drain of the amplification transistor, has a first region extending in a first direction. The first region has a portion of the mesh wiring layer that corresponds to one of the sides of the opening along the first direction and a region that overlaps along the first direction. The second wiring, electrically connected to the other of the source or drain of the reset transistor, has a second region extending in the first direction. The second region has a portion of the mesh wiring layer that corresponds to the other side of the first opening along the first direction and a region that overlaps along the first direction. A third wire is provided which is electrically connected to the other of the source or drain of the readout transistor. The third wiring has a region extending in the first direction, The third wiring has a region that overlaps with the mesh wiring layer, A first gate wire is provided which is electrically connected to the gate of the transfer transistor. A second gate wire is provided which is electrically connected to the gate of the reset transistor. A third gate wire is provided which is electrically connected to the gate of the readout transistor. An insulating layer is provided in contact with the first gate wire, the second gate wire, and the third gate wire. The imaging device is provided with the first wiring, the second wiring, and the third wiring in contact with the insulating layer.

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