Hardware accelerator for lookup table-based general matrix operations

The hardware accelerator addresses inefficiencies in generative language models by using a lookup table-based approach for matrix operations, enhancing efficiency and reducing resource requirements.

JP7884110B1Active Publication Date: 2026-07-02NAVER CLOUD CORP +1

Patent Information

Authority / Receiving Office
JP · JP
Patent Type
Patents
Current Assignee / Owner
NAVER CLOUD CORP
Filing Date
2025-04-01
Publication Date
2026-07-02

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Abstract

This provides a hardware accelerator for lookup table-based general matrix operations. [Solution] The hardware accelerator 100 includes a weight buffer that stores a weight matrix in which the weights of the target model have been quantized, an input buffer that stores an input matrix including floating-point-based input activation values ​​for the target model, and a matrix processing unit 130 that performs matrix operations between the weight matrix and the input matrix. The matrix processing unit includes a lookup table generator that calculates each calculation result value corresponding to all possible cases between the quantum weights and input activation values ​​that can occur during matrix operations and generates a lookup table containing the calculation result values, and a plurality of processing elements that extract calculation result values ​​corresponding to the quantum weights from the lookup table during matrix operations and generate a partial sum.
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