Semiconductor equipment

Abstract

To provide a semiconductor device in which the influence of variation in threshold voltage of a transistor is relieved to make it accurate and easy to distinguish a plurality of states, and a manufacturing method and a driving method for the semiconductor device.SOLUTION: A semiconductor device includes a source line SL, a bit line BL, a word line WL, a memory cell 200 connected to the bit line and the word line, a driving circuit for a plurality of second signal lines S2 and the word lines that drives the second signal lines and the word lines so as to select a memory cell designated by an input address signal, a writing circuit that outputs a writing potential to a first signal line S1, a readout circuit that compares a potential of the bit line input from the bit line connected to the designated memory cell and a plurality of readout potentials, a control circuit that selects any of a plurality of correction voltages on the basis of the result of comparing the potential of the bit line and the readout potentials, and a potential generation circuit that generates a writing potential and a plurality of readout potentials and supplies the potentials to the writing circuit and the readout circuit.SELECTED DRAWING: Figure 14

Description

[Technical Field]

[0001] The disclosed invention relates to a semiconductor device utilizing a semiconductor element, a method for manufacturing the same, and a method for driving the same. It concerns this matter. [Background technology]

[0002] Memory devices using semiconductor elements are volatile memory devices, meaning that the stored data is lost when the power supply is cut off. They are broadly classified into two types: memory devices and non-volatile memory devices that retain their contents even when the power supply is cut off. It can be done.

[0003] A typical example of a volatile memory device is DRAM (Dynamic Random Access Memory). DRAM has a memory (cess memory). DRAM selects transistors that make up the memory elements. By accumulating electric charge in the capacitor, it stores information.

[0004] Based on the principle described above, in DRAM, when information is read, the charge in the capacitor is lost. Therefore, a write operation is required each time data is read. Also, the memory element The transistors that make up the circuit have leakage current, and when no transistor is selected... Because charge flows out or into, the data retention period is short. Therefore, at a predetermined interval A rewrite operation (refresh operation) is required, and power consumption must be kept sufficiently low. This is difficult. Also, if the power supply is cut off, the contents of the memory will be lost, so long-term memory For retention, another storage device utilizing magnetic or optical materials would be required.

[0005] Another example of volatile memory is SRAM (Static Random Access Memory). SRAM has memory. SRAM uses circuits such as flip-flops to store information. For retention, a refresh operation is not required, which is advantageous over DRAM in this regard. However, since circuits such as flip-flops are used, there is a problem that the unit price per storage capacity becomes high. Also, in terms of the fact that the stored content is lost when the power supply is cut off, there is no difference from DRAM.

[0006] A typical example of a non-volatile memory device is a flash memory. The flash memory has a floating gate between the gate electrode and the channel formation region of a transistor, and stores data by holding charges in the floating gate. Therefore, the data retention period is extremely long (semi-permanent), and it has the advantage that the refresh operation required for volatile memory devices is unnecessary (for example, see Patent Document 1).

[0007] However, since the gate insulating layer constituting the memory element deteriorates due to the tunneling current generated during writing, there is a problem that the memory element stops functioning after a predetermined number of writes. To mitigate the influence of this problem, for example, a technique for equalizing the number of writes of each memory element is adopted. However, to realize this, complex peripheral circuits are required. Therefore, even if such a technique is adopted, the fundamental lifetime problem is not solved. That is, flash memory is not suitable for applications where the information rewrite frequency is high.

[0008] Also, to hold charges in the floating gate or to remove the charges, a high voltage is required. Furthermore, it takes a relatively long time to hold or remove charges, and there is also a problem that it is not easy to speed up writing and erasing.

[0009] Furthermore, in a so-called multi-value memory in which a plurality of states are held in a single memory element, a complex circuit is required to ensure the accuracy of writing, and there is also a problem that the operating speed decreases due to this. Furthermore, in a so-called multi-value memory in which a plurality of states are held in a single memory element, a complex circuit is required to ensure the accuracy of writing, and there is also a problem that the operating speed decreases due to this. There is also such a problem.

Prior Art Documents

Patent Documents

[0010]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0011] In view of the above problems, in one aspect of the disclosed invention, a semiconductor device with a new structure is provided that can hold memory contents even in a situation where no power is supplied and has no limitation on the number of write operations. In view of the above problems, in one aspect of the disclosed invention, a semiconductor device with a new structure is provided that can hold memory contents even in a situation where no power is supplied and has no limitation on the number of write operations. This is one of the objectives.

[0012] Or, one of the objectives is to provide a semiconductor device that reduces the influence of variations in the threshold voltage of transistors and accurately and easily distinguishes between a plurality of states (for example, three or more states). [[ID=​​​​​​​​​​​​​​​​​​​​

[0015] For example, the following configuration can be adopted.

[0016] One aspect of the present invention comprises a source line, a bit line, a word line, and a connection between the bit line and the word line. The system selects the memory cell specified by the input address signal. The second signal line and word line drive multiple second signal lines and multiple word lines. A drive circuit, a writing circuit that outputs the write potential to the first signal line, and a specified memory The potential of the bit line input from the bit line connected to the cell is compared with the potentials of multiple readouts. The readout circuit being compared, and based on the comparison results of the bit line potential and multiple readout potentials, A control circuit that selects one of the correction voltages, and generates a write potential and multiple read potentials. A semiconductor having a potential generation circuit that supplies power to a writing circuit and a reading circuit. It is a device.

[0017] Another aspect of the present invention includes a source line, a bit line, a word line, and a line tangent to the bit line and the word line. Select the connected memory cell and the memory cell specified by the input address signal. To that end, the second signal line and word line drive multiple second signal lines and multiple word lines. The line drive circuit and, in the first writing operation, output the first writing potential to the first signal line. Furthermore, in the second write operation, one of the multiple second write potentials is set to the first signal line. The output write circuit and, in the first read operation, connected to the specified memory cell The potential of the first bit line input from the bit line is compared with the potentials of multiple first readouts. In contrast, in the second read operation, input from the bit line connected to the specified memory cell. The potential of the second bit line being powered is compared with multiple second read potentials to determine the memory cell. A readout circuit that reads out the data, the potential of the first bit line, and multiple first readouts Based on the comparison of potentials, select one of several correction voltages and then select one of several second writing voltages. A control circuit that selects one of the positions, a first write potential, and multiple second write potentials, Multiple first read potentials and multiple second read potentials are generated, and the writing circuit This is a semiconductor device having a potential generation circuit that supplies power to a reading circuit.

[0018] Another aspect of the present invention includes a source line, a bit line, a first signal line, and a plurality of second signal lines. Multiple word lines, and multiple memory cells connected in parallel between the source line and the bit line. Multiple second memory cells are selected to select a memory cell specified by the input address signal. A second signal line and word line drive circuit that drives the signal line and multiple word lines, and writing A writing circuit that outputs the incoming potential to the first signal line, and connected to the designated memory cell. The readout cycle compares the potential of the bit line input from the bit line with multiple readout potentials. Based on the comparison of the potential of the path and the bit line and the multiple readout potentials, multiple correction voltages are applied. A control circuit that selects one of the options, generates a write potential and multiple read potentials, and writes It has a potential generation circuit that supplies power to the circuit and the read circuit, and one of the plurality of memory cells is , a first trap having a first gate electrode, a first source electrode, and a first drain electrode The device comprises an inverter, a second gate electrode, a second source electrode, and a second drain electrode. The second transistor, the third gate electrode, the third source electrode, and the third drain electrode A third transistor having poles, and a first transistor having a base containing semiconductor material. The second transistor is provided on a plate and is composed of an oxide semiconductor layer, and the first gate electrode The electrode and either the second source electrode or the second drain electrode are electrically connected, The wire and the first source electrode are electrically connected, and the first drain electrode and the third source The drain electrode is electrically connected to the bit wire, and the third drain electrode is electrically connected to the bit wire. The first signal line and the other of the second source electrode or the second drain electrode are electrically connected. The second gate electrode is electrically connected to one of the multiple second signal lines, and multiple wires A semiconductor device in which one of the electrode wires and the third gate electrode are electrically connected.

[0019] Another aspect of the present invention includes a source line, a bit line, a first signal line, and a plurality of second signal lines. Multiple word lines, and multiple memory cells connected in parallel between the source line and the bit line. Multiple second memory cells are selected to select a memory cell specified by the input address signal. A second signal line and word line drive circuit that drives the signal line and multiple word lines, and the first In the writing operation, the first writing potential is output to the first signal line, and the second writing potential In this work, a programming circuit outputs one of several second programming potentials to the first signal line. In the first read operation, input is received from the bit line connected to the specified memory cell. The potential of the first bit line is compared with multiple first readout potentials, and the second readout is performed. In operation, the second bit is input from the bit line connected to the specified memory cell. The data in the memory cell is read by comparing the potential of the line with multiple second readout potentials. Based on the reading circuit, the potential of the first bit line, and the comparison result of multiple first read potentials Select one of several correction voltages and one of several second write potentials. A control circuit, a first write potential, multiple second write potentials, and multiple first read potentials It generates a potential and multiple second read potentials to supply to the write circuit and the read circuit. It has a potential generation circuit that supplies power, and one of the plurality of memory cells has a first gate electrode, a first socket A first transistor having a drain electrode and a first drain electrode, and a second gate electrode A second transistor having a second source electrode and a second drain electrode, and a third A third transistor having a gate electrode, a third source electrode, and a third drain electrode. The first transistor is provided on a substrate containing a semiconductor material, and the second transistor The sta consists of an oxide semiconductor layer, a first gate electrode, and a second source electrode or One side of the second drain electrode is electrically connected to the source wire, and the first source electrode is connected to the source wire. The first drain electrode and the third source electrode are electrically connected. The bit line and the third drain electrode are electrically connected, and the first signal line and the second saw The other of the drain electrode or the second drain electrode is electrically connected to one of the multiple second signal lines. The second gate electrode is electrically connected to one of several word lines and the third gate electrode. A pole is an electrically connected semiconductor device.

[0020] In the above, the first transistor is a channel forming device provided on a substrate containing a semiconductor material. A region, an impurity region provided so as to sandwich the channel formation region, and on the channel formation region A first gate insulating layer, a first gate electrode on the first gate insulating layer, an impurity region and an electrical It has a first source electrode and a first drain electrode that are connected to each other.

[0021] Furthermore, in the above, the second transistor is a second gate electrode on a substrate containing semiconductor material. The electrode, the second gate insulating layer on the second gate electrode, and the oxide semiconductor on the second gate insulating layer. A body layer and a second source electrode and a second drain electrode electrically connected to the oxide semiconductor layer. It has, and

[0022] Furthermore, in the above, the substrate containing the semiconductor material may be a single-crystal semiconductor substrate or an SOI substrate. It is preferable to use a plate. In particular, silicon is preferred as the semiconductor material.

[0023] Furthermore, in the above, the oxide semiconductor layer is an In-Ga-Zn-O based oxide semiconductor material. It is preferable that it contains. Furthermore, the oxide semiconductor layer is made of In2Ga2ZnO7 crystals. It may contain it. Furthermore, the hydrogen concentration of the oxide semiconductor layer is 5 × 10 19 atoms / cm 3 The following is preferable. Also, the off-current of the second transistor is 1 × 10⁻⁶. -13 It is preferable to set it to A or less.

[0024] Another aspect of the present invention includes a source line, a bit line, a word line, a first signal line, and a Two signal lines and a second signal line to select the memory cell specified by the input address signal. A drive circuit for the second signal line and word line that drives the second signal line and word line, and a write circuit A path, a readout circuit, a control circuit, a potential generation circuit, a source line, a bit line, a word line, A semiconductor device having a memory cell connected to a first signal line and a second signal line, In the first write operation, the write potential is transmitted from the write circuit to the specified memory cell. The output is sent to the first signal line connected to the first read operation, and in the read circuit, the specified The potential of the first bit line input from the bit line connected to the modified memory cell, and multiple The first readout potential is compared with the current value, and based on the comparison result, the control circuit sets a plurality of correction voltages. Select one of the options, and in the second write operation, the write potential is corrected based on the correction voltage. A method for driving a semiconductor device that outputs a signal to a first signal line connected to a designated memory cell. ru.

[0025] Another aspect of the present invention comprises a source line, a bit line, a word line, a first signal line, and a second signal A line and a second signal to select the memory cell specified by the input address signal. A second signal line and word line drive circuit for driving the line and word line, and a writing circuit, Readout circuit, control circuit, potential generation circuit, source line, bit line, word line, first signal A semiconductor device having a memory cell connected to a signal line and a second signal line, the first During the write operation, the write potential is connected from the write circuit to the specified memory cell. The output is sent to the first signal line, and in the first read operation, the read circuit, specified The potential of the first bit line input from the bit line connected to the memory cell, and multiple first The readout potential is compared with the control circuit, and based on the comparison result, one of several correction voltages is selected. Select and, in the second write operation, the write potential corrected based on the correction voltage is indicated The signal is output to the first signal line connected to the specified memory cell, and in the second read operation, In the output circuit, the second bit is input from the bit line connected to the specified memory cell. The semiconductor reads the data from the memory cell by comparing the potential of the line with multiple second readout potentials. This is a method for driving a conductive device.

[0026] In this specification, the terms "above" and "below" refer to the relative position of the constituent elements, meaning "directly above". Or it does not limit to being "directly below". For example, "the first on the gate insulating layer The expression "gate electrode" implies that other components are included between the gate insulating layer and the gate electrode. This does not exclude them. Also, the terms "upper" and "lower" are merely expressions used for the sake of explanation. Unless otherwise specified, this also includes the inverted versions of the same thing.

[0027] Furthermore, in this specification, the terms "electrode" and "wiring" refer to these components functionally. It is not limited to that. For example, "electrode" can be used as part of "wiring". And the reverse is also true. Furthermore, the terms "electrode" and "wiring" can refer to multiple "electrodes." This also includes cases where "or wiring" is formed as a single unit.

[0028] Furthermore, the "source" and "drain" functions are used when employing transistors with different polarities. However, this can change when the direction of current changes during circuit operation. In this specification, the terms "source" and "drain" are interchangeable. It is assumed that this is possible.

[0029] In this specification, etc., "electrically connected" means "having some kind of electrical effect." This includes cases where the connection is made via ". Here, "something that has some electrical effect" The term "connection" is not particularly limited as long as it enables the exchange of electrical signals between connected objects.

[0030] For example, "something that has some kind of electrical effect" includes not only electrodes and wiring, but also... Switching elements such as inverters, resistive elements, inductors, capacitors, and various other components. This includes elements that possess certain capabilities.

[0031] Furthermore, generally speaking, an "SOI substrate" is a substrate in which a silicon semiconductor layer is provided on an insulating surface. However, in this specification, etc., a semiconductor layer made of a material other than silicon is provided on the insulating surface. It is used as a concept that also includes the substrate with the specified configuration. In other words, the semiconductor that the "SOI substrate" possesses The layer is not limited to a silicon semiconductor layer. Also, the substrate in "SOI substrate" is silicon This applies not only to semiconductor substrates such as wafers, but also to glass substrates, quartz substrates, sapphire substrates, and metal substrates. This also includes non-semiconductor substrates such as those mentioned above. In other words, semiconductors on conductive substrates or insulating plates having insulating surfaces. The term "SOI substrate" broadly includes those having layers made of materials. Furthermore, as specified herein, In this context, "semiconductor substrate" refers not only to a substrate made solely of semiconductor materials, but also to semiconductor materials This refers to all substrates including the above. In other words, in this specification, the term "SOI substrate" is also used broadly. It is listed under "semiconductor substrate". [Effects of the Invention]

[0032] In one aspect of the present invention, the lower part has a transistor made of a material other than an oxide semiconductor, and the upper A semiconductor device having a transistor made of an oxide semiconductor is provided.

[0033] Transistors using oxide semiconductors have extremely low off-currents, so we decided to use them. It is possible to retain memory content for an extremely long period of time. In other words, refresh function This eliminates the need for manual operation, or makes it possible to significantly reduce the frequency of refresh operations. Therefore, power consumption can be significantly reduced. Also, even if there is no power supply... It is possible to retain memory content over a long period of time.

[0034] Furthermore, it does not require high voltage for writing information, and there are no issues with component degradation. Because information is written depending on whether the inverter is on or off, high-speed operation is also possible. It can be easily implemented. Furthermore, it has the advantage of not requiring any action to erase the information. .

[0035] Furthermore, transistors using materials other than oxide semiconductors are... Compared to the previous method, it enables even faster operation, and by using this, the reading of stored contents can be performed. It is possible to perform deviations at high speed.

[0036] Alternatively, in one aspect of the present invention, the potential of the bit line is compared with the readout potential to obtain a suitable solution. By selecting a positive voltage, it is possible to accurately distinguish between multiple states (e.g., 3 or more states), This makes it easier to provide a multi-level semiconductor device with excellent characteristics. can.

[0037] Thus, transistors using materials other than oxide semiconductors and transistors using oxide semiconductors By integrating the transistor, and also by comparing the potential of the bit line with the readout potential, By having a circuit that selects a correction voltage based on this, it has unprecedented features. A conductive device can be realized. [Brief explanation of the drawing]

[0038] [Figure 1]A circuit diagram used to explain a semiconductor device. [Figure 2] Cross-sectional and plan views illustrating a semiconductor device. [Figure 3] A cross-sectional diagram illustrating the manufacturing process of semiconductor devices. [Figure 4] A cross-sectional diagram illustrating the manufacturing process of semiconductor devices. [Figure 5] A cross-sectional diagram illustrating the manufacturing process of semiconductor devices. [Figure 6] Cross-sectional view of a transistor using an oxide semiconductor. [Figure 7] The energy band diagram (schematic diagram) in the A-A' section of Figure 6. [Figure 8] (A) shows the state where a positive potential (VG>0) is applied to the gate (GE1), and (B) shows the state where a negative potential (VG<0) is applied to the gate (GE1). [Figure 9] This diagram shows the relationship between the vacuum level, the work function (φM) of metals, and the electron affinity (χ) of oxide semiconductors. [Figure 10] A cross-sectional diagram illustrating a semiconductor device. [Figure 11] A cross-sectional diagram illustrating a semiconductor device. [Figure 12] A cross-sectional diagram illustrating a semiconductor device. [Figure 13] A cross-sectional diagram illustrating a semiconductor device. [Figure 14] A diagram illustrating memory cells. [Figure 15] A diagram illustrating the programming circuit. [Figure 16] A diagram illustrating the readout circuit. [Figure 17] A diagram to explain the writing process. [Figure 18] A diagram showing the distribution of electrical potential. [Figure 19] A flowchart diagram to explain the operation. [Figure 20] This diagram shows an example of the state after data writing without correction and an example of the state after data writing with correction. [Figure 21]A diagram illustrating semiconductor devices. [Figure 22] A diagram used to explain electronic devices. [Modes for carrying out the invention]

[0039] An example of an embodiment of the present invention will be described below with reference to the drawings. However, the present invention is as follows The description is not limited to the present invention, and without departing from the spirit and scope of the present invention, its form and Those skilled in the art will readily understand that the details can be modified in various ways. Therefore, the present invention is as follows: The description of the embodiment shown is not to be limited to the content described therein.

[0040] Furthermore, the location, size, and scope of each component shown in the drawings, etc., are for ease of understanding. The actual location, size, and range may not be represented. Therefore, drawings and other diagrams are not always accurate. It is not limited to the location, size, scope, etc. disclosed herein.

[0041] Furthermore, the ordinal numbers such as "1st," "2nd," and "3rd" used in this specification, etc., are intended to avoid confusion of constituent elements. This is added to avoid any misunderstandings and does not mean that the number is limited.

[0042] (Embodiment 1) In this embodiment, the configuration and manufacturing method of a semiconductor device according to one aspect of the disclosed invention are described below. This will be explained with reference to Figures 1 to 13.

[0043] <Circuit configuration of semiconductor device> Figure 1 shows an example of the circuit configuration of a semiconductor device. This semiconductor device is made of materials other than oxide semiconductors. It consists of a transistor 160 made of material and a transistor 162 made of oxide semiconductor. This is achieved. Note that Figure 1 clearly indicates that an oxide semiconductor was used for transistor 162. Therefore, the OS code is matched and attached accordingly.

[0044] Here, the gate electrode of transistor 160 and the source electrode or dot of transistor 162 It is electrically connected to one of the rain electrodes. Also, the first line The source wire (also called the source line) and the source electrode of transistor 160 are electrically connected, and the second The wiring (2nd Line: also called the bit line) and the drain electrode of transistor 160 and They are electrically connected. And the third wire (3rd Line: also known as the 1st signal line) The other of the source electrode or drain electrode of transistor 162 is electrically connected. And the fourth wire (4th Line: also called the second signal line) and transistor 162 The gate electrode is electrically connected.

[0045] Transistor 160, which uses materials other than oxide semiconductors, is a transistor that uses oxide semiconductors. Compared to standard, it allows for even faster operation, and by using this, the stored contents can be processed It is possible to perform readouts and other operations at high speed. Furthermore, it uses an oxide semiconductor transistor. Transistor 162 has the characteristic of having an extremely low off-current. Therefore, transistor 1 By turning off 62, the potential of the gate electrode of transistor 160 can be kept at that level for an extremely long time. It is possible to hold it across.

[0046] By taking advantage of the characteristic that the potential of the gate electrode can be maintained, information can be obtained as follows: It is possible to write, hold, and read data.

[0047] First, we will explain how to write and retain information. First, the potential of the fourth wire is... The potential at which transistor 162 turns on is set to the ON state, and transistor 162 is turned ON. As a result, the potential of the third wire is applied to the gate electrode of transistor 160 (write (Including). Then, the potential of the fourth wire is set as the potential at which transistor 162 is in the off state. By turning off transistor 162, the gate electrode of transistor 160 The electric potential is maintained (held).

[0048] Since the off-current of transistor 162 is extremely small, the gate electrode of transistor 160 The potential is maintained for a long time. For example, the potential of the gate electrode of transistor 160 is If the potential is such that transistor 160 is turned on, then transistor 160 will remain in the turned-on state for a long time. This will be maintained over time. Also, the potential of the gate electrode of transistor 160 If the potential is such that transistor 160 is in the off state, then transistor 160 will remain in the off state for a long time. It is retained over time.

[0049] Next, we will explain how to read the information. As mentioned above, the ON state of transistor 160 Alternatively, when the OFF state is maintained, a predetermined potential (low potential) is applied to the first wiring. When this happens, the potential of the second wiring differs depending on whether transistor 160 is on or off. It takes a value such that, for example, when transistor 160 is ON, the potential of the first wiring is Accordingly, the potential of the second wiring decreases. Conversely, transistor 160 is in the off state. In this case, the potential of the second wire does not change.

[0050] In this way, while the information is retained, the potential of the second wiring is compared with a predetermined potential. This allows us to extract the information.

[0051] Next, we will explain how to rewrite information. Rewriting information involves writing the information as described above and This is done in the same way as holding. In other words, the potential of the fourth wire is set when transistor 162 is ON. To achieve this potential, transistor 162 is turned ON. This results in the potential of the third wiring. (A potential related to new information) is applied to the gate electrode of transistor 160. Then, The potential of the fourth wire is set to the potential at which transistor 162 is in the OFF state, By turning off 62, the new information is retained.

[0052] Thus, the semiconductor device relating to the disclosed invention directly generates information through subsequent writing. It is possible to rewrite the information. Therefore, it is necessary in flash memory and other applications. This eliminates the need for an erase operation, thus suppressing the decrease in operating speed caused by the erase operation. In other words, high-speed operation of semiconductor devices will be achieved.

[0053] Note that the above explanation refers to an n-type transistor (n-channel transistor) that uses electrons as the majority carrier. This concerns the case where a st(s) is used, but instead of an n-type transistor, a large number of holes are used. It goes without saying that a p-type transistor can be used as the carrier.

[0054] Furthermore, it goes without saying that additional elements can be added to the above configuration. For example, The gate electrode of transistor 160, or the source electrode or drain electrode of transistor 162 Even if a configuration is adopted in which a capacitive element is connected to one of the poles to increase the tolerance to potential fluctuations, good.

[0055] <Planar and cross-sectional configurations of semiconductor devices> Figure 2 shows an example of the configuration of the semiconductor device described above. Figure 2(A) shows a cross-section of the semiconductor device. Figure 2(B) shows the planes of the semiconductor device. Here, Figure 2(A) is the same as Figure 2(B). This corresponds to the cross-section along lines A1-A2 and B1-B2. Figures 2(A) and 2(B) The semiconductor device shown in ) has a transistor 160 at the bottom that uses a material other than an oxide semiconductor. It has a transistor 162 made of oxide semiconductor on its upper part. Transistor 160 and transistor 162 are both described as n-type transistors. However, a p-type transistor may also be used. In particular, transistor 160 should be a p-type transistor. This is easy.

[0056] The transistor 160 is located in a channel formation region 11 provided on a substrate 100 containing semiconductor material. 6 and the impurity region 114 and high concentration impurity region provided so as to sandwich the channel formation region 116. The pure material region 120 (these are also simply called the impurity region) and the channel-forming region 11 A gate insulating layer 108 provided on 6, and a gate electrode provided on the gate insulating layer 108 Source electrode or drain electrode 130a that is electrically connected to 110 and the impurity region 114. It has a source electrode or a drain electrode 130b.

[0057] Here, a sidewall insulating layer 118 is provided on the side surface of the gate electrode 110. Furthermore, in the area of ​​the substrate 100 that does not overlap with the sidewall insulating layer 118 when viewed in plan view, It has a high-concentration impurity region 120, and a metal compound region 124 exists on the high-concentration impurity region 120. It is present. Also, on the substrate 100, there is an element isolation insulating layer 106 surrounding the transistor 160. A structure is provided, and the interlayer insulating layer 126 and interlayer insulating layer are provided so as to cover the transistor 160. A layer 128 is provided. Source electrode or drain electrode 130a, source electrode or The drain electrode 130b has openings formed in the interlayer insulating layer 126 and the interlayer insulating layer 128. Through this, it is electrically connected to the metal compound region 124. In other words, the source electrode or The rain electrode 130a, source electrode or drain electrode 130b are located in the metal compound region 124 It is electrically connected to the high-concentration impurity region 120 and the impurity region 114 via this. Furthermore, the gate electrode 110 has a source electrode or drain electrode 130a or source electrode or Electrode 130c, which is provided in the same manner as the drain electrode 130b, is electrically connected.

[0058] The transistor 162 has a gate electrode 136d provided on the interlayer insulating layer 128, and a gate A gate insulating layer 138 provided on electrode 136d, and a gate insulating layer 138 provided on An oxide semiconductor layer 140, and provided on the oxide semiconductor layer 140, and The electrically connected source electrode or drain electrode 142a, source electrode or drain It has an in electrode 142b.

[0059] Here, the gate electrode 136d is embedded in the insulating layer 132 formed on the interlayer insulating layer 128. It is provided so as to be inserted. Also, similar to the gate electrode 136d, the source electrode or Electrode 136a is in contact with drain electrode 130a, and is connected to source electrode or drain electrode 130b Electrode 136b is formed in contact with electrode 130c, and electrode 136c is formed in contact with electrode 130c. ru.

[0060] Furthermore, a protective layer is placed on top of the transistor 162 so as to be in contact with a portion of the oxide semiconductor layer 140. An insulating layer 144 is provided, and an interlayer insulating layer 146 is provided on the protective insulating layer 144. Here, the protective insulating layer 144 and the interlayer insulating layer 146 are provided with openings reaching the source electrode or drain electrode 142a and the source electrode or drain electrode 142b. Through the openings, the electrodes 150d and 150e are formed in contact with the source electrode or drain electrode 142a and the source electrode or drain electrode 142b. Similarly, through the openings provided in the gate insulating layer 138, the protective insulating layer 144, and the interlayer insulating layer 146, the electrodes 150a, 150b, and 150c that contact the electrodes 136a, 136b, and 136c are formed.

[0061] Here, it is desirable that the oxide semiconductor layer 140 has sufficiently removed impurities such as hydrogen and is highly purified. Specifically, the hydrogen concentration in the oxide semiconductor layer 140 is 5×10 atoms / cm 19 or less, preferably 5×10 3 atoms / cm 18 [[ID=Z7]]or less, more preferably 5×10 3 atoms / cm or less. Also, in the oxide semiconductor layer 140 with a sufficiently reduced hydrogen concentration and highly purified, the carrier concentration is less than 1×10 17 / cm 3 preferably 1×10 / cm 12 or less. Thus, by using an oxide semiconductor with a sufficiently reduced hydrogen concentration, highly purified, and i-type or substantially i-type, a transistor 162 with extremely excellent off-current characteristics can be obtained. For example, the drain voltage 3 11 3 ​​​​​​​​​When Vd is +1V or +10V, and the gate voltage Vg is in the range of -5V to -20V In the enclosure, the off-current is 1 × 10 -13 It is less than or equal to A. Thus, the hydrogen concentration is sufficiently reduced. By applying a highly purified oxide semiconductor layer 140, the off-current of the transistor 162 is reduced. By reducing this, a new semiconductor device configuration can be realized. The hydrogen concentration in the semiconductor layer 140 was determined by secondary ion mass spectrometry (SIMS). This was measured using ion mass spectrometry (Ion Mass Spectroscopy).

[0062] Furthermore, an insulating layer 152 is provided on the interlayer insulating layer 146, and embedded in the insulating layer 152. Electrodes 154a, 154b, 154c, and 154d are provided so as to be inserted. Here, electrode 154a is in contact with electrode 150a, and electrode 154b is in contact with electrode 150 It is in contact with b, and electrode 154c is in contact with electrode 150c and electrode 150d, and electrode 1 Electrode 54d is in contact with electrode 150e.

[0063] In other words, in the semiconductor device shown in Figure 2, the gate electrode 110 of transistor 160 and The source electrode or drain electrode 142a of the lampistor 162 is connected to electrode 130c, electrode 1 36c, electrode 150c, electrode 154c and electrode 150d are electrically connected. ru.

[0064] <Method for fabricating semiconductor devices> Next, we will describe an example of a method for manufacturing the above semiconductor device. Below, we will first explain the lower part The method for fabricating the transistor 160 will be explained with reference to Figure 3, and then the upper transistor The method for manufacturing Ta162 will be explained with reference to Figures 4 and 5.

[0065] <Method for fabricating the lower transistor> First, prepare a substrate 100 containing semiconductor material (see Figure 3(A)). The plate 100 can be a single-crystal semiconductor substrate such as silicon or silicon carbide, or a polycrystalline semiconductor substrate. Compound semiconductor substrates such as silicon germanium, SOI substrates, etc. can be applied. Here, we will use a single-crystal silicon substrate as the substrate 100 containing semiconductor material. An example will be shown. Generally speaking, an "SOI substrate" is a substrate with silicon semiconductor on an insulating surface. This refers to a substrate having a conductive layer, but in this specification, it refers to a substrate with silicon on the insulating surface. This concept is used to include substrates with a semiconductor layer made of materials other than those mentioned above. The semiconductor layer of the "SOI substrate" is not limited to a silicon semiconductor layer. The substrate has a configuration in which a semiconductor layer is provided on an insulating substrate such as a glass substrate, with an insulating layer in between. It shall include the following.

[0066] A protective layer 102 is formed on the substrate 100, which serves as a mask for forming an element isolation insulating layer. (See Figure 3(A)). The protective layer 102 can be, for example, silicon oxide or silicon nitride. An insulating layer made of silicon nitride or similar material can be used. In order to control the threshold voltage of the transistor, an impurity is imparted to impart n-type conductivity. Monochemical elements or impurity elements that impart p-type conductivity may be added to the substrate 100. In the case of ricon, impurities that impart n-type conductivity include, for example, phosphorus and arsenic. This can be achieved. Furthermore, examples of impurities that impart p-type conductivity include boron and aluminum. Materials such as nium and gallium can be used.

[0067] Next, etching is performed using the protective layer 102 as a mask, and the material covered by the protective layer 102 is then... A portion of the substrate 100 in the area that is not present (exposed area) is removed. This separates the half A conductive region 104 is formed (see Figure 3(B)). Dry etching is used for this etching process. It is preferable to use an etching gas, but wet etching may also be used. The etching solution can be appropriately selected depending on the material to be etched.

[0068] Next, an insulating layer is formed to cover the semiconductor region 104, and the region superimposed on the semiconductor region 104 By selectively removing the insulating layer, an element isolation insulating layer 106 is formed (see Figure 3(B)). The insulating layer is formed using silicon oxide, silicon nitride, silicon nitride oxide, etc. Methods for removing the insulating layer include polishing treatments such as CMP and etching treatments. Either of these may be used. Note that after the formation of the semiconductor region 104, or after device isolation and insulation After the formation of layer 106, the protective layer 102 is removed.

[0069] Next, an insulating layer is formed on the semiconductor region 104, and a layer containing a conductive material is formed on the insulating layer. ru.

[0070] The insulating layer will later become the gate insulating layer, and can be obtained using methods such as CVD or sputtering. Silicon oxide, silicon nitride, silicon nitride, hafnium oxide, aluminum oxide A single-layer or multi-layer structure of a film containing aluminum, tantalum oxide, etc. is preferable. By oxidizing and nitriding the surface of the semiconductor region 104 through lazma treatment or thermal oxidation treatment, The above insulating layer may be formed. High-density plasma treatment may be performed using, for example, He, Ar, Kr, Using noble gases such as Xe and mixed gases such as oxygen, nitrogen oxides, ammonia, nitrogen, and hydrogen This can be done. Furthermore, the thickness of the insulating layer is not particularly limited, but for example, 1 nm or more. It can be reduced to 0 nm or less.

[0071] The layer containing conductive material is made of metallic materials such as aluminum, copper, titanium, tantalum, and tungsten. It can be formed using semiconductor materials such as polycrystalline silicon containing conductive materials. A layer containing a conductive material may be formed using [a specific method]. The formation method is not particularly limited and may include vapor deposition, C [another specific method]. Various film deposition methods such as the VD method, sputtering method, and spin coating method can be used. In this embodiment, an example of forming a layer containing a conductive material using a metal material is described below. This shall be shown.

[0072] Subsequently, the insulating layer and the layer containing the conductive material are selectively etched to form the gate insulating layer 108 , forming the gate electrode 110 (see Figure 3(C)).

[0073] Next, an insulating layer 112 is formed to cover the gate electrode 110 (see Figure 3(C)). Then, half By adding phosphorus (P) or arsenic (As) to the conductive region 104, a shallow bonding depth with the substrate 100 is achieved. This forms an impurity region 114 (see Figure 3(C)). Note that this is an n-type transistor. Phosphorus or arsenic is added to form the transistor, but when forming a p-type transistor, You can add impurity elements such as boron (B) or aluminum (Al). The formation of region 114 results in channel formation below the gate insulating layer 108 of the semiconductor region 104. Region 116 is formed (see Figure 3(C)). Here, the concentration of the added impurities is set as appropriate. However, when semiconductor devices are miniaturized to a high degree, it is possible to increase the concentration. This suppresses the short-channel effect. Also, here, impurities are removed after forming the insulating layer 112. The process employs the formation of region 114, but after forming the impurity region 114, an insulating layer 1 This can also be a process for forming 12.

[0074] Next, the sidewall insulating layer 118 is formed (see Figure 3(D)). Layer 118 is formed to cover the insulating layer 112, and then an insulating layer is formed to provide high anisotropy to the insulating layer. By applying an etching process, it can be formed in a self-aligned manner. The insulating layer 112 is partially etched, and the upper surface of the gate electrode 110 and the impurity region 1 It's best to expose the top surface of part 14.

[0075] Next, to cover the gate electrode 110, impurity region 114, sidewall insulating layer 118, etc. Then, an insulating layer is formed. And in the region where the insulating layer is in contact with the impurity region 114, phosphorus ( By adding P or arsenic (As), a high-concentration impurity region 120 is formed (see Figure 3(E)). (Illuminate). After that, remove the above insulating layer, gate electrode 110, sidewall insulating layer 118, A metal layer 122 is formed to cover the high-concentration impurity region 120, etc. (See Figure 3(E)). The metal layer 122 is formed by various thin-film deposition methods such as vacuum deposition, sputtering, and spin coating. It can be formed using the semiconductor material that constitutes the semiconductor region 104. It is desirable to form this using a metallic material that reacts with the material to form a low-resistance metallic compound. Examples of such metallic materials include titanium, tantalum, tungsten, nickel, and cobalt. Examples include platinum, etc.

[0076] Next, heat treatment is performed to react the metal layer 122 with the semiconductor material. This results in high A metal compound region 124 is formed adjacent to the concentration impurity region 120 (see Figure 3(F)). Furthermore, when using polycrystalline silicon or the like as the gate electrode 110, A metal compound region will also be formed in the area that comes into contact with the metal layer 122.

[0077] As for the above heat treatment, for example, heat treatment by irradiation with a flash lamp can be used. Of course, other heat treatment methods may be used, but the chemical reaction involved in the formation of metal compounds is important. To improve controllability, it is desirable to use a method that enables very short heat treatment times. It appears that the above-mentioned metallic compound region is formed by the reaction between a metallic material and a semiconductor material. This is a region in which conductivity is sufficiently enhanced. This allows for a significant reduction in electrical resistance and improvement of the device characteristics. After forming region 124, the metal layer 122 is removed.

[0078] Next, an interlayer insulating layer 126 and an interlayer insulating layer are formed to cover each of the components formed by the above process. Forms 128 (see Figure 3(G)). Interlayer insulating layers 126 and 128 are formed of oxides Silicon nitride, silicon nitride, hafnium oxide, aluminum oxide, tahnix oxide It can be formed using materials containing inorganic insulating materials such as tar. Also, polyimide, It is also possible to form it using organic insulating materials such as acrylic. The structure consists of two layers: an edge layer 126 and an interlayer insulating layer 128. However, the configuration of the interlayer insulating layer is not limited to this. No. After the formation of the interlayer insulating layer 128, its surface is subjected to CMP or etching treatment, etc. Therefore, it is desirable to flatten it.

[0079] Subsequently, an opening is formed in the interlayer insulating layer that extends to the metal compound region 124, and the opening Then, the source electrode or drain electrode 130a and the source electrode or drain electrode 130b are connected. Form (see Figure 3(H)). Source electrode or drain electrode 130a or source electrode or The drain electrode 130b is, for example, subjected to PVD or CVD methods in the region including the opening. After forming the conductive layer, a portion of the conductive layer is removed using methods such as etching or CMP. It can be formed by removal.

[0080] Furthermore, a portion of the above conductive layer can be removed to form the source electrode or drain electrode 130a or source electrode. Alternatively, when forming the drain electrode 130b, the surface is processed to be flat. This is desirable. For example, after forming a thin titanium film or titanium nitride film in the region including the opening, When forming a tungsten film to fill an opening, subsequent CMP (Chemical Polishing) can cause problems. The necessary tungsten film, titanium film, titanium nitride film, etc., are removed, and the flatness of the surface is improved. This can improve the source electrode or drain electrode 130a, By planarizing the surface including the drain electrode 130b, in subsequent processes This makes it possible to form good electrodes, wiring, insulating layers, semiconductor layers, etc.

[0081] In this case, the source electrode or drain electrode 130 that comes into contact with the metal compound region 124 Although only a and the source electrode or drain electrode 130b are shown, in this process, The electrode that comes into contact with the electrode 110 (for example, electrode 130c in Figure 2) is then combined to form This can be achieved. Source electrode or drain electrode 130a, source electrode or drain There are no particular limitations on the material that can be used as electrode 130b; various conductive materials can be used. It can be used. For example, molybdenum, titanium, chromium, tantalum, tungsten, Conductive materials such as aluminum, copper, neodymium, and scandium can be used.

[0082] As a result, a transistor 160 is formed using a substrate 100 containing semiconductor material. After the above process, electrodes, wiring, insulating layers, etc. may be formed. Furthermore, by adopting a multilayer wiring structure consisting of a laminated structure of interlayer insulating layers and conductive layers, high We can provide a semiconductor device with integrated components.

[0083] <Method for fabricating the upper transistor> Next, using Figures 4 and 5, the process of fabricating the transistor 162 on the interlayer insulating layer 128 is described. The process will be explained. Figures 4 and 5 show various electrodes on the interlayer insulating layer 128 and the trap. This shows the manufacturing process for transistor 162, and is therefore located at the bottom of transistor 162. Details regarding transistor 160 and other components have been omitted.

[0084] First, the interlayer insulating layer 128, the source electrode or drain electrode 130a, the source electrode or drain An insulating layer 132 is formed on the rain electrode 130b and electrode 130c (see Figure 4(A)). The marginal layer 132 can be formed using methods such as PVD or CVD. Silicon nitride, silicon nitride, hafnium oxide, aluminum oxide, tantalum oxide It can be formed using materials containing inorganic insulating materials such as ru.

[0085] Next, the source electrode or drain electrode 130a, source electrode or An opening is formed that extends to the drain electrode 130b and electrode 130c. An opening is also formed in the region where the gate electrode 136d is formed. A conductive layer 134 is formed to embed it (see Figure 4(B)). The above opening is made using a mask. It can be formed by methods such as etching. The mask is a photomask. It can be formed by methods such as exposure. Etching can be done using wet etching. Either etching or dry etching can be used, but from the perspective of microfabrication, dry etching is preferable. It is preferable to use a ching. The conductive layer 134 is formed by methods such as PVD or CVD. This can be done using a film method. Materials that can be used to form the conductive layer 134 include Molybdenum, titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium Examples include conductive materials such as scandium, as well as alloys and compounds of these materials (e.g., nitrides). It is possible.

[0086] More specifically, for example, a thin titanium film is formed in the region including the opening by the PVD method, and CV After forming a thin titanium nitride film using method D, a tungsten film was formed to embed it in the opening. A method can be applied to achieve this. Here, the titanium film formed by the PVD method is below Partial electrode (here, source electrode or drain electrode 130a, source electrode or drain electrode The oxide film at the interface with electrode 130b, electrode 130c, etc. is reduced, lowering the contact resistance with the lower electrode. It has the function of reducing. Furthermore, the titanium nitride film that is formed afterward reduces the diffusion of conductive materials. It has a barrier function that suppresses it. In addition, a barrier film made of titanium or titanium nitride is formed. Later, a copper film may be formed by a plating method.

[0087] After forming the conductive layer 134, the conductive layer 13 is formed using methods such as etching and CMP. Remove a portion of 4 to expose the insulating layer 132, and then remove electrodes 136a, 136b, and 13 6c, forming the gate electrode 136d (see Figure 4(C)). Note that one of the conductive layers 134 Remove the portion to form electrodes 136a, 136b, 136c, and gate electrode 136d. When doing so, it is desirable to process the surface so that it becomes flat. In this way, insulating layer 132 The surfaces of electrodes 136a, 136b, 136c, and gate electrode 136d are planarized. This allows for the formation of good electrodes, wiring, insulating layers, semiconductor layers, etc., in subsequent processes. This becomes possible.

[0088] Next, insulating layer 132, electrode 136a, electrode 136b, electrode 136c, gate electrode 136d A gate insulating layer 138 is formed to cover it (see Figure 4(D)). Gate insulating layer 138 This can be formed using methods such as CVD or sputtering. Also, the gate insulating layer 138 is silicon oxide, silicon nitride, silicon oxide nitride, silicon oxide nitride, aluminum oxide, oxide It is preferable to form the gate insulation to include hafnium, tantalum oxide, etc. Layer 138 may be a single-layer structure or a multi-layer structure. For example, as a raw material gas By plasma CVD using silane (SiH4), oxygen, and nitrogen, silicon oxide nitride is produced. A gate insulating layer 138 can be formed. The thickness of the gate insulating layer 138 is not particularly limited. However, it is not possible to set it to, for example, 10 nm to 500 nm. For example, a first gate insulating layer with a film thickness of 50 nm or more and 200 nm or less, and the first gate insulating It is preferable to laminate a second gate insulating layer with a thickness of 5 nm to 300 nm on the layer.

[0089] Furthermore, by removing impurities, the oxide semiconductor can be made i-type or substantially i-type (high Purified oxide semiconductors are extremely sensitive to interface states and interface charges, therefore When using oxide semiconductors like the one shown in the image for the oxide semiconductor layer, the interface with the gate insulating layer is important. Therefore, the gate insulating layer 138 in contact with the highly purified oxide semiconductor layer is made of high-grade material. This will require a change in quality.

[0090] For example, high-density plasma CVD using μ-wave (2.45 GHz) is a method that produces dense materials with high dielectric strength. It is suitable in that it can form a high-quality gate insulating layer 138. The close contact between the conductor layer and the high-quality gate insulating layer reduces the interface state and improves the interface properties. Because it can be made into something desirable.

[0091] Of course, if it can form a good insulating layer as a gate insulating layer, then high-purity material Even when using an oxide semiconductor layer, other methods such as sputtering and plasma CVD are used. The method can be applied. Furthermore, by heat treatment after formation, the film quality and oxide semiconductor layer can be modified. An insulating layer that modifies the interface properties may be applied. In any case, the gate insulating layer 138 The film quality is good, and the interface level density with the oxide semiconductor layer is reduced, resulting in a good interface. You just need to create something that can form a surface.

[0092] Furthermore, 85℃, 2×10 6 V / cm, 12-hour gate bias thermal stress test (B In the T test, if impurities are added to the oxide semiconductor, the impurities and the oxide semiconductor... The bond with the main component is broken by a strong electric field (B: bias) and high temperature (T: temperature), and is generated. The uncoupled hands induce a drift in the threshold voltage (Vth).

[0093] In contrast, impurities in oxide semiconductors, especially hydrogen and water, are eliminated as much as possible, and as described above, By improving the interface characteristics with the insulating layer, stable transients are achieved even under BT testing. It is possible to obtain the result.

[0094] Next, an oxide semiconductor layer is formed on the gate insulating layer 138, and etching is performed using a mask. The oxide semiconductor layer is processed by methods such as those described above to form island-shaped oxide semiconductor layers 140. (See Figure 4(E)).

[0095] Examples of oxide semiconductor layers include quaternary metal oxides such as In-Sn-Ga-Zn-O and ternary metal oxides. In-Ga-Zn-O, In-Sn-Zn-O, In-Al-Zn- O, Sn-Ga-Zn-O, Al-Ga-Zn-O, Sn-Al-Zn-O, and binary gold systems. The group oxides are In-Zn-O, Sn-Zn-O, Al-Zn-O, Zn-Mg-O, S Oxide semiconductors such as n-Mg-O, In-Mg-O, and In-O, Sn-O, and Zn-O are used. A conductive layer can be applied. Furthermore, SiO2 may be included in the oxide semiconductor layer. stomach.

[0096] Furthermore, the oxide semiconductor layer is InMO3(ZnO) m We use thin films denoted as (m>0). This is possible. Here, M is one or more selected from Ga, Al, Mn, and Co. This indicates a metallic element. For example, M could be Ga, Ga and Al, Ga and Mn, or Ga and Examples include Co., InMO3(ZnO).m Oxide semiconductor film with a structure represented by (m>0) Among these, oxide semiconductors with a structure containing Ga as M are called In-Ga-Zn-O oxide semiconductors. This is called an In-Ga-Zn-O oxide semiconductor film (In-Ga-Zn-O amorphous We will refer to it as a membrane, etc.

[0097] In this embodiment, the oxide semiconductor layer is an In-Ga-Zn-O based oxide semiconductor film deposition material. An amorphous oxide semiconductor layer will be formed using a target by sputtering. Furthermore, by adding silicon to the amorphous oxide semiconductor layer, its crystallization can be suppressed. Therefore, for example, using a target containing 2% to 10% by weight of SiO2 An oxide semiconductor layer may be formed.

[0098] For example, an oxide semiconductor layer can be fabricated using the sputtering method. A metal oxide target with zinc as the main component can be used. In addition, In, Ga, and a target for oxide semiconductor film deposition containing Zn (composition ratio: In2O3:Ga2O 3:ZnO=1:1:1[mol ratio], In:Ga:Zn=1:1:0.5[atom You can also use %]), etc. In addition, oxide semiconductor components containing In, Ga, and Zn For membrane targets, In2O3:Ga2O3:ZnO = 1:1:2 [molar ratio] Alternatively, a composition ratio of In2O3:Ga2O3:ZnO = 1:1:4 [molar ratio] You may also use a target such as a GET. The packing density of the oxide semiconductor film deposition target should be 90% or more. The packing density is 0% or less, preferably 95% or more (for example, 99.9%). By using a target for film deposition, a dense oxide semiconductor layer is formed.

[0099] The formation atmosphere of the oxide semiconductor layer is preferably a noble gas (typically argon) atmosphere, an oxygen atmosphere, or a mixed atmosphere of a noble gas (typically argon) and oxygen. Specifically, for example, it is preferable to use a high-purity gas in which the concentration of impurities such as hydrogen, water, hydroxyl groups, or hydrides is removed to about several ppm (desirably about several ppb in terms of concentration). During the formation of the oxide semiconductor layer, the substrate is held in a processing chamber maintained in a reduced-pressure state, and the substrate temperature is set to 100°C or higher and 600°C or lower, preferably 200°C or higher and 400°C or lower. By forming the oxide semiconductor layer while heating the substrate, the impurity concentration contained in the oxide semiconductor layer can be reduced. Also, the damage due to sputtering is reduced. Then, a sputtering gas from which hydrogen and water have been removed while removing residual moisture in the processing chamber is introduced, and an oxide semiconductor layer is formed using a metal oxide as a target. To remove the residual moisture in the processing chamber, it is preferable to use an adsorption-type vacuum pump. For example, a cryopump, an ion pump, or a titanium sublimation pump can be used. Also, as an exhaust means, a turbo pump with a cold trap added thereto may be used. The film formation chamber evacuated using a cryopump is, for example, exhausted of compounds containing hydrogen atoms such as hydrogen atoms and water (H2O) (more preferably compounds containing carbon atoms as well), so that the concentration of impurities contained in the oxide semiconductor layer formed in the film formation chamber can be reduced. Specific formation conditions include, for example, a distance between the substrate and the target of 100 mm, a pressure of 0.6 Pa, a direct current (DC) power of 0.5 kW, and an oxygen (oxygen flow rate ratio 100%) atmosphere.

[0100]

[0101] ​ Such conditions can be applied. When using a pulsed direct current (DC) power supply, the powdery substances (also referred to as particles or dust) generated during film formation can be reduced, and the film thickness distribution can also become uniform. Therefore, it is preferable. The thickness of the oxide semiconductor layer is 2 nm or more and 200 nm or less, preferably 5 nm or more and 30 nm or less. Note that the appropriate thickness varies depending on the oxide semiconductor material to be applied. Therefore, the thickness can be appropriately selected according to the material used.

[0102] Before forming the oxide semiconductor layer by sputtering, it is preferable to perform reverse sputtering to generate plasma by introducing argon gas and remove the dust adhering to the surface of the gate insulating layer 138. Here, reverse sputtering means a method of modifying the surface by colliding ions with the processing surface, whereas in normal sputtering, ions are collided with the sputtering target. As a method of colliding ions with the processing surface, there is a method of applying a high-frequency voltage to the processing surface side in an argon atmosphere to generate plasma near the substrate. Note that a nitrogen atmosphere, a helium atmosphere, an oxygen atmosphere, etc. may be used instead of the argon atmosphere.

[0103] For etching the above oxide semiconductor layer, either dry etching or wet etching may be used. Of course, both can also be used in combination. The etching conditions (etching gas, etching solution, etching time, temperature, etc.) are appropriately set according to the material so that the desired shape can be etched.

[0104] Examples of the etching gas used for dry etching include gases containing chlorine (chlorine-based gases, For example, chlorine (Cl2), boron chloride (BCl3), silicon chloride (SiCl4), carbon tetrachloride ( Examples include CCl4, etc. Also, fluorine-containing gases (fluorinated gases, such as carbon tetrafluoride) are used. Fluorine (CF4), sulfur hexafluoride (SF6), nitrogen trifluoride (NF3), trifluoromethane (C) HF3, etc., hydrogen bromide (HBr), oxygen (O2), and helium (He) in these gases Gases to which noble gases such as argon (Ar) have been added may also be used.

[0105] As for dry etching methods, parallel plate type RIE (Reactive Ion Etching) Methods such as the ing method and ICP (Inductively Coupled Plasma: induction) A coupled plasma etching method can be used. It can etch into the desired shape. Etching conditions (amount of power applied to the coil-type electrode, amount of power applied to the electrode on the substrate side) The power consumption, electrode temperature on the substrate, etc., should be set as appropriate.

[0106] The etching solution used for wet etching is a solution of phosphoric acid, acetic acid, and nitric acid, Ammonia Hydrogenated Water (31% hydrogen peroxide by weight: 28% ammonia by weight: water = 5:2:2) These can be used. In addition, etching solutions such as ITO07N (manufactured by Kanto Chemical Co., Ltd.) can be used. It's okay to be there.

[0107] Next, it is desirable to perform a first heat treatment on the oxide semiconductor layer. This first heat treatment This allows for the dehydration or dehydrogenation of the oxide semiconductor layer. The temperature of the first heat treatment is The temperature should be between 300°C and 750°C, preferably above 400°C and below the substrate's strain point. For example, The substrate is introduced into an electric furnace using a resistance heating element, and the oxide semiconductor layer 140 is exposed to a nitrogen atmosphere. Perform a heat treatment at 450 °C for 1 hour. During this time, ensure that the oxide semiconductor layer 140 is not exposed to air and that no re-mixing of water or hydrogen occurs. Prevent exposure to air and avoid re-mixing of water or hydrogen.

[0108] Note that the heat treatment apparatus is not limited to an electric furnace, and it may be a device that heats the workpiece by heat conduction from a medium such as heated gas or by thermal radiation. For example, an RTA (Rapid Thermal Anneal) device such as a GRTA (Gas Rapid Thermal Anneal) device or an LRTA (Lamp Rapid Thermal Anneal) device can be used. An LRTA device is a device that heats the workpiece by radiation of light (electromagnetic waves) emitted from lamps such as halogen lamps, metal halide lamps, xenon arc lamps, carbon arc lamps, high-pressure sodium lamps, high-pressure mercury lamps, etc. A GRTA device is a device that performs heat treatment using a high-temperature gas. As the gas, an inert gas such as argon or a gas that does not react with the workpiece during heat treatment, such as nitrogen, is used. For example, as the first heat treatment, a GRTA treatment can be performed in which the substrate is introduced into an inert gas heated to a high temperature of 650 °C to 700 °C, heated for several minutes, and then the substrate is taken out from the inert gas. Using GRTA treatment enables high-temperature heat treatment in a short time. Also, since it is a short-time heat treatment, it can be applied even under temperature conditions exceeding the distortion point of the substrate.

[0109] Note that the first heat treatment is preferably performed in an atmosphere mainly composed of nitrogen or an inert gas (helium, neon, argon, etc.) and containing no water, hydrogen, etc. For example it is possible.

[0110] ​The purity of nitrogen, or noble gases such as helium, neon, and argon, introduced into the heat treatment apparatus, 6N (99.9999%) or higher, preferably 7N (99.99999%) or higher (i.e.) The impurity concentration shall be 1 ppm or less, preferably 0.1 ppm or less.

[0111] Depending on the conditions of the first heat treatment, or the material of the oxide semiconductor layer, the oxide semiconductor layer may crystallize. Furthermore, it may be microcrystalline or polycrystalline. For example, the crystallinity rate may be 90% or higher, or 80%. In some cases, a microcrystalline oxide semiconductor layer of % or more may be formed. Also, depending on the conditions of the first heat treatment, Depending on the material of the oxide semiconductor layer, it may become an amorphous oxide semiconductor layer that does not contain crystalline components. There are also combinations.

[0112] Furthermore, microcrystals (with a particle size of 1 nm or less) can be placed on amorphous oxide semiconductors (for example, on the surface of an oxide semiconductor layer). The oxide semiconductor layer will have a mixture of elements smaller than 20 nm (typically between 2 nm and 4 nm). In some cases, it may be the case.

[0113] Furthermore, by arranging microcrystals within an amorphous material, the electrical properties of the oxide semiconductor layer can be altered. It is also possible to use an In-Ga-Zn-O-based oxide semiconductor film deposition target. When forming an oxide semiconductor layer using In2Ga2ZnO7, which has electrical anisotropy, By forming microcrystalline regions with oriented crystal grains, the electrical properties of the oxide semiconductor layer are changed. It is possible.

[0114] More specifically, for example, if the c-axis of In2Ga2ZnO7 is perpendicular to the surface of the oxide semiconductor layer By orienting the material in a specific direction, the conductivity in the direction parallel to the surface of the oxide semiconductor layer is improved. This allows for improved insulation in the direction perpendicular to the surface of the oxide semiconductor layer. These microcrystalline regions have the function of suppressing the intrusion of impurities such as water and hydrogen into the oxide semiconductor layer. It has.

[0115] Furthermore, the oxide semiconductor layer having the above-mentioned microcrystalline portion is an oxide semiconductor layer obtained by GRTA treatment. It can be formed by surface heating. Also, the Zn content is related to the In or Ga content. By using a smaller sputtering target, it is possible to form the material more favorably.

[0116] The first heat treatment of the oxide semiconductor layer 140 involves processing it into island-shaped oxide semiconductor layers 140. This can also be done on the previous oxide semiconductor layer. In that case, after the first heat treatment, a heating device or The substrate is then removed and subjected to the photolithography process.

[0117] Furthermore, the first heat treatment described above has the effect of dehydrating and dehydrogenating the oxide semiconductor layer 140. Therefore, it can also be called a dehydration treatment, a dehydrogenation treatment, etc. Such dehydration treatment, de Hydrogenation treatment involves, after the formation of the oxide semiconductor layer, placing a source electrode or a dot on the oxide semiconductor layer 140. After stacking the rain electrodes, a protective insulating layer is formed on the source electrode or drain electrode. This can be done at times such as, and also, such dehydration treatment, dewatering The grading process can be performed multiple times, not just once.

[0118] Next, the source electrode or drain electrode 142a is brought into contact with the oxide semiconductor layer 140. A source electrode or drain electrode 142b is formed (see Figure 4(F)). The drain electrode 142a, the source electrode or drain electrode 142b are oxide semiconductor layer 1 After forming a conductive layer to cover 40, selectively etch the conductive layer by It can be formed.

[0119] The conductive layer is produced using PVD methods such as sputtering, or CVD methods such as plasma CVD. It can be formed by [doing something]. Also, the conductive layer material can be aluminum, chromium, copper, Elements selected from tantalum, titanium, molybdenum, and tungsten, or the elements mentioned above Alloys and the like can be used as components. Manganese, magnesium, zirconium, beryllium One or more materials selected from thorium and thorium may be used. Luminium, titanium, tantalum, tungsten, molybdenum, chromium, neodymium, sucrose Materials consisting of one or more elements selected from dnium may be used.

[0120] Furthermore, the conductive layer may be formed from a conductive metal oxide. Examples of conductive metal oxides include acid Indium oxide (In2O3), tin oxide (SnO2), zinc oxide (ZnO), indium oxide Indiene tin oxide alloy (In2O3-SnO2, sometimes abbreviated as ITO), indiene oxide Zinc oxide alloy (In2O3-ZnO) or silicon oxide in these metal oxide materials Alternatively, a material containing silicon oxide can be used.

[0121] The conductive layer may be a single layer or a laminated structure of two or more layers. For example, sil A single-layer structure of an aluminum film containing condensate, and a two-layer structure in which a titanium film is laminated on top of an aluminum film. Examples include a three-layer structure in which a titanium film, an aluminum film, and another titanium film are stacked.

[0122] Here, the exposure used during mask formation for etching includes ultraviolet light, KrF laser light, and ArF Using laser light is preferable.

[0123] The channel length (L) of the transistor is the length between the lower end of the source electrode or drain electrode 142a and the lower end of the source electrode or drain electrode 142a. This is determined by the distance between the source electrode or the lower end of the drain electrode 142b. When exposure is performed with a channel length (L) of less than 25 nm, the range is from a few nanometers to several tens of nanometers. For the first time, using extremely short wavelength ultraviolet light, a mask shape Perform exposure. Ultra-ultraviolet exposure provides high resolution and a large depth of field. Therefore, later The channel length (L) of the formed transistor shall be between 10 nm and 1000 nm. This is also possible, and the operating speed of the circuit can be increased. Furthermore, because the off-current value is extremely small, This prevents increased power consumption.

[0124] Furthermore, when etching the conductive layer, care is taken to ensure that the oxide semiconductor layer 140 is not removed. Adjust the materials and etching conditions as appropriate. In this process, a portion of the oxide semiconductor layer 140 is etched, and grooves (recesses) are formed. ) can also form an oxide semiconductor layer having ).

[0125] Furthermore, between the oxide semiconductor layer 140 and the source electrode or drain electrode 142a, and the oxide semiconductor An oxide conductive layer is formed between the conductive layer 140 and the source electrode or drain electrode 142b. It may also be an oxide conductive layer and a source electrode or drain electrode 142a or source electrode or The metal layer for forming the drain electrode 142b is formed continuously (continuous deposition). It is possible. The oxide conductive layer can function as either a source region or a drain region. By providing a conductive oxide layer, the resistance of the source region or drain region can be reduced. This enables high-speed operation of transistors.

[0126] Furthermore, in order to reduce the number of masks used and the number of processes, exposure is performed in which transmitted light has multiple intensities. A resist mask is formed using a multi-gradation mask, and this is used for etching. The process may be carried out. A resist mask formed using a multi-gradation mask has multiple thicknesses. It takes on a stepped shape, and the shape can be further deformed by ashing, It can be used in multiple etching processes to process different patterns. In other words, one sheet A multi-gradation mask allows for registration masks that correspond to at least two different patterns. A cavity can be formed. Therefore, the number of exposure masks can be reduced, and the corresponding cavity can be formed. Since the trisography process can also be reduced, the process can be simplified.

[0127] Furthermore, after the above-mentioned process, plasma treatment is performed using gases such as N2O, N2, or Ar. It is preferable to perform the following: The plasma treatment will cause the surface of the exposed oxide semiconductor layer to Adhering water and other substances are removed. Additionally, plasma treatment is performed using a mixed gas of oxygen and argon. You may go.

[0128] Next, a protective insulating layer 14 that is in contact with a portion of the oxide semiconductor layer 140 without being exposed to the atmosphere. Form 4 (see Figure 4(G)).

[0129] The protective insulating layer 144 is formed by methods such as sputtering, which introduces impurities such as water and hydrogen into the protective insulating layer 144. It can be formed using appropriate methods that do not involve condensation. Furthermore, its thickness is at least 1 nm. The above applies. Materials that can be used for the protective insulating layer 144 include silicon oxide, silicon nitride, Examples include silicon oxide nitride and silicon oxide nitride. Furthermore, their structure can be a single-layer structure. A laminated structure is also acceptable. The substrate temperature when forming the protective insulating layer 144 should be above room temperature and up to 300°C. The following is preferable, and the atmosphere should be a noble gas atmosphere (typically argon) or an oxygen atmosphere. Alternatively, a mixed atmosphere of a noble gas (typically argon) and oxygen is preferred.

[0130] If hydrogen is present in the protective insulating layer 144, the hydrogen may penetrate into the oxide semiconductor layer, and the hydrogen may... This can lead to oxygen abstraction in the oxide semiconductor layer, and the back channel side of the oxide semiconductor layer This can lead to a decrease in resistance and the formation of parasitic channels. Therefore, protective insulating layer 1 It is important to avoid using hydrogen in the formation process of 44, as it contains as little hydrogen as possible. That is the case.

[0131] Furthermore, it is preferable to form the protective insulating layer 144 while removing residual moisture in the processing chamber. The ion semiconductor layer 140 and the protective insulating layer 144 are designed to not contain hydrogen, hydroxyl groups, or water. That is the reason.

[0132] To remove residual moisture from the processing chamber, it is preferable to use an adsorption-type vacuum pump. For example, cryopumps, ion pumps, and titanium sublimation pumps can be used. It is preferable. Furthermore, as an exhaust method, a turbo pump with a cold trap is used. It is also acceptable. The deposition chamber, which has been evacuated using a cryopump, contains, for example, hydrogen atoms and water (H2 Because compounds containing hydrogen atoms, such as O), are removed, the protective insulation formed in the deposition chamber is The concentration of impurities in layer 144 can be reduced.

[0133] The sputtering gas used when forming the protective insulating layer 144 may be hydrogen, water, hydroxyl groups or The concentration of impurities such as hydrides is reduced to about a few ppm (preferably, about a few ppb). It is preferable to use a highly purified gas from which the gas has been removed.

[0134] Next, a second heat treatment (preferably 20) is performed under an inert gas atmosphere or an oxygen gas atmosphere. It is desirable to perform the procedure at temperatures between 0°C and 400°C (for example, between 250°C and 350°C). Next, a second heat treatment is performed at 250°C for 1 hour under a nitrogen atmosphere. After the second heat treatment, This can reduce variations in the electrical characteristics of the converter.

[0135] Furthermore, even if heat treatment is performed in air at temperatures between 100°C and 200°C for 1 hour to 30 hours Good. This heat treatment may be performed by heating while maintaining a constant heating temperature, or from room temperature to 100°C or higher. The process involves repeatedly raising the temperature to a heating temperature of 200°C or lower, and then lowering it from the heating temperature back to room temperature. This may be done. Alternatively, this heat treatment may be performed under reduced pressure before the formation of the protective insulating layer. Performing heat treatment under reduced pressure can shorten the heating time. Note that this heat treatment is as described above. This can be performed in place of the second heat treatment, or before or after the second heat treatment.

[0136] Next, an interlayer insulating layer 146 is formed on the protective insulating layer 144 (see Figure 5(A)). The marginal layer 146 can be formed using methods such as PVD or CVD. Silicon nitride, silicon nitride, hafnium oxide, aluminum oxide, tantalum oxide Formation of interlayer insulating layer 146 is possible using materials containing inorganic insulating materials such as ru. Afterward, it is desirable to planarize the surface using methods such as CMP or etching. It's nice.

[0137] Next, the interlayer insulating layer 146, the protective insulating layer 144, and the gate insulating layer 138 are treated with electrode 1 36a, electrode 136b, electrode 136c, source electrode or drain electrode 142a, source An opening is formed that reaches the electrode or drain electrode 142b, and the electrode is embedded in the opening. A conductive layer 148 is formed (see Figure 5(B)). The above opening is made by etching using a mask, etc. It can be formed by the following method. The mask can be formed by methods such as exposure using a photomask. Therefore, it is possible to form it. Etching methods include wet etching and dry etching. Either etching method can be used, but from the perspective of microfabrication, dry etching is recommended. The following is preferable. The conductive layer 148 is formed using a film deposition method such as PVD or CVD. This is possible. Materials that can be used to form the conductive layer 148 include molybdenum, cyanoacrylate, and cyanoacrylate. Tan, chromium, tantalum, tungsten, aluminum, copper, neodymium, scandium Examples include conductive materials, their alloys, and compounds (such as nitrides).

[0138] Specifically, for example, a thin titanium film is formed in the region including the opening by the PVD method, and then the CVD method is applied. After forming a thin titanium nitride film, a tungsten film is formed to fill the opening. The following method can be applied. Here, the titanium film formed by the PVD method is the lower electric Electrodes (here, electrode 136a, electrode 136b, electrode 136c, source electrode or drain) The oxide film at the interface between electrode 142a and the source electrode or drain electrode 142b is reduced, It has the function of reducing contact resistance with the electrode. Furthermore, the titanium nitride formed thereafter is It also has a barrier function that suppresses the diffusion of conductive materials. After forming the barrier film, a copper film may be formed by a plating method.

[0139] After forming the conductive layer 148, the conductive layer 148 is processed using methods such as etching and CMP. By removing a portion and exposing the interlayer insulating layer 146, electrodes 150a, 150b, and 15 0c, electrode 150d, and electrode 150e are formed (see Figure 5(C)). Note that the above conductive layer 1 Remove a portion of 48 to obtain electrode 150a, electrode 150b, electrode 150c, electrode 150d, electrode When forming 150e, it is desirable to process the surface so that it becomes flat. The interlayer insulating layer 146, electrode 150a, electrode 150b, electrode 150c, electrode 150d, By planarizing the surface of electrode 150e, good electrodes, wiring, and insulation can be achieved in subsequent processes. This makes it possible to form layers, semiconductor layers, and so on.

[0140] Furthermore, an insulating layer 152 is formed, and electrodes 150a, 150b, and 1 An opening is formed that extends to electrode 50c, electrode 150d, and electrode 150e, and the material is embedded in the opening. After forming a conductive layer, a portion of the conductive layer is removed using methods such as etching or CMP. , exposing the insulating layer 152, electrode 154a, electrode 154b, electrode 154c, electrode 154 Form d (see Figure 5(D)). This step is the same as when forming electrode 150a, etc. Since there is some information available, I will omit the details.

[0141] When transistor 162 is fabricated using the method described above, the hydrogen concentration of the oxide semiconductor layer 140 The degree is 5x10 19 atoms / cm 3 The following applies, and also the off-current of transistor 162. is 1 x 10 -13 It becomes A or less. In this way, the hydrogen concentration is sufficiently reduced and the purity is increased. By applying the oxide semiconductor layer 140, a transistor 162 with excellent characteristics can be obtained. This is possible. Furthermore, it has a transistor 160 at the bottom made of a material other than an oxide semiconductor, and the top To fabricate a semiconductor device with excellent properties having a transistor 162 made of oxide semiconductor in the part. It is possible.

[0142] Furthermore, as a semiconductor material that can be compared to oxide semiconductors, silicon carbide (for example, 4H) is a suitable example. There is -SiC). Oxide semiconductors and 4H-SiC have several things in common. The riah density is one example. The intrinsic carrier density of oxide semiconductors at room temperature is 10 -7 / cm 3 It is estimated to be around 6.7 × 10 in 4H-SiC. -11 / cm 3 and Similarly, the intrinsic carrier density of silicon is (1.4 × 10⁻⁶). 10 / cm 3 degree Comparing it to a degree makes it clear just how extraordinary its level is.

[0143] Furthermore, the energy band gap of oxide semiconductors is 3.0~3.5eV, and 4H-S Since the energy bandgap of iC is 3.26 eV, it is a wide-bandgap semiconductor. In this respect, oxide semiconductors and silicon carbide have something in common.

[0144] On the other hand, there is a very significant difference between oxide semiconductors and silicon carbide. This is the process temperature. For example, in semiconductor processes using silicon carbide, dopant activation requires 1 Because it requires heat treatment at 500°C to 2000°C, it differs from semiconductor devices using other semiconductor materials. Such a layered structure is difficult. At such high temperatures, semiconductor substrates and semiconductor elements will be destroyed. This is because it will be affected. On the other hand, oxide semiconductors have a glass transition temperature of 300°C to 500°C. The following can be manufactured by heat treatment (up to approximately 700°C), and other semiconductor materials By using this method to form an integrated circuit, it becomes possible to form semiconductor elements using oxide semiconductors. Yes.

[0145] Furthermore, unlike with silicon carbide, it is possible to use substrates with low heat resistance, such as glass substrates. It has the advantage of not requiring high-temperature heat treatment. It has the advantage of being able to keep energy costs sufficiently low.

[0146] Furthermore, while much research has been done on the physical properties of oxide semiconductors, this research is related to energy The invention disclosed does not include the idea of ​​sufficiently reducing the localized energy levels within the G-gap itself. In one embodiment, water and hydrogen, which can be the cause of localized energy levels, are removed from the oxide semiconductor. We will fabricate highly purified oxide semiconductors. This is because the localized energy levels in the energy gap themselves... It is based on the idea of ​​significantly reducing it. And by doing so, extremely excellent This enables the manufacture of industrial products.

[0147] Furthermore, when removing hydrogen or water, oxygen may also be removed at the same time. Therefore, oxygen is supplied to the unbonded metals that occur due to oxygen deficiency, and localization due to oxygen vacancies. By reducing the number of existing energy levels, an even higher purity (type i) oxide semiconductor can be obtained. This is possible. For example, by forming an oxygen-rich oxide film in close proximity to the channel-forming region. By performing heat treatment at temperatures between 200°C and 400°C, typically around 250°C, the It is possible to reduce localized energy levels caused by oxygen vacancies by supplying oxygen from the oxide film.

[0148] Following the second heat treatment, a precipitation procedure is performed in an oxygen atmosphere, or in an atmosphere from which hydrogen and water have been thoroughly removed. It is also possible to supply oxygen to oxide semiconductors through a thermal process.

[0149] In oxide semiconductors, donors are located in the shallow zone below the conduction band (0.1 eV to 0.2 eV) due to excess hydrogen. These defects are thought to be caused by factors such as the position of the oxygen or deep energy levels due to oxygen deficiency. The technological concept of thoroughly removing hydrogen and supplying sufficient oxygen to achieve this is correct. That is probably the case.

[0150] Furthermore, although oxide semiconductors are generally considered to be n-type, in one aspect of the disclosed invention, impurities, In particular, the removal of water and hydrogen is used to achieve the i-type transformation. In this respect, silicon and other materials Since this is not a type i formation process that involves adding impurities, it can be said to involve a new technological concept that is unlike anything before. .

[0151] <Conductivity mechanism of transistors using oxide semiconductors> Here, the conductivity mechanism of an oxide semiconductor transistor will be explained using Figures 6 to 9. To clarify, the following explanation assumes an ideal situation for the sake of ease of understanding. Not everything reflects reality. Also, the following explanation is merely one possible interpretation. It should be noted that this is merely a minor detail and does not affect the effectiveness of the invention.

[0152] Figure 6 is a cross-sectional view of a transistor (thin-film transistor) using an oxide semiconductor. An oxide semiconductor layer (OS) is provided on the gate electrode (GE1) via a gate insulating layer (GI). A source electrode (S) and a drain electrode (D) are provided on top of it, and the source electrode (S) An insulating layer is provided so as to cover the drain electrode (D).

[0153] Figure 7 shows the energy band diagram (schematic diagram) in the A-A' section of Figure 6. In diagram 7, the black circles (●) represent electrons, and the white circles (○) represent holes, with their respective charges (-q, +q). ) has a positive voltage (V) across the drain electrode. D After applying >0), the dashed line represents the gate voltage. When no voltage is applied to the pole (V G (=0), the solid line represents a positive voltage (V) across the gate electrode. G Mark >0) This shows the case where voltage is applied. When no voltage is applied to the gate electrode, the high potential barrier is due to This indicates an off state where no carriers (electrons) are injected from the electrode to the oxide semiconductor, resulting in no current flow. On the other hand, applying a positive voltage to the gate lowers the potential barrier, allowing current to flow. To show a certain state.

[0154] Figure 8 shows a schematic diagram of the energy bands in the cross-section B-B' in Figure 6. Figure 8(A) shows a positive voltage (V) applied to the gate electrode (GE1). G The given state is >0. This indicates the ON state, where carriers (electrons) flow between the source electrode and the drain electrode. Furthermore, Figure 8(B) shows a negative voltage (V) applied to the gate electrode (GE1). G With <0) applied This indicates the off state (where minority carriers are not flowing).

[0155] Figure 9 shows the vacuum level and the work function of the metal (φ M ), the relationship of electron affinity (χ) of oxide semiconductors show.

[0156] At room temperature, electrons in metals are degenerate, and the Fermi level is located within the conduction band. On the other hand, Conventional oxide semiconductors are n-type, and their Fermi level (E F ) is at the center of the band gap The intrinsic Fermi level (E) is located there. i It is located away from the conduction band and closer to it. In semiconductor materials, it is known that some hydrogen acts as a donor, which is one of the factors that causes n-type semiconductors. Yes, they are.

[0157] In contrast, the oxide semiconductor according to one aspect of the disclosed invention uses hydrogen, which is a factor in n-type formation, as an acid By removing elements from oxide semiconductors, the oxide semiconductor contains as few elements other than the main components (impurity elements) as possible. By increasing the purity in such a way, it is made into true (type i), or attempted to be made into true. In other words, instead of adding impurity elements to create type i, impurities such as hydrogen and water are removed as much as possible. This process is characterized by producing highly purified type i (intrinsic semiconductor) or something close to it. This results in the Fermi level (E F ) is the true Fermi level (E i ) to the same extent as It is possible.

[0158] Band gap (E) of oxide semiconductors g The voltage is 3.15 eV, and the electron affinity (χ) is 4.3 V It is said that the work function of titanium (Ti) that makes up the source electrode and drain electrode is , is approximately equal to the electron affinity (χ) of the oxide semiconductor. In this case, at the metal-oxide semiconductor interface In this case, no Schottky-type barrier is formed for electrons.

[0159] At this time, as shown in Figure 8(A), electrons are in the gate insulating layer and the highly purified oxide semiconductor. It moves near the interface (the lowest, most energetically stable part of the oxide semiconductor).

[0160] Furthermore, as shown in Figure 8(B), when a negative potential is applied to the gate electrode (GE1), a decimal Since the number of holes, which act as carriers, is virtually zero, the current will be extremely close to zero.

[0161] In this way, high purity is achieved by minimizing the presence of elements other than the main components of oxide semiconductors (impurity elements). By degree conversion, it becomes intrinsic (type i) or substantially intrinsic, thus the gate insulating layer The interfacial properties with the semiconductor become apparent. Therefore, the gate insulating layer has a good interface with the oxide semiconductor. The ability to form such a thing is required. Specifically, for example, power supply frequencies in the VHF band to microwave band. Insulating layers fabricated by CVD using high-density plasma generated in large quantities, and sputtering It is preferable to use an insulating layer manufactured by law.

[0162] To improve the purity of the oxide semiconductor while ensuring a good interface between the oxide semiconductor and the gate insulating layer. By doing so, for example, the channel width (W) of the transistor becomes 1 × 10 4 μm, channel length If (L) is 3 μm, then 10 -13 Off-current of less than A, sub-voltage of 0.1V / dec. A threshold swing value (S value) (gate insulating layer thickness: 100 nm) can be achieved.

[0163] In this way, the oxide semiconductor is processed to minimize the presence of elements other than its main component (impurity elements). Purification can improve the operation of transistors.

[0164] <Variation> Figures 10 to 13 show modified configurations of semiconductor devices. In the following description, these are modified configurations. Next, we will explain a configuration of transistor 162 that differs from the above. The configuration of the Zista 160 is the same as described above.

[0165] Figure 10 shows a gate electrode 136d located beneath an oxide semiconductor layer 140, and a source electrode or The drain electrode 142a, or the source electrode or drain electrode 142b, is located in the oxide semiconductor layer 1 The transistor 162 has a configuration in which it is in contact with the oxide semiconductor layer 140 on the lower surface of 40. An example of a semiconductor device is shown. Note that the planar structure can be modified as appropriate to correspond to the cross-section. Here, we will only show the cross-section.

[0166] A major difference between the configuration shown in Figure 10 and the configuration shown in Figure 2 is the source electrode or drain electrode. The contact between the electrode 142a, or the source electrode or drain electrode 142b, and the oxide semiconductor layer 140. There is a continuation position. In other words, in the configuration shown in Figure 2, on the upper surface of the oxide semiconductor layer 140 The source electrode or drain electrode 142a, or the source electrode or drain electrode 142b In contrast to the configuration shown in Figure 10, the lower surface of the oxide semiconductor layer 140 is in contact with , source electrode or drain electrode 142a, or source electrode or drain electrode 142b They make contact. And due to this difference in contact, the arrangement of other electrodes, insulating layers, etc., is different. The details of each component are the same as in Figure 2.

[0167] Specifically, the semiconductor device has a gate electrode 136d provided on the interlayer insulating layer 128, and A gate insulating layer 138 provided on the electrode 136d, and provided on the gate insulating layer 138 Furthermore, source electrode or drain electrode 142a, source electrode or drain electrode 142b and , on the source electrode or drain electrode 142a, source electrode or drain electrode 142b It has an oxide semiconductor layer 140 in contact with the side surface.

[0168] Here, the gate electrode 136d is embedded in the insulating layer 132 formed on the interlayer insulating layer 128. It is provided so as to be inserted. Also, similar to the gate electrode 136d, the source electrode or Electrode 136a is in contact with drain electrode 130a, and is connected to source electrode or drain electrode 130b Electrode 136b is formed in contact with electrode 130c, and electrode 136c is formed in contact with electrode 130c. ru.

[0169] Furthermore, a protective layer is placed on top of the transistor 162 so as to be in contact with a portion of the oxide semiconductor layer 140. An insulating layer 144 is provided, and an interlayer insulating layer 146 is provided on the protective insulating layer 144. Here, the protective insulating layer 144 and the interlayer insulating layer 146 have a source electrode or drain. An opening is provided that reaches the source electrode 142a, or the drain electrode 142b. Furthermore, through the opening, electrodes 150d and 150e are connected to the source electrode or drain electrode. It is formed in contact with electrode 142a, source electrode or drain electrode 142b. Similar to pole 150d and electrode 150e, the gate insulating layer 138, protective insulating layer 144, and interlayer insulating layer Through the opening provided in layer 146, electrodes 136a, 136b, and 136c are in contact. Electrodes 150a, 150b, and 150c are formed.

[0170] Furthermore, an insulating layer 152 is provided on the interlayer insulating layer 146, and embedded in the insulating layer 152. Electrodes 154a, 154b, 154c, and 154d are provided so as to be inserted. Here, electrode 154a is in contact with electrode 150a, and electrode 154b is in contact with electrode 150 It is in contact with b, and electrode 154c is in contact with electrode 150c and electrode 150d, and electrode 1 Electrode 54d is in contact with electrode 150e.

[0171] Figure 11 shows an example of a configuration having a gate electrode 136d on an oxide semiconductor layer 140. Here, Figure 11(A) shows the source electrode or drain electrode 142a, or the source electrode or drain The rain electrode 142b is located on the lower surface of the oxide semiconductor layer 140. This is an example of a configuration in which the source electrode or drain electrode 142a is in contact with the following: Figure 11(B) shows the source electrode or drain electrode 142a, The source electrode or drain electrode 142b is acid on the upper surface of the oxide semiconductor layer 140. This is an example of a configuration in which the ionized semiconductor layer 140 is in contact with the semiconductor layer.

[0172] The main difference between the configurations shown in Figures 2 and 10 and the configuration shown in Figure 11 is the oxide semiconductor layer 140. The point is that it has a gate electrode 136d on top. Also, the configuration shown in Figure 11(A) and Figure 11(B) The major difference in the configuration shown is the source electrode or drain electrode 142a, or the source electrode Alternatively, the drain electrode 142b is either on the lower or upper surface of the oxide semiconductor layer 140. The point is whether or not contact occurs in that situation. And due to these differences, other electricity The arrangement of electrodes, insulating layers, etc., differs. Details of each component are the same as in Figure 2, etc. That is the case.

[0173] Specifically, the semiconductor device shown in Figure 11(A) has a source provided on the interlayer insulating layer 128. Electrode or drain electrode 142a, source electrode or drain electrode 142b, and source electrode Contact the upper surface of the electrode or drain electrode 142a, or the source electrode or drain electrode 142b. An oxide semiconductor layer 140 and a gate insulating layer 138 provided on the oxide semiconductor layer 140 And the gate electrode 136d in the region overlapping with the oxide semiconductor layer 140 on the gate insulating layer 138. It has, and

[0174] Furthermore, the semiconductor device shown in Figure 11(B) is an oxide semiconductor provided on an interlayer insulating layer 128. The layer 140 and the source electrode provided so as to be in contact with the upper surface of the oxide semiconductor layer 140 It consists of a drain electrode 142a, a source electrode or drain electrode 142b, and an oxide semiconductor layer 1 40, source electrode or drain electrode 142a, and source electrode or drain electrode A gate insulating layer 138 provided on 142b, and an oxide semiconductor layer on the gate insulating layer 138 It has a gate electrode 136d in a region that overlaps with 140.

[0175] In addition, in the configuration shown in Figure 11, compared to the configuration shown in Figure 2, etc., some components can be omitted. There are combinations (for example, electrode 150a and electrode 154a). In this case, the manufacturing process is simplified. This also provides the secondary effect of... It goes without saying that some components can be omitted.

[0176] Figure 12 shows the case where the device size is relatively large, with a gauge below the oxide semiconductor layer 140. This is an example of a configuration having an electrode 136d. In this case, the flatness of the surface and coverage Since the requirements are relatively lenient, the wiring and electrodes are formed to be embedded within the insulating layer. It is not necessary. For example, by performing patterning after the formation of the conductive layer, the gate electrode 13 It is possible to form 6d, etc. Although not shown in the diagram here, transistor 16 The value 0 can also be created in the same way.

[0177] The main difference between the configuration shown in Figure 12(A) and the configuration shown in Figure 12(B) is the source electrode or The drain electrode 142a, or the source electrode or drain electrode 142b, is located in the oxide semiconductor layer 1 The point is whether contact occurs on the lower or upper surface of 40. These differences result in variations in the arrangement of other electrodes, insulating layers, and other components. The details of each component are the same as in Figure 2, etc.

[0178] Specifically, the semiconductor device shown in Figure 12(A) has a gate provided on the interlayer insulating layer 128. Electrode 136d, gate insulating layer 138 provided on gate electrode 136d, gate insulating A source electrode or drain electrode 142a is provided on layer 138, source electrode or drain Rain electrode 142b and source electrode or drain electrode 142a, source electrode or drain It has an oxide semiconductor layer 140 in contact with the upper surface of the in electrode 142b.

[0179] Furthermore, the semiconductor device shown in Figure 12(B) has a gate electrode 1 provided on the interlayer insulating layer 128. 36d, gate insulating layer 138 provided on gate electrode 136d, and gate insulating layer 13 An oxide semiconductor layer 140 is provided in the region overlapping with the gate electrode 136d on 8, and an oxide Source electrode or drain electrode 14 provided so as to be in contact with the upper surface of the semiconductor layer 140 2a, a source electrode or drain electrode 142b, and

[0180] Furthermore, in the configuration shown in Figure 12, compared to the configuration shown in Figure 2, etc., some components can be omitted. In some cases, this is possible. In this case as well, the benefit of simplifying the manufacturing process can be obtained.

[0181] Figure 13 shows the case where the device size is relatively large, with a gauge on the oxide semiconductor layer 140. This is an example of a configuration having an electrode 136d. In this case as well, surface flatness and coverage The requirements are relatively lenient, so wiring and electrodes can be embedded in the insulating layer. It is not necessary to form it. For example, by patterning after the formation of the conductive layer, the gate electrode It is possible to form 136d and the like. Note that, although not shown in the diagram, transistors The same process can be used to manufacture the 160.

[0182] The main difference between the configuration shown in Figure 13(A) and the configuration shown in Figure 13(B) is the source electrode or The drain electrode 142a, or the source electrode or drain electrode 142b, is located in the oxide semiconductor layer 1 The point is whether contact occurs on the lower or upper surface of 40. These differences result in variations in the arrangement of other electrodes, insulating layers, and other components. The details of each component are the same as in Figure 2, etc.

[0183] Specifically, the semiconductor device shown in Figure 13(A) has a source provided on the interlayer insulating layer 128. Electrode or drain electrode 142a, source electrode or drain electrode 142b, and source electrode Contact the upper surface of the electrode or drain electrode 142a, or the source electrode or drain electrode 142b. The oxide semiconductor layer 140, the source electrode or drain electrode 142a, and the source electrode The drain electrode 142b and the gate insulating layer 138 provided on the oxide semiconductor layer 140, A gate electrode 1 is provided in the region that overlaps with the oxide semiconductor layer 140 on the gate insulating layer 138. It has 36d and .

[0184] Furthermore, the semiconductor device shown in Figure 13(B) is an oxide semiconductor provided on an interlayer insulating layer 128. The layer 140 and the source electrode provided so as to be in contact with the upper surface of the oxide semiconductor layer 140 The drain electrode 142a, the source electrode or drain electrode 142b, and the source electrode or Drain electrode 142a, source electrode or drain electrode 142b, oxide semiconductor layer 140 A gate insulating layer 138 provided on top, and an oxide semiconductor layer 140 on the gate insulating layer 138 It has a gate electrode 136d provided in the overlapping region.

[0185] Furthermore, in the configuration shown in Figure 13, compared to the configuration shown in Figure 2, etc., some components can be omitted. In some cases, this is possible. In this case as well, the benefit of simplifying the manufacturing process can be obtained.

[0186] As described above, one aspect of the disclosed invention realizes a semiconductor device with a new configuration. In this embodiment, transistors 160 and 162 are stacked to form the transistor. Although an example has been given, the configuration of the semiconductor device is not limited to this. In this configuration, the channel length directions of transistors 160 and 162 are perpendicular to each other. I have explained an example, but the positional relationship between transistor 160 and transistor 162 is not the same. It is not limited. Furthermore, by superimposing transistor 160 and transistor 162 It is permissible to set one up.

[0187] Furthermore, in this embodiment, for the sake of ease of understanding, the semiconductor device is the smallest memory unit (1 bit). As explained above, the configuration of semiconductor devices is not limited to this. Multiple semiconductor devices can be used. By connecting them appropriately, it is also possible to configure more advanced semiconductor devices. For example, the above semiconductor device By using multiple units, it is possible to configure NAND and NOR type semiconductor devices. The configuration is not limited to Figure 1 and can be changed as appropriate.

[0188] The semiconductor device according to this embodiment is extremely efficient due to the low off-current characteristics of the transistor 162. It is possible to retain information for a long period of time. In other words, it is required for DRAM, etc. Refresh operations are unnecessary, and power consumption can be reduced. Furthermore, it is virtually non-volatile. It can be used as a self-sustaining memory device.

[0189] Furthermore, information is written through the switching operation of transistor 162, It does not require high voltage and there are no issues with component degradation. Furthermore, the on / off switching of the transistor... Therefore, because information is written to and erased, high-speed operation can be easily achieved. Also, It is unnecessary to perform an operation to erase information required in flash memory, etc. There are also advantages.

[0190] Furthermore, transistors using materials other than oxide semiconductors are different from transistors using oxide semiconductors. Compared to standard, it allows for even faster operation, and by using this, the stored contents can be processed It is possible to perform reading at high speed.

[0191] The configurations and methods shown in this embodiment may be combined with the configurations and methods shown in other embodiments as appropriate. They can be used together.

[0192] (Embodiment 2) This embodiment describes the circuit configuration and operation of a semiconductor device according to one aspect of the present invention. do.

[0193] Figure 14 shows an example of a circuit diagram of a semiconductor device (hereinafter also referred to as a memory cell). Memory cell 200 has a source line SL, a bit line BL, a first signal line S1, and a second signal line S2, word line WL, transistor 201, transistor 202, transistor It consists of transistors 201 and 203. Transistors 201 and 203 are made of oxide It is formed using materials other than semiconductors, and transistor 202 uses an oxide semiconductor. It is formed.

[0194] Here, the gate electrode of transistor 201 and the source electrode or dot of transistor 202 It is electrically connected to one of the rain electrodes. Also, the source wire SL and the transistor The source electrode of transistor 201 is electrically connected to the drain electrode of transistor 201, and The source electrode of the transistor 203 is electrically connected. And the bit line BL and The drain electrode of transistor 203 is electrically connected to the first signal line S1, and the transistor The source electrode or drain electrode of the converter 202 is electrically connected to the other, and the second signal Line S2 and the gate electrode of transistor 202 are electrically connected to the word line WL. It is electrically connected to the gate electrode of transistor 203.

[0195] Figure 15 shows an example of the writing circuit 211. The first signal line S1 is used via a switch for writing. It is electrically connected to the loaded potential Vwrite or Vs1_0. The above switch is a signal It is controlled by Φw1 and signal Φw2.

[0196] Figure 16 shows an example of the readout circuit 212. The readout circuit 212 uses a sense amplifier circuit. It has. The read circuit 212 is electrically connected to the bit line BL. The bit line BL is One terminal of resistor R is connected via a switch. The other terminal of resistor R is connected to Vdd. It is determined by the resistance ratio between resistor R and the load connected to bit line BL. The potential Vin is input to one of the input terminals of the sense amplifier circuit. One of the input terminals of the circuit is connected to the bit line BL via a switch, etc., and the potential Vin This is also called the potential of the bit line. Resistance R is not limited to resistive elements, but can function as an effective resistor. Often, this involves diode connections in transistors, or controlling the gate electrode with other signals. It can be a transistor or any other circuit. The input terminal of the sense amplifier circuit The other end of the child is connected to the read potential Vread. Also, the bit line BL is a switch. It is connected to potential VBL_0 via the above switch. The above switch is connected to signals Φr1 and Φr2. Therefore, it is controlled.

[0197] Next, we will explain the write and read operations of the memory cell 200 shown in Figure 14. The Morissel 200, depending on the charge or potential accumulated at node A, controls transistor 2 Because the effective resistance of 01 changes, it can take on various states. And the transient Since the off-current of TA202 is extremely small, or practically zero, the charge at node A, Alternatively, the potential is maintained for a long period of time. In the following explanation, "writing" refers to "memo". This refers to transferring memory cells to a predetermined state by charging and discharging node A of the recell. Reading refers to comparing the potential, which is determined according to the state of the memory cell, with a predetermined potential. The terms "write" and "read" can also be used in the following senses, depending on the context: write, or Data writing refers to a series of operations that write predetermined data to a memory cell. Reading Or, data reading refers to a series of operations to read data stored in a memory cell. cormorant.

[0198] When writing to memory cell 200, set source line SL to 0V and word line WL to 0V. By turning transistor 203 to the OFF state, and setting the second signal line S2 to Vdd, transistor 20 Set 2 to the ON state. The read circuit 212 connected to the bit line BL receives the signal Φr2. The signal Φr1 is activated and deasserted. As a result, bit line B The potential VBL_0 is applied to L. The programming circuit 211 is connected to the first signal line S1. This deasserts signal Φw2 and asserts signal Φw1 to enter the write state. As a result, a write potential Vwrite corresponding to the data to be written is applied to the first signal line. Oh, when writing is finished, before the potential of the first signal line S1 changes, the second signal line S Set 2 to 0V and turn off transistor 202.

[0199] As a result, a charge corresponding to the potential Vwrite of the first signal line is accumulated at node A, and data The state corresponding to the terminal is written. The off-current of transistor 202 is extremely small, or Since it is essentially 0, the potential of the gate electrode of transistor 201 can be maintained for a long time. It is held.

[0200] When reading from memory cell 200, set source line SL to 0V and word line WL to Vd Let d be the ON state of transistor 203, and set the second signal line S2 to 0V. 202 is set to the OFF state. The writing circuit 211 connected to the first signal line S1 receives the signal Φw Assert 2 and deassert signal Φw1. As a result, VS1_0 is marked on the first signal line. The readout circuit 212 connected to the bit line BL deasserts the signal Φr2. Assert signal Φr1 to enter read operation mode.

[0201] As a result, depending on the state of node A of memory cell 200, the transient of memory cell 200 The effective resistance value of 201 is determined. The read circuit 212 reads the transistor of the memory cell 200. The potential Vin (potential Vin of the bit line) is determined according to the effective resistance of ZISTA 201, Readout is performed by comparing the readout potential Vread.

[0202] Note that the "bit line potential Vin (potential Vin)" used for comparison during reading is a switch. The potential of the node at the input terminal of the sense amplifier circuit, which is connected to the bit line via a cable, etc., is included. It shall be assumed that the potentials compared in the readout circuit are strictly the potentials of the bit lines. It does not need to be identical.

[0203] Next, a writing operation, which is one aspect of the present invention, will be described. Writing operation, one aspect of the present invention As shown in Figure 17, the first write (write for obtaining variation information), the first Reading (reading to obtain variation information), second write (data to be stored) It involves three steps (writing). Each step is explained below.

[0204] The first write operation aims to initialize the memory cell, writing the memory cell to a predetermined state. Specifically, Vwi (initialization potential) is used as the write potential Vwrite, as described above. Perform the write operation.

[0205] The first read operation aims to acquire information on the variability of the memory cells. The threshold voltage of the transistor 201 varies depending on the memory cell. For example, as shown in FIG. 18(A), it has a distribution as shown.

[0206] As a result, after the first writing operation, when the above-described reading operation is performed, the potential Vin of the node at the input terminal of the sense amplifier circuit (or the potential of the bit line BL) determined according to the effective resistance value of the memory cell also varies depending on the memory cell. For example, as shown in FIG. 18(B), it has a distribution as shown. it has a distribution as shown.

[0207] Therefore, in the first reading, in order to obtain the variation information of the memory cell, a detailed reading of the potential Vin of the bit line BL related to the reading is performed. Specifically, as the reading potential Vread given to the sense amplifier circuit in the reading circuit 21 2, a potential Vri_j (j is an integer not less than 0 and less than m) selected from a plurality of potentials Vri_ 0 to Vri_m (m is an integer greater than 0) is used to compare Vin with Vri_j. The comparison is performed a plurality of times by changing j in Vri_j. As a result, it is determined which interval (the interval delimited by Vri_j and Vri_(j + 1)) the potential Vin of the bit line related to the reading belongs to. 0 to Vri_m (m is an integer greater than 0) is used to compare Vin with Vri_j. The comparison is performed a plurality of times by changing j in Vri_j. As a result, it is determined which interval (the interval delimited by Vri_j and Vri_(j + 1)) the potential Vin of the bit line related to the reading belongs to. At Vri_j, By changing j, the comparison is performed multiple times. As a result, it is determined which interval (the interval delimited by Vri_j and Vri_(j + 1)) the potential Vin of the bit line related to the reading belongs to. The interval delimited by Vri_j (the interval delimited by Vri_j and Vri_(j + 1)) to which it belongs is determined.

[0208] Each of the plurality of potentials Vri_j (j is an integer not less than 0 and not more than m) is determined such that, for example, in a memory cell where the threshold voltage Vth of the transistor 201 satisfies V0 + j×ΔVth < Vth < V0 + (j + 1)×ΔV th, Vri_j < Vin < Vri_(j + 1). Among the intervals delimited by V0 + j×ΔVth (j is an integer not less than 0 and not more than m), the interval delimited by V0 + i×ΔVth and V0 + (i + 1)×ΔVth is defined as interval i (i is an integer not less than ] 0). Let us call this an integer less than or equal to m-1. A Vri_j that satisfies this condition is, for example, It is possible to determine this through simulations and experiments.

[0209] V0, m, and ΔVth are the threshold voltages of transistor 201 that a normal memory cell has. The interval is determined to be between V0 and V0+(m+1)×ΔVth. ΔVth is a quantity that determines the distribution width of the memory cell state after writing. If ΔVth is small, writing The distribution of the memory cell states becomes narrower afterward. The degree of multi-level data written to the memory cell. The value is determined by considering factors such as "n" and the power supply potential.

[0210] Note that the variation in Vri is mainly due to the variation in Vth of transistor 201, but other Variations due to the following factors are also possible. In other words, even if the Vth of transistor 201 is fixed The potential Vin is still thought to have a narrow distribution. When considering this, a more precise calculation is needed. This can be achieved by setting Vri_j to, for example, a representative value of the distribution of Vri_j.

[0211] In the first readout, multiple potentials Vri_0 to Vri_m (where m is an integer greater than 0) The method of making multiple comparisons using this will be explained with an example. For example, multiple potentials Vri_1~ By comparing Vri_(m-1) sequentially m-1 times, the transistor 20 of the memory cell It is possible to determine which interval a threshold voltage Vth of 1 belongs to.

[0212] Furthermore, as shown in Figure 19, a method is used in which the comparison results are fed back and comparisons are repeated. It is also possible to perform three comparisons using Figure 19 for the case where m=8. How to determine which interval the threshold voltage Vth of Morissel transistor 201 belongs to. Explain the law.

[0213] First, as the read potential Vread, the midpoint of multiple potentials Vri_0 to Vri_8 is The first comparison is made using the potential Vri_4, which is the electric potential, with the potential Vin. The comparison results showed that the output of the sense amplifier circuit was "0" (SA_OUT="0"), meaning the potential Vi When n < potential Vri_4, it is the potential near the center of multiple potentials Vri_1 to Vri_4. Then, read out potential Vri_2 as potential Vread and perform a second comparison with potential Vin. Also, the output of the sense amplifier circuit is "1" (SA_OUT="1"), meaning the potential Vin >In the case of potential Vri_4, it is a potential near the center of multiple potentials Vri_4 to Vri_7. The potential Vri_6 is read out as the potential Vread, and a second comparison is made with the potential Vin.

[0214] The potential Vri_2 was read out and set as the potential Vread. The comparison result showed SA_OUT = "0". In other words, if potential Vin < potential Vri_2, read potential Vri_1 and potential Vread and Then, a third comparison with the potential Vin is performed. Similarly, SA_OUT = "1", that is, the potential If Vin > potential Vri_2, then read potential Vri_3 as potential Vread, A third comparison with Vin is performed. Similarly, the potential Vri_6 is read out as the potential Vread. As a result of the comparison, when SA_OUT = "0", that is, when potential Vin < potential Vri_6, Using Vri_5 as the read potential Vread, perform a third comparison with the potential Vin. For SA_OUT=”1”, that is, when potential Vin>potential Vri_6, then potential Vri_7 The read potential Vread is used as the reading potential, and a third comparison is made with the potential Vin.

[0215] The results of the third comparison show that when potential Vin < potential Vri_1, the memory cell transistor 2 The threshold voltage Vth of 01 can be determined to belong to interval 0. Similarly, If potential Vin > potential Vri_1, go to section 1; if potential Vin < potential Vri_3, go to section 2. If potential Vin > potential Vri_3, go to section 3; if potential Vin < potential Vri_5, go to section 4. If potential Vin > potential Vri_5, then enter section 5; if potential Vin < potential Vri_7, enter section 6. If position Vin > potential Vri_7, then in interval 7, the threshold voltage of the memory cell transistor 201. Pressure Vth can be determined to belong to the group. As described above, the comparison results are fed back. By repeatedly comparing, the interval m=2 M Even in the case of individuals, the number of comparisons can be reduced to M times. The data can be reduced and read.

[0216] Note that when performing multiple comparisons in the first read operation, the bits are used for all comparisons except the initial one. Because it does not involve charging or discharging the wire, high-speed reading is possible.

[0217] In the first readout, multiple potentials VVri_0~Vri_m (where m is greater than 0) We have explained an example of performing multiple comparisons using integers, but we have also explained the method of performing only one comparison. It is also possible to perform comparisons. Specifically, m-1 sense amplifier circuits are added to the readout circuit. Just set it up.

[0218] Next, in the second write operation (writing the data to be stored), the desired data is stored in the memory cell. Write the data. The n values ​​will be written as "0", "1", ... "n-1". Furthermore, the threshold voltage of transistor 201 is the typical value Vth_typ of the memory cell. Let Vw_i be the write potential when writing data "i" (an integer from i=0 to n) to the device.

[0219] In the second write operation, when writing data "i" to the memory cell, which section of the memory cell Writing is performed using a corrected writing potential based on whether it belongs to the intermediate range. For example, Let interval i0 be the interval that includes the typical threshold voltage value Vth_typ of ZISTA201. In this case, the correction voltage in the interval i0+k (where k is an integer from -i0 to m-1-i0) is k × ΔVth. Table 1 shows the threshold voltage ranges for each interval of transistor 201. The voltage and correction voltage are shown.

[0220] [Table 1]

[0221] For example, in interval i0, the correction voltage is 0, and in the adjacent interval which is ΔVth greater than interval i0, the correction is applied. Let the voltage be ΔVth. In the adjacent interval where the voltage is less than ΔVth than interval i0, the correction voltage is -ΔV Let th be the case. Then, if the memory cell belongs to interval (i0+k), the corrected writing power The writing process is performed using the position Vw_i + k × ΔVth.

[0222] By performing this type of writing, the distribution of the state after writing can be narrowed. As a result, it is possible to improve the degree of multi-values. Also, in one aspect of the present invention, writing In this operation, the data is written and read only once on the first attempt, unlike conventional verification writing. This operation achieves faster writing compared to repeatedly writing and reading. It is possible.

[0223] Figure 20 shows the data when no correction is applied (i.e., when all correction voltages are set to 0V). An example after data writing (Figure 20(A)) and an example after data writing with correction applied ( Figure 20(B)) shows the respective figures. In Figure 20(A), the write potential does not depend on the memory cell. It remains constant, and the state after writing is similar to the threshold voltage distribution of transistor 201. It has a distribution. As a result, for example, a memory cell can only store four or fewer states. i. On the other hand, in Figure 20(B), the write potential is corrected for each memory cell, so write The subsequent states have a narrow distribution of approximately ΔVth. As a result, for example, the memory cell has 16 values. It can store the state.

[0224] Next, regarding a read operation (a read operation of stored data) according to one aspect of the present invention: explain.

[0225] To read out the n values ​​"0", "1", ... "n-1" as data, Multiple potentials Vr_j ~ Vr_n-2 (where n-2 is an integer greater than 0) are used as the potential Vread. Multiple comparisons are performed using the potential Vr_j (an integer between 0 and n-2) selected from the data. The output potential Vr_j is the value of the potential Vin when the memory cell containing data "j" is read. This will be the potential between the values ​​of the potential Vin when reading the memory cell containing data "j+1". I've decided on sea urchin.

[0226] Multiple comparisons using multiple potentials Vr_j ~ Vr_n-2 (where n-2 is an integer greater than 0) Let's explain how to do this with an example. For example, multiple potentials Vr_j (an integer from 0 to n-2) By comparing the data n-1 times in sequence, the state of the memory cell is determined to be data "0", "1", ... It is possible to determine which state of "n" it is in. Also, in the first read operation, Figure 1 It is also possible to use a method similar to the one described using 9. As a result, fewer comparisons It is also possible to read the results by number of times. Furthermore, by providing n-1 sense amplifier circuits, a single comparison can be performed. It is also possible to read the data using this method.

[0227] Table 2 shows an example of a specific operating voltage (potential). For example, if the degree of multi-values ​​is n=16, the power supply... Set the voltage to Vdd = 2V, and the typical threshold voltage of transistor 201 to Vth_typ = 0. 3V, the threshold voltage interval width of transistor 201 is ΔVth = 0.04V, transistor The number of intervals for the threshold voltage of TA201, and the number of intervals for the read potential Vin of the first read operation. The number of intervals should be m=8, and the write potential for the first write operation should be Vwi=0.98V. .

[0228] [Table 2]

[0229] Furthermore, the correction voltages corresponding to each interval range of the threshold voltage of transistor 201 are shown in Table 3. The value is the read potential Vri_0 to Vri_8 (an integer from i=0 to 8) related to the first readout. ) are the values ​​shown in Table 4, and the pre-correction write potential Vw_0~Vw_15(i= The integers (0 to 15) are the values ​​shown in Table 5, and the read potential V is related to reading the stored data. The values ​​shown in Table 6 can be used for r_0 to Vr_14. Such voltage values By using this, write and read operations can be performed at a potential of Vdd = 2V or less. It is possible.

[0230] [Table 3]

[0231] [Table 4]

[0232] [Table 5]

[0233] [Table 6]

[0234] As described above, the writing according to one aspect of the present invention is the first writing (for obtaining variation information) (Writing), first read (read for obtaining variation information), second write It has three steps (writing the data to be stored). The first write and the first read By performing the output, information on the variation of memory cells is obtained, and in the second write operation, the acquired information is used. The writing voltage, corrected based on the variation information of the memory cells, is used to write the predetermined data. It is characterized by writing on a Morisel. As a result, the distribution of the state after writing is narrowed. This becomes possible.

[0235] Figure 21 shows a semiconductor according to one embodiment of the present invention, having a memory cell array of kr × (kc × kW). An example of a block circuit diagram of a device is shown. For example, if the degree of multi-values ​​is n=4, the memory capacity If the quantity is 2 × kr × (kc × kW) bits and n = 16, then the memory capacity is 4 × kr × (kc It becomes ×kW) bits. In general, n=2 k (If k is an integer greater than or equal to 1, then the case of a binary value and In comparison, the memory capacity becomes k times larger.

[0236] The semiconductor device shown in Figure 21 has kr word lines WL and a second signal line S2, and kc × kW lines bit line BL(1_1)~BL(kw_kc) and first signal line S1(1_1)~S1( kw_kc) and multiple memory cells 200(1,1)~200(kr,kw_kc) are arranged vertically A matrix with kr rows and kc x kw columns (where kr, kc, and kw are natural numbers). A memory cell array 210 is arranged, along with a read circuit 212, a write circuit 211, and multiple Number multiplexer 219, second signal line and word line drive circuit 213, column decoder 21 4. Address buffer 215, data buffer 218, potential generation circuit 217, control circuit 2 It is composed of peripheral circuits such as 16. Other peripheral circuits include a refresh circuit, etc. A `column` may be provided. Note that kc is the number of columns that can be independently selected by the column decoder 214. kw is the number of columns that can be selected simultaneously.

[0237] The memory cell 200 can use the circuit shown in Figure 14. Each memory cell (representative and Next, consider memory cell 200(i, j). Here, i is an integer between 1 and kr, and j is An integer between 1 and kc × kW is used for the bit line BL(j), the first signal line S1(j), and the word. Line WL(i) and the second signal line S2(i) are connected to the source wiring, respectively. Bit line BL(1_1)~BL(kw_kc) and first signal line S1(1_1)~S1(k w_kc) is connected to multiplexer 219. Word line WL(1)~WL(k r) and the second signal lines S2(1)~S2(kr) are driven by the word line and the second signal line drive circuit 21 Each of them is connected to 3.

[0238] Next, we will explain each circuit. The writing circuit 211 and the reading circuit 212 are, respectively The circuits shown in Figures 15 and 16 can be used.

[0239] The multiplexer 219 receives the output signal of the column decoder 214 as a control signal, and kc The bit line selected from the bit lines is connected to the read circuit 212. Specifically, kc One of the control signals is asserted, and the bit controlled by the asserted control signal Connect the T line to the BL_S line. Also, the multiplexer 219 connects to the first signal line S1 of the kc line. The first signal line selected from is connected to the programming circuit 211. Specifically, the control of kc lines One of the signals is asserted, and the first signal line controlled by the asserted control signal is Connect to the S1_S line.

[0240] The column decoder 214 receives the column address output from the address buffer 215, and the control circuit 2 The control signals output from 16 are used as input signals, and the single output signal specified by the address is A It engages and deasserts other output signals.

[0241] Furthermore, when using a semiconductor device with a kc=1 configuration, the column decoder 214 and multiplexer There is no need to provide 219. In this case, the writing circuit 211 and the first signal line S1 are directly connected. Therefore, the readout circuit 212 and the bit line BL can be directly connected.

[0242] The drive circuit 213 for the second signal line and word line is the line output from the address buffer 215. The address and control signals output from the control circuit 216 are used as input signals, and the address is specified. A predetermined potential is applied to the word line and second signal line that are connected to the other word lines and second signal lines. Apply the solution.

[0243] The potential generation circuit 217 generates the write potential according to the control signal output by the control circuit 216. Outputs Vwrite, read potential Vread, VBL_0, VS1_0, etc. The Vwrite operation uses Vwi in the first write operation and writes in the second write operation. The write potential (Vw_j(j=0)) is corrected according to the write data and the result of the first read. Outputs an integer of ~n-1). The read potential Vread is V In the first readout operation, the potential of one of the r_j (an integer from j=0 to n-2) is read by Vri_ It outputs one of the potentials j (an integer from j=0 to m+1). These potentials are used in the control circuit. It is specified by the output signal. For example, a digital signal representing the voltage level output from the control circuit. It may also have a digital-to-analog converter (DAC) that takes the signal as an input signal.

[0244] The potential generation circuit 217 has multiple write potentials Vwrite and multiple read potentials. It is also acceptable to output the potential Vread. For example, if there are multiple programming circuits 211, If you need to write different potentials to each, you can use multiple write potentials Vwrite. This allows for the supply of the appropriate potential to each of the programming circuits 211. Also, for example For example, if there are multiple readout circuits 212, the comparison results are fed as shown in Figure 19. When using a method that involves going back and repeatedly comparing, multiple readout voltages Vread are used. This allows for the supply of an appropriate potential to each of the readout circuits 212.

[0245] The address buffer 215 outputs the address signals and control signals that are input to the semiconductor device from the control signal circuit. The applied control signal is used as the input signal, and according to the control signal, a predetermined column address is set at a predetermined timing. Outputs response and line addresses. It may also have an address register.

[0246] The data buffer 218 receives the Din signal input to the semiconductor device and the readout circuit 212. The output signal and the control signal output from the control circuit 216 are used as input signals, and the writing circuit 21 The signal input to 1, the Dout signal output from the semiconductor device, and the input to the control circuit 216. The signal is used as the output signal. The data buffer 218 has data registers and follows the control signal. Then, various input signals are stored in the data register at a predetermined timing. Control circuit 216 The input output signal can be selected as either the write potential Vwrite or the read potential Vread. These are signals necessary for writing data to memory cells and reading data from memory cells. be.

[0247] The control circuit 216 processes signals such as WE, RE, and CLK input to the semiconductor device, as well as data buffers. The output signal from 218 is used as the input signal, and the potential generation circuit 217 and address buffer 215 , data buffer 218, column decoder 214, second signal line and word line drive circuit 213 It outputs various control signals to the following: data writing operations and data reading operations. This is a control signal that contains information such as timing control signals and potentials to be used for execution. In the second write operation, the information on the write potential and the correction voltage information are used to correct the value. The control circuit 216 generates and outputs information about the write potential. The control circuit 216 corrects the information about the write potential. It may also have a ROM for generating corrected write potential information from voltage information. For example, 4 bits for information on the write potential, 3 bits for information on the correction voltage, and the corrected write If the potential is represented by 6 bits, an 8kbit ROM may be used. Alternatively, A program to generate corrected write potential information from write potential information and correction voltage information. It may have an arithmetic circuit.

[0248] In this embodiment, the readout potential Vread is generated by the potential generation circuit 217. However, it is also possible to generate the readout potential Vread using other configurations. For example If so, a reference circuit with the same configuration as the circuit that generates the memory cell and Vin is provided, and the reference circuit has By controlling the potential of node A of the memory cell, it is possible to generate Vread. Although the readout circuit 212 is shown to have one sense amplifier circuit, multiple It may have a sense amplifier circuit. The readout circuit 212 has multiple sense amplifier circuits. This makes it possible to reduce the number of read operations.

[0249] The semiconductor device according to this embodiment is extremely efficient due to the low off-current characteristics of the transistor 202. It is possible to retain information for a long period of time. In other words, it is required for DRAM, etc. Refresh operations are unnecessary, and power consumption can be reduced. Furthermore, it is virtually non-volatile. It can be used as a memory device.

[0250] Furthermore, information is written through the switching operation of transistor 202, It does not require high voltage and there are no issues with component degradation. Furthermore, the on / off switching of the transistor... Therefore, because information is written to and erased, high-speed operation can be easily achieved. Also, By controlling the potential input to a transistor, it is possible to directly rewrite the information. This eliminates the need for erasure operations required in flash memory and other devices. This can suppress the decrease in operating speed caused by the operation.

[0251] Furthermore, transistors using materials other than oxide semiconductors are... Compared to the previous method, it enables even faster operation, and by using this, the reading of stored contents can be performed. It is possible to perform deviations at high speed.

[0252] Furthermore, since the semiconductor device according to this embodiment is a multi-level type, the memory capacity per unit area can be increased. This makes it possible to miniaturize and highly integrate semiconductor devices.

[0253] As described above, information on the variation of memory cells is obtained, and the writing power is determined according to the variation information. By writing a value to a memory cell, the distribution of the memory cell's state after writing is narrowed. This can be achieved. As a result, it is possible to improve the degree of multi-value. One aspect of the present invention In a write operation, the potential of the floating node can be directly controlled. Therefore, the writing process involves three steps: the first write, the first read, and the second write. This operation enables high-precision threshold voltage control. As a result, it surpasses conventional verifiers. Compared to repeatedly writing and reading in a file writing operation, it is faster. Writing can be performed.

[0254] (Embodiment 3) In this embodiment, an example of an electronic device equipped with the semiconductor device obtained in the previous embodiment is described below. This will be explained using Figure 22. The semiconductor device obtained in the above embodiment does not have a power supply. Even in such cases, it is possible to retain information. Furthermore, no degradation occurs due to writing and erasing. Furthermore, its operation is also high-speed. For this reason, a new configuration of electric device can be created using this semiconductor device. It is possible to provide sub-devices. Furthermore, the semiconductor device according to the above embodiment is integrated These components are then mounted on circuit boards and installed inside various electronic devices.

[0255] Figure 22(A) shows a notebook-type personal computer including a semiconductor device according to the above embodiment. It is a data system consisting of the main unit 301, the casing 302, the display unit 303, the keyboard 304, etc. This has been done. A semiconductor device according to one aspect of the present invention is used in a notebook-type personal computer. By applying this technology, it becomes possible to retain information even when there is no power supply. Also, There is no degradation associated with writing and erasing. Furthermore, the operation is also fast. For this reason, It is preferable to apply a semiconductor device according to one embodiment of the invention to a notebook-type personal computer. That is the case.

[0256] Figure 22(B) shows a personal digital assistant (PDA) including a semiconductor device according to the previous embodiment. The main unit 311 includes a display unit 313, an external interface 315, and operation buttons 314, etc. A stylus 312 is provided as an accessory for operation. By applying the semiconductor device mentioned above to a PDA, information can be retained even when there is no power supply. It is possible to do so. Furthermore, no degradation occurs due to writing and erasing. Moreover, its operation is It is high-speed. For this reason, it is preferable to apply a semiconductor device according to one aspect of the present invention to a PDA. That is the case.

[0257] Figure 22(C) shows an example of electronic paper including a semiconductor device according to the above embodiment, This shows the e-book 320. The e-book 320 is housed in two enclosures, enclosure 321 and enclosure 323. It is constructed such that the housing 321 and housing 323 are integrated by the shaft portion 337. The shaft portion 337 can be used as an axis for opening and closing operations. With this configuration, ebooks 320 can be used like a paper book. Semiconductor device according to one aspect of the present invention By applying this to electronic paper, it is possible to retain information even when there is no power supply. It is capable of handling data. Furthermore, there is no degradation associated with writing or erasing data. Moreover, its operation is high-speed. Therefore, it is preferable to apply a semiconductor device according to one aspect of the present invention to electronic paper. ru.

[0258] The display unit 325 is incorporated into the housing 321, and the display unit 327 is incorporated into the housing 323. The display units 325 and 327 may be configured to display a continuation screen, or differently. It is also possible to configure the system to display a different screen. By configuring the system to display different screens, for example, Text is displayed on the right-hand display unit (display unit 325 in Figure 22(C)), and on the left-hand display unit (Figure 22 (C) allows an image to be displayed on the display unit 327).

[0259] Furthermore, Figure 22(C) shows an example in which the housing 321 is equipped with an operating section, etc. The body 321 is equipped with a power supply 331, operation keys 333, speaker 335, etc. Pages can be turned using -333. Note that the keyboard and port are located on the same surface as the display unit. The configuration may also include input devices, etc. Connection terminals (earphone jack, USB terminal, or AC adapter and USB cable, etc.) The configuration may also include terminals that can be connected to various cables, a recording medium insertion section, and so on. Furthermore, eBook 320 may be configured to also function as an electronic dictionary.

[0260] Furthermore, the e-book 320 may be configured to transmit and receive information wirelessly. It is also possible to configure the system to allow users to purchase and download desired book data from a sub-book server. It is possible.

[0261] Furthermore, electronic paper can be applied to any field that displays information. For example, in addition to ebooks, there are posters, advertisements on trains and other vehicles, and credit cards. This can be applied to displays on various types of cards, such as TCG cards.

[0262] Figure 22(D) shows a mobile phone including a semiconductor device according to the previous embodiment. The telephone consists of two housings, housing 340 and housing 341. Housing 341 is front Display panel 342, speaker 343, microphone 344, pointing device 3 It is equipped with 46, a camera lens 347, an external connection terminal 348, etc. Also, the housing 340 This includes a solar cell 349 for charging the mobile phone, an external memory slot 350, etc. It is equipped with. Furthermore, the antenna is built into the housing 341. Semiconductor according to one aspect of the present invention By applying the device to a mobile phone, information can be retained even when there is no power supply. This is possible. Furthermore, there is no degradation associated with writing and erasing. Moreover, the operation is also high-speed. Therefore, it is preferable to apply a semiconductor device according to one aspect of the present invention to a mobile phone. be.

[0263] The display panel 342 has a touch panel function, and the image displayed in Figure 22(D) is Multiple operation keys 345 are shown with dotted lines. Note that the mobile phone has a solar cell 34 A boost circuit is implemented to increase the voltage output from 9 to the voltage required for each circuit. Furthermore, in addition to the above configuration, the configuration will incorporate a contactless IC chip, a small recording device, etc. It's also possible.

[0264] The display panel 342 changes its orientation as appropriate depending on the usage mode. Since the camera lens 347 is located on the same plane as 42, video calls are possible. Speaker 343 and microphone 344 are not limited to voice calls, but also video calls, recording, and playback. Raw materials can be used. Furthermore, the housing 340 and housing 341 slide together, as shown in Figure 22(D). It can be transformed from an unfolded state to an overlapping state, and can be made smaller for portability. It is Noh.

[0265] External connection terminal 348 can be connected to various cables such as AC adapters and USB cables. It also enables charging and data communication. In addition, the external memory slot 350 can be used for recording media. By inserting this, it can handle the storage and movement of larger amounts of data. In addition to the above functions, It may also be equipped with infrared communication capabilities, television reception capabilities, etc.

[0266] Figure 22(E) shows a digital camera including a semiconductor device according to the previous embodiment. The digital camera consists of the main unit 361, the display unit (A) 367, the eyepiece 363, and the operation switch 364. It consists of a display unit (B) 365, a battery 366, and the like. One aspect of the present invention By applying the semiconductor device to a digital camera, information can be transmitted even when there is no power supply. It is possible to retain it. Furthermore, no degradation occurs due to writing or erasing. Its operation is also fast. For this reason, a semiconductor device according to one aspect of the present invention is suitable for a digital camera. It is preferable to use it.

[0267] Figure 22(F) shows a television apparatus including a semiconductor device according to the previous embodiment. In the vision device 370, the display unit 373 is incorporated into the housing 371. This makes it possible to display video. Note that here, the enclosure is connected by stand 375. This shows the configuration that supported 371.

[0268] The television device 370 can be operated using the control switches on the housing 371 or a separate remote control. This can be done using the control unit 380. The operation keys 379 on the remote control unit 380 This allows you to control the channel and volume, and manipulate the image displayed on the display unit 373. It is possible to output from the remote control unit 380 to the remote control unit 380. A configuration may also be provided that includes a display unit 377 for displaying the information. Semiconductor according to one aspect of the present invention By applying this device to a television system, information can be retained even when there is no power supply. It is possible to do so. Furthermore, no degradation occurs due to writing and erasing. Moreover, its operation is It is high-speed. For this reason, a semiconductor device according to one aspect of the present invention is applied to a television apparatus. This is preferable.

[0269] Furthermore, it is preferable that the television equipment 370 be configured to include a receiver, modem, etc. The receiver can receive regular television broadcasts. It can also receive broadcasts via a modem. By connecting to a wired or wireless communication network, one-way communication (from sender to receiver) is possible. (Sender) or two-way information communication (between sender and receiver, or between receivers, etc.) This is possible.

[0270] The configurations and methods shown in this embodiment may be combined with the configurations and methods shown in other embodiments as appropriate. Can be used together [Explanation of Symbols]

[0271] 100 circuit boards 102 Protective layer 104 Semiconductor field 106 element isolation insulating layer 108 Gate Insulation Layer 110 Guard Station 112 Insulating layer 114 Impurity region 116 Channel formation region 118 Sidewall insulation layer 120 High concentration impurity region 122 Metal layer 124 Metal compound area 126 Interlayer insulating layer 128 Interlayer insulating layer 130a Source electrode or drain electrode 130b Source electrode or drain electrode 130c electrode 132 Insulating layer 134 Conductive layer 136a electrode 136b Electrode 136c electrode 136d Gate 138 Gate Insulation Layer 140 Oxide semiconductor layer 142a Source electrode or drain electrode 142b Source electrode or drain electrode 144 Protective insulating layer 146 Interlayer insulating layer 148 Conductive layer 150a electrode 150b electrode 150c electrode 150d electrode 150e electrode 152 Insulating layer 154a electrode 154b electrode 154c electrode 154d electrode 160 transistors 162 transistors 200 memory cells 201 Transistors 202 transistors 203 Transistors 210 memory cell array 211 Programming Circuit 212 Readout Circuit 213 Drive Circuit 214-row decoder 215 Address Buffer 216 Control circuits 217 Potential generation circuit 218 data buffers 219 Multiplexer 301 Main Unit 302 enclosures 303 Display section 304 Keyboard 311 Main Unit 312 Stylus 313 Display section 314 Operation Buttons 315 External Interface 320 eBooks 321 cabinet 323 enclosures 325 Display section 327 Display section 331 Power supply 333 Operation Keys 335 speakers 337 Shaft 340 cabinets 341 cabinets 342 Display Panel 343 speakers 344 Microphone 345 Operation Keys 346 Pointing devices 347 Camera Lenses 348 External connection terminals 349 solar cells 350 external memory slots 361 Main Unit 363 Eyepiece 364 Operation Switches 365 Display section (B) 366 Battery 367 Display section (A) 370 Television equipment 371 cabinets 373 Display section 375 Stand 377 Display section 379 Operation Keys 380 Remote Control Unit

Claims

1. It has a first transistor and a second transistor, A semiconductor device in which the source or drain of the second transistor is electrically connected to the gate of the first transistor, A silicon semiconductor layer, A first insulating layer having a region located above the silicon semiconductor layer, A first electrode having a region in contact with the upper surface of the first insulating layer, A second electrode having a region in contact with the upper surface of the first insulating layer, A third electrode having a region in contact with the upper surface of the first insulating layer, An oxide semiconductor layer having a region located above the second electrode, A second insulating layer having a region located above the oxide semiconductor layer, A fourth electrode having a region located above the second insulating layer, The silicon semiconductor layer has a channel formation region for the first transistor, The oxide semiconductor layer has a channel formation region for the second transistor, The first electrode has a region that overlaps with the gate electrode of the first transistor. The first electrode does not have a region that overlaps with the channel formation region of the second transistor. The second electrode has a region that overlaps with the channel formation region of the second transistor. The third electrode has a region that overlaps with the fourth electrode, The oxide semiconductor layer does not have a region that overlaps with the gate electrode of the first transistor.

2. It has a first transistor and a second transistor, A semiconductor device in which the source or drain of the second transistor is electrically connected to the gate of the first transistor, A silicon semiconductor layer, A first insulating layer having a region located above the silicon semiconductor layer, A first electrode having a region in contact with the upper surface of the first insulating layer, A second electrode having a region in contact with the upper surface of the first insulating layer, A third electrode having a region in contact with the upper surface of the first insulating layer, An oxide semiconductor layer having a region located above the second electrode, A second insulating layer having a region located above the oxide semiconductor layer, A fourth electrode having a region located above the second insulating layer, The silicon semiconductor layer has a channel formation region for the first transistor, The oxide semiconductor layer has a channel formation region for the second transistor, The first electrode has a region that overlaps with the gate electrode of the first transistor. The first electrode does not have a region that overlaps with the channel formation region of the second transistor. The second electrode has a region that overlaps with the channel formation region of the second transistor. The third electrode has a region that overlaps with the fourth electrode, The oxide semiconductor layer does not have a region that overlaps with the channel formation region of the first transistor.

3. It has a first transistor and a second transistor, A semiconductor device in which the source or drain of the second transistor is electrically connected to the gate of the first transistor, A silicon semiconductor layer, A first insulating layer having a region located above the silicon semiconductor layer, A first electrode having a region in contact with the upper surface of the first insulating layer, A second electrode having a region in contact with the upper surface of the first insulating layer, A third electrode having a region in contact with the upper surface of the first insulating layer, An oxide semiconductor layer having a region located above the second electrode, A second insulating layer having a region located above the oxide semiconductor layer, A fourth electrode having a region located above the second insulating layer, The silicon semiconductor layer has a channel formation region for the first transistor, The oxide semiconductor layer has a channel formation region for the second transistor, The first electrode has a region that overlaps with the gate electrode of the first transistor. The first electrode does not have a region that overlaps with the channel formation region of the second transistor. The second electrode has a region that overlaps with the channel formation region of the second transistor. The second electrode does not have a region that overlaps with the fourth electrode. The third electrode has a region that overlaps with the fourth electrode, The oxide semiconductor layer does not have a region that overlaps with the gate electrode of the first transistor.

4. It has a first transistor and a second transistor, A semiconductor device in which the source or drain of the second transistor is electrically connected to the gate of the first transistor, A silicon semiconductor layer, A first insulating layer having a region located above the silicon semiconductor layer, A first electrode having a region in contact with the upper surface of the first insulating layer, A second electrode having a region in contact with the upper surface of the first insulating layer, A third electrode having a region in contact with the upper surface of the first insulating layer, An oxide semiconductor layer having a region located above the second electrode, A second insulating layer having a region located above the oxide semiconductor layer, A fourth electrode having a region located above the second insulating layer, The silicon semiconductor layer has a channel formation region for the first transistor, The oxide semiconductor layer has a channel formation region for the second transistor, The first electrode has a region that overlaps with the gate electrode of the first transistor. The first electrode does not have a region that overlaps with the channel formation region of the second transistor. The second electrode has a region that overlaps with the channel formation region of the second transistor. The second electrode does not have a region that overlaps with the fourth electrode. The third electrode has a region that overlaps with the fourth electrode, The oxide semiconductor layer does not have a region that overlaps with the channel formation region of the first transistor.

5. In any one of claims 1 to 4, The oxide semiconductor layer comprises In, M (where M is Ga, Al, Mn, or Co), and Zn.

Images