Gaming machine

Abstract

To provide a game machine capable of making a configuration regarding a setting value suitable.SOLUTION: Based on execution of setting change operation when operating power starts to be supplied, setting value update processing is started. By switching of a setting key insertion part 68a from an ON state to an OFF state, setting value update processing is completed. A main-side RAM 65 includes a setting reference area for storing information on a setting value to be used, and a setting update area for storing information on a setting value selected as an update target in setting value update processing. In a stop of supply of operating power during execution of setting value update processing, the setting value update processing can be started even if setting confirmation operation is performed when resuming supply of operating power, and at the same time a setting value is changed from the setting value selected in the last setting value update processing. In the meantime, when RAM clearing operation is performed, the setting value update processing is not performed.SELECTED DRAWING: Figure 6

Description

Technical Field

[0004] , , , , , , ,

[0001] The present invention relates to a gaming machine.

Background Art

[0002] As gaming machines, pachinko machines and slot machines are known. For example, a pachinko machine includes a dish storage unit for storing game balls given to a player on the front surface of the gaming machine, and the game balls stored in the dish storage unit are guided to a game ball launching device and launched toward the game area according to the player's launching operation. Then, for example, when a game ball enters a ball entrance provided in the game area, game balls are paid out from a payout device to the dish storage unit. In addition, in a pachinko machine, a configuration including an upper dish storage unit and a lower dish storage unit as dish storage units is also known. In this case, the game balls stored in the upper dish storage unit are guided to the game ball launching device, and the surplus game balls in the upper dish storage unit are discharged to the lower dish storage unit (see, for example, Patent Document 1).

[0003] In addition, in a slot machine, when a start lever is operated in a situation where medals are bet and a new game is started, a lottery process is executed by control means. Further, when the lottery process is executed, rotation start control is executed by the control means to start the rotation of the reel, and when a stop button is operated during the rotation of the reel, rotation stop control is executed by the control means to stop the rotation of the reel. Then, when the stop result after the rotation stop of the reel corresponds to the winning combination of the lottery process, a privilege corresponding to the winning combination is given to the player.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] In the case of gaming machines such as those shown in the examples above, The management of gaming machines must be carried out appropriately. There is still room for improvement in this regard.

[0006] This invention was made in view of the circumstances described above, This makes it possible to manage gaming machines effectively. The purpose is to provide gaming machines. [Means for solving the problem]

[0007] In order to solve the above problems, the invention described in claim 1 is: A history storage execution means that stores the history information of a game corresponding to a predetermined event that occurs when a game is played, Information deriving means for deriving behavioral information corresponding to the result of the game using the history information stored in the history storage means, A configuration information storage means for storing the configuration information derived by the information derivation means, A manner information display control means that controls the display of manner information corresponding to the manner information stored in the manner information storage means to be displayed by the information display means, A predetermined corresponding display control means that controls the information display means to ensure that a predetermined corresponding display is performed before a new display corresponding to the aspect information is initiated, based on the occurrence of a predetermined display trigger. A setting means for setting a value corresponding to the player's advantage, A condition generating means that creates a condition in which the setting value can be set by the setting means, Equipped with, The aforementioned aspect information storage means includes a plurality of specific storage areas that enable the storage of each of the plurality of aspect information, The aspect information display control means controls the information display means to sequentially execute displays corresponding to each of the multiple aspect information stored in the multiple specific storage areas according to a predetermined display order, and when the information display means is to be made to perform a display corresponding to the aspect information after the predetermined corresponding display has been performed, it starts with the display corresponding to the aspect information corresponding to the first order in the predetermined display order. The information derivation means derives the aspect information using the historical information during a predetermined advantageous period. This gaming machine is equipped with control means for performing various processes, The control means is An in-area processing execution means that executes in-area processing, which is processing that uses a program stored in a predetermined address range storage area of ​​a program storage means, An out-of-bounds processing execution means for executing out-of-bounds processing, which is processing that utilizes a program stored in a storage area of ​​an address range outside the predetermined address range of the program storage means, Equipped with, This gaming machine is When processing within the aforementioned region is performed, information can be written to and read from the corresponding storage area within the region, while when processing outside the aforementioned region is performed, information can be read but information cannot be written to the corresponding storage area within the region. When the aforementioned out-of-area processing is performed, information can be written to and read from the out-of-area corresponding storage area, while when the aforementioned in-area processing is performed, information can be read but information cannot be written to the out-of-area corresponding storage area, Equipped with, The domain-based processing execution means includes means capable of executing a process as a domain-based process that can determine whether or not the setting value set as the target for use is normal. It is characterized by the following: [Effects of the Invention]

[0008] According to the present invention, This makes it possible to manage gaming machines effectively. This is the result. [Brief explanation of the drawing]

[0009] [Figure 1] It is a perspective view showing a pachinko machine in the first embodiment. [Figure 2] It is a perspective view showing the main components of the pachinko machine disassembled. [Figure 3] It is a front view showing the configuration of the game board. [Figure 4] It is an explanatory diagram for explaining the configuration related to the discharge of the game balls that have flowed down in the game area. [Figure 5] It is a front view of the main control device. [Figure 6] It is a block diagram showing the electrical configuration of the pachinko machine. [Figure 7] It is an explanatory diagram for explaining the contents of various counters used for winning / losing lottery and the like. [Figure 8] It is an explanatory diagram for explaining various tables stored in the main side ROM. [Figure 9] It is a flowchart showing the main processing executed by the main side CPU. [Figure 10] It is a flowchart showing the setting value update processing executed by the main side CPU. [Figure 11] It is a flowchart showing the timer interrupt processing executed by the main side CPU. [Figure 12] It is a flowchart showing the special drawing special electricity control processing executed by the main side CPU. [Figure 13] It is a flowchart showing the special drawing variation start processing executed by the main side CPU. [Figure 14] It is an explanatory diagram for explaining the configuration that enables the detection result of the ball entry detection sensor to be input to the main side CPU. [Figure 15] It is a flowchart showing the ball entry detection processing executed by the main side CPU. [[ID=4*]] [Figure 16] It is a block diagram for explaining the electrical configuration of the payout control device and various devices that communicate with the payout control device. [Figure 17] It is a flowchart showing the timer interrupt processing executed by the payout side CPU. [Figure 18] This is a block diagram illustrating the electrical configuration of the management IC. [Figure 19] This is an explanatory diagram illustrating the configuration of the input ports on the management interface. [Figure 20] This is an explanatory diagram illustrating the configuration of the memory used for correspondence relationships. [Figure 21] This is an explanatory diagram illustrating the configuration of the history memory. [Figure 22] This flowchart shows the recognition process executed by the main CPU. [Figure 23] This is a flowchart showing the management processes executed by the management CPU. [Figure 24] (a) to (d) are time charts showing how information regarding the correspondence between the 1st to 15th buffers and the types of signals is stored in the correspondence memory. [Figure 25] This flowchart shows the management output processing performed by the main CPU. [Figure 26] This is a flowchart showing the history setting process executed by the management CPU. [Figure 27] (a) to (e) are time charts showing how history information is stored in the history memory. [Figure 28] This flowchart shows the output process of the setting value update signal executed by the main CPU. [Figure 29] This flowchart shows the process for recognizing configuration updates, which is executed on the management CPU. [Figure 30] This flowchart shows the display output process executed by the management CPU. [Figure 31] This flowchart shows the display processing performed by the management CPU. [Figure 32] (a) A flowchart showing the data output process executed by the main CPU, and (b) A flowchart showing the external output process executed by the management CPU. [Figure 33] This is an explanatory diagram illustrating the various tables stored in the main ROM in the second embodiment. [Figure 34] This is an explanatory diagram illustrating the configuration of the separate storage memory in the third embodiment. [Figure 35] This flowchart shows the process for recognizing configuration updates, which is executed on the management CPU. [Figure 36] This flowchart shows the recurring change monitoring process executed by the management CPU. [Figure 37] This flowchart shows the recurring change monitoring process executed by the main CPU in the fourth embodiment. [Figure 38] This flowchart shows the configuration update recognition process executed by the management CPU in the fifth embodiment. [Figure 39] This is an explanatory diagram illustrating the configuration of the history memory in the sixth embodiment. [Figure 40] This is a flowchart showing the history setting process executed by the management CPU. [Figure 41] This flowchart shows the process for recognizing configuration updates, which is executed on the management CPU. [Figure 42] This is an explanatory diagram illustrating the configuration of the history memory in the seventh embodiment. [Figure 43] This flowchart shows the process for recognizing configuration updates, which is executed on the management CPU. [Figure 44] This is an explanatory diagram illustrating the configuration of the history memory in the eighth embodiment. [Figure 45] This flowchart shows the process for recognizing configuration updates, which is executed on the management CPU. [Figure 46] This is a flowchart showing the history setting process executed by the management CPU. [Figure 47] This flowchart shows the display output process executed by the management CPU. [Figure 48] This is an explanatory diagram illustrating the configuration of the input ports of the management interface in the ninth embodiment. [Figure 49]This flowchart shows the recognition process executed by the main CPU. [Figure 50] This is a flowchart showing the management processes executed by the management CPU. [Figure 51] (a) to (h) are time charts showing how information regarding the correspondence between the 1st to 12th buffers and the types of signals is stored in the correspondence memory. [Figure 52] This is a block diagram illustrating the configuration of the signal path for transmitting the detection results of each ball entry detection sensor to the main CPU and the management IC in the 10th embodiment. [Figure 53] This is a front view of the main control device in the 11th embodiment. [Figure 54] This block diagram illustrates the electrical configuration for displaying various information in the first to fourth notification display devices based on the control of the MPU. [Figure 55] This flowchart shows the display processing performed by the management CPU. [Figure 56] This flowchart shows the configuration value update process executed by the main CPU. [Figure 57] (a) This is an explanatory diagram for explaining the display modes of the first to fourth notification display devices when the results of the game history management are displayed, and (b) This is an explanatory diagram for explaining the display modes of the first to fourth notification display devices when the settings state of the pachinko machine is changed. [Figure 58] (a) to (h) are time charts showing when the 1st to 4th notification display devices enter their display state. [Figure 59] (a) is an explanatory diagram illustrating the configuration of the first notification display device in the twelfth embodiment, and (b) is an explanatory diagram illustrating the configuration of the second notification display device. [Figure 60] This is an explanatory diagram illustrating the display content of the first and second notification display devices when displaying the results of game history management on the first to fourth notification display devices, and when indicating that the settings of the pachinko machine can be changed. [Figure 61]This flowchart shows the configuration value update process executed by the main CPU. [Figure 62] This is an explanatory diagram illustrating the configuration of the abnormality display area in the 13th embodiment. [Figure 63] This flowchart shows the abnormal setting process executed by the main CPU. [Figure 64] This flowchart shows the error display process executed by the main CPU. [Figure 65] This is a flowchart showing the management output processing performed by the main CPU in the 14th embodiment. [Figure 66] This flowchart shows the main processing performed by the primary CPU in a different configuration. [Figure 67] This is an explanatory diagram illustrating the setting configuration of the program and data of the main ROM in the 15th embodiment. [Figure 68] This is an explanatory diagram illustrating the configuration of each area in the main RAM. [Figure 69] This flowchart shows the timer interrupt processing performed by the main CPU. [Figure 70] This flowchart shows the management processes executed on the primary CPU. [Figure 71] This is a flowchart showing the management execution processes performed on the primary CPU. [Figure 72] This is an explanatory diagram illustrating the various areas of the work area used for non-specific control, which is used to manage game history. [Figure 73] This flowchart shows the check process executed by the primary CPU. [Figure 74] This is a flowchart showing the normal ball entry management process executed by the main CPU. [Figure 75] This flowchart shows the result calculation process performed by the primary CPU. [Figure 76] This flowchart shows the display processing performed by the main CPU. [Figure 77]This flowchart shows the management process executed by the main CPU in the 16th embodiment. [Figure 78] This is a flowchart showing the management execution process performed by the main CPU in the 17th embodiment. [Figure 79] This is a flowchart showing the management execution process performed by the main CPU in the 18th embodiment. [Figure 80] This is a flowchart showing the management execution process performed by the main CPU in the 19th embodiment. [Figure 81] This flowchart shows the management process executed by the main CPU in the 20th embodiment. [Figure 82] This is a flowchart showing the management execution processes performed on the primary CPU. [Figure 83] This is an explanatory diagram illustrating the electrical configuration in the 21st embodiment. [Figure 84] This is a flowchart showing the main processing performed by the main CPU in the 22nd embodiment. [Figure 85] This flowchart shows the configuration value update process executed by the main CPU. [Figure 86] This flowchart shows the timer interrupt processing performed by the main CPU. [Figure 87] This flowchart shows the configuration verification process executed on the main CPU. [Figure 88] This flowchart shows the RAM monitoring process executed by the primary CPU. [Figure 89] This flowchart shows the main processing performed by the primary CPU in a different configuration. [Figure 90] This flowchart shows the configuration value update process executed by the main CPU in a different configuration. [Figure 91] This is a flowchart showing the main processing performed by the main CPU in the 23rd embodiment. [Figure 92]This is a flowchart showing the RAM monitoring process executed by the main CPU in the 24th embodiment. [Figure 93] This is a flowchart showing the RAM monitoring process executed by the main CPU in the 25th embodiment. [Figure 94] This is a flowchart showing the management execution processes performed on the primary CPU. [Figure 95] This flowchart shows a separate monitoring process executed on the primary CPU. [Figure 96] This flowchart shows the management process executed by the main CPU in the 26th embodiment. [Figure 97] This flowchart shows the management process executed by the main CPU in the 27th embodiment. [Figure 98] This flowchart shows the management process executed by the main CPU in the 28th embodiment. [Figure 99] This flowchart shows the management process executed by the main CPU in the 29th embodiment. [Figure 100] This flowchart shows the main processing performed by the main CPU in the 30th embodiment. [Figure 101] This flowchart shows the power outage information storage process executed by the main CPU. [Figure 102] (a) A block diagram illustrating the configuration of the MPU, and (b) A time chart showing the output of the reset signal by the reset signal output unit. [Figure 103] This flowchart shows the timer interrupt processing performed by the main CPU. [Figure 104] This flowchart shows the configuration monitoring process executed by the main CPU. [Figure 105] This flowchart shows the management processes executed on the primary CPU. [Figure 106] This is a flowchart showing the management execution processes performed on the primary CPU. [Figure 107]This flowchart shows a separate monitoring process executed on the primary CPU. [Figure 108] This is a flowchart showing the main processing performed by the main CPU in the 31st embodiment. [Figure 109] This flowchart shows the error clearing process executed by the primary CPU. [Figure 110] This flowchart shows the clearing process for non-specific control that is executed on the main CPU. [Figure 111] This is a flowchart showing the power outage information storage process executed by the main CPU in the 32nd embodiment. [Figure 112] This flowchart shows the checksum monitoring process performed by the primary CPU. [Figure 113] This flowchart shows the clearing process for non-specific control that is executed on the main CPU. [Figure 114] This is a flowchart showing the main processing performed by the main CPU in the 33rd embodiment. [Figure 115] This flowchart shows the configuration verification process executed on the main CPU. [Figure 116] This flowchart shows the configuration value update process executed by the main CPU. [Figure 117] This flowchart shows the first timer interrupt processing performed by the main CPU. [Figure 118] This flowchart shows the configuration monitoring process executed by the main CPU. [Figure 119] This is a block diagram illustrating the configuration for controlling various display circuits using the main CPU. [Figure 120] (a) This is an explanatory diagram for illustrating the various buffers provided in the work area for specific control, and (b) This is an explanatory diagram for illustrating the various storage areas provided in the work area for non-specific control. [Figure 121] This is an explanatory diagram illustrating the electrical configuration of the display IC. [Figure 122](a) to (g) are time charts showing how type data and display data are transmitted from the main CPU to the display IC, and how the display data transmitted from the display IC is received by the first or second display circuit. [Figure 123] This flowchart shows the second timer interrupt processing performed by the main CPU. [Figure 124] (a) This is an explanatory diagram for explaining the display content of the first to fourth notification devices when the setting value is being updated, and (b) This is an explanatory diagram for explaining the display content of the first to fourth notification devices when the setting value is being confirmed. [Figure 125] This is a flowchart showing the setting value update process executed by the main CPU in the 34th embodiment. [Figure 126] This is an explanatory diagram illustrating the electrical configuration of the calculation result storage area in the 35th embodiment. [Figure 127] (a) to (d) are explanatory diagrams for explaining the display contents of the 1st to 4th notification display devices. [Figure 128] (a) to (c) are explanatory diagrams for explaining the display contents of the 1st to 4th notification display devices. [Figure 129] (a) to (e) are time charts showing how the base values ​​for various areas are broadcast on the 1st to 4th notification display devices. [Figure 130] This flowchart shows the result calculation process performed by the primary CPU. [Figure 131] This flowchart shows the display processing performed by the main CPU. [Figure 132] This flowchart shows the main processing performed by the primary CPU. [Figure 133] This flowchart shows the first timer interrupt processing performed by the main CPU. [Figure 134] This flowchart shows the second timer interrupt processing performed by the main CPU. [Figure 135] This flowchart shows the normal configuration process executed by the main CPU. [Figure 136] This flowchart shows the configuration verification process executed on the main CPU. [Figure 137] This flowchart shows the configuration value update process executed by the main CPU. [Figure 138] (a) to (f) are time charts to explain the display contents of the 1st to 4th notification display devices when the supply of operating power to the main CPU is started. [Figure 139] This is a flowchart showing the main processing performed by the main CPU in the 36th embodiment. [Figure 140] This is a flowchart showing the main processing performed by the main CPU in the 37th embodiment. [Figure 141] This flowchart shows the normal setting process executed by the main CPU in the 38th embodiment. [Figure 142] (a) to (d) are explanatory diagrams illustrating the setting-compatible storage area provided in the main ROM in the 39th embodiment. [Figure 143] This flowchart shows the process of reading the success / failure table executed by the main CPU. [Figure 144] This flowchart shows the setting process for the fifth display data buffer during a configuration update performed by the main CPU. [Figure 145] (a) to (c) are explanatory diagrams illustrating the setting-compatible storage area provided in the main ROM in the 40th embodiment. [Figure 146] (a) An explanatory diagram for illustrating the various display units provided in an area visible from the front of the pachinko machine through the window panel in the 41st embodiment, and (b) An explanatory diagram for illustrating the display content of the round display unit. [Figure 147] This flowchart shows the main processing performed by the main CPU in the 42nd embodiment. [Figure 148] This flowchart shows the first timer interrupt processing performed by the main CPU. [Figure 149]This flowchart shows the result calculation process executed by the main CPU in the 43rd embodiment. [Figure 150] This flowchart shows the display processing performed by the main CPU. [Figure 151] (a) to (g) are time charts showing how the base values ​​for various areas are announced on the 1st to 4th notification display devices. [Figure 152] (a) to (g) are time charts showing how the base values ​​of various areas are reported by the first to fourth notification display devices in the 44th embodiment. [Figure 153] This flowchart shows the main processing performed by the main CPU in the 45th embodiment. [Figure 154] This is an explanatory diagram illustrating the contents of the memory area for set values ​​provided in the work area for specific control. [Figure 155] This flowchart shows the configuration verification process executed on the main CPU. [Figure 156] This flowchart shows the setting process for the fifth display data buffer during configuration verification, which is performed by the main CPU. [Figure 157] This flowchart shows the configuration value update process executed by the main CPU. [Figure 158] This flowchart shows the setting process for the fifth display data buffer during a configuration update performed by the main CPU. [Figure 159] This diagram explains the process executed in the main process when power is restored after a power outage occurs while a setting value update process or setting confirmation process is running. [Figure 160] (a) to (e) are time charts showing the completion timing of the setting value update process and the setting confirmation process in relation to the operation status of the setting key insertion part. [Figure 161] This is a flowchart showing the main processing performed by the main CPU in the 46th embodiment. [Figure 162]This diagram explains the process executed in the main process when power is restored after a power outage occurs while a setting value update process or setting confirmation process is running. [Figure 163] This is an explanatory diagram illustrating the content of the processing performed in the main process when the power supply is resumed after a power outage is executed while the setting value update process or setting confirmation process is being executed in the 47th embodiment. [Figure 164] This is an explanatory diagram illustrating the content of the processing performed in the main process when the power supply is restored after a power outage is executed while the setting value update process or setting confirmation process is being executed in the 48th embodiment. [Modes for carrying out the invention]

[0010] <First Embodiment> The following describes in detail, based on the drawings, a first embodiment of a pachinko gaming machine (hereinafter referred to as "pachinko machine"), which is a type of gaming machine. Figure 1 is a perspective view of the pachinko machine 10, and Figure 2 is a perspective view showing the main components of the pachinko machine 10 in an exploded view. For convenience, the components within the gaming area PA of the pachinko machine 10 are omitted in Figure 2.

[0011] As shown in Figure 1, the pachinko machine 10 has an outer frame 11 that forms the outer shell of the pachinko machine 10, and a game machine body 12 that is rotatably attached to the outer frame 11 in the forward direction. The outer frame 11 is constructed by connecting wooden boards on all four sides and has a rectangular frame shape. The pachinko machine 10 is installed in a game hall by attaching and fixing the outer frame 11 to the island equipment. Note that the outer frame 11 is not an essential component of the pachinko machine 10, and the outer frame 11 may be installed on the island equipment of the game hall.

[0012] As shown in Figure 2, the gaming machine body 12 comprises an inner frame 13, a front door frame 14 positioned in front of the inner frame 13, and a back pack unit 15 positioned behind the inner frame 13. The inner frame 13 of the gaming machine body 12 is rotatably supported by the outer frame 11. In detail, the inner frame 13 is rotatable forward with the left side as the base end of rotation and the right side as the tip end of rotation when viewed from the front.

[0013] The front door frame 14 is rotatably supported on the inner frame 13, and can rotate forward with the left side as the pivot end and the right side as the pivot end when viewed from the front. The rear pack unit 15 is also rotatably supported on the inner frame 13, and can rotate backward with the left side as the pivot end and the right side as the pivot end when viewed from the front.

[0014] Furthermore, the gaming machine body 12 is equipped with a locking device at its rotating tip, which has the function of locking the gaming machine body 12 to the outer frame 11 in a state where it cannot be opened, and also has the function of locking the front door frame 14 to the inner frame 13 in a state where it cannot be opened. These locking states can be released by performing an unlocking operation using an unlocking key on a cylinder lock 17 that is exposed on the front of the pachinko machine 10.

[0015] Next, we will describe the configuration of the front side of the gaming machine body 12.

[0016] The inner frame 13 is mainly composed of a resin base 21 whose outer shape is almost identical to that of the outer frame 11. A roughly oval-shaped window opening 23 is formed in the center of the resin base 21. A game board 24 is detachably attached to the resin base 21. The game board 24 is made of plywood, and the game area PA formed on the front of the game board 24 is exposed to the front side of the inner frame 13 through the window opening 23 of the resin base 21.

[0017] Here, the configuration of the game board 24 will be explained based on Figure 3. Figure 3 is a front view of the game board 24.

[0018] The game board 24 is fitted with an inner rail section 25 and an outer rail section 26 so as to demarcate a part of the outer edge of the game area PA, and these inner rail section 25 and outer rail section 26 constitute a guide rail that serves as a guide means. Game balls launched from the game ball launching mechanism 27 (see Figure 2), which is attached below the window hole 23 on the resin base 21, are guided to the upper part of the game area PA by the guide rail.

[0019] Incidentally, the game ball launching mechanism 27 includes a launching rail 27a extending toward a guide rail, a ball feeding device 27b that supplies game balls stored in the upper tray 55a (described later) onto the launching rail 27a, and a solenoid 27c, which is an electric actuator that launches the game balls supplied onto the launching rail 27a toward the guide rail. The solenoid 27c is driven and controlled by the rotation of the launching operation device (or operation handle) 28 provided on the front door frame 14, and the game balls are launched.

[0020] The game board 24 has multiple openings of varying sizes that penetrate in the front-to-back direction. Each opening is provided with a general prize entry point 31, a special electric prize entry device 32, a first operation opening 33, a second operation opening 34, a through gate 35, a variable display unit 36, a special symbol unit 37, and a regular symbol unit 38, among others. There are a total of four general prize entry points 31, and one of each of the other types.

[0021] Even if a ball enters the through gate 35, no game balls will be dispensed. On the other hand, if a ball enters the general prize entry opening 31, the special electric prize entry device 32, the first operation opening 33, or the second operation opening 34, a predetermined number of game balls will be dispensed. Specifically regarding the number of prize balls dispensed, if one game ball enters the first operation opening 33 or one game ball enters the second operation opening 34, one prize ball will be dispensed; if one game ball enters the general prize entry opening 31, ten prize balls will be dispensed; and if one game ball enters the special electric prize entry device 32, fifteen prize balls will be dispensed.

[0022] The above number of prize balls is arbitrary; for example, the second operating port 34 may be configured to award fewer prize balls than the first operating port 33, or the second operating port 34 may be configured to award more prize balls than the first operating port 33.

[0023] In addition, an outlet 24a is provided at the bottom of the game board 24, and game balls that do not enter the various prize slots are discharged from the game area PA through the outlet 24a. Furthermore, the game board 24 is equipped with numerous nails 24b to appropriately disperse and adjust the direction in which the game balls fall, as well as various components such as windmills.

[0024] Here, "entering the game" means that a game ball passes through a predetermined opening, and includes not only the mode in which the game ball is discharged from the game area PA after passing through the opening, but also the mode in which the game ball continues to flow down the game area PA without being discharged after passing through the opening. However, in the following explanation, in order to clearly distinguish it from the entry of a game ball into the out opening 24a, the entry of a game ball into the general prize entry opening 31, the special electric prize entry device 32, the first operation opening 33, the second operation opening 34, and the through gate 35 will also be expressed as "winning a prize."

[0025] The first operating port 33 and the second operating port 34 are unitized as an operating port device and installed on the game board 24. Both the first operating port 33 and the second operating port 34 are open upwards. Furthermore, both operating ports 33 and 34 are aligned vertically so that the first operating port 33 is at the top. The second operating port 34 is provided with a guide piece, a general-purpose device 34a, which consists of a pair of movable pieces on the left and right. When the general-purpose device 34a is closed, game balls cannot enter the second operating port 34, but when the general-purpose device 34a is opened, it becomes possible for game balls to enter the second operating port 34.

[0026] A through gate 35 is provided upstream of the second operating port 34 in the direction of the flow of the game ball. The through gate 35 has a through hole (not shown) that penetrates vertically, and game balls that enter the through gate 35 flow down the game area PA after entering. This makes it possible for game balls that enter the through gate 35 to enter the second operating port 34.

[0027] Based on the entry of a ball into the through gate 35, the normal electric mechanism 34a of the second operating port 34 is switched from a closed state to an open state. Specifically, an internal lottery is conducted triggered by the entry of a ball into the through gate 35, and the normal diagram display section 38a of the normal diagram unit 38, which is located in the lower right corner of the game area PA where the game ball does not pass, displays a changing pattern. If the result of the internal lottery is a win for opening the electric mechanism, and the stop result corresponding to that result is displayed and the changing display on the normal diagram display section 38a ends, the system transitions to the normal electric open state. In the normal electric open state, the normal electric mechanism 34a is in an open state in a predetermined manner.

[0028] The general display unit 38a is configured as a segment display in which multiple LED display segments are arranged in a predetermined manner, but is not limited to this, and may be configured as other types of display devices such as liquid crystal displays, organic EL displays, CRTs, or dot matrix displays. Furthermore, the patterns that can be displayed in the general display unit 38a may include configurations in which multiple types of characters are displayed in a variable manner, configurations in which multiple types of symbols are displayed in a variable manner, configurations in which multiple types of characters are displayed in a variable manner, or configurations in which multiple types of colors are switched and displayed.

[0029] In the regular display unit 38, a regular display reserve display unit 38b is provided adjacent to the regular display unit 38a. Up to four game balls are reserved when they enter the through gate 35, and the number of reserved balls is displayed by the illumination of the regular display reserve display unit 38b.

[0030] A prize draw is triggered when a ball enters the first or second operating port 33. The result of the draw is then clearly displayed through the display effects on the symbol display device 41 of the special display unit 37 and the variable display unit 36.

[0031] More specifically, the special symbol unit 37 is provided with a special symbol display unit 37a. The display area of ​​the special symbol display unit 37a is narrower than the display surface 41a of the symbol display device 41. In the special symbol display unit 37a, a winning lottery is held triggered by a win in the first operation opening 33 or the second operation opening 34, resulting in a display of changing patterns or a predetermined display. The result corresponding to the lottery result is then displayed. The special symbol display unit 37a is composed of a segment display device in which multiple display segments made of LEDs are arranged in a predetermined manner, but is not limited to this, and may be composed of other types of display devices such as liquid crystal displays, organic EL displays, CRTs or dot matrix displays. Furthermore, the patterns displayed in the special symbol display unit 37a may include configurations that display multiple types of characters, multiple types of symbols, multiple types of characters, or multiple types of colors.

[0032] In the special feature unit 37, a special feature hold display unit 37b is provided adjacent to the special feature display unit 37a. Up to four game balls are held in the first operation opening 33 or the second operation opening 34, and the number of held balls is displayed by the illumination of the special feature hold display unit 37b.

[0033] More specifically, the pattern display device 41 is configured as a liquid crystal display device equipped with a liquid crystal display, and its display content is controlled by a display control device described later. The pattern display device 41 is not limited to a liquid crystal display device; it may be another display device having a display screen, such as a plasma display device, an organic EL display device, or a CRT, or it may be a dot matrix display device.

[0034] In the symbol display device 41, when a symbol variation display or predetermined display is performed on the special symbol display unit 37a based on a win in the first operation opening 33 or a win in the second operation opening 34, the symbol variation display or predetermined display is performed accordingly. For example, the display surface 41a of the symbol display device 41 has three symbol rows set as multiple display areas: upper, middle, and lower. In each symbol row, the main symbols numbered "1" to "9" are displayed in ascending or descending order in a scrolling display. In this scrolling display, scrolling is started for all symbol rows first, then switches from scrolling to standby display in the order of upper symbol row → lower symbol row → middle symbol row, and finally ends with a predetermined symbol displayed statically in each symbol row. In a game round in which the game result is a jackpot, a predetermined combination of symbols is displayed statically on the active line set in advance on the display surface 41a of the symbol display device 41. Specifically, in the case of the most advantageous jackpot result described later, the same odd-numbered symbol combination will be displayed as the stop display; in the case of the low-probability jackpot result described later, the same even-numbered symbol combination will be displayed as the stop display; and in the case of the low-winning high-probability jackpot result described later, the symbol combination will not be the same, but will not be displayed as the stop display in the case of the low-winning high-probability jackpot result.

[0035] Furthermore, the symbol display device 41 not only displays an effect triggered by a win in the first or second operating port 33, but also displays an effect during the opening / closing execution mode that is entered after a win is achieved. In addition, based on a win in either operating port 33 or 34, the display on the special symbol display unit 37a and the symbol display device 41 starts, and the period until the predetermined result is displayed and the display ends constitutes one round of play. Moreover, the manner in which the symbols are displayed in the symbol display device 41 is not limited to those described above and is arbitrary, and the number of symbol rows, the direction of the symbol display in the symbol rows, and the number of symbols in each symbol row can be changed as appropriate. Furthermore, the symbols displayed in the symbol display device 41 are not limited to those described above, and for example, a configuration in which only numbers are displayed as symbols is also possible.

[0036] If a jackpot is won in the winning lottery based on a ball entering the first operating port 33 or the second operating port 34, the system transitions to an opening / closing execution mode in which a ball can enter the special electric prize entry device 32. The special electric prize entry device 32 has a large prize entry port (not shown) that leads to the back of the game board 24, and also has an opening / closing door 32a that opens and closes the large prize entry port. The opening / closing door 32a can be positioned in either a closed state or an open state. Specifically, the opening / closing door 32a is normally in a closed state in which game balls cannot enter, and is switched to an open state in which game balls can enter if the internal lottery results in a transition to the opening / closing execution mode. Incidentally, the opening / closing execution mode is the mode that is entered when a winning result is obtained. Note that while it is not impossible to enter in the closed state, it may be configured in such a way that it is less likely to result in a win than in the open state.

[0037] Figure 4 is an explanatory diagram illustrating the configuration for discharging game balls that have flowed down the game area PA.

[0038] As already explained, game balls that enter any of the general prize entry slot 31, the special electric prize entry device 32, the first operation slot 33, the second operation slot 34, and the out slot 24a are discharged from the game area PA. In other words, game balls launched from the game ball launching mechanism 27 and flowing into the game area PA are discharged from the game area PA by entering any of the general prize entry slot 31, the special electric prize entry device 32, the first operation slot 33, the second operation slot 34, and the out slot 24a. Game balls that enter any of the general prize entry slot 31, the special electric prize entry device 32, the first operation slot 33, the second operation slot 34, and the out slot 24a are guided to the back side of the game board 24.

[0039] On the back of the game board 24, discharge passages 42 to 48 are formed corresponding to the general prize entry opening 31, the special electric prize entry device 32, the first operation opening 33, the second operation opening 34, and the out opening 24a, respectively. Game balls that flow into the discharge passages 42 to 48 are guided down the discharge passages 42 to 48 to the lower end of the game board 24 on the back side of the game board 24 and are collected in a discharge ball collection section (not shown). The game balls collected in the discharge ball collection section are then discharged into the ball circulation device of the island equipment where the pachinko machine 10 is installed in the game hall.

[0040] Each of the discharge passages 42 to 48 is equipped with various detection sensors 42a to 48a for detecting game balls. These discharge passages 42 to 48 and detection sensors 42a to 48a are described below. As already explained, there are four general prize slots 31, and there are discharge passages 42 to 44 corresponding to each of these four slots. In this case, one detection sensor 42a and one detection sensor 43a are provided for the first discharge passage 42 corresponding to the leftmost general prize slot 31 and the second discharge passage 43 corresponding to the general prize slot 31 to its right. Specifically, the first prize slot detection sensor 42a is provided such that its detection range is located midway through the first discharge passage 42, and the second prize slot detection sensor 43a is provided such that its detection range is located midway through the second discharge passage 43. A game ball that enters the leftmost general prize slot 31 is detected by the first prize slot detection sensor 42a while passing through the first discharge passage 42, and a game ball that enters the general prize slot 31 to its right is detected by the second prize slot detection sensor 43a while passing through the second discharge passage 43. In addition, a third discharge passage 44 is provided that is formed to merge with the two general prize slots 31 on the right at an intermediate position. The third discharge passage 44 has an entrance-side region corresponding to each of the two general prize slots 31, and these entrance-side regions merge midway to form a single exit-side region. A third prize slot detection sensor 44a is provided such that the detection range exists at an intermediate position in the exit-side region of the third discharge passage 44. A game ball that enters either of the two general prize slots 31 on the right is detected by the third prize slot detection sensor 44a while passing through the third discharge passage 44.

[0041] A fourth discharge passage section 45 exists corresponding to the special electric prize entry device 32. A special electric detection sensor 45a is provided so that its detection range is located midway through the fourth discharge passage section 45, and game balls that enter the special electric prize entry device 32 are detected by the special electric detection sensor 45a as they pass through the fourth discharge passage section 45. A fifth discharge passage section 46 exists corresponding to the first operation port 33. A first operation port detection sensor 46a is provided so that its detection range is located midway through the fifth discharge passage section 46, and game balls that enter the first operation port 33 are detected by the first operation port detection sensor 46a as they pass through the fifth discharge passage section 46. A sixth discharge passage section 47 exists corresponding to the second operation port 34. A second operation port detection sensor 47a is provided such that its detection range exists midway through the sixth discharge passage 47, and a game ball that enters the second operation port 34 is detected by the second operation port detection sensor 47a while passing through the sixth discharge passage 47. A seventh discharge passage 48 exists corresponding to the out port 24a. An out port detection sensor 48a is provided such that its detection range exists midway through the seventh discharge passage 48, and a game ball that enters the out port 24a is detected by the out port detection sensor 48a while passing through the seventh discharge passage 48.

[0042] Furthermore, a game ball detected by any one of the various detection sensors 42a to 48a will not be detected by the other detection sensors 42a to 48a. In addition, a gate detection sensor 49a is also provided for the through gate 35, and game balls that pass through the through gate 35 while flowing down the game area PA are detected by the gate detection sensor 49a.

[0043] The various detection sensors 42a to 49a are all electromagnetic induction type proximity sensors, but any sensor can be used as long as it can individually detect the game balls. Furthermore, the various detection sensors 42a to 49a are electrically connected to the main control unit 60, which will be described later, and the detection results from the various detection sensors 42a to 49a are output to the main control unit 60. Specifically, the various detection sensors 42a to 49a output a LOW level signal when they do not detect a game ball, and a HI level signal when they detect a game ball. However, this is not the only way to do it; the relationship between HI and LOW may be reversed.

[0044] As shown in Figure 2, a front door frame 14 is provided so as to cover the entire front side of the inner frame 13, to which the game board 24 configured above is attached to the resin base 21. As shown in Figure 1, the front door frame 14 has a window portion 51 formed therein so that almost the entire area of ​​the game area PA can be seen from the front. The window portion 51 is roughly elliptical in shape, and a window panel 52 is fitted into it. The window panel 52 is made of glass and is colorless and transparent, but is not limited to this and may be made of synthetic resin and is colorless and transparent, or it may be made of colored transparent material as long as the game area PA can be seen from the front of the pachinko machine 10 through the window panel 52.

[0045] An indicator light-emitting unit 53 is provided above the window section 51. A pair of left and right speaker sections 54 are also provided, which output sound effects according to the game state. Below the window section 51, an upper bulge 55 and a lower bulge 56 are arranged vertically side by side, bulging outwards towards the front. An upper tray 55a, which opens upwards, is provided inside the upper bulge 55, and a lower tray 56a, which also opens upwards, is provided inside the lower bulge 56. The upper tray 55a has the function of temporarily storing game balls dispensed from the dispensing device (described later) and guiding them to the game ball launching mechanism 27 while aligning them in a line. The lower tray 56a has the function of storing game balls that are left over in the upper tray 55a.

[0046] Next, we will describe the configuration of the back side of the gaming machine body 12.

[0047] As shown in Figure 2, a main control device 60, which is responsible for the main control of the game, is mounted on the back of the inner frame 13 (specifically, the game board 24). Figure 5 is a front view of the main control device 60.

[0048] As shown in Figure 5, the main control device 60 consists of a main control board 61 housed in a board box 60a. An MPU 62 is mounted on one of the board surfaces of the main control board 61, which is the element mounting surface. The board box 60a is made transparent so that the MPU 62 housed inside the board box 60a can be visually inspected from outside the board box 60a. Although the board box 60a is made of colorless transparency, it may be made of colored transparency if it is possible to visually inspect the MPU 62 housed inside the board box 60a from outside the board box 60a. The main control device 60 is mounted on the back of the resin base 21 such that the opposing wall portion 60b facing the element mounting surface of the main control board 61 faces the rear of the pachinko machine 10. Therefore, by opening the gaming machine body 12 in front of the pachinko machine 10 relative to the outer frame 11 and exposing the back surface of the resin base 21, it becomes possible to visually inspect the opposing wall portion 60b of the circuit board box 60a, and to visually inspect the MPU 62 through the opposing wall portion 60b.

[0049] The circuit board box 60a is formed by combining multiple case bodies 60c front to back. These case bodies 60c are provided with connecting parts 60e to prevent separation of the case bodies 60c and to leave a trace when the case bodies 60c are separated. Multiple connecting parts 60e are arranged in parallel on one side of the roughly rectangular circuit board box 60a. As a result, even if some of the connecting parts 60e are used to prevent separation of the case bodies 60c and those connecting parts 60e are destroyed to separate the case bodies 60c, it is possible to prevent separation of the case bodies 60c again by connecting other connecting parts 60e afterward. In addition, since the connecting parts 60e are destroyed and a trace is left when the case bodies 60c are separated, it is possible to determine whether the separation of the case bodies 60c has been performed improperly by visually checking the connecting parts 60e. Furthermore, on the side of the circuit board box 60a opposite to the side where the connecting portion 60e is located, a sealing sticker 60f is attached so as to straddle the boundary between the case bodies 60c. When the sealing sticker 60f is peeled off, the adhesive layer remains on the case body 60c. This makes it possible to leave a trace if the sealing sticker 60f is peeled off when separating the case bodies 60c.

[0050] In the main control device 60 configured as described above, the main control board 61 is provided with a setting key insertion unit 68a into which a setting key owned by the administrator of the gaming hall is inserted and turned ON in order to create an opportunity to change the setting state of the pachinko machine 10 within the range of "setting 1" to "setting 6"; an update button 68b which is operated to sequentially change the setting state of the pachinko machine 10 after the setting key insertion unit 68a has been turned ON; a reset button 68c which is operated to clear the data in the main RAM 65, which will be described later, provided in the MPU 62 of the main control device 60; and first to third notification display devices 69a to 69c for notifying the results of the game history management. Furthermore, the MPU 62 mounted on the main control board 61 is provided with a reading terminal 68d for connecting the terminals of an external device in order to read the results of the game history management or information (programs and data) stored in the main ROM 64 from the external device. Furthermore, the settings for the pachinko machine 10 are not limited to the six levels from "Setting 1" to "Setting 6," but can be any number of levels.

[0051] The setting key insertion section 68a, update button 68b, reset button 68c, reading terminal 68d (i.e., MPU 62), and the first to third notification display devices 69a to 69c are all located on the element mounting surface of the main control board 61. As previously explained, the element mounting surface of the main control board 61 faces the opposing wall 60b of the board box 60a, but the setting key insertion section 68a, update button 68b, reset button 68c, and reading terminal 68d are not covered by the opposing wall 60b. In other words, the opposing wall 60b has separate openings in the areas facing the setting key insertion section 68a, update button 68b, reset button 68c, and reading terminal 68d, respectively. This makes it possible to insert a setting key into the setting key insertion section 68a, press the update button 68b, press the reset button 68c, and connect the terminals of an external device to the reading terminal 68d without having to open the board box 60a.

[0052] By inserting a setting key into the setting key insertion section 68a and rotating it in a predetermined direction, the setting key insertion section 68a is turned ON. In this state, by starting the supply of operating power to the pachinko machine 10 (i.e., by starting the supply of operating power to the MPU 62 of the main control device 60), the setting state of the pachinko machine 10 becomes changeable. In this state, each time the update button 68b is pressed, the setting state of the pachinko machine 10 is changed one step at a time in ascending order within the range of "Setting 1" to "Setting 6". If the update button 68b is operated while the setting state is "Setting 6", it will be updated to "Setting 1". Furthermore, by rotating the setting key inserted in the setting key insertion section 68a from the ON position in the opposite direction to the predetermined direction and returning it to its initial position, the setting key insertion section 68a is turned OFF. When the setting key insertion section 68a is turned OFF, the above changeable state ends, and the game becomes playable with the setting value at that time. In other words, you cannot change the setting value by operating the update button 68b after the changeable state has ended.

[0053] The ON operation on the setting key insertion unit 68a is only effective when power is supplied to the pachinko machine 10 (i.e., when power is supplied to the MPU 62 of the main control unit 60). Therefore, even if the ON operation on the setting key insertion unit 68a is performed after the power supply start process has been completed in the MPU 62 of the main control unit 60, the setting value cannot be changed.

[0054] The settings of the pachinko machine 10 determine the degree of advantage per unit time in that pachinko machine 10, and the larger the value of "setting n" (where n is an integer from "1" to "6"), the higher the degree of advantage. As will be explained in detail later, there are two win / loss lottery modes that determine the probability of winning a jackpot: a low probability mode where the probability of winning is relatively low, and a high probability mode where the probability of winning is relatively high. The higher the setting value, the higher the probability of winning a jackpot in the low probability mode. On the other hand, the probability of winning a jackpot in the high probability mode remains constant regardless of the setting value.

[0055] As described above, the reset button 68c is operated to clear the data in the main RAM 65. However, in order for this data clearing to occur, it is necessary to start supplying operating power to the pachinko machine 10 while the reset button 68c is pressed (i.e., it is necessary to start supplying operating power to the MPU 62 of the main control unit 60). The ON operation of the reset button 68c is only effective when the supply of operating power to the pachinko machine 10 is started (i.e., when the supply of operating power to the MPU 62 of the main control unit 60 is started). Therefore, even if the reset button 68c is pressed after the processing for starting the supply of operating power has been completed in the MPU 62 of the main control unit 60, it is not possible to clear the data in the main RAM 65.

[0056] As previously explained, the reading terminal 68d is connected to the terminal of an external device in order to read the game history management results or information (programs and data) stored in the main ROM 64. However, in order to output to an external device, it is necessary to start supplying operating power to the pachinko machine 10 with the connection terminal of the external device connected to the reading terminal 68d (i.e., it is necessary to start supplying operating power to the MPU 62 of the main control device 60). The connection of an external device to the reading terminal 68d is only valid when the supply of operating power to the pachinko machine 10 is started (i.e., when the supply of operating power to the MPU 62 of the main control device 60 is started). Therefore, even if an external device is connected to the reading terminal 68d after the processing for starting the supply of operating power has been completed in the MPU 62 of the main control device 60, no external output will be performed to that external device.

[0057] The first to third notification display devices 69a to 69c are all segment displays with seven LED display segments arranged in a row, but are not limited to this; they may also be single multi-color light-emitting devices, liquid crystal displays, or organic EL displays. The first to third notification display devices 69a to 69c are all installed so that their display surfaces face the direction of the element mounting surface of the main control board 61, and are covered by the opposing wall portion 60b of the board box 60a. In this case, because the board box 60a is made transparent, it is possible to visually inspect the display surfaces of the first to third notification display devices 69a to 69c housed inside the board box 60a from outside the board box 60a. Furthermore, as already explained, the main control device 60 is mounted on the back of the resin base 21 in the circuit board box 60a such that the opposing wall portion 60b facing the element mounting surface of the main control board 61 faces the rear of the pachinko machine 10. Therefore, when the game machine body 12 is opened in front of the pachinko machine 10 relative to the outer frame 11, and the back of the resin base 21 is exposed in front of the pachinko machine 10, the display surfaces of the first to third notification display devices 69a to 69c can be visually inspected through the opposing wall portion 60b.

[0058] The display surface of the first notification display device 69a displays not only the numbers "0" to "9" but also various characters, including alphabetical characters. On the other hand, the second notification display device 69b and the third notification display device 69c display only the numbers "0" to "9". The results of managing the game history are notified using the first to third notification display devices 69a to 69c, and the content of this notification will be explained in detail later. Furthermore, when the setting state of the pachinko machine 10 is in a changeable state where it is possible to change the setting state, the value corresponding to the current setting is displayed on the third notification display device 69c. Note that the value corresponding to the setting may be displayed on the first notification display device 69a or on the second notification display device 69b. Alternatively, the setting value before the changeable state is entered may be displayed on one of the first to third notification display devices 69a to 69c, and the current setting value may be displayed on the other of the first to third notification display devices 69a to 69c.

[0059] As shown in Figure 2, the back pack unit 15 is installed so as to cover the back side of the inner frame 13, including the main control device 60. The back pack unit 15 is equipped with a back pack 72 made of transparent synthetic resin, and the dispensing mechanism 73 and the control device assembly unit 74 are attached to the back pack 72.

[0060] The dispensing mechanism 73 includes a tank 75 into which game balls supplied from the island equipment of the gaming hall are replenished sequentially, and a dispensing device 76 for dispensing the game balls stored in the tank 75. The game balls dispensed from the dispensing device 76 are discharged into the upper tray 55a or lower tray 56a through a dispensing passage provided downstream of the dispensing device 76. The dispensing mechanism 73 is supplied with a main power supply of, for example, 24 volts AC, and is equipped with a back-pack circuit board having a power switch for turning the power ON and OFF.

[0061] The control unit 74 includes a payout control device 77 that has the function of controlling the payout device 76, and a power supply / launch control device 78 that generates and outputs predetermined power required by various control devices, and controls the launch of game balls in accordance with the operation of the launching device 28 by the player. The payout control device 77 and the power supply / launch control device 78 are arranged front to back, with the payout control device 77 facing the rear of the pachinko machine 10.

[0062] <Electrical configuration of pachinko machine 10> Figure 6 is a block diagram showing the electrical configuration of the pachinko machine 10.

[0063] The main control device 60 comprises a main control board 61 that is in charge of the main control of the game, and a power failure monitoring board 67 that monitors the power supply. The main control board 61 is equipped with an MPU 62. In addition to the main CPU 63, which is an arithmetic processing unit including a control unit and an arithmetic unit, the MPU 62 also incorporates a main ROM 64, a main RAM 65, and a management IC 66. In addition to the above elements, the MPU 62 also incorporates interrupt circuits, timer circuits, data input / output circuits, and various counter circuits as random number generators.

[0064] The main ROM 64 is a memory (i.e., a non-volatile storage means) that does not require an external power supply for storage, such as NOR flash memory and NAND flash memory, and is used in read-only mode. The main ROM 64 stores various control programs and fixed value data executed by the main CPU 63.

[0065] The main RAM 65 is a memory (i.e., volatile memory) that requires an external power supply for memory retention, such as SRAM and DRAM, and is used for both reading and writing. The main RAM 65 allows random access and, when compared with the main ROM 64 for the same data capacity, has a faster read time. The main RAM 65 temporarily stores various data for the execution of the control program stored in the main ROM 64.

[0066] The management IC 66 is a management device that manages the game history based on information supplied from the main CPU 63. As will be described in detail later, the management IC 66 grasps the history of game balls entering the general prize entry port 31, the special electric prize entry device 32, the first operation port 33, the second operation port 34, and the out port 24a, and also grasps the frequency of balls entering the general prize entry port 31, the special electric prize entry device 32, the first operation port 33, and the second operation port 34 according to the grasped entry history. In addition, the management IC 66 grasps the frequency of occurrence of the opening / closing execution mode and the high-frequency support mode, which will be described later.

[0067] The MPU62 is provided with input and output ports. The input side of the MPU62 is connected to the power outage monitoring board 67 and the payout control device 77, which are provided on the main control device 60. The power outage monitoring board 67 is connected to the power supply / launch control device 78, which has the function of supplying operating power, and the MPU62 is supplied with operating power via the power outage monitoring board 67.

[0068] Various sensors, such as ball entry detection sensors 42a to 49a, are connected to the input side of the MPU 62. As previously explained, the ball entry detection sensors 42a to 49a include the first prize entry sensor 42a, the second prize entry sensor 43a, the third prize entry sensor 44a, the special electric sensor 45a, the first operation opening sensor 46a, the second operation opening sensor 47a, the out opening sensor 48a, and the gate detection sensor 49a. Based on the detection results of these ball entry detection sensors 42a to 49a, the main CPU 63 makes a determination of ball entry into each entry section. In addition, the main CPU 63 executes various lotteries based on ball entry into the first operation opening 33 and also executes various lotteries based on ball entry into the second operation opening 34.

[0069] The input side of the MPU 62 is provided with a setting key insertion section 68a, an update button 68b, and a reset button 68c, which are located on the main control board 61. The setting key insertion section 68a is equipped with a sensor (not shown) that detects whether the setting key insertion section 68a is in the ON position or the OFF position. The main CPU 63 then determines whether the setting key insertion section 68a is in the ON position or the OFF position based on the detection result from the sensor. The update button 68b is equipped with a sensor (not shown) that detects whether the update button 68b is being pressed or not. The main CPU 63 then determines whether the update button 68b is being pressed or not based on the detection result from the sensor. The reset button 68c is equipped with a sensor (not shown) that detects whether the reset button 68c is being pressed or not. The main CPU 63 then determines whether the reset button 68c is being pressed or not based on the detection result from the sensor.

[0070] The output side of the MPU62 is connected to a power outage monitoring board 67, a payout control device 77, and a sound and light emission control device 81. The payout control device 77 outputs a prize ball command based on, for example, when a game ball enters the prize ball corresponding entry section of the ball entry section, where the occurrence of a ball entry corresponds to the payout of game balls. The sound and light emission control device 81 outputs various commands such as variation commands, type commands, and opening commands.

[0071] The output side of the MPU 62 is connected to the special electric drive unit 32b, which opens and closes the opening and closing door 32a of the special electric prize winning device 32; the general electric drive unit 34b, which opens and closes the general electric mechanism 34a of the second operating port 34; the special symbol unit 37; and the general symbol unit 38. Incidentally, the special symbol unit 37 is equipped with a special symbol display unit 37a and a special symbol hold display unit 37b, all of which are connected to the output side of the MPU 62. Similarly, the general symbol unit 38 is equipped with a general symbol display unit 38a and a general symbol hold display unit 38b, all of which are connected to the output side of the MPU 62. Various driver circuits are provided on the main control board 61, and the MPU 62 performs drive control of the various drive units and various display units through these driver circuits.

[0072] In other words, in the opening / closing execution mode, the main CPU 63 controls the drive unit 32b for the special electric prize device 32 so that it is opened and closed. Also, if the open state of the regular electric prize device 34a is selected, the main CPU 63 controls the drive unit 34b for the regular electric prize device 34a so that it is opened and closed. Furthermore, for each game round, the main CPU 63 controls the display of the special symbol display unit 37a. In addition, when the result of the lottery to determine whether or not to open the regular electric prize device 34a is displayed, the main CPU 63 controls the display of the regular symbol display unit 38a. Furthermore, when a prize is awarded in the first operation port 33 or the second operation port 34, or when a variable display is started in the special display unit 37a, the main CPU 63 executes display control of the special hold display unit 37b. When a prize is awarded in the through gate 35, or when a variable display is started in the general display unit 38a, the main CPU 63 executes display control of the general hold display unit 38b.

[0073] The output side of the MPU62 is connected to the first to third notification display devices 69a to 69c. In addition, the results of the game history management by the management IC66 are notified through the displays on the first to third notification display devices 69a to 69c. Furthermore, when the setting state of the pachinko machine 10 is changed, the current setting value is displayed on the third notification display device 69c. In this case, the first notification display device 69a and the second notification display device 69b are displayed and controlled by the management IC66 but not by the main CPU63, whereas the third notification display device 69c is displayed and controlled by both the main CPU63 and the management IC66. The display on the third notification display device 69c is prioritized by the main CPU63 over the display control by the management IC66.

[0074] However, the configuration is not limited to this, and the third notification display device 69c may also be configured to be controlled by the management IC 66 and not controlled by the main CPU 63. In this case, when the current setting value is to be displayed on the third notification display device 69c when the setting state of the pachinko machine 10 is changed, it is preferable that the main CPU 63 instructs the management IC 66 to display the setting value.

[0075] The MPU 62 is provided with a read terminal 68d. A sensor (not shown) is provided on the read terminal 68d, and this sensor detects whether or not an external device's connection terminal is connected to the read terminal 68d. The main CPU 63 then determines whether or not an external device's connection terminal is connected to the read terminal 68d based on the detection result from the sensor. Furthermore, if an external device is connected to the read terminal 68d, the management results of the game history in the management IC 66 or information (programs and data) stored in the main ROM 64 is output to the external device.

[0076] The power outage monitoring board 67 relays the main control board 61 and the power supply / launch control device 78, and monitors the DC stable voltage of 24 volts, which is the maximum voltage output from the power supply / launch control device 78. The payout control device 77 controls the payout of prize balls and loaned balls by the payout device 76 based on the prize ball command received from the main control device 60.

[0077] The power supply and launch control device 78 is connected to a commercial power supply (external power supply) in, for example, a gaming hall. Based on the external power supplied from the commercial power supply, it generates the necessary operating power for the main control board 61, the payout control device 77, etc., and supplies the generated operating power. Incidentally, the power supply and launch control device 78 is equipped with a power supply unit for when the power is off, such as a backup capacitor, so that even when the power to the pachinko machine 10 is OFF, power for memory retention is supplied from this power supply unit to the main RAM 65 of the main control device 60 and the payout control device 77. Furthermore, the power supply and launch control device 78 is responsible for the launch control of the game ball launching mechanism 27, and the game ball launching mechanism 27 is driven when predetermined launch conditions are met. In addition, as already explained, the payout mechanism unit 73 is equipped with a power switch, and when the power switch is turned ON, the supply of operating power to the pachinko machine 10 is started, and when the power switch is turned OFF, the supply of operating power to the pachinko machine 10 is stopped.

[0078] The sound and light emission control device 81 drives and controls the display light emission unit 53 and speaker unit 54 provided on the front door frame 14 based on various commands received from the main control device 60, and also controls the display control device 82. The display control device 82 performs display control of the pattern display device 41 based on commands received from the sound and light emission control device 81.

[0079] <Electrical configuration for performing various lottery draws on the main CPU 63> Next, the electrical configuration for performing various lotteries on the main CPU 63 will be explained using Figure 7.

[0080] The main CPU 63 uses various counter information during gameplay to perform tasks such as the lottery for the occurrence of a jackpot, setting the display of the special symbol display unit 37a, setting the symbol display of the symbol display device 41, and setting the display of the regular symbol display unit 38a. Specifically, as shown in Figure 7, it uses a random number counter C1 used for the lottery for the occurrence of a jackpot, a jackpot type counter C2 used for determining the type of jackpot, a random number counter C3 used for the lottery for the occurrence of a reach when the symbol display device 41 is fluctuating to a miss, a random number initial value counter CINI used for setting the initial value of the random number counter C1, and a fluctuation type counter CS that determines the display duration in the special symbol display unit 37a and the symbol display device 41. Furthermore, it uses a regular power function release counter C4 used for the lottery for whether or not to set the regular power function 34a of the second operation port 34 to the regular power release state. Note that each of the above counters C1 to C3, CINI, CS, and C4 are provided in the various counter areas 65b of the main RAM 65.

[0081] Each counter C1-C3, CINI, CS, and C4 is a loop counter in which 1 is added to the previous value each time it is updated, and it returns to "0" after reaching the maximum value. Each counter is updated at short intervals. Information corresponding to the winning random number counter C1, the jackpot type counter C2, and the reach random number counter C3 is stored in the reserve storage area 65a provided as an acquired information storage means in the main RAM 65 when a prize is awarded to the first operation port 33 or the second operation port 34.

[0082] The hold storage area 65a comprises a hold area RE and an execution area AE. The hold area RE comprises a first hold area RE1, a second hold area RE2, a third hold area RE3, and a fourth hold area RE4. In accordance with the winning history of the first operation port 33 or the second operation port 34, a combination of numerical information from the winning random number counter C1, the jackpot type counter C2, and the reach random number counter C3 is stored as hold information in one of the hold areas RE1 to RE4.

[0083] In this case, when multiple consecutive entries into the first or second operating port 33 occur, the numerical information is stored chronologically in the first to fourth holding areas RE1, RE2, RE3, and RE4, respectively. With these four holding areas RE1 to RE4, up to four entries of the game ball entry history into the first or second operating port 33 can be stored in reserve.

[0084] Furthermore, the number of items that can be stored in reserve is not limited to four; it can be any number, such as two, three, five or more, or even a single item.

[0085] The execution area AE is an area for moving the numerical information stored in the first reserve area RE1 of the reserve area RE when the variable display of the special display unit 37a is started. At the start of each game round, a win / loss determination is made based on the various numerical information stored in the execution area AE.

[0086] The above counters will be explained in detail below.

[0087] First, let's explain the regular electric feature release counter C4. The regular electric feature release counter C4 is configured to increment by 1 sequentially within the range of 0 to 250, and then return to "0" after reaching the maximum value. The regular electric feature release counter C4 is updated periodically and stored in the regular electric reserve area 65c of the main RAM 65 when a game ball enters the through gate 35. Then, at a predetermined timing, a lottery is held to determine whether or not to control the regular electric feature 34a to the open state based on the value of the stored regular electric feature release counter C4.

[0088] In this pachinko machine 10, multiple support modes are set so that the manner of support provided by the electric power supply mechanism 34a differs from one another. Specifically, the support modes include a high-frequency support mode and a low-frequency support mode, which are set so that the frequency at which the electric power supply mechanism 34a of the second operating port 34 is open per unit time is relatively high or low when compared in a situation where game balls are continuously launched in the game area PA in a similar manner.

[0089] In both the high-frequency support mode and the low-frequency support mode, the probability of winning the normal electric power opening state in the normal electric power opening lottery using the normal electric power opening counter C4 is the same (for example, 4 / 5 in both modes). However, in the high-frequency support mode, the number of times the normal electric power opening state is opened when the normal electric power opening state is won is set to be greater than in the low-frequency support mode, and the duration of each opening is also set to be longer. In this case, when the normal electric power opening state is won in the high-frequency support mode and the normal electric power opening state of the normal electric power opening state occurs multiple times, the closing time from the end of one opening state to the start of the next opening state is set to be shorter than the duration of one opening. Furthermore, in the high-frequency support mode, the minimum time required to ensure that the next normal electric power opening lottery is held after one normal electric power opening lottery is held (i.e., the duration of one display in the normal electric power display unit 38a) is set to be shorter than in the low-frequency support mode.

[0090] As described above, in high-frequency support mode, the probability of a ball entering the second operating port 34 is higher than in low-frequency support mode. In other words, in low-frequency support mode, the probability of a ball entering the first operating port 33 is higher than in the second operating port 34, but in high-frequency support mode, the probability of a ball entering the second operating port 34 is higher than in the first operating port 33. When a ball enters the second operating port 34, a predetermined number of game balls are dispensed, so in high-frequency support mode, players can play without significantly reducing their number of balls.

[0091] Furthermore, the configuration for making the high-frequency support mode more frequent than the low-frequency support mode in terms of the frequency of normal power opening per unit time is not limited to the above, and for example, a configuration that increases the probability of winning the normal power opening state in the normal power opening lottery may also be used. In addition, in a configuration where multiple types of reservation time are available for the period between one normal power opening lottery and the next normal power opening lottery (for example, the time for the variable display executed by the normal power display unit 38a based on the entry into the through gate 35), the high-frequency support mode may be set to be more likely to select a shorter reservation time or to have a shorter average reservation time than the low-frequency support mode. Moreover, the advantage of the high-frequency support mode over the low-frequency support mode may be increased by applying any one of the following conditions or any combination of conditions: increasing the number of openings, increasing the opening time, decreasing the reservation time between one normal power opening lottery and the next normal power opening lottery, decreasing the average time of the reservation time, and increasing the probability of winning.

[0092] As explained earlier, the pachinko machine 10 has six settings, "Setting 1" to "Setting 6". However, the opening frequency and manner of the electric device 34a in the low-frequency support mode are the same regardless of the setting value, and the opening frequency and manner of the electric device 34a in the high-frequency support mode are also the same regardless of the setting value. However, this is not the only option, and the machine may be configured such that at least one of the opening frequency and manner of the electric device 34a in at least one of the low-frequency support mode and high-frequency support mode varies according to the setting of the pachinko machine 10. For example, the machine may be configured such that the opening frequency of the electric device 34a in the low-frequency support mode increases as the setting value increases, or the probability of a game ball entering the second operating port 34 when the electric device 34a is open once in the low-frequency support mode increases. Furthermore, the higher the setting value, the more frequently the regular electric device 34a opens in high-frequency support mode, and the higher the probability of a game ball entering the second operating port 34 when the regular electric device 34a opens once in high-frequency support mode.

[0093] Next, let's explain the winning random number counter C1. The winning random number counter C1 is configured to increment by 1 sequentially within a range of, for example, 0 to 599, and then return to "0" after reaching the maximum value. In particular, when the winning random number counter C1 completes one cycle, the value of the random number initial value counter CINI at that time is read as the initial value of the winning random number counter C1. The random number initial value counter CINI is a loop counter similar to the winning random number counter C1 (value = 0 to 599). The winning random number counter C1 is updated periodically and stored in the reserve storage area 65a of the main RAM 65 when a game ball enters the first operation opening 33 or the second operation opening 34.

[0094] The random number values ​​that result in a jackpot are stored in the main ROM 64 as a win / loss table. Figure 8 is an explanatory diagram for illustrating the various tables stored in the main ROM 64. The win / loss tables stored are low-probability win / loss tables 64a to 64f for low-probability mode and high-probability win / loss table 64g for high-probability mode.

[0095] Low probability win / loss tables 64a to 64f are provided with a one-to-one correspondence to the setting states "Setting 1" to "Setting 6". In other words, there is a low probability win / loss table 64a for Setting 1, which is referenced when the setting state of the pachinko machine 10 is "Setting 1", a low probability win / loss table 64b for Setting 2, which is referenced when the setting state of the pachinko machine 10 is "Setting 2", a low probability win / loss table 64c for Setting 3, which is referenced when the setting state of the pachinko machine 10 is "Setting 3", a low probability win / loss table 64d for Setting 4, which is referenced when the setting state of the pachinko machine 10 is "Setting 4", a low probability win / loss table 64e for Setting 5, which is referenced when the setting state of the pachinko machine 10 is "Setting 5", and a low probability win / loss table 64f for Setting 6, which is referenced when the setting state of the pachinko machine 10 is "Setting 6".

[0096] These low-probability win / loss tables 64a to 64f are set so that the higher the setting value, the higher the probability of winning a jackpot. Specifically, when low-probability win / loss table 64a for setting 1 is referenced, the probability of winning a jackpot is approximately 1 / 320; when low-probability win / loss table 64b for setting 2 is referenced, the probability of winning a jackpot is approximately 1 / 310; when low-probability win / loss table 64c for setting 3 is referenced, the probability of winning a jackpot is approximately 1 / 300; when low-probability win / loss table 64d for setting 4 is referenced, the probability of winning a jackpot is approximately 1 / 290; when low-probability win / loss table 64e for setting 5 is referenced, the probability of winning a jackpot is approximately 1 / 280; and when low-probability win / loss table 64f for setting 6 is referenced, the probability of winning a jackpot is approximately 1 / 270. As a result, when the setting state of the pachinko machine 10 is a higher value, jackpot results are more likely to occur in low-probability mode, which is advantageous for the player.

[0097] On the other hand, there is only one high-probability win / loss table 64g, which is common to all settings from "Setting 1" to "Setting 6". High-probability win / loss table 64g is set so that the probability of winning a jackpot is higher than that of low-probability win / loss tables 64a to 64f, regardless of the setting from "Setting 1" to "Setting 6". Specifically, when high-probability win / loss table 64g is referenced, there is approximately a 1 / 30 chance of winning a jackpot. This makes it possible to make the high-probability mode more advantageous than the low-probability mode, regardless of the setting of the pachinko machine 10. Furthermore, even in the lowest setting state, "Setting 1", the probability of winning a jackpot is higher than in the low-probability mode of the highest setting state, "Setting 6", because it is in high-probability mode. In addition, it is possible to make the high-probability mode so that there is no advantage or disadvantage depending on the setting of the pachinko machine 10, and it is possible to reduce the memory capacity required to pre-store high-probability win / loss table 64g in the main ROM 64.

[0098] The jackpot type counter C2 is configured to increment by 1 in the range of 0 to 29, and then return to "0" after reaching the maximum value. The jackpot type counter C2 is updated periodically and stored in the reserve storage area 65a when a game ball enters the first operation opening 33 or the second operation opening 34.

[0099] In this pachinko machine 10, multiple jackpot results are set. These multiple jackpot results are set by making differences in three conditions: (1) the manner of opening and closing control of the special electric prize entry device 32 in the opening and closing execution mode, (2) the lottery mode in the win / loss lottery means after the opening and closing execution mode has ended, and (3) the support mode of the regular electric mechanism 34a of the second operating port 34 after the opening and closing execution mode has ended.

[0100] In the opening and closing execution mode, the opening and closing control of the special electric prize winning device 32 is configured such that the frequency of winning to the special electric prize winning device 32 during the period from the start to the end of the opening and closing execution mode is relatively high or low, with a high-frequency winning mode and a low-frequency winning mode being set. Specifically, in either the high-frequency winning mode or the low-frequency winning mode, the game is executed up to a predetermined number of rounds.

[0101] A round game is a game that continues until either a predetermined maximum duration has elapsed, or a predetermined maximum number of game balls have entered the special electric prize winning device 32, is met. Furthermore, the number of round games in the opening / closing execution mode triggered by a jackpot result is fixed and the same regardless of the type of jackpot result that triggered the transition. Specifically, regardless of the type of jackpot result, the maximum number of round games is set to 15 rounds.

[0102] Furthermore, in this pachinko machine 10, the opening mode of the special electric prize winning device 32 is set to have multiple variations, differing in the duration of opening from the time the special electric prize winning device 32 is opened until it is closed. Specifically, there is a long-duration mode in which the duration of opening is set to a long 29 seconds, and a short-duration mode in which the duration of opening is set to a shorter 0.06 seconds.

[0103] In this pachinko machine 10, when the launching device 28 is operated by the player, the game ball launching mechanism 27 is driven and controlled so that one game ball is launched towards the game area PA every 0.6 seconds. Also, the maximum number of balls required to complete a round game is set to 9. In this case, in the long-duration mode of opening, the opening duration is set to be longer than the product of the game ball launching cycle and the duration of one round game. On the other hand, in the short-duration mode, the opening duration is set to be shorter than the product of the game ball launching cycle and the duration of one round game, or more specifically, shorter than the game ball launching cycle. Therefore, when an opening occurs in the long-duration mode, it is expected that the special electric prize winning device 32 will receive the maximum number of balls that can be won in one round game, while when an opening occurs in the short-duration mode, it is expected that no balls will be won into the special electric prize winning device 32, or that only about one ball will be won.

[0104] In the high-frequency winning mode, the special electric winning device 32 is opened once in a long-duration manner during each round of gameplay. On the other hand, in the low-frequency winning mode, the special electric winning device 32 is opened once in a short-duration manner during each round of gameplay.

[0105] Furthermore, the number of times the special electric prize device 32 is opened and closed, the number of rounds played, the duration of opening for each opening, and the maximum number of prizes per round in the high-frequency prize mode and low-frequency prize mode are not limited to the above values ​​and are arbitrary, as long as the frequency of prizes entering the special electric prize device 32 from the start to the end of the opening and closing execution mode is higher in the high-frequency prize mode than in the low-frequency prize mode.

[0106] As shown in Figure 8, the distribution destinations for jackpot results for the jackpot type counter C2 are stored in the main ROM 64 as a distribution table 64h. In the distribution table 64h, when a jackpot result occurs, the distribution destinations for the jackpot result are set as low probability jackpot result, low-scoring high probability jackpot result, and most advantageous jackpot result.

[0107] A low-probability jackpot result is one in which the opening / closing execution mode becomes the high-frequency winning mode, and after the opening / closing execution mode ends, the win / loss lottery mode becomes the low-probability mode, and the support mode becomes the high-frequency support mode. However, this high-frequency support mode will revert to the low-frequency support mode if the number of games played after the transition reaches the termination threshold (specifically, 100 games).

[0108] A low-stakes, high-probability jackpot result is one in which the opening / closing execution mode becomes the low-frequency winning mode, and after the opening / closing execution mode ends, the win / fail lottery mode becomes the high-probability mode, and the support mode becomes the high-frequency support mode. These high-probability modes and high-frequency support modes continue until the lottery result in a jackpot state is won, and the game transitions to the jackpot state as a result.

[0109] The most advantageous jackpot result is one in which the opening / closing execution mode becomes a high-frequency winning mode, and after the opening / closing execution mode ends, the win / fail lottery mode becomes a high-probability mode, and the support mode becomes a high-frequency support mode. These high-probability modes and high-frequency support modes continue until the lottery result in a jackpot state is won, and the game transitions to the jackpot state.

[0110] Furthermore, in relation to the above game states, the "normal game state" refers to a state that is not in the opening / closing execution mode, and furthermore, the win / loss lottery mode is in the low probability mode, and the support mode is in the low-frequency support mode. In addition, the game result may be configured so that a low-winning, high-probability jackpot result is not set. Also, in the opening / closing execution mode for the low-winning, high-probability jackpot result, the number of rounds played may be configured to be fewer than in the case of the low-probability jackpot result and the most advantageous jackpot result.

[0111] In the distribution table 64h, among the values ​​of the jackpot type counter C2 from "0 to 29", "0 to 9" correspond to low probability jackpot results, "10 to 14" correspond to low-winning high probability jackpot results, and "15 to 29" correspond to the most advantageous jackpot results.

[0112] Only one distribution table 64h is provided so that it is common regardless of whether the setting state is "Setting 1" to "Setting 6". This makes it possible to prevent any advantage or disadvantage in the distribution of jackpot results depending on the setting state of the pachinko machine 10, and also makes it possible to reduce the storage capacity required to pre-store the distribution table 64h in the main ROM 64.

[0113] Furthermore, the distribution of jackpot results may differ depending on the settings of the pachinko machine 10. For example, the higher the setting value, the higher the probability of being allocated to the most advantageous jackpot result, or the higher the setting value, the higher the probability of being allocated to either the most advantageous jackpot result or the low-entry high-probability jackpot result. In this case, the higher the setting value, the higher the probability of entering high-probability mode after a jackpot result. Alternatively, the higher the setting value, the lower the probability of being allocated to the low-entry high-probability jackpot result, or the higher the setting value, the less likely the result is to be allocated to the low-entry high-probability jackpot result, while the lower the setting value may result in a low-entry high-probability jackpot result. In this case, the higher the setting value, the higher the probability of the high-frequency entry mode opening and closing execution mode occurring.

[0114] Next, the reach random number counter C3 will be explained. The reach random number counter C3 is configured to increment by 1 sequentially within the range of 0 to 238, for example, and then return to "0" after reaching the maximum value. This pachinko machine 10 has an expectation effect set as a type of display effect in the symbol display device 41. An expectation effect is a display state that makes the player think that the symbol display state is likely to result in the aforementioned assigned result, in a game machine equipped with a symbol display device 41 that can display the variation of symbols, and in a game round that results in a predetermined jackpot result, the final stop result is the assigned result, from the start of the variation display of symbols in the symbol display device 41 until the stop result is derived and displayed. Specifically, the assigned result is a combination of symbols with the same number on any of the active lines that is stopped and displayed.

[0115] There are two types of anticipation-based effects: a "reach" display and a pre-announcement display that anticipates the occurrence of a reach display or the corresponding result before the reach display occurs.

[0116] The reach display includes a display state in which a combination of reach symbols is displayed by stopping the symbols in some of the multiple symbol sequences displayed on the display surface 41a of the symbol display device 41, and then the remaining symbol sequences are displayed in a variable state. Furthermore, the reach effect is performed by displaying the combination of reach symbols as described above, then displaying the remaining symbol sequences in a variable state, and displaying predetermined characters as animations on the background screen, or by reducing or hiding the combination of reach symbols, and then displaying predetermined characters as animations on almost the entire display surface 41a to perform the reach effect.

[0117] The notification display includes a mode in which a character is displayed separately from the symbols on the symbol rows when the symbol variation display has started on the display surface 41a of the symbol display device 41, and when the symbols are varying in all symbol rows, or when the symbols are varying in some symbol rows but multiple symbol rows are varying. It also includes modes in which the background screen is changed to a predetermined mode different from the previous mode, or when the symbols on the symbol rows are changed to a predetermined mode different from the previous mode. Such notification displays can occur in both game rounds when a reach display is made and when a reach display is not made, but they are set to occur with a higher probability when a reach display is made than when a reach display is not made.

[0118] The reach display is executed regardless of the value of the reach random number counter C3 in game rounds where the same combination of symbols ultimately stops and is displayed. Also, in game rounds corresponding to a jackpot result where the same combination of symbols does not stop and is not displayed, the reach display is not executed regardless of the value of the reach random number counter C3. Furthermore, in game rounds corresponding to a losing result, the reach display is executed if the reach random number counter C3, obtained at a predetermined timing by referring to the reach table stored in the main ROM 64, corresponds to the occurrence of a reach display.

[0119] On the other hand, the decision of whether or not to display a notification is made not by the main control device 60, but by the sound and light emission control device 81. In this case, the sound and light emission control device 81 executes a lottery process for displaying notifications so that at least one of the following conditions is met: the notification is more likely to occur in the game round corresponding to a jackpot result compared to the game round corresponding to a losing result, and the notification with a low appearance rate is more likely to occur. Incidentally, the result of this lottery is reflected when the game round's effects are executed by the symbol display device 41.

[0120] Here, the probability of a reach display occurring in a game round that results in a loss is the same regardless of whether the setting is "Setting 1" to "Setting 6". This makes it possible to ensure that there is no advantage or disadvantage depending on the setting of the pachinko machine 10 regarding the probability of a reach display occurring in a game round that results in a loss. However, this is not the only option, and the machine may be configured so that the probability of a reach display occurring in a game round that results in a loss increases with higher setting values.

[0121] Next, the variation type counter CS will be explained. The variation type counter CS is configured to increment by 1 sequentially within a range of, for example, 0 to 198, and then return to "0" after reaching the maximum value. The variation type counter CS is used by the main CPU 63 to determine the display duration in the special display unit 37a and the display duration of the symbols in the symbol display device 41. The variation type counter CS is updated once each time the timer interrupt processing described later is executed, and is repeatedly updated within the remaining time until the next timer interrupt processing is executed. The buffer value of the variation type counter CS is acquired when determining the variation pattern at the start of the variation display in the special display unit 37a and at the start of the variation of the symbols by the symbol display device 41.

[0122] <Regarding the processing configuration of the main CPU63> Next, we will explain the processes executed by the main CPU 63 to advance the game. These processes of the main CPU 63 can be broadly divided into the main process, which is started when the power is turned on, and the timer interrupt process, which is started periodically (at a 4-millisecond interval in this embodiment).

[0123] <Main Processing> First, the main process will be explained while referring to the flowchart in Figure 9.

[0124] First, a power-on wait process is performed (step S101). In this power-on wait process, for example, the system waits without proceeding to the next process until a predetermined waiting time (specifically 1 second) has elapsed after the main process has started. During the execution period of this power-on wait process, the operation start and initial setup of the graphic display device 41 are completed. After that, access to the main RAM 65 is permitted (step S102).

[0125] Subsequently, it is determined whether the setting key insertion unit 68a is turned ON (step S103). If the setting key insertion unit 68a is not turned ON (step S103: NO), it is determined whether the reset button 68c is pressed (step S104). If the reset button 68c is pressed (step S104: YES), each area of ​​the main RAM 65 is cleared to "0" except for the area where setting value information indicating the setting state of the pachinko machine 10 is set, and initial settings are performed on the areas that have been cleared to "0" (step S105). In other words, if the supply of operating power to the pachinko machine 10 is started while the reset button 68c is pressed without turning ON the setting key insertion unit 68a, the setting value information is maintained in the state it was in before the supply of operating power to the pachinko machine 10 was stopped, and the clearing process of the main RAM 65 is performed, and initial settings are performed on the memory areas where the clearing process was performed. This makes it possible to initialize other areas of the main RAM 65 without having to change the setting value. In step S105, the various registers of the main CPU 63 are also cleared to "0" before initializing them.

[0126] If the reset button 68c is not pressed (step S104: NO), it is determined whether the power outage flag is set to "1" (step S106). The power outage flag is located in the main RAM 65, and if the predetermined power outage processing is executed successfully when the power supply to the main CPU 63 is stopped, the power outage flag is set to "1". If the power outage flag is set to "1", it is determined whether the calculated checksum matches the checksum saved when the power was cut off, i.e., the validity of the stored data (step S107). If the process in step S105 is executed, or if an affirmative determination is made in step S107, it is determined whether the setting value of the pachinko machine 10 is normal by checking the main RAM 65 (step S108). Specifically, it is determined to be normal if the setting value is one of "setting 1" to "setting 6", and abnormal if it is "0" or 7 or more.

[0127] If a negative result is obtained in any of steps S106 to S108, the operation prohibition process is executed. In the operation prohibition process, an error notification process is executed to notify the hall manager, etc., of the occurrence of an error (step S109), and then an infinite loop is entered. This operation prohibition process is released when the all-clear process (step S117), which will be described later, is executed.

[0128] If all of steps S106 to S108 result in a positive determination, the power-on setting process is executed (step S110). In the power-on setting process, predetermined areas of the main RAM 65, such as the power outage flag, are set to their initial values, and a command corresponding to the current game state is sent to the sound and light emission control device 81. After executing the process in step S110, a recognition process (step S111) is executed to allow the management IC 66 to recognize various information, and a data output process (step S112) is executed to output various data to an external device connected to the reading terminal 68d of the MPU 62. Details of these recognition and data output processes will be explained later.

[0129] The main CPU 63 is configured to periodically execute timer interrupt processing, but the generation of timer interrupt processing is prohibited when the main processing starts. This state of prohibition on timer interrupt processing is released when the processing in step S112 is completed and before the processing in step S113 is executed, and the execution of timer interrupt processing is permitted. As a result, when power supply to the main CPU 63 is started, the timer interrupt processing will not be executed until the data output processing in step S112 is completed and before the processing in step S113 is started. Therefore, until this situation occurs, the processing to advance the game will not be started by the main CPU 63.

[0130] Subsequently, the process proceeds to the residual processing steps S113 to S116. In other words, the main CPU 63 is configured to periodically execute timer interrupt processing, but there is residual time between one timer interrupt processing and the next. This residual time will vary depending on the processing completion time of each timer interrupt processing, and the residual processing steps S113 to S116 are repeatedly executed using this irregular time. In this respect, the residual processing steps S113 to S116 can be said to be an irregular process that is executed irregularly.

[0131] In the remaining processing, first in step S113, the interrupt disable setting is performed to prevent the occurrence of timer interrupt processing. In the following step S114, the random number initial value update process is executed to update the random number initial value counter CINI, and in step S115, the variation counter update process is executed to update the variation type counter CS. In these update processes, the current numerical information is read from the corresponding counter in the main RAM 65, the read numerical information is incremented by 1, and then the original counter is overwritten. In this case, if the counter value exceeds the maximum value, it is cleared to "0". After that, in step S116, the interrupt enable setting is performed to switch from a state where the occurrence of timer interrupt processing is prohibited to a state where it is enabled. If the process in step S116 is executed, the process returns to step S113 and steps S113 to S116 are repeated.

[0132] On the other hand, if the setting key insertion unit 68a is turned ON (step S103: YES), all areas of the main RAM 65, including the area where setting value information indicating the setting state of the pachinko machine 10 is set, are cleared to "0", and initial settings are performed on the areas that have been cleared to "0" (step S117). In other words, if an operation to change the setting state of the pachinko machine 10 is being performed, all areas of the main RAM 65 are cleared to "0" and initial settings are performed on the memory areas where the clearing process was performed. In addition, in step S117, various registers of the main CPU 63 are also cleared to "0" and then initial settings are performed. However, this is not the only configuration; even if an operation to change the setting state of the pachinko machine 10 is being performed, if the reset button 68c is not pressed, the complete clearing process of the main RAM 65 is not performed, and the complete clearing process is performed only when an operation to change the setting state of the pachinko machine 10 is being performed and the reset button 68c is pressed.

[0133] Subsequently, the setting value update process is executed in step S118, and the setting value update signal output process is executed in step S119, after which the process proceeds to step S110. The setting value update process will be described below. The setting value update signal output process will be explained in detail later. Figure 10 is a flowchart of the setting value update process.

[0134] First, the setting value counter located in the main RAM 65 is set to "1" (step S201). The setting value counter is used by the main CPU 63 to determine which setting value the pachinko machine 10 is currently set to. When the setting value counter is set to "1", the setting value becomes "Setting 1" regardless of the previous setting value when the setting value update process is executed.

[0135] Subsequently, the process to start displaying the setting value is executed (step S202). During the process to start displaying the setting value, the display control of the third notification display device 69c is performed so that the number "1" corresponding to "Setting 1" is displayed. When changing the setting value, the manager of the amusement hall can check the third notification display device 69c to understand the current setting status of the pachinko machine 10.

[0136] Subsequently, assuming that the setting key insertion unit 68a is not in the OFF position (step S203: NO), it is determined whether the update button 68b has been pressed once (step S204). Specifically, it is determined whether the signal from the sensor that detects the pressing of the update button 68b has switched from a LOW level to a HI level. If a negative determination is made in step S204, the process returns to step S203, and it is determined whether the setting key insertion unit 68a is in the OFF position.

[0137] If the update button 68b is pressed once (step S204: YES), the value of the setting value counter in the main RAM 65 is incremented by 1 (step S205). Furthermore, if the value of the setting value counter after incrementing by 1 exceeds "6" (step S206: YES), the setting value counter is set to "1" (step S207). As a result, each time the update button 68b is pressed, the setting value is updated to the next higher level, and if the update button 68b is pressed once while the setting is "6", it will return to "1".

[0138] If a negative result is obtained in step S206, or if the process in step S207 is executed, the setting value display update process is executed (step S208). In the setting value display update process, the display control of the third notification display device 69c is performed so that a number corresponding to the value of the setting value counter in the main RAM 65 is displayed. By checking the third notification display device 69c, the manager of the amusement hall can understand the setting status of the pachinko machine 10 after pressing the update button 68b.

[0139] After executing the process in step S208, the process returns to step S203 to determine whether the setting key insertion unit 68a is in the OFF position. If it is not in the OFF position (step S203: NO), the process from step S204 onwards is executed again. If it is in the OFF position (step S203: YES), the process to terminate the display of the setting value is executed (step S209). In the process to terminate the display of the setting value, the display of the setting value on the third notification display device 69c is terminated.

[0140] <Timer interrupt handling> Next, we will explain the timer interrupt handling process while referring to the flowchart in Figure 11. The timer interrupt handling process is executed periodically (for example, every 4 milliseconds).

[0141] First, the power outage information storage process is executed (step S301). In the power outage information storage process, the power outage monitoring board 67 monitors whether or not a power outage signal corresponding to the occurrence of a power interruption has been received. If a power outage is identified, the power outage processing is executed, followed by an infinite loop. In the power outage processing, the power outage flag in the main RAM 65 is set to "1", a checksum is calculated, and the calculated checksum is saved.

[0142] Subsequently, the random number update process for the lottery is executed (step S302). In the random number update process for the lottery, the winning random number counter C1, the jackpot type counter C2, the reach random number counter C3, and the normal electric device release counter C4 are updated. Specifically, the current numerical information is read sequentially from the winning random number counter C1, the jackpot type counter C2, the reach random number counter C3, and the normal electric device release counter C4, and after incrementing each of the read numerical values ​​by 1, the original counters are overwritten. In this case, if the counter value exceeds the maximum value, it is cleared to "0". Subsequently, in step S303, the random number initial value update process is executed in the same way as in step S114, and in step S304, the variable counter update process is executed in the same way as in step S115.

[0143] Subsequently, a fraud detection process is executed to monitor whether a predetermined event, which is set as a target for monitoring fraud, has occurred (step S305). In this fraud detection process, the occurrence of multiple types of events is monitored, and upon confirming that a predetermined event has occurred, the game stop flag provided in the main RAM 65 is set to "1". In the following step S306, it is determined whether the game has stopped by checking whether the game stop flag is set to "1". If the determination in step S306 is negative, the processes from step S307 onwards are executed.

[0144] In step S307, port output processing is performed. In port output processing, if output information was set in the previous timer interrupt processing, processing is performed to output the corresponding output information to the various drive units 32b and 34b. For example, if information is set to switch the special electric prize device 32 to the open state, the output of a drive signal to the special electric drive unit 32b is started, and if information is set to switch it to the closed state, the output of the drive signal is stopped. Also, if information is set to switch the regular electric mechanism 34a of the second operating port 34 to the open state, the output of a drive signal to the regular electric drive unit 34b is started, and if information is set to switch it to the closed state, the output of the drive signal is stopped.

[0145] Subsequently, a read operation is performed (step S308). In the read operation, signals other than the power outage signal and the winning signal are read, and the read information is stored for use in subsequent processing.

[0146] Subsequently, ball entry detection processing is performed (step S309). In this ball entry detection processing, signals received from each ball entry detection sensor 42a to 49a are read, and based on the reading results, it is determined whether or not a ball has entered the out gate 24a, the general prize gate 31, the special electric prize device 32, the first operation gate 33, the second operation gate 34, and the through gate 35. Details of the ball entry detection processing will be explained later.

[0147] Subsequently, a timer update process is executed to update the numerical information of multiple types of timer counters provided in the main RAM 65 (step S310). In this case, the configuration is to aggregate and handle timer counters whose stored numerical information is updated by subtraction, but it is also possible to aggregate and perform updates for both subtraction-type timer counters and addition-type timer counters.

[0148] Subsequently, a launch control process is executed to control the launch of the game balls (step S311). If the launch operation to the launch operation device 28 is continued, one game ball is launched every 0.6 seconds, which is a predetermined launch cycle. In the following step S312, as an input state monitoring process, based on the information read in the reading process of step S308, the system checks for disconnections in each ball entry detection sensor 42a to 49a and confirms that the game machine body 12 and the front door frame 14 are open.

[0149] Subsequently, a special feature and special electrical control process is executed to control the execution of the game rounds and the opening / closing execution mode (step S313). The special feature and special electrical control process will be explained in detail later.

[0150] Subsequently, the regular power control process is executed (step S314). In the regular power control process, if a prize is awarded at the through gate 35, a process is executed to acquire the regular power reserve information. If the regular power reserve information is stored, an opening determination is made for that reserve information, and a process is executed to perform a regular power effect triggered by that opening determination. Furthermore, based on the result of the opening determination, a process is executed to open and close the regular power mechanism 34a of the second operating port 34. In this case, if the support mode is the low-frequency support mode, the corresponding process is executed, and if the support mode is the high-frequency support mode, the corresponding process is executed. Also, if the opening / closing execution mode is selected, the mode becomes the low-frequency support mode even if the previous support mode was the high-frequency support mode.

[0151] In the following step S315, based on the processing results of the preceding steps S313 and S314, output information is set to reflect the increase or decrease in the number of reserved information related to the special figure display unit 37a in the special figure reserved display unit 37b, and output information is set to reflect the increase or decrease in the number of reserved information related to the general figure display unit 38a in the general figure reserved display unit 38b. Also in step S315, based on the processing results of the preceding steps S313 and S314, output information is set to update the display content of the special figure display unit 37a, and output information is set to update the display content of the general figure display unit 38a.

[0152] Subsequently, the system checks the contents of the commands and signals received from the payout control device 77 and executes a payout status reception process to perform processing corresponding to the confirmation results (step S316). It also executes a payout output process to set the prize ball command as the output target (step S317). Furthermore, it executes an external information setting process to control the start and end of the output of external signals according to the processing results of the various processes performed in this timer interrupt process (step S318). Finally, it executes a management output process to output information corresponding to the ball entry results in the game area PA to the management IC 66 (step S319). Details of the management output process will be explained later.

[0153] Next, the special electric control process in step S313 will be explained with reference to the flowchart in Figure 12.

[0154] First, the process for acquiring pending information is executed (step S401). In the pending information acquisition process, it is determined whether or not a prize has been won in the first operation port 33 or the second operation port 34. If a prize has been won, it is determined whether or not the number of pending items in the pending storage area 65a is less than the upper limit (4 in this embodiment). If the number of pending items is less than the upper limit, the number of pending items is increased by 1, and the numerical information of the winning random number counter C1, the big win type counter C2, and the reach random number counter C3, which were updated in the previous step S302, is stored in the first pending area among the empty pending areas RE1 to RE4 of the pending area RE. If prizes are won in both the first operation port 33 and the second operation port 34 simultaneously, the process for acquiring the pending information is executed multiple times within the time frame in which the pending information acquisition process is executed once. In addition, if new pending information is acquired, the corresponding acquisition command is sent to the voice and light emission control device 81. When the audio light emission control device 81 receives the command, it updates the image displayed on the pattern display device 41, which shows the number of pending information items, to reflect the increase in pending information.

[0155] Subsequently, the information of the special feature and special power counter provided in the main RAM 65 is read (step S402), and the special feature and special power address table provided in the main ROM 64 is read (step S403). Then, the starting address corresponding to the information of the special feature and special power counter is obtained from the special feature and special power address table (step S404), and the system jumps to the process indicated by the obtained starting address among the processes in steps S406 to S412 (step S405). The special feature and special power counter is a counter used by the main CPU 63 to determine which of the various processes in steps S406 to S412 should be executed, and the special feature and special power address table has the starting addresses of the programs for executing the processes in steps S406 to S412 set in correspondence with the numerical information of the special feature and special power counter.

[0156] Step S406 executes the special feature variation start process. Figure 13 is a flowchart of the special feature variation start process.

[0157] In the special feature variation start process, the data setting process is executed (step S502) on the condition that the number of reserved information stored in the reserved area RE is 1 or more (step S501: YES). In the data setting process, first the number of reserved items is deducted by 1, and the data stored in the first reserved area RE1 of the reserved area RE is moved to the execution area AE. After that, a process is executed to shift the data stored in each reserved area RE1 to RE4 of the reserved area RE. This data shift process shifts the data stored in the first reserved area RE1 to the fourth reserved area RE4 sequentially to the lower areas. Specifically, the data in each area is shifted from the second reserved area RE2 to the first reserved area RE1, from the third reserved area RE3 to the second reserved area RE2, and from the fourth reserved area RE4 to the third reserved area RE3, and then the fourth reserved area RE4 is cleared to "0". At this time, a shift command is sent to the voice light emission control device 81 to recognize that the data in the reserved areas has been shifted. When the audio light emission control device 81 receives the command, it updates the image displayed on the pattern display device 41, which shows the number of pending information items, to reflect the decrease in pending information.

[0158] After executing the data setting process, the win / loss table is read from the main ROM 64 (step S503). Specifically, the current win / loss lottery mode is first determined by reading the information indicating the win / loss lottery mode from the main RAM 65. If it is the high probability mode, the high probability win / loss table 64g is read from the main ROM 64. On the other hand, if it is the low probability mode, the setting state of the pachinko machine 10 is determined by reading the value of the setting value counter in the main RAM 65. Then, the low probability win / loss tables 64a to 64f corresponding to the determined setting value are read from the main ROM 64.

[0159] Subsequently, the system executes a win / failure determination process by referring to the win / failure tables 64a to 64g read in step S503 (step S504). In the win / failure determination process, it is determined whether the information for win / failure determination, i.e., the numerical information related to the winning random number counter C1, among the information stored in the execution area AE matches the jackpot numerical information set in the win / failure tables 64a to 64g read in step S503.

[0160] If the result of the win / failure determination process is a jackpot win (step S505: YES), the distribution determination process is executed (step S506). In the distribution determination process, the information for distribution determination, i.e., the numerical information related to the jackpot type counter C2, is read from the information stored in the execution area AE. Then, the distribution table 64h provided in the main ROM 64 is referred to to determine which jackpot result the numerical information related to the jackpot type counter C2 read above corresponds to. Specifically, it is determined which of the following jackpot results it corresponds to: low probability jackpot result, low-winning high probability jackpot result, and most advantageous jackpot result.

[0161] Subsequently, the process for setting the stop result for the jackpot is executed (step S507). Specifically, the information of the pattern to be ultimately stopped and displayed on the special symbol display unit 37a in the game round related to the start of the current variation is identified from the jackpot result stop result table pre-stored in the main ROM 64, and this identified information is written to the main RAM 65. In this jackpot result stop result table, the information of the pattern to be stopped and displayed on the special symbol display unit 37a is set differently for each type of jackpot result.

[0162] Subsequently, a flag setting process corresponding to the distribution determination result is executed (step S508). Specifically, the main RAM 65 is equipped with flags corresponding to each type of jackpot result, and in step S508, the flag corresponding to the result of the distribution determination process in step S506 is set to "1".

[0163] On the other hand, if it is determined in step S505 that the result is not a jackpot win, the stop result setting process for a losing result is executed (step S509). Specifically, the information of the pattern of symbols to be ultimately stopped and displayed on the special symbol display unit 37a in the game round related to the start of the current variation is identified from the stop result table for losing results that is pre-stored in the main ROM 64, and this identified information is written to the main RAM 65. The information of the pattern of symbols selected in this case is different from the information of the pattern of symbols selected in the case of a jackpot result.

[0164] After executing either step S508 or step S509, the process of determining the duration of the game round is executed (step S510). In this process, numerical information of the variation type counter CS is obtained. It is also determined whether or not a reach display occurs on the symbol display device 41 during the current game round. Specifically, if the game round related to the start of the variation results in a low probability jackpot or a most advantageous jackpot, it is determined that a reach display will occur. Furthermore, if it is neither a jackpot result, and the numerical information related to the reach random number counter C3 stored in the execution area AE is numerical information corresponding to the occurrence of a reach, it is determined that a reach display will occur.

[0165] If it is determined that a reach display will occur, the duration of the game rounds corresponding to the numerical information of the current variation type counter CS is obtained by referring to the reach occurrence duration table stored in the main ROM 64. On the other hand, if it is determined that a reach display will not occur, the duration of the game rounds corresponding to the numerical information of the current variation type counter CS is obtained by referring to the reach non-occurrence duration table stored in the main ROM 64. Incidentally, the duration of the game rounds that can be obtained by referring to the reach non-occurrence duration table is different from the duration of the game rounds that can be obtained by referring to the reach occurrence duration table.

[0166] In addition, the duration of the game round when a reach does not occur is set such that the longer the number of hold information stored in the hold area RE, the shorter the duration of the game round. Also, in a situation where the support mode is the high-frequency support mode, a reach non-occurrence duration table is set so that a shorter game round duration is selected compared to a situation where the support mode is the low-frequency support mode when the number of hold information is the same. However, it is not limited to this, and the configuration may be such that the duration of the game round does not vary according to the number of hold information or the support mode, or it may be the reverse of the above relationship. Furthermore, the above configuration may be applied to the duration of the game round when a reach occurs. Also, for each case of various jackpot results, a duration table may be set individually for each case of a miss reach, a reach non-occurrence miss result. In this case, the distribution of the duration of the game round according to each game result will be performed.

[0167] Thereafter, the information on the duration of the game round obtained in step S510 is set in the special drawing special electricity timer counter provided in the main side RAM65 (step S511). The update of the numerical information set in the special drawing special electricity timer counter is executed in the timer update process (step S310). Incidentally, as an effect for the game, a variable display of the pattern in the special drawing display unit 37a and a variable display of the pattern in the pattern display device 41 are performed. When each of these variable displays ends, the stop result of that game round is displayed in the final stop display for a final stop period (for example, 0.5 seconds) in a state where a predetermined combination of patterns is waiting on the effective line in the pattern display device 41. In this case, the duration of the game round obtained in step S510 is the total time for one game round.

[0168] Thereafter, the variable command and the type command are transmitted to the audio-visual control device 81 (step S512). The variable command includes information on the duration of the game round. Here, since the duration of the game round obtained by referring to the non-reach occurrence duration table as described above is different from the duration of the game round obtained by referring to the reach occurrence duration table, even if the variable command does not include information on the presence or absence of a reach, the audio-visual control device 81 can specify the presence or absence of a reach from the information on the duration of the game round. In this regard, it can be said that the variable command includes information indicating the presence or absence of a reach. Note that the variable command may directly include information indicating the presence or absence of a reach. The type command includes information on the game result.

[0169] When the audio-visual control device 81 receives the variable command and the type command from the main CPU 63, it causes the display light-emitting unit 53, the speaker unit 54, and the symbol display device 41 to perform an effect for the game. In this case, the effect for the game is performed in a manner corresponding to the contents of the variable command and the type command. Further, in the symbol display device 41, a variable display of symbols is performed as an effect for the game, and when the effect for the game ends, a combination of symbols corresponding to the results of the win / loss determination process and the distribution determination process is stopped and displayed.

[0170] Thereafter, the variable display of the picture in the special figure display unit 37a is started (step S513). Then, the special figure special power counter is incremented by 1 (step S514). In this case, since the numerical information of the special figure special power counter when the special figure variable start process is executed is "0", the numerical information of the special figure special power counter becomes "1". Thereafter, "1" is set in the 11th output flag provided in the main RAM 65 (step S515). The 11th output flag is a flag for the main CPU 63 to specify that the information output indicating that the game round has started should be executed for the management IC 66.

[0171] Returning to the explanation of the special symbol special electric control processing (Figure 52), step S407 executes the special symbol variation processing. In the special symbol variation processing, it is determined whether it is during the duration of the game round but before the final stop display. If it is before the final stop display, processing is executed to regularly change the display pattern of the symbols in the special symbol display unit 37a. When it is time to display the final stop, the numerical information of the special symbol special electric counter is incremented by 1, updating the numerical information of the counter from that corresponding to the special symbol variation processing to that corresponding to the special symbol confirmation processing. In this embodiment, the main CPU 63 does not send a final stop command to the sound and light emission control device 81.

[0172] Step S408 executes the special symbol confirmation process. During the special symbol confirmation process, the display mode of the symbols in the special symbol display unit 37a is set to the display mode corresponding to the lottery result of the current game round. In addition, the special symbol confirmation process determines whether the final stop period has elapsed, and if so, determines whether a transition to the opening / closing execution mode occurs. If a transition to the opening / closing execution mode does not occur, the numerical information of the special symbol special electric counter is cleared to "0". If a transition to the opening / closing execution mode occurs, the numerical information of the special symbol special electric counter is increased by 1, updating the numerical information of the counter from that corresponding to the special symbol confirmation process to that corresponding to the special electric start process.

[0173] In step S409, the special electric start process is executed. In the special electric start process, if the process to start the opening period in the current opening / closing execution mode has not yet been executed, the process to set the opening period is executed. An opening command is also sent to the sound and light emission control device 81. Upon receiving the opening command, the sound and light emission control device 81 causes the opening effect to be executed on the display and light emission unit 53, the speaker unit 54, and the symbol display device 41. If the opening period has elapsed, the start process to start the first round of game is executed. In this start process, the special electric prize winning device 32 is opened and the conditions for ending the round of game are set. When setting these conditions, the maximum duration for keeping the special electric prize winning device 32 open during the first round of game is set, and the maximum number of game balls that can be awarded to the special electric prize winning device 32 during the first round of game is set in the award counter provided in the main RAM 65.

[0174] In step S410, the special electric opening process is executed. The special electric opening process determines whether or not the round game termination conditions have been met. If the termination conditions have been met, the special electric prize entry device 32 is closed. If the round game that has just ended is not the last round game to be executed, the numerical information of the special symbol special electric counter is incremented by 1 to update the numerical information of the counter from one corresponding to the special electric opening process to one corresponding to the special electric closing process. If the round game that has just ended is the last round game to be executed, the numerical information of the special symbol special electric counter is incremented by 2 to update the numerical information of the counter from one corresponding to the special electric opening process to one corresponding to the special electric termination process.

[0175] In step S411, the special electric closing process is executed. The special electric closing process determines whether or not the interval period between round games has elapsed. The interval period is set when the previous round game ends. If the interval period has elapsed, the special electric prize device 32 is opened and the conditions for ending the round game are set. Then, by subtracting 1 from the numerical information of the special electric counter, the numerical information of the counter is updated from the one corresponding to the special electric closing process to the one corresponding to the special electric open process.

[0176] In step S412, the special operation termination process is executed. In the special operation termination process, if the process to start the ending period for the current opening / closing execution mode has not yet been executed, the ending period (for example, 5 seconds) is set and an ending command is sent to the sound and light emission control device 81. Upon receiving the ending command, the sound and light emission control device 81 causes the ending performance to be executed on the display and light emission unit 53, the speaker unit 54, and the symbol display device 41. If the ending period has elapsed, the win / loss lottery mode and the support mode after the end of the opening / closing execution mode are set to the mode corresponding to the jackpot result that triggered the start of the current opening / closing execution mode.

[0177] Next, we will explain the configuration for the main CPU 63 to determine whether or not a game ball has entered the out gate 24a, the general prize gate 31, the special electric prize device 32, the first operation gate 33, the second operation gate 34, and the through gate 35, based on the detection results of each ball entry detection sensor 42a to 49a. Figure 14 is an explanatory diagram illustrating the configuration in which the detection results of the ball entry detection sensors 42a to 49a are input to the main CPU 63.

[0178] The main CPU 63 is provided with an input port 63a. The input port 63a is configured as an 8-bit parallel interface to handle eight types of signals simultaneously. Each terminal has a corresponding area where information of "0" or "1" is stored according to the voltage of each signal. Specifically, this area consists of bits 0 (D0) to 7 (D7). In addition, more than eight types of signals may be input to the input port 63a, but in order to limit the number of signals that can be input simultaneously to eight, the group of signals that can be input to the input port 63a is switched via switching control by a driver IC.

[0179] In the ball entry detection process (step S309) of the timer interrupt processing (Figure 11), the group of signals to be input to input port 63a is set to the group of signals from each ball entry detection sensor 42a to 49a. In this setting, bit 0 D0 stores information corresponding to the detection signal from the first prize entry detection sensor 42a, bit 1 D1 stores information corresponding to the detection signal from the second prize entry detection sensor 43a, bit 2 D2 stores information corresponding to the detection signal from the third prize entry detection sensor 44a, bit 3 D3 stores information corresponding to the detection signal from the special electric detection sensor 45a, bit 4 D4 stores information corresponding to the detection signal from the first operation entry detection sensor 46a, bit 5 D5 stores information corresponding to the detection signal from the second operation entry detection sensor 47a, bit 6 D6 stores information corresponding to the detection signal from the out entry detection sensor 48a, and bit 7 D7 stores information corresponding to the detection signal from the gate detection sensor 49a.

[0180] Each of the ball entry detection sensors 42a to 49a outputs a LOW level signal indicating no detection when it does not detect the passage of a game ball, and outputs a HI level signal indicating detection when it does detect the passage of a game ball. The input port 63a stores "0" information in the corresponding bit when it receives a LOW level signal, and stores "1" information in the corresponding bit when it receives a HI level signal. In other words, when the ball entry detection sensors 42a to 49a do not detect the passage of a game ball, "0" information corresponding to the information indicating no detection is stored in the corresponding bit, and when the passage of a game ball is detected, "1" information corresponding to the information indicating detection is stored in the corresponding bit.

[0181] Figure 15 is a flowchart showing the ball entry detection process executed in step S309 of the timer interrupt processing (Figure 11).

[0182] When it is confirmed that the state in the 0th bit D0 has switched from storing the information "0" to storing the information "1", the first prize-winning slot detection sensor 42a determines that one game ball has been detected (step S601: YES). In this case, the first output flag provided in the main RAM 65 is set to "1" (step S602), and the value of the 10-ball payout counter provided in the main RAM 65 is incremented by 1 (step S603). The first output flag is a flag used by the main CPU 63 to determine that the management IC 66 should output information indicating that one game ball has been detected by the first prize-winning slot detection sensor 42a. The 10-ball payout counter is a counter used by the main CPU 63 to determine the number of times the payout of 10 game balls should be performed. If the value of the 10-prize ball counter is 1 or greater, the payout output process in step S317 of the timer interrupt processing (Figure 11) outputs a 10-prize ball command to the payout control device 77, and if the 10-prize ball command is output once, the value of the 10-prize ball counter is decremented by 1. When the payout control device 77 receives the 10-prize ball command, it drives and controls the payout device 76 so that 10 game balls are dispensed.

[0183] When it is confirmed that the first bit D1 has switched from storing the information "0" to storing the information "1", it is determined that one game ball has been detected by the second prize-winning slot detection sensor 43a (step S604: YES). In this case, the second output flag provided in the main RAM 65 is set to "1" (step S605), and the value of the 10-prize ball counter provided in the main RAM 65 is incremented by 1 (step S606). The second output flag is a flag used by the main CPU 63 to specify to the management IC 66 that it should output information indicating that one game ball has been detected by the second prize-winning slot detection sensor 43a.

[0184] When it is confirmed that the second bit D2 has switched from storing the information "0" to storing the information "1", the third prize-winning slot detection sensor 44a determines that one game ball has been detected (step S607: YES). In this case, the third output flag provided in the main RAM 65 is set to "1" (step S608), and the value of the 10-prize ball counter provided in the main RAM 65 is incremented by 1 (step S609). The third output flag is a flag used by the main CPU 63 to specify that the management IC 66 should output information indicating that one game ball has been detected by the third prize-winning slot detection sensor 44a.

[0185] When it is confirmed that the third bit D3 has switched from storing the information "0" to storing the information "1", the special electric detection sensor 45a determines that one game ball has been detected (step S610: YES). In this case, the special electric prize flag provided in the main RAM 65 is set to "1" (step S611), the fourth output flag provided in the main RAM 65 is set to "1" (step S612), and the value of the 15-ball prize counter provided in the main RAM 65 is incremented by 1 (step S613). The special electric prize flag is a flag used by the main CPU 63 to identify that one game ball has entered the special electric prize device 32 during a round game in the opening / closing execution mode. In the timer interrupt processing (Figure 11), the special feature special electric control processing (step S313) confirms that the special electric prize entry flag is set to "1", thereby identifying that one game ball has entered the special electric prize entry device 32, and the remaining number of balls that can enter the special electric prize entry device 32 in the round game is reduced by 1. When this process of reducing the number of balls that can enter by 1 is executed, the special electric prize entry flag is cleared to "0". The fourth output flag is a flag used by the main CPU 63 to identify that the management IC 66 should output information indicating that one game ball has been detected by the special electric detection sensor 45a. The 15-ball prize counter is a counter used by the main CPU 63 to identify the number of times that 15 game balls should be dispensed. If the value of the 15-prize ball counter is 1 or greater, the payout output process in step S317 of the timer interrupt processing (Figure 11) outputs a 15-prize ball command to the payout control device 77, and if the 15-prize ball command is output once, the value of the 15-prize ball counter is decremented by 1. When the payout control device 77 receives the 15-prize ball command, it drives and controls the payout device 76 so that 15 game balls are dispensed.

[0186] When it is confirmed that the information stored in the 4th bit D4 has switched from "0" to "1", the first operation port detection sensor 46a determines that one game ball has been detected (step S614: YES). In this case, the first operation entry flag provided in the main RAM 65 is set to "1" (step S615), the 5th output flag provided in the main RAM 65 is set to "1" (step S616), and the value of the 1-ball prize counter provided in the main RAM 65 is incremented by 1 (step S617). The first operation entry flag is a flag used by the main CPU 63 to identify that one game ball has entered the first operation port 33. In the timer interrupt processing (Figure 11), the special feature special electric control processing (step S313) confirms that the first operation prize flag is set to "1", and if the number of reserve information stored in the reserve area RE of the reserve storage area 65a is less than the upper limit of 4, the processing to newly store reserve information is executed. In the special electric electric control processing (step S313), if it is confirmed that the first operation prize flag is set to "1" and the processing corresponding to that confirmation is executed, the first operation prize flag is cleared to "0". The fifth output flag is a flag used by the main CPU 63 to specify that the management IC 66 should output information indicating that one game ball has been detected by the first operation port detection sensor 46a. The single prize ball counter is a counter used by the main CPU 63 to specify the number of times that a single game ball should be dispensed. If the value of the single-prize ball counter is 1 or greater, the payout output process in step S317 of the timer interrupt processing (Figure 11) outputs a single-prize ball command to the payout control device 77, and if the single-prize ball command is output once, the value of the single-prize ball counter is decremented by 1. When the payout control device 77 receives a single-prize ball command, it drives and controls the payout device 76 so that one game ball is dispensed.

[0187] When it is confirmed that the information stored in the 5th bit D5 has switched from "0" to "1", the second operation port detection sensor 47a determines that one game ball has been detected (step S618: YES). In this case, the second operation entry flag provided in the main RAM 65 is set to "1" (step S619), the 6th output flag provided in the main RAM 65 is set to "1" (step S620), and the value of the 1-ball prize counter provided in the main RAM 65 is incremented by 1 (step S621). The second operation entry flag is a flag used by the main CPU 63 to identify that one game ball has entered the second operation port 34. In the timer interrupt processing (Figure 11), the special feature special electric control processing (step S313) confirms that the second operation winning flag is set to "1", and if the number of hold information stored in the hold area RE of the hold storage area 65a is less than the upper limit of 4, the processing to newly store hold information is executed. In the special electric electric control processing (step S313), if it is confirmed that the second operation winning flag is set to "1" and the processing corresponding to that confirmation is executed, the second operation winning flag is cleared to "0". The sixth output flag is a flag used by the main CPU 63 to specify to the management IC 66 that it should output information indicating that one game ball has been detected by the second operation opening detection sensor 47a.

[0188] When it is confirmed that the information stored in the 6th bit D6 has switched from "0" to "1", the out-port detection sensor 48a determines that one game ball has been detected (step S622: YES). In this case, the 7th output flag provided in the main RAM 65 is set to "1" (step S623). The 7th output flag is a flag used by the main CPU 63 to specify that the management IC 66 should output information indicating that one game ball has been detected by the out-port detection sensor 48a.

[0189] When it is confirmed that the situation has switched from the state where the information "0" is stored in the 7th bit D7 to the state where the information "1" is stored, it is determined that one game ball has been detected by the gate detection sensor 49a (step S624: YES). In this case, "1" is set in the gate winning flag provided in the main side RAM 65 (step S625). The gate winning flag is a flag for the main side CPU 63 to identify that one game ball has entered the through gate 35. In the general diagram general power control process (step S314) of the timer interrupt process (FIG. 11), by confirming that "1" is set in the gate winning flag, on the condition that the number of the reserved information on the general diagram side stored in the general power reserved area 65c is less than the upper limit number of 4, the process of storing the numerical information of the current general power accessory release counter C4 as the reserved information on the general diagram side in the general power reserved area 65c is executed. When it is confirmed in the general diagram general power control process (step S314) that "1" is set in the gate winning flag and the process corresponding to the confirmation is executed, the gate winning flag is cleared to "0".

[0190] Note that since the timer interrupt process (FIG. 11) is activated at a cycle of 4 milliseconds as already described, when the detection of one game ball is started by one of the ball entry detection sensors 42a to 49a, in the situation where the detection of that one game ball is continued by the ball entry detection sensors 42a to 49a, the main side CPU 63 identifies that one game ball has been detected by the ball entry detection sensors 42a to 49a. Therefore, it is sufficient to provide one each of the first to seventh output flags.

[0191] Next, the processing content executed by the payout control device 77 will be described. First, the electrical configuration of the payout control device 77 and various devices that communicate with the payout control device 77 will be described while referring to the block diagram of FIG. 16.

[0192] The payout control device 77 includes an MPU 91. In the MPU 91, in addition to the payout side CPU 92 which is an arithmetic processing device including a control unit and an arithmetic unit, a payout side ROM 93, a payout side RAM 94, an interrupt circuit, a timer circuit, a data input / output circuit, etc. are built in.

[0193] The dispensing-side ROM 93 is a memory (i.e., a non-volatile storage means) that does not require an external power supply for storage, such as NOR-type flash memory and NAND-type flash memory, and is used for read-only purposes. The dispensing-side ROM 93 stores various control programs and fixed value data executed by the dispensing-side CPU 92.

[0194] The dispensing-side RAM 94 is a memory (i.e., volatile memory) that requires an external power supply for memory retention, such as SRAM and DRAM, and is used for both reading and writing. The dispensing-side RAM 94 allows random access and, when compared with the same data capacity, has a faster read time than the dispensing-side ROM 93. The dispensing-side RAM 94 temporarily stores various data for the execution of the control program stored in the dispensing-side ROM 93.

[0195] The payout-side CPU 92 is capable of bidirectional communication with the main-side CPU 63. Upon receiving a prize ball command from the main-side CPU 63, the payout-side CPU 92 drives and controls the payout device 76 so that the number of game balls corresponding to the prize ball command are dispensed. The payout-side CPU 92 also monitors whether it is possible to dispense game balls normally, and if it determines that it is not possible to dispense them normally, it stops the payout device 76 even if the payout-side RAM 94 has information on the number of undispensed prize balls stored in it. The payout-side CPU 92 also sends a payout restriction command to the main-side CPU 63 indicating that it is not possible to dispense game balls normally. Upon receiving this payout restriction command, the main-side CPU 63 sends a notification command to the sound and light emission control device 81 so that a notification indicating that it is not possible to dispense game balls normally is executed by the symbol display device 41, the display light emission unit 53, and the speaker unit 54. The following states make it impossible to dispense game balls normally: a full state where the lower tray 56a is completely filled with game balls; a ball-less state where the tank 75 is not replenished with game balls; a payout abnormal state where the payout device 76 does not operate normally; a body-open state where the game machine body 12 is separated from the outer frame 11; and a front door open state where the front door frame 14 is separated from the inner frame 13.

[0196] A full-tank detection sensor (not shown) is provided at an intermediate position in the game ball passage leading from the payout device 76 to the lower tray 56a, and the detection result of the full-tank detection sensor is input to the payout-side CPU 92. The payout-side CPU 92 determines that the machine is full when the full-tank detection sensor continuously detects game balls, and determines that the machine is no longer full when the full-tank detection sensor stops continuously detecting game balls.

[0197] A ball-less detection sensor (not shown) is installed at an intermediate position in the game ball passage leading from the tank 75 to the payout device 76, and the detection result of the ball-less detection sensor is input to the payout-side CPU 92. The payout-side CPU 92 identifies a ball-less state when no game balls are continuously detected by the ball-less detection sensor, and identifies the ball-less state as being released when the state of no game balls being continuously detected by the ball-less detection sensor is released.

[0198] The dispensing device 76 is equipped with a dispensing detection sensor (not shown) for detecting game balls dispensed from the dispensing device 76, and the detection result of the dispensing detection sensor is input to the dispensing-side CPU 92. The dispensing-side CPU 92 determines that one game ball has been dispensed from the dispensing device 76 when a game ball is detected by the dispensing detection sensor. Furthermore, the dispensing-side CPU 92 determines that there is a dispensing abnormality if the dispensing device 76 is being driven and controlled to dispense game balls, but no game balls are continuously detected by the dispensing detection sensor, and determines that the dispensing abnormality has been resolved when the state in which no game balls are continuously detected by the dispensing detection sensor is resolved.

[0199] A front door open sensor 95 is provided on the front of the inner frame 13 (see Figure 2), and the detection result of the front door open sensor 95 is input to the dispensing side CPU 92. In this case, if the front door frame 14 is closed relative to the inner frame 13, the front door open sensor 95 sends a closed detection signal to the dispensing side CPU 92, and if the front door frame 14 is open relative to the inner frame 13, the front door open sensor 95 sends an open detection signal to the dispensing side CPU 92. The dispensing side CPU 92 identifies the front door frame 14 as closed when it receives a closed detection signal from the front door open sensor 95, and identifies the front door frame 14 as open when it receives an open detection signal from the front door open sensor 95. Furthermore, the dispensing side CPU 92 sends a front door open command to the main side CPU 63 when it identifies that the front door frame 14 has changed from a closed state to an open state, and sends a front door closed command to the main side CPU 63 when it identifies that the front door frame 14 has changed from an open state to a closed state. The main CPU 63 determines that the front door frame 14 is in an open state when it receives a front door open command, and determines that the front door frame 14 is in a closed state when it receives a front door close command.

[0200] A main unit open sensor 96 is provided on the front of the back pack unit 15 (see Figure 2), and the detection result of the main unit open sensor 96 is input to the payout side CPU 92. In this case, when the gaming machine main unit 12 is closed relative to the outer frame 11, the main unit open sensor 96 sends a closed detection signal to the payout side CPU 92, and when the gaming machine main unit 12 is open relative to the outer frame 11, the main unit open sensor 96 sends an open detection signal to the payout side CPU 92. The payout side CPU 92 identifies the gaming machine main unit 12 as being in a closed state when it receives a closed detection signal from the main unit open sensor 96, and identifies the gaming machine main unit 12 as being in an open state when it receives an open detection signal from the main unit open sensor 96. Furthermore, when the payout side CPU 92 identifies that the gaming machine main unit 12 has changed from a closed state to an open state, it sends a main unit open command to the main side CPU 63, and when it identifies that the gaming machine main unit 12 has changed from an open state to a closed state, it sends a main unit closed command to the main side CPU 63. The main CPU 63 determines that the gaming machine body 12 is in an open state when it receives a main unit open command, and determines that the gaming machine body 12 is in a closed state when it receives a main unit close command.

[0201] Referring to the flowchart in Figure 17, the timer interrupt processing executed by the payout-side CPU 92 will be explained. The timer interrupt processing is repeatedly activated at a predetermined period (for example, 2 milliseconds).

[0202] First, the full tank processing is performed (step S701). In the full tank processing, as already explained, it is determined whether or not the tank is full based on the detection result of the full tank detection sensor. If the tank is full, processing is performed to stop the payout of game balls, and a command indicating that the tank is full is sent to the main CPU 63. If the full tank state is released, processing is performed to enable the payout of game balls, and a command indicating that the full tank state has been released is sent to the main CPU 63.

[0203] Subsequently, the "no balls" processing is performed (step S702). In the "no balls" processing, as already explained, it is determined whether or not there are no balls based on the detection result of the no ball detection sensor. If there are no balls, processing is performed to stop the payout of game balls, and a command indicating that there are no balls is sent to the main CPU 63. If the "no balls" state is resolved, processing is performed to enable the payout of game balls, and a command indicating that the "no balls" state has been resolved is sent to the main CPU 63.

[0204] Subsequently, the payout abnormality monitoring process is executed (step S703). In the payout abnormality monitoring process, as already explained, the system determines whether or not there is a payout abnormality based on the detection result of the payout detection sensor. If there is a payout abnormality, the system executes a process to stop the payout of game balls and sends a command to the main CPU 63 indicating that there is a payout abnormality. If the payout abnormality is resolved, the system executes a process to enable the payout of game balls and sends a command to the main CPU 63 indicating that the payout abnormality has been resolved.

[0205] Subsequently, the front door open monitoring process is executed (step S704). In the front door open monitoring process, as already explained, the system determines whether the front door frame 14 is open or not based on the detection result of the front door open sensor 95. If the front door frame 14 is open, the system executes a process to stop the payout of game balls and sends a front door open command to the main CPU 63. If the front door frame 14 is closed, the system executes a process to enable the payout of game balls and sends a front door closed command to the main CPU 63.

[0206] Subsequently, the main unit open monitoring process is executed (step S705). In the main unit open monitoring process, as already explained, it is determined whether or not the gaming machine main unit 12 is in an open state based on the detection result of the main unit open sensor 96. If the gaming machine main unit 12 is in an open state, a process is executed to stop the payout of game balls, and a main unit open command is sent to the main CPU 63. If the gaming machine main unit 12 is closed, a process is executed to enable the payout of game balls, and a main unit closed command is sent to the main CPU 63.

[0207] Subsequently, a command reading process is executed (step S706). In this command reading process, a process is executed to read the prize ball command sent by the main CPU 63 and store the prize ball command in the payout RAM 94. Then, a prize ball setting process is executed to add the number corresponding to the received prize ball command to the unpaid prize ball count information in the payout RAM 94 (step S707), and then a payout control process is executed to control the execution of the payout of game balls by the payout device 76 (step S708). In the payout control process, if the unpaid prize ball count information stored in the payout RAM 94 is a value of 1 or more, the drive control of the payout device 76 is performed, and when one game ball is detected by the payout detection sensor, the value of the prize ball count information is deducted by 1. Then, when the value of the prize ball count information becomes "0", the drive control of the payout device 76 is stopped. Subsequently, an external information setting process is executed to control the start and end of the output of external signals according to the processing results of the various processes performed in this timer interrupt process (step S709).

[0208] Next, we will explain the configuration for outputting information from the pachinko machine 10 to the hall computer HC installed in the gaming hall.

[0209] As shown in Figure 2, the back pack unit 15 is provided with an external terminal board 97. The external terminal board 97 is provided with numerous external terminals, some of which are electrically connected to the main CPU 63, and some of which are electrically connected to the payout CPU 92. Because the main CPU 63 and the payout CPU 92 are each electrically connected to the external terminal board 97 in this way, as shown in Figure 16, the main CPU 63 and the payout CPU 92 can output information to the hall computer HC.

[0210] One external terminal on the external terminal board 97 is electrically connected to the front door open sensor 95, and another external terminal on the external terminal board 97 is electrically connected to the main unit open sensor 96. In detail regarding the configuration of this electrical connection, a signal relay board 98 is provided at an intermediate position in the signal path from the front door open sensor 95 to the payout side CPU 92. The signal relay board 98 is provided with a branch path SL2 that branches off from the signal path SL1 from the front door open sensor 95 to the payout side CPU 92. This branch path SL2 is connected to the external terminal for front door opening on the external terminal board 97. Therefore, the electrical signal corresponding to the detection result of the front door open sensor 95 is input not only to the payout side CPU 92, but also to the external terminal for front door opening on the external terminal board 97. This makes it possible to output a signal indicating whether the front door frame 14 is in an open state to the hall computer HC without going through control by the payout side CPU 92.

[0211] More specifically regarding the main unit open sensor 96, the signal relay board 98 is provided with a branch path SL4 that branches off from the signal path SL3 that runs from the main unit open sensor 96 to the payout-side CPU 92. This branch path SL4 is connected to the external terminal for main unit open on the external terminal board 97. Therefore, the electrical signal corresponding to the detection result of the main unit open sensor 96 is input not only to the payout-side CPU 92 but also to the external terminal for main unit open on the external terminal board 97. This makes it possible to output a signal to the hall computer HC indicating whether or not the gaming machine main unit 12 is in an open state, without going through control by the payout-side CPU 92.

[0212] Next, we will explain the contents of the information output externally from the main CPU 63 and the payout CPU 92 to the hall computer HC. First, we will explain the contents of the information output externally from the main CPU 63 to the hall computer HC.

[0213] In the timer interrupt processing (Figure 11), the main CPU 63 sets the output of information to each external terminal assigned to the main CPU 63 on the external terminal board 97 during the external information setting process (step S318). The information output from the main CPU 63 to the external terminal board 97 includes information indicating that the system is in open / close execution mode, information indicating that the support mode is in high-frequency support mode, information indicating that one game round has ended, information indicating that a predetermined number of game balls (for example, 100) have been ejected from the game area PA through one of the out-out port 24a, general prize-winning port 31, special electric prize-winning device 32, first operation port 33, and second operation port 34, information indicating that a game ball has entered the first operation port 33, and information indicating that a game ball has entered the second operation port 34.

[0214] In the timer interrupt processing (Figure 17), the payout-side CPU 92 sets the output of information to each external terminal assigned to the payout-side CPU 92 on the external terminal board 97 during the external information setting process (step S709). The information output from the payout-side CPU 92 to the external terminal board 97 includes information indicating that 10 game balls have been dispensed.

[0215] The hall computer HC can understand the execution method of dispensing game balls in the pachinko machine 10 in accordance with various information received from the pachinko machine 10 via the external terminal board 97. For example, • Payout rate: This is the ratio of the number of game balls dispensed to the number of game balls dispensed from the game area PA of the pachinko machine 10 until 100 game balls are dispensed. • Payout rate in normal gameplay mode, excluding open / close execution mode and high-frequency support mode (hereinafter, this payout rate will be referred to as "B"). • Payout rate in opening / closing mode • Payout rate in high-frequency support mode The number of game rounds played until 100 game balls are dispensed from the game area PA of the pachinko machine 10 (hereinafter, this ratio will be referred to as "S"). • BS × "Number of prize balls awarded for winning in the first operating port 33 and the second operating port 34" The number of game balls that enter the first operating port 33 until 100 game balls are discharged from the game area PA of the pachinko machine 10 (hereinafter, this ratio will be referred to as "S1"). The number of game balls that enter the second operating port 34 before 100 game balls are discharged from the game area PA of the pachinko machine 10 (hereinafter, this ratio will be referred to as "S2"). B - (S1 × "Number of prize balls awarded for winning in the first operating port 33" + S2 × "Number of prize balls awarded for winning in the second operating port 34") • Probability of opening / closing execution mode occurring per unit of gameplay • Probability of high-frequency support mode occurring per game round These are calculated. This makes it possible for the hall computer HC to manage the way game balls enter the game area PA of the pachinko machine 10. The number of prize balls refers to the number of game balls that are dispensed when one game ball enters the corresponding ball entry section.

[0216] <Configuration for managing the winning patterns of game balls> Next, we will explain the configuration for managing game history using the management IC66. First, we will explain the electrical configuration of the management IC66, referring to the block diagram in Figure 18.

[0217] As already explained, the MPU 62 of the main control unit 60 includes a main CPU 63, a main ROM 64, a main RAM 65, and a management IC 66. In addition to these, the MPU 62 also includes an I / F 101 and a read terminal 68d, as previously described.

[0218] I / F101 is an interface for sending and receiving signals between the MPU62 and external devices. I / F101 is electrically connected to the main CPU63 via the internal bus 103. Detection results from sensors such as the ball entry detection sensors 42a to 49a, and commands from the payout CPU92 are input to the MPU62 through the input port of I / F101, and various processes are executed in the main CPU63 based on the input detection results and command content as previously described. Furthermore, if a signal output is performed to devices such as the special electric drive unit 32b as a result of the various processes performed in the main CPU63, this signal output is performed through the output port of I / F101. Similarly, if a command output is performed to the payout CPU92 and the sound and light emission control device 81 as a result of the various processes performed in the main CPU63, this command output is performed through the output port of I / F101.

[0219] The management IC66 includes a management interface 111, a management CPU 112, a management ROM 113, a management RAM 114, an RTC 115, a memory for correspondence relationships 116, a history memory 117, and a memory for calculation results 131. These devices are connected bidirectionally via an internal bus 66a provided on the management IC66.

[0220] The management interface 111 is an interface for receiving various signals from the main CPU 63 via a unidirectional communication signal path group 118 built into the MPU 62, and for transmitting various signals to the read terminal 68d via a unidirectional communication signal path group 119 built into the MPU 62. Various signals from the main CPU 63 are input to the input port of the management interface 111, and various signals to the read terminal 68d are output from the output port of the management interface 111. The main CPU 63 is electrically connected to the read terminal 68d via a bidirectional communication signal path group 120 built into the MPU 62.

[0221] The management CPU 112 is an arithmetic processing unit including a control unit and an arithmetic unit. The management ROM 113 is a memory (i.e., non-volatile storage means) such as NOR flash memory and NAND flash memory that does not require an external power supply for storage, and is used for read-only purposes. The management ROM 113 stores various control programs and fixed value data executed by the management CPU 112. The management RAM 114 is a memory (i.e., volatile storage means) such as SRAM and DRAM that requires an external power supply for storage, and is used for both read and write purposes. The management RAM 114 allows random access and has a faster read time than the management ROM 113 when compared with the same data capacity. The management RAM 114 temporarily stores various data for the execution of control programs stored in the management ROM 113.

[0222] The RTC115 is a real-time clock that constantly measures date and time information and, in accordance with instructions from the management CPU 112, can output the measured date and time information (hereinafter also referred to as date and time information). The RTC115 is equipped with a backup power supply, allowing it to measure date and time information even when the power to the pachinko machine 10 is cut off.

[0223] The correspondence memory 116 is a memory (i.e., volatile memory) such as SRAM and DRAM that requires an external power supply for memory retention, and is used for both reading and writing. The correspondence memory 116 is used to store information on the correspondence between each buffer 122a to 122p provided at the input port 121 of the management I / F 111 and the types of signals input to those buffers 122a to 122p. Details of the contents of the correspondence memory 116 will be explained later.

[0224] The history memory 117 is a memory that does not require an external power supply for storage (i.e., a non-volatile storage means), such as NOR-type flash memory and NAND-type flash memory, and is used for both reading and writing. The history memory 117 is used to store information regarding the game history received from the main CPU 63 via the management I / F 111. Details of the contents of the history memory 117 will be explained later.

[0225] The calculation result memory 131 is a memory that does not require an external power supply for storage (i.e., a non-volatile storage means), such as NOR flash memory and NAND flash memory, and is used for both reading and writing. The calculation result memory 131 is used to sequentially store various parameters calculated by the management CPU 112 using the history information stored in the history memory 117. The contents of the various parameters stored in the calculation result memory 131 are sequentially displayed on the first to third notification display devices 69a to 69c and output to an external device connected to the reading terminal 68d.

[0226] Next, the configuration of the input port 121 provided on the management interface 111 will be described. Figure 19 is an explanatory diagram illustrating the configuration of the input port 121 of the management interface 111.

[0227] Input port 121 is provided with multiple buffers 122a to 122p. Specifically, the first to sixteenth buffers 122a to 122p are provided. Each of the first to sixteenth buffers 122a to 122p can receive one type of signal through signal paths 118a to 118p. When the input signal is at a LOW level, each of the first to sixteenth buffers 122a to 122p stores "0" as the first data, and when the input signal is at a HI level, it stores "1" as the second data. Note that the relationship between LOW and HI and the first and second data may be reversed.

[0228] The first buffer 122a receives a first signal corresponding to the detection result of the first prize-winning slot detection sensor 42a. In this case, the main CPU 63 outputs a LOW level first signal when no new game balls are detected by the first prize-winning slot detection sensor 42a, and outputs a HI level first signal for a specific period when one game ball is detected by the first prize-winning slot detection sensor 42a. This specific period is sufficient for the management CPU 112 to determine that a HI level first signal has been input to the first buffer 122a.

[0229] The second buffer 122b receives a second signal corresponding to the detection result of the second prize-winning slot detection sensor 43a. In this case, the main CPU 63 outputs a LOW level second signal when no new game balls are detected by the second prize-winning slot detection sensor 43a, and outputs a HI level second signal for a specific period when one game ball is detected by the second prize-winning slot detection sensor 43a. This specific period is sufficient for the management CPU 112 to determine that a HI level second signal has been input to the second buffer 122b.

[0230] The third buffer 122c receives a third signal corresponding to the detection result of the third prize-winning slot detection sensor 44a. In this case, the main CPU 63 outputs a LOW level third signal when no new game balls are detected by the third prize-winning slot detection sensor 44a, and outputs a HI level third signal for a specific period when one game ball is detected by the third prize-winning slot detection sensor 44a. This specific period is sufficient for the management CPU 112 to determine that a HI level third signal has been input to the third buffer 122c.

[0231] The fourth buffer 122d receives a fourth signal corresponding to the detection result of the special electric detection sensor 45a. In this case, the main CPU 63 outputs a LOW level fourth signal when no new game balls are detected by the special electric detection sensor 45a, and outputs a HI level fourth signal for a specific period when one game ball is detected by the special electric detection sensor 45a. This specific period is sufficient for the management CPU 112 to determine that a HI level fourth signal has been input to the fourth buffer 122d.

[0232] The fifth buffer 122e receives the fifth signal corresponding to the detection result of the first operation port detection sensor 46a. In this case, the main CPU 63 outputs a LOW level fifth signal when no new game balls are detected by the first operation port detection sensor 46a, and outputs a HI level fifth signal for a specific period when one game ball is detected by the first operation port detection sensor 46a. This specific period is sufficient for the management CPU 112 to determine that a HI level fifth signal has been input to the fifth buffer 122e.

[0233] The sixth buffer 122f receives the sixth signal corresponding to the detection result of the second operation port detection sensor 47a. In this case, the main CPU 63 outputs a LOW level sixth signal when no new game balls are detected by the second operation port detection sensor 47a, and outputs a HI level sixth signal for a specific period when one game ball is detected by the second operation port detection sensor 47a. This specific period is sufficient for the management CPU 112 to determine that a HI level sixth signal has been input to the sixth buffer 122f.

[0234] The seventh buffer 122g receives the seventh signal corresponding to the detection result of the out-port detection sensor 48a. In this case, the main CPU 63 outputs a LOW level seventh signal when no new game balls are detected by the out-port detection sensor 48a, and outputs a HI level seventh signal for a specific period when one game ball is detected by the out-port detection sensor 48a. This specific period is sufficient for the management CPU 112 to determine that a HI level seventh signal has been input to the seventh buffer 122g.

[0235] The eighth buffer 122h receives the eighth signal, which corresponds to whether or not the switch is in switch execution mode. In this case, the main CPU 63 continuously outputs the eighth signal at a LOW level when it is not in switch execution mode, and continuously outputs the eighth signal at a HI level when it is in switch execution mode.

[0236] The ninth buffer 122i receives the ninth signal, which corresponds to whether or not the high-frequency support mode is active. In this case, the main CPU 63 continuously outputs the ninth signal at a LOW level when it is not in high-frequency support mode, and continuously outputs the ninth signal at a HI level when it is in high-frequency support mode.

[0237] The tenth buffer 122j receives a tenth signal corresponding to whether or not the front door frame 14 is open. In this case, the main CPU 63 continuously outputs a LOW level tenth signal when the front door frame 14 is closed, and continuously outputs a HI level tenth signal when the front door frame 14 is open.

[0238] The 11th buffer 122k receives the 11th signal, which corresponds to whether or not a game round has started. In this case, the main CPU 63 continuously outputs a LOW level 11th signal until a game round starts, and then outputs a HI level 11th signal for a specific period once a game round has started. This specific period is sufficient for the management CPU 112 to determine that a HI level 11th signal has been input to the 11th buffer 122k.

[0239] The 15th buffer 122o receives a setting value update signal to the management CPU 112, which allows the main CPU 63 to recognize that a new setting has been made for the pachinko machine 10. In this case, the main CPU 63 outputs a LOW level setting value update signal if no new setting has been made for the pachinko machine 10, and outputs a pulse signal that maintains a HI level setting value update signal for a specific period of time, corresponding to the newly set setting value, when a new setting has been made for the pachinko machine 10. This specific period is sufficient for the management CPU 112 to determine that a HI level setting value update signal has been input to the 15th buffer 122o.

[0240] The 16th buffer 122p receives an output instruction signal to the management CPU 112 to recognize the trigger for outputting history information stored in the history memory 117 and various parameters stored in the calculation result memory 131 to the read terminal 68d. In this case, the main CPU 63 outputs a LOW level output instruction signal when there is no need to output history information, and outputs a HI level output instruction signal for a specific period when there is a need to output history information. This specific period is sufficient for the management CPU 112 to determine that a HI level output instruction signal has been input to the 16th buffer 122p.

[0241] The 12th buffer 122l, the 13th buffer 122m, and the 14th buffer 122n are capable of receiving signals from the main CPU 63, but in this pachinko machine 10, they are blank and do not receive normal signals. In this way, the number of buffers 122a to 122p is provided as input port 121 of the management I / F 111, which is greater than the number of signals output from the main CPU 63 to the management IC 66 in this pachinko machine 10. This makes it possible to reuse the management IC 66 in models other than this pachinko machine 10. This increases the versatility of the management IC 66. Incidentally, signal paths 118a to 118p are formed between the main CPU 63 and each of the first to 16th buffers 122a to 122p in a one-to-one correspondence. However, this is not the only option, and a configuration is also possible in which signal paths 118l to 118n are not formed between the CPU 63 and the buffers 122l to 122n that are to be blanked out.

[0242] The fact that a setting value update signal is input to the 15th buffer 122o and an output instruction signal is input to the 16th buffer 122p is determined during the design phase of the management IC 66. Therefore, the management CPU 112 can determine that a setting value update signal is input to the 15th buffer 122o and an output instruction signal is input to the 16th buffer 122p without receiving instructions from the main CPU 63. On the other hand, the types of signals that are input to the 1st to 14th buffers 122a to 122n are not determined during the design phase of the management IC 66. The types of these signals are determined by the management CPU 112 after receiving instructions from the main CPU 63. The determination of the types of these signals by the management CPU 112 is performed by sending a type identification command from the main CPU 63 to the management CPU 112 when control is started in both the main CPU 63 and the management CPU 112 in conjunction with the start of power supply to the MPU 62, as will be described in detail later. In this case, the information on the types of signals provided by the type identification command is stored in the correspondence memory 116, and when the management CPU 112 identifies the types of signals while operating power is supplied, the information stored in the correspondence memory 116 is referenced.

[0243] Figure 20 is an explanatory diagram illustrating the configuration of the correspondence memory 116. The correspondence memory 116 is provided with first to 14 correspondence areas 123a to 123n that correspond one-to-one with the first to 14th buffers 122a to 122n provided at the input port 121 of the management I / F 111.

[0244] The first correspondence area 123a stores information indicating that the signal input to the first buffer 122a is a general prize slot 31, which is used by the management CPU 112 to identify the type of signal. In addition, the first correspondence area 123a also stores information (10) indicating the number of game balls that will be dispensed when one game ball enters the general prize slot 31. The second correspondence area 123b stores information indicating that the signal input to the second buffer 122b is a general prize slot 31, which is used by the management CPU 112 to identify the type of signal. In addition, the second correspondence area 123b also stores information (10) indicating the number of game balls that will be dispensed when one game ball enters the general prize slot 31. The third correspondence area 123c stores information indicating that the signal input to the third buffer 122c is a general prize slot 31, which is used by the management CPU 112 to identify the type of signal. In addition, the third correspondence area 123c also stores information (10 balls) indicating the number of game balls that will be dispensed when one game ball enters the general prize slot 31.

[0245] The fourth correspondence area 123d stores information indicating that the signal input to the fourth buffer 122d is the special electric prize winning device 32, which is used by the management CPU 112 to identify the type of signal. In addition, the fourth correspondence area 123d also stores information (15) indicating the number of game balls that will be dispensed when one game ball enters the special electric prize winning device 32. The fifth correspondence area 123e stores information indicating that the signal input to the fifth buffer 122e is the first operation port 33, which is used by the management CPU 112 to identify the type of signal. In addition, the fifth correspondence area 123e also stores information (1) indicating the number of game balls that will be dispensed when one game ball enters the first operation port 33. The sixth correspondence area 123f stores information indicating that the signal input to the sixth buffer 122f is the second operation port 34, which is used by the management CPU 112 to identify the type of signal. In addition, the sixth correspondence area 123f also stores information indicating that the signal is the second operation port 34, as well as information indicating the number of game balls that will be dispensed (1) when one game ball enters the second operation port 34. The seventh correspondence area 123g stores information indicating that the signal input to the seventh buffer 122g is the output port 24a, which is used by the management CPU 112 to identify the type of signal.

[0246] The 8th correspondence area 123h stores information indicating that it is the open / close execution mode, which is used by the management CPU 112 to identify the type of signal input to the 8th buffer 122h. The 9th correspondence area 123i stores information indicating that it is the high-frequency support mode, which is used by the management CPU 112 to identify the type of signal input to the 9th buffer 122i. The 10th correspondence area 123j stores information indicating that it is the front door frame 14, which is used by the management CPU 112 to identify the type of signal input to the 10th buffer 122j. The 11th correspondence area 123k stores information indicating that it is the start of a game round, which is used by the management CPU 112 to identify the type of signal input to the 11th buffer 122k.

[0247] The 12th correspondence area 123l stores information indicating that it is a blank, which does not correspond to any of the signals, for the management CPU 112 to identify the type of signal input to the 12th buffer 122l. The 13th correspondence area 123m stores information indicating that it is a blank, which does not correspond to any of the signals, for the management CPU 112 to identify the type of signal input to the 13th buffer 122m. The 14th correspondence area 123n stores information indicating that it is a blank, which does not correspond to any of the signals, for the management CPU 112 to identify the type of signal input to the 14th buffer 122n.

[0248] As described above, by configuring the system so that the type of signal input to the first to fourteenth buffers 122a to 122n is determined by the management CPU 112 upon receiving instructions from the main CPU 63, the management IC 66 can be reused in models other than this pachinko machine 10. This increases the versatility of the management IC 66.

[0249] Furthermore, instead of outputting information to recognize the type of signal each time a signal corresponding to the storage of history information is output to the first to 14th buffers 122a to 122n, the system outputs information to recognize the type of signal in advance, and based on that output information, information for the management CPU 112 to identify the type of signal to be input to the first to 14th buffers 122a to 122n is stored in the correspondence memory 116. This configuration makes it possible to reduce the amount of information output from the main CPU 63 to the management CPU 112 each time a signal is output, compared to a configuration where information to recognize the type of signal is output each time a signal corresponding to the storage of history information is output to the first to 14th buffers 122a to 122n.

[0250] Furthermore, the output of information for the management CPU 112 to identify the types of signals input to the first to fourteenth buffers 122a to 122n is performed when the power supply for operation begins. This makes it possible for the management CPU 112 to identify the types of signals input to the first to fourteenth buffers 122a to 122n when gameplay begins on the pachinko machine 10.

[0251] Furthermore, the information setting that a setting value update signal is input to the 15th buffer 122o and the information setting that an output instruction signal is input to the 16th buffer 122p are performed during the design phase of the management IC 66. As a result, not only in this pachinko machine 10 but also in other pachinko machines that use the management IC 66, it is possible to omit the processing required to identify the type of signal input to the 15th buffer 122o and the 16th buffer 122p for the setting value update signal and output instruction signal that are reliably used. Therefore, the processing load required to identify the type of such signal can be reduced.

[0252] Next, we will describe the history memory 117 of the management IC 66. Figure 21 is an explanatory diagram illustrating the configuration of the history memory 117.

[0253] The history memory 117 is provided with a history area 124 for sequentially storing history information. The history area 124 has multiple pointer information set sequentially, and a history information storage area 125 is set to correspond one-to-one with each pointer information. The history information storage area 125 can store combinations of RTC information and correspondence information. In this case, each history information storage area 125 has a data capacity of 2 bytes, with 1 byte allocated for the area to store RTC information and 1 byte allocated for the area to store correspondence information. When it becomes necessary to store correspondence information in response to signals input to the 1st to 14th buffers 122a to 122n (actually the 1st to 11th buffers 122a to 122k in the case of this pachinko machine 10), first the date and time information measured by the current RTC 115 is stored in the area of ​​the history information storage area 125 that is set to store RTC information and corresponds to the pointer information currently being written. Subsequently, the correspondence information corresponding to buffers 122a to 122n, which triggered the current information storage, is read from correspondence areas 123a to 123n in the correspondence memory 116 that correspond to buffers 122a to 122n, and the read correspondence information is stored in the area for storing correspondence information in the history information storage area 125 that corresponds to the pointer information currently being written to.

[0254] Specifically, regarding the correspondence information stored in the history information storage area 125, as already explained, the first to seventh buffers 122a to 122g receive signals corresponding to the detection results of the ball entry detection sensors 42a to 48a, so the first to seventh correspondence areas 123a to 123g in the correspondence memory 116 store information corresponding to the types of ball entry detection sensors 42a to 48a. More specifically, the first to seventh correspondence areas 123a to 123g store information corresponding to the type of ball entry section corresponding to each of the ball entry detection sensors 42a to 48a. In this pachinko machine 10, as already explained, the first to third prize entry detection sensors 42a to 44a all detect game balls that have entered the general prize entry area 31, so the first to third correspondence areas 123a to 123c corresponding to these first to third prize entry detection sensors 42a to 44a all store information indicating that it is the general prize entry area 31. Furthermore, the fourth correspondence area 123d stores information indicating that it is the special electric prize winning device 32, the fifth correspondence area 123e stores information indicating that it is the first operating port 33, the sixth correspondence area 123f stores information indicating that it is the second operating port 34, and the seventh correspondence area 123g stores information indicating that it is the out port 24a. If the buffers 122a to 122n that triggered the information storage in this case are any of the first to seventh buffers 122a to 122g, then the information of the type of ball entry area corresponding to that buffer 122a to 122g is read from any of the first to seventh correspondence areas 123a to 123g, and the read information of the type of ball entry area is stored as is in the area for storing correspondence information in the history information storage area 125.

[0255] On the other hand, the 8th buffer 122h receives a signal indicating whether or not it is in opening / closing execution mode, the 9th buffer 122i receives a signal indicating whether or not it is in high-frequency support mode, the 10th buffer 122j receives a signal indicating whether or not the front door frame 14 is open, and the 11th buffer 122k receives a signal indicating whether or not a game round has started. Therefore, the 8th corresponding relationship area 123h stores information indicating that it is in opening / closing execution mode, the 9th corresponding relationship area 123i stores information indicating that it is in high-frequency support mode, the 10th corresponding relationship area 123j stores information indicating that it is the front door frame 14, and the 11th corresponding relationship area 123k stores information indicating that it is a game round.

[0256] As previously explained, the main CPU 63 continuously outputs the 8th signal at a LOW level when it is not in the opening / closing execution mode, and continuously outputs the 8th signal at a HI level when it is in the opening / closing execution mode. Therefore, the management CPU 112 can determine that the opening / closing execution mode has started when the 8th signal changes from a LOW level to a HI level, and that the opening / closing execution mode has ended when the 8th signal changes from a HI level to a LOW level. In both cases, the management CPU 112 determines that an opportunity has arisen to store correspondence information in the history information storage area 125. In other words, when the 8th signal changes from a LOW level to a HI level, not only the information indicating that it is in the opening / closing execution mode, read from the 8th correspondence area 123h, but also the start information is stored together in the area for storing correspondence information in the history information storage area 125. Furthermore, when the 8th signal changes from a HI level to a LOW level, not only the information indicating that it is in the opening / closing execution mode, read from the 8th correspondence area 123h, but also the termination information is stored together in the area for storing correspondence information in the history information storage area 125.

[0257] As previously explained, the main CPU 63 continuously outputs the 9th signal at a LOW level when not in high-frequency support mode, and continuously outputs the 9th signal at a HI level when in high-frequency support mode. Therefore, the management CPU 112 can determine that high-frequency support mode has started when the 9th signal changes from LOW to HI, and that high-frequency support mode has ended when the 9th signal changes from HI to LOW. In both cases, the management CPU 112 determines that an opportunity has arisen to store correspondence information in the history information storage area 125. In other words, when the 9th signal changes from LOW to HI, not only the information indicating that it is in high-frequency support mode, read from the 9th correspondence area 123i, but also the start information is stored together in the area of ​​the history information storage area 125 for storing correspondence information. Furthermore, when the 9th signal changes from a HI level to a LOW level, not only the information indicating that it is in high-frequency support mode, read from the 9th correspondence area 123i, but also the termination information is stored together in the area for storing correspondence information in the history information storage area 125.

[0258] As previously explained, the main CPU 63 continuously outputs a LOW level 10th signal when the front door frame 14 is closed, and a HI level 10th signal when the front door frame 14 is open. Therefore, the management CPU 112 can determine that the front door frame 14 has been opened when the 10th signal changes from LOW to HI, and that the front door frame 14 has been closed when the 10th signal changes from HI to LOW. In both cases, the management CPU 112 determines that an opportunity has arisen to store correspondence information in the history information storage area 125. In other words, when the 10th signal changes from LOW to HI, not only the information indicating that it is the front door frame 14 read from the 10th correspondence area 123j, but also the opening start information is stored together in the area for storing correspondence information in the history information storage area 125. Furthermore, when the 10th signal changes from a HI level to a LOW level, not only the information indicating that it is the front door frame 14, read from the 10th correspondence area 123j, but also the information indicating that the door has been opened are stored together in the area for storing correspondence information in the history information storage area 125.

[0259] As previously explained, the main CPU 63 continuously outputs the 11th signal at a LOW level until the start of a game round, and then outputs the 11th signal at a HI level for a specific period of time once the game round has started. Therefore, the management CPU 112 identifies that a game round has started when the 11th signal changes from a LOW level to a HI level. In other words, when the 11th signal changes from a LOW level to a HI level, the information indicating that it is a game round, read from the 11th correspondence area 123k, is stored in the area of ​​the history information storage area 125 used to store correspondence information.

[0260] The history information storage area 125 is provided with enough space to store all the history information that occurs during a 10-day consecutive business day, even if the pachinko machine 10 continues to fire game balls from opening to closing time. For example, if 60,000 history information entries are generated per day, then more than 600,000 history information storage areas 125 are provided. This makes it possible to store and retain all history information in the history memory 117 for at least 10 days.

[0261] The history memory 117 has a pointer area 126 separate from the history area 124. The pointer area 126 stores information that allows the management CPU 112 to identify the pointer information currently being written to in the history memory 117. Specifically, at the time of shipment of the pachinko machine 10, the pointer area 126 is set to specify the pointer information of "0" as the writing target. Each time a new piece of history information is stored in the history information storage area 125, the information in the pointer area 126 is updated so that the value of the pointer information to be written is incremented by 1. When the last pointer information in the sequence becomes the writing target and history information is stored in the history information storage area 125 corresponding to that last pointer information, the information in the pointer area 126 is updated so that the pointer information of "0" becomes the writing target. As a result, if the number of history information items that can be stored exceeds the number of history information items that need to be stored, the new history information will overwrite the oldest history information in the history information storage area 125 first.

[0262] Furthermore, if an external device reads history information from the history memory 117, the history information storage area 125 is completely cleared to "0", and the information in the pointer area 126 is updated so that the "0" pointer information becomes the target of writing. This prevents history information that has already been read from becoming the target of reading again.

[0263] Next, we will explain the specific processing configuration for managing game history using the management IC66. First, we will explain the processing configuration for storing information on the correspondence between the first to 14th buffers 122a to 122n, provided at the input port 121 of the management I / F111, and the types of signals in the correspondence memory 116. Figure 22 is a flowchart showing the recognition process executed by the main CPU 63. The recognition process is executed in step S111 of the main process (Figure 9).

[0264] First, the recognition output counter in the main RAM 65 is set to "14" (step S801). The recognition output counter is a counter used by the main CPU 63 to determine the remaining number of times information output is required to allow the management CPU 112 to recognize which type of signal each of the first to 14 buffers 122a to 122n of the input port 121 in the management I / F 111 corresponds to. As explained earlier, the 14 buffers 122a to 122n are the targets for signal type recognition, so the recognition output counter is set to "14".

[0265] Subsequently, the output process for the identification start command is executed (step S802). The main CPU 63 outputs various commands to the management CPU 112 to make it aware of which type of signal each of the first to fourteenth buffers 122a to 122n corresponds to. The first to eighth signals input to the first to eighth buffers 122a to 122h are used for this command output. In other words, the first to eighth signals (i.e., the first to eighth signal paths 118a to 118h) used to instruct the management CPU 112 on the trigger for storing history information are used to output commands to make it aware of which type of signal each of the first to fourteenth buffers 122a to 122n corresponds to. This makes it possible to reduce the number of signal paths and simplify the configuration compared to a configuration in which a separate signal path for outputting such commands is provided in addition to the signal paths 118a to 118p for outputting signals to the first to sixteenth buffers 122a to 122p. The identification start command has an 8-bit data capacity, and the data of each bit is input as the 1st to 8th signals to the 1st to 8th buffers 122a to 122h. In the output processing of the identification start command, the output state of the 9th signal is switched to HI level at the timing when the output of the identification start command begins, so that the management CPU 112 recognizes that a new command has been sent. The output period of the identification start command and the period during which the output state of the 9th signal is maintained at HI level are set to be sufficient for the management CPU 112 to recognize these identification start commands and the output state of the 9th signal. Upon receiving the identification start command, the management CPU 112 determines that it should start processing to store information on the correspondence between the 1st to 14th buffers 122a to 122n and the types of signals in the correspondence memory 116.

[0266] Subsequently, a type identification command corresponding to the current value of the recognition output counter in the main RAM 65 is read from the main ROM 64 (step S803). In this case, the first buffer 122a is the first to be set as the signal type, and then the n+1 buffer is set as the signal type, so that the recognition setting of the signal types corresponding to the 1st to 14th buffers 122a to 122n is performed. Therefore, if the recognition output counter is "14" to "12", a type identification command indicating that it is the general prize entry port 31 and the number of prize balls is read; if the recognition output counter is "11", a type identification command indicating that it is the special electric prize entry device 32 and the number of prize balls is read; if the recognition output counter is "10", a type identification command indicating that it is the first operation port 33 and the number of prize balls is read; if the recognition output counter is "9", a type identification command indicating that it is the second operation port 34 and the number of prize balls is read; and if the recognition output counter is "8", an out port is read. The system reads a type identification command indicating that it is 24a, reads a type identification command indicating that it is in opening / closing execution mode if the recognition output counter is "7", reads a type identification command indicating that it is in high-frequency support mode if the recognition output counter is "6", reads a type identification command indicating that it is front door frame 14 if the recognition output counter is "5", reads a type identification command indicating that it is a game round if the recognition output counter is "4", and reads a type identification command indicating that it is blank if the recognition output counter is "3" to "1".

[0267] Subsequently, the output processing of the read type identification command is executed (step S804). The type identification command, like the identification start command, has a data capacity of 8 bits, and the data of each bit is input as the 1st to 8th signals to the 1st to 8th buffers 122a to 122h. In addition, in the output processing of the identification type command, the output state of the 9th signal is switched to the HI level at the timing when the output of the identification type command begins, so that the management CPU 112 recognizes that a new command has been sent. The output period of the identification type command and the period during which the output state of the 9th signal is maintained at the HI level are set to be sufficient for the management CPU 112 to recognize these identification type commands and the output state of the 9th signal. Upon receiving the identification type command, the management CPU 112 stores the information corresponding to that identification type command in the corresponding relationship areas 123a to 123n of the 1st to 14th buffers 122a to 122n that are the target of this configuration.

[0268] Subsequently, the value of the recognition output counter in the main RAM 65 is decremented by 1 (step S805), and it is determined whether the value of the recognition output counter after the 1-decrement is "0" or not (step S806). If the value of the recognition output counter is 1 or greater (step S806: NO), processing is performed to output a type identification command corresponding to the value of the recognition output counter after the 1-decrement (steps S803 and S804).

[0269] On the other hand, if the value of the recognition output counter is "0" (step S806: YES), the output processing of the identification end command is executed (step S807). The identification end command has a data capacity of 8 bits, and the data of each bit is input as the 1st to 8th signals to the 1st to 8th buffers 122a to 122h. In addition, in the output processing of the identification end command, the output state of the 9th signal is switched to the HI level at the timing when the output of the identification end command begins in order to make the management CPU 112 recognize that a new command has been sent. The output period of the identification end command and the period during which the output state of the 9th signal is maintained at the HI level are set to be sufficient periods for the management CPU 112 to recognize these identification end commands and the output state of the 9th signal. Upon receiving the identification end command, the management CPU 112 determines that the processing to store the correspondence information between the 1st to 14th buffers 122a to 122n and the signal types in the correspondence memory 116 has been completed.

[0270] Next, the management process executed by the management CPU 112 will be explained with reference to the flowchart in Figure 23. The management process starts when power is supplied to the management CPU 112. The management CPU 112 is configured to have a faster processing speed than the main CPU 63, and the combination of processes from step S908 onwards in the management process is executed 16 or more times between the start of one timer interrupt process (Figure 11) on the main CPU 63 and the start of the next timer interrupt process (Figure 11).

[0271] First, it is determined whether or not an identification start command has been received from the main CPU 63 (step S901). If an identification start command has not been received (step S901: NO), the setting update recognition process is executed (step S902), and then the process returns to step S901. In the setting update recognition process, although the details will be described later, if a new setting is made in the setting state of the pachinko machine 10 by the main CPU 63, the corresponding process is executed.

[0272] When the identification start command is received from the main CPU 63 (step S901: YES), the value of the setting target counter in the management RAM 114 is cleared to "0" (step S903). The setting target counter is a counter used by the management CPU 112 to identify the types of buffers 122a to 122n that are subject to signal type setting. The first buffer 122a is the first to be subject to signal type setting, and thereafter the nth buffer, followed by the (n+1)th buffer, becomes the target of signal type setting.

[0273] Subsequently, conditional on receiving a type identification command from the main CPU 63 (step S904: YES), the correspondence relationship setting process is executed (step S905). In the correspondence relationship setting process, the signal type information set in the type identification command received is stored in the correspondence relationship area of ​​the first to 14th correspondence relationship areas 123a to 123n of the correspondence relationship memory 116 that corresponds to the current value of the setting target counter in the management RAM 114. Then, the value of the setting target counter in the management RAM 114 is incremented by 1 (step S906).

[0274] If a negative determination is made in step S904, or if the process in step S906 is executed, it is determined whether or not an identification completion command has been received from the main CPU 63 (step S907). If an identification completion command has not been received (step S907: NO), the process returns to step S904, and steps S905 and S906 are executed again, provided that a new type identification command is received from the main CPU 63 (step S904: YES).

[0275] If an identification completion command is received from the main CPU 63 (step S907: YES), the processes from steps S908 to S910 are repeatedly executed. In step S908, as will be described in detail later, a history setting process is executed to store history information corresponding to the type of signal received from the main CPU 63 in the history memory 117. In step S909, as will be described in detail later, various parameters are calculated using the history information stored in the history memory 117, and a display output process is executed to announce the calculation results on the first to third notification display devices 69a to 69c. In step S910, as will be described in detail later, an external output process is executed to output the history information stored in the history memory 117 and the various parameters stored in the calculation result memory 131 to the read terminal 68d.

[0276] Figure 24 is a time chart showing how information regarding the correspondence between the first to 14th buffers 122a to 122n and the types of signals input to these buffers 122a to 122n is stored in the correspondence memory 116. Figure 24(a) shows the period during which commands are output from the main CPU 63 to the management CPU 112 using the first to 8th signals (i.e., the first to 8th signal paths 118a to 118h), Figure 24(b) shows the period during which the output state of the 9th signal is at a HI level, Figure 24(c) shows the execution period of the identification state during which processing is performed to identify the correspondence between the first to 14th buffers 122a to 122n and the types of signals input to these buffers 122a to 122n, and Figure 24(d) shows the timing when the correspondence setting process (step S905) is executed in the management CPU 112.

[0277] When power is supplied to the main CPU 63 and the management CPU 112, at timing t1, the output of an identification start command using the 1st to 8th signals begins, as shown in Figure 24(a). Also at timing t1, the output state of the 9th signal is changed from LOW to HI, as shown in Figure 24(b). Subsequently, at timing t2, while the output of the identification start command is still continuing, the output state of the 9th signal is changed again from HI to LOW, as shown in Figure 24(b). The management CPU 112 confirms that a command has been sent from the main CPU 63 by checking the information in the 1st to 8th buffers 122a to 122h, and understands the content of the command received from the main CPU 63. In this case, since an identification start command has been received, the management CPU 112 enters the identified state by making an affirmative judgment in step S901 of the management process (Figure 23). Subsequently, at timing t3, the output of the identification start command is stopped, as shown in Figure 24(a).

[0278] Subsequently, at timing t4, the output of the first type identification command using the 1st to 8th signals begins, as shown in Figure 24(a). Also at timing t4, the output state of the 9th signal is changed from LOW to HI, as shown in Figure 24(b). Then, at timing t5, while the output of the type identification command is still continuing, the output state of the 9th signal is changed again from HI to LOW, as shown in Figure 24(b). The management CPU 112 confirms that a command has been sent from the main CPU 63 by checking that the output state of the 9th signal has changed from HI to LOW, and understands the content of the command received from the main CPU 63 by checking the information in the 1st to 8th buffers 122a to 122h. In this case, since the first type identification command has been received, the management CPU 112 executes the correspondence setting process at timing t5, as shown in Figure 24(d). In this correspondence setting process, information indicating that it is a general prize slot 31 and information on the number of prize balls awarded are stored in the first correspondence area 123a of the correspondence memory 116. Subsequently, at timing t6, the output of the type identification command is stopped as shown in Figure 24(a).

[0279] Subsequently, at timings t7 to t9, t10 to t12, t13 to t15, and t16 to t18, the management CPU 112 executes a correspondence setting process corresponding to the type identification command output from the main CPU 63, similar to the timings t4 to t6. In this case, the correspondence setting process corresponding to the 14th type identification command is completed at timings t16 to t18.

[0280] Subsequently, at timing t19, the output of an identification termination command using the 1st to 8th signals begins, as shown in Figure 24(a). Also at timing t19, the output state of the 9th signal is changed from LOW to HI, as shown in Figure 24(b). Then, at timing t20, while the output of the identification termination command is still continuing, the output state of the 9th signal is changed again from HI to LOW, as shown in Figure 24(b). The management CPU 112 confirms that a command has been sent from the main CPU 63 by checking the information in the 1st to 8th buffers 122a to 122h, and understands the content of the command received from the main CPU 63. In this case, since an identification termination command has been received, the identification state of the management CPU 112 ends at timing t20, as shown in Figure 24(c). Then, at timing t21, the output of the identification termination command is stopped, as shown in Figure 24(a).

[0281] As described above, by using the 9th signal to allow the management CPU 112 to recognize whether or not a command is being output, it is possible to clearly allow the management CPU 112 to recognize that a command is being output, even in a configuration where command output is performed using the 1st to 8th signals (i.e., the 1st to 8th signal path) which are used to instruct the management CPU 112 on when to store history information.

[0282] Next, we will describe the processing configuration for storing history information in the history memory 117. Figure 25 is a flowchart showing the management output processing executed by the main CPU 63. The management output processing is executed in step S319 of the timer interrupt processing (Figure 11).

[0283] First, the managed counter in the main RAM 65 is set to "11" (step S1001). The managed counter is used by the main CPU 63 to determine whether or not there are managed items that are not the target of the determination of whether or not the signal output state to the management CPU 112 should be changed in this management output processing, and also to determine whether or not the signal output state to the management CPU 112 should be changed for each managed item. In one management output processing, the managed items that the main CPU 63 determines whether or not the signal output state to the management CPU 112 should be changed are a total of 11 items: the seven ball entry detection sensors 42a to 48a, whether or not the opening / closing execution mode is executed, whether or not the high-frequency support mode is executed, whether or not the front door frame 14 is opened or closed, and whether or not a game round has started. Therefore, the managed counter is set to "11" first.

[0284] Next, it is determined whether the signal output status to the management CPU 112 for the managed object corresponding to the current managed counter value is at a HI level (step S1002). If it is not at a HI level (step S1002: NO), it is determined whether the managed object corresponding to the managed counter value is 5 or greater, thereby identifying whether it is one of the seven ball entry detection sensors 42a to 48a (step S1003).

[0285] If a positive determination is made in step S1003, it is determined whether the output flag of the main RAM 65 corresponding to the value of the managed counter is set to "1" (step S1004). Specifically, if the value of the managed counter is "11" and corresponds to the first prize-winning slot detection sensor 42a, it is determined whether the first output flag is set to "1", if the value of the managed counter is "10" and corresponds to the second prize-winning slot detection sensor 43a, it is determined whether the second output flag is set to "1", if the value of the managed counter is "9" and corresponds to the third prize-winning slot detection sensor 44a, it is determined whether the third output flag is set to "1", and if the value of the managed counter is "8" and corresponds to the special electric detection sensor 45 If it corresponds to a, it is determined whether the fourth output flag is set to "1". If the value of the managed counter is "7" and it corresponds to the first operation port detection sensor 46a, it is determined whether the fifth output flag is set to "1". If the value of the managed counter is "6" and it corresponds to the second operation port detection sensor 47a, it is determined whether the sixth output flag is set to "1". If the value of the managed counter is "5" and it corresponds to the out port 24a, it is determined whether the seventh output flag is set to "1". As previously explained, these first to seventh output flags are set to "1" during the ball entry detection process (Figure 15).

[0286] If the output flag corresponding to the value of the managed counter is set to "1" (step S1004: YES), the output state of the signal corresponding to the value of the managed counter among the 1st to 7th signals is set to HI level (step S1005). Then, the output flag corresponding to the value of the managed counter is cleared to "0" (step S1006).

[0287] If a negative result is obtained in step S1003, it is determined whether an event has occurred that would cause the output state of the signal corresponding to the value of the managed counter to be switched to the HI level (step S1007). Specifically, if the value of the managed counter is "4", it is determined whether a transition to the opening / closing execution mode has occurred; if the value of the managed counter is "3", it is determined whether a transition to the high-frequency support mode has occurred; if the value of the managed counter is "2", it is determined whether the front door frame 14 has been opened; and if the value of the managed counter is "1", it is determined whether the 11th output flag is set to "1" to determine whether a game round has started. If a positive result is obtained in step S1007, the output state of the signal corresponding to the value of the managed counter is set to the HI level (step S1008). Note that if the value of the managed counter is "1" and the process in step S1008 is executed, the 11th output flag is cleared to "0".

[0288] If a positive result is obtained in step S1002, it is determined whether an event has occurred that triggers a switch to a LOW level for the output state of the signal corresponding to the value of the managed counter (step S1009). Specifically, if the value of the managed counter is 5 or greater or "1" and the current managed object is one of the ball entry detection sensors 42a to 48a or the start of a game round, it is determined whether a period of HI output continuation (specifically 10 milliseconds) has elapsed since the output state of the signal corresponding to the value of the managed counter among the 1st to 7th signals and the 11th signal was switched from a LOW level to a HI level. This HI output continuation period is set in the management CPU 112 to be longer than the longest processing interval of the history setting process (step S908) of the management process (Figure 23), and is a period during which the management CPU 112 can reliably identify the output state of the signal that has switched from a LOW level to a HI level. Furthermore, if the value of the managed counter is "4" and the current managed object is in opening / closing execution mode, it is determined whether the opening / closing execution mode has ended. If the value of the managed counter is "3" and the current managed object is in high-frequency support mode, it is determined whether the high-frequency support mode has ended. If the value of the managed counter is "2" and the current managed object is the front door frame 14, it is determined whether the front door frame 14 is in a closed state. If an event occurs that triggers switching the output state of the signal corresponding to the value of the managed counter to a LOW level (step S1009: YES), the output state of the signal corresponding to the value of the managed counter is set to a LOW level (step S1010).

[0289] If a negative result is obtained in step S1004, if the process in step S1006 is executed, if a negative result is obtained in step S1007, if the process in step S1008 is executed, if a negative result is obtained in step S1009, or if the process in step S1010 is executed, the value of the managed counter in the main RAM 65 is decremented by 1 (step S1011). Then, it is determined whether the value of the managed counter after the decrement is "0" (step S1012). If the value of the managed counter is 1 or greater (step S1012: NO), the process from step S1002 onwards is executed for the managed object corresponding to the new managed counter value.

[0290] Next, the history setting process executed by the management CPU 112 will be explained with reference to the flowchart in Figure 26. The history setting process is executed in step S908 of the management process (Figure 23).

[0291] First, the number of buffers to be checked by the management CPU 112 from among the first to 14th buffers 122a to 122n is set in the verification target counter provided in the management RAM 114 (step S1101). Specifically, the number of correspondence areas in the correspondence memory 116 that store information other than information indicating that they are blank is identified, and this identified number of items is set in the verification target counter. In this pachinko machine 10, as already explained, information other than information indicating that they are blank is stored in the first to 11th correspondence areas 123a to 123k, so in step S1101, "11" is set in the verification target counter.

[0292] Subsequently, the system checks whether the numerical information stored in the buffer corresponding to the current value of the counter to be checked among the first to fourteenth buffers 122a to 122n has changed from "0" to "1", thereby determining whether the output state of the input signal from the main CPU 63 to the buffer has switched from a LOW level to a HI level (step S1102). If the value of the counter to be checked is "n", then the nth buffer 122a to 122n will be the target of numerical information check. For example, if the value of the counter to be checked is "11", then the eleventh buffer 122k will be the target of numerical information check, and if the value of the counter to be checked is "5", then the fifth buffer 122e will be the target of numerical information check.

[0293] If a positive determination is made in step S1102, the RTC information, which consists of date and time information, is read from the RTC 115 (step S1103). Then, the write process to the history memory 117 is executed (step S1104). In this write process, the pointer information of the history area 124 currently being written to is identified by referring to the pointer area 126 of the history memory 117, and the RTC information read in step S1103 is written to the history information storage area 125 of the history area 124 corresponding to the pointer information being written to. In addition, correspondence information is read from the correspondence areas 123a to 123n corresponding to the current value of the counter to be checked, and this correspondence information is written to the history information storage area 125 corresponding to the pointer information being written to. Furthermore, if the correspondence information is any of the information indicating that it is in opening / closing execution mode, information indicating that it is in high-frequency support mode, or information indicating that it is the front door frame 14, then not only the correspondence information but also start information is written to the history information storage area 125 corresponding to the pointer information being written to. If the value of the counter to be checked is "n", then the nth correspondence area 123a to 123n will be the target for reading the correspondence information. For example, if the value of the counter to be checked is "11", then the 11th correspondence area 123k will be the target for reading the correspondence information, and if the value of the counter to be checked is "5", then the 5th correspondence area 123e will be the target for reading the correspondence information.

[0294] As described above, when the write process is executed, if the value of the counter to be checked is one of the following: the out port 24a, the general prize port 31, the special electric prize device 32, the first operation port 33, the second operation port 34, or the number of games played, the history information storage area 125 corresponding to the pointer information to be written will store a combination of RTC information and correspondence information indicating that it is one of the following: the out port 24a, the general prize port 31, the special electric prize device 32, the first operation port 33, the second operation port 34, or the number of games played, as history information. Also, if the value of the counter to be checked is one of the following: the open / close execution mode, the high-frequency support mode, or the front door frame 14, the history information storage area 125 corresponding to the pointer information to be written will store a combination of RTC information, correspondence information indicating that it is one of the following: the open / close execution mode, the high-frequency support mode, or the front door frame 14, and the start information, as history information.

[0295] Subsequently, the update process for the target pointer is executed (step S1105). In this update process, the numerical information stored in the pointer area 126 of the history memory 117 is read and incremented by 1. It is then determined whether the pointer information after the increment exceeds the maximum value of the pointer information in the history area 124. If it does not exceed the maximum value, the pointer information after the increment is overwritten in the pointer area 126 as the new pointer information to be written. If it exceeds the maximum value, the pointer area 126 is cleared to "0" so that the pointer information to be written becomes the first pointer information.

[0296] If a negative determination is made in step S1102, or if the process in step S1105 is executed, it is determined whether the corresponding relationship information that should be checked to determine whether the signal output has been switched to a LOW level is stored in the corresponding relationship area 123a to 123n that corresponds to the current value of the counter to be checked (step S1106). Specifically, if the current value of the counter to be checked is "8" to "10", then one of the following information is stored in the corresponding relationship area 123h to 123j: information indicating that it is in opening / closing execution mode, information indicating that it is in high-frequency support mode, or information indicating that it is the front door frame 14. Therefore, an affirmative determination is made in step S1106.

[0297] If a positive determination is made in step S1106, it is determined whether the output state of the input signal from the main CPU 63 to the buffer has been switched from a HI level to a LOW level by checking whether the numerical information stored in the buffer corresponding to the current value of the counter to be checked among the first to fourteenth buffers 122a to 122n has been changed from "1" to "0" (step S1107). If a positive determination is made in step S1107, the RTC information is read in the same way as in step S1103 (step S1108), and then the write process to the history memory 117 is executed (step S1109). In this write process, the RTC information read in step S1108 is written to the history information storage area 125 of the history area 124 corresponding to the pointer information to be written. In addition, correspondence information is read from the correspondence area 123a to 123n corresponding to the current value of the counter to be checked, and this correspondence information is written to the history information storage area 125 corresponding to the pointer information to be written. Furthermore, in addition to the correspondence information, termination information is also written to the history information storage area 125 corresponding to the pointer information to be written. When this writing process is executed, if the value of the counter to be checked is one of the opening / closing execution mode, high-frequency support mode, or front door frame 14, the history information storage area 125 corresponding to the pointer information to be written will store as history information a combination of RTC information, correspondence information indicating that it is one of the opening / closing execution mode, high-frequency support mode, or front door frame 14, and termination information. After that, the update process for the target pointer is executed in the same way as in step S1105 (step S1110).

[0298] If a negative determination is made in step S1106, if a negative determination is made in step S1107, or if the process in step S1110 is executed, the value of the check target counter in the management RAM 114 is decremented by 1 (step S1111). Then, it is determined whether the value of the check target counter after the decrement is "0" (step S1112). If the value of the check target counter is 1 or greater (step S1112: NO), the process from step S1102 onwards is executed for the check target corresponding to the new check target counter value.

[0299] Next, we will explain how history information is stored in the history memory 117, referring to the time chart in Figure 27. Figure 27(a) shows the period when a HI level signal is input to any of the 1st to 7th or 11th buffers 122a to 122g or 122k; Figure 27(b) shows the period when a HI level signal is input to the 8th buffer 122h; Figure 27(c) shows the period when a HI level signal is input to the 9th buffer 122i; Figure 27(d) shows the period when a HI level signal is input to the 10th buffer 122j; and Figure 27(e) shows the timing of writing history information to the history memory 117.

[0300] At timing t1, as shown in Figure 27(a), the output state of the signal input to one of the first to seventh or eleventh buffers 122a to 122g or 122k is switched from LOW level to HI level. Therefore, at timing t1, history information is written to the history memory 117 as shown in Figure 27(e). Subsequently, at timing t2, as shown in Figure 27(a), the signal that was switched to HI level at timing t1 is switched to LOW level. However, since this signal is input to one of the first to seventh or eleventh buffers 122a to 122g or 122k, and the LOW level switch is not subject to storage of history information, the writing of history information is not performed at timing t2 as shown in Figure 27(e).

[0301] Subsequently, at timings t3, t5, t6, t9, t10, t13, and t14, the output state of the signal input to one of the first to seventh and eleventh buffers 122a to 122g and 122k is switched from LOW level to HI level, as shown in Figure 27(a). Therefore, history information is written at each of these timings, as shown in Figure 27(e).

[0302] As shown in Figure 27(b), the output state of the signal input to the eighth buffer 122h is at a HI level from timing t4 to timing t7. This eighth buffer 122h corresponds to whether or not the opening / closing execution mode has occurred. Therefore, as shown in Figure 27(e), history information is written at timing t4, which is the timing when the output state of the signal input to the eighth buffer 122h switches to a HI level, and at timing t7, which is the timing when the output state of the signal switches to a LOW level. In this case, the history information written at timing t4 includes start information, and the history information written at timing t7 includes end information. This makes it possible to understand the execution period of the opening / closing execution mode by checking the history information in the history memory 117.

[0303] Furthermore, history information is written to the history memory 117 in chronological order. Therefore, it is possible to distinguish whether or not the history information indicating that a ball has entered any of the out slots 24a, general prize slot 31, special electric prize device 32, first operation slot 33, and second operation slot 34 occurred during the opening / closing execution mode. In addition, since the history information includes RTC information, it is also possible to distinguish whether or not the history information indicating that a ball has entered any of the out slots 24a, general prize slot 31, special electric prize device 32, first operation slot 33, and second operation slot 34 occurred during the opening / closing execution mode by comparing it with the RTC information.

[0304] As shown in Figure 27(c), the output state of the signal input to the ninth buffer 122i is at a HI level from timing t8 to timing t11. This ninth buffer 122i corresponds to whether or not the high-frequency support mode is occurring. Therefore, as shown in Figure 27(e), history information is written at timing t8, which is the timing when the output state of the signal input to the ninth buffer 122i switches to a HI level, and at timing t11, which is the timing when the output state of the signal switches to a LOW level. In this case, the history information written at timing t8 includes start information, and the history information written at timing t11 includes end information. This makes it possible to understand the execution period of the high-frequency support mode by checking the history information in the history memory 117.

[0305] Furthermore, history information is written to the history memory 117 in chronological order. Therefore, it is possible to distinguish whether or not the history information indicating that a ball entered any of the out slot 24a, general prize slot 31, special electric prize device 32, first operation slot 33, and second operation slot 34 occurred during high-frequency support mode. In addition, since the history information includes RTC information, it is also possible to distinguish whether or not the history information indicating that a ball entered any of the out slot 24a, general prize slot 31, special electric prize device 32, first operation slot 33, and second operation slot 34 occurred during high-frequency support mode by comparing it with the RTC information.

[0306] As shown in Figure 27(d), the output state of the signal input to the 10th buffer 122j is at a HI level from timing t12 to timing t15. This 10th buffer 122j corresponds to whether the front door frame 14 is open or closed. Therefore, as shown in Figure 27(e), history information is written at timing t12, which is the timing when the output state of the signal input to the 10th buffer 122j switches to a HI level, and at timing t15, which is the timing when the output state of the signal switches to a LOW level. In this case, the history information written at timing t12 includes start information, and the history information written at timing t15 includes end information. This makes it possible to determine the period during which the front door frame 14 is in an open state by checking the history information in the history memory 117.

[0307] Furthermore, history information is written to the history memory 117 in chronological order. Therefore, it is possible to distinguish whether or not the history information indicating that a ball has entered any of the out-out port 24a, general prize-winning port 31, special electric prize-winning device 32, first operation port 33, and second operation port 34 occurred while the front door frame 14 was open. In addition, since the history information includes RTC information, it is also possible to distinguish whether or not the history information indicating that a ball has entered any of the out-out port 24a, general prize-winning port 31, special electric prize-winning device 32, first operation port 33, and second operation port 34 occurred while the front door frame 14 was open by comparing it with the RTC information.

[0308] Next, we will explain the output process of the setting value update signal, which is executed when the setting state of the pachinko machine 10 is set by the main CPU 63. Figure 28 is a flowchart showing the output process of the setting value update signal executed by the main CPU 63. Note that the output process of the setting value update signal is executed in step S119 of the main process (Figure 9).

[0309] The pulse counter in the main RAM 65 is set to a value corresponding to the setting value of the pachinko machine 10 that has just been set (step S1201). Specifically, the value of the setting value counter in the main RAM 65 is set to the pulse counter. Then, it is determined whether or not the setting value update signal directed to the management CPU 112 is at a HI level (step S1202). As already explained, the setting value update signal is input to the 15th buffer 122o of the input port 121 of the management IC 66. Here, the output processing of the setting value update signal is performed at a timing before the recognition processing, which is the processing that causes the management CPU 112 to identify the type of signal input to the 1st to 14th buffers 122a to 122n of the input port 121 in the main processing (Figure 9). In contrast, since the setting value update signal is set to be input to the 15th buffer 122o in the management IC 66 during the design phase of the pachinko machine 10, even if the output processing of the setting value update signal is performed before the recognition processing, the management CPU 112 can identify that the signal input to the 15th buffer 122o is a setting value update signal.

[0310] If a negative determination is made in step S1202, the value of the LOW level counter provided in the main RAM 65 is deducted by 1 (step S1203), and it is determined whether the value of the LOW level counter after the deduction is "0" (step S1204). The LOW level counter is a counter used by the main CPU 63 to determine whether the setting value update signal has been maintained at a LOW level for a predetermined period of time while the setting value update signal outputs multiple pulses that make the setting value update signal HI level. If the value of the LOW level counter is "0" (step S1204: YES), it means that it is time to set the setting value update signal to HI level, so the setting value update signal is set to HI level (step S1205).

[0311] Subsequently, the HI level counter in the main RAM 65 is set to "20" (step S1206). The HI level counter is used by the main CPU 63 to determine the period during which the setting value update signal is maintained at the HI level. The value set in the HI level counter is decremented by 1 approximately every 10 microseconds, so the setting value update signal is maintained at the HI level for 200 microseconds with each pulse output. This period of maintaining the HI level is sufficient for the management CPU 112 to determine that the setting value update signal has changed from the LOW level to the HI level.

[0312] If the setting value update signal is at the HI level (step S1202: YES), the value of the HI level counter in the main RAM 65 is decremented by 1 (step S1207), and it is determined whether the value of the HI level counter after the decrement is "0" (step S1208). If the value of the HI level counter is "0" (step S1208: YES), it means that it is time to set the setting value update signal to the LOW level, so the setting value update signal is set to the LOW level (step S1209).

[0313] Subsequently, the pulse counter value of the main RAM 65 is decremented by 1 (step S1210), and it is determined whether the pulse counter value after the decrement is "0" (step S1211). If the pulse counter value is not "0" (step S1211: NO), it means that the output of pulse signals by the setting value update signal corresponding to the setting value of the pachinko machine 10 has not been completed, so the LOW level counter of the main RAM 65 is set to "20" (step S1212). Since the value set in the LOW level counter is decremented by 1 at a period of approximately 10 microseconds, it is maintained at a LOW level for 200 microseconds between multiple pulse outputs by the setting value update signal. This period of maintaining the LOW level is sufficient for the management CPU 112 to determine that the setting value update signal has changed from a HI level to a LOW level.

[0314] If the pulse count counter value is "0" (step S1211: YES), it means that the output of pulse signals with setting value update signals corresponding to the setting value of the pachinko machine 10 that was set has been completed, and the output process of the setting value identification completion command is executed (step S1213). The setting value identification completion command is a command to make the management CPU 112 recognize that the output of setting value update signals for recognizing the setting value of the pachinko machine 10 that was set has been completed. When outputting the setting value identification completion command, the first to eighth signals input to the first to eighth buffers 122a to 122h are used, similar to the identification start command, type identification command, and identification completion command. However, the signal pattern of the setting value identification completion command is different from that of the identification start command, type identification command, and identification completion command.

[0315] As described above, in the output processing of the setting value update signal, the management IC 66 outputs pulse signals consisting of a number of setting value update signals corresponding to the setting value of the pachinko machine 10 that was set when the power supply for operation was started. The management CPU 112 performs setting update recognition processing to determine the number of pulse signals consisting of the setting value update signal and, based on that, determines the setting value of the pachinko machine 10 that was set this time.

[0316] Figure 29 is a flowchart showing the configuration update recognition process executed on the management CPU 112. The configuration update recognition process is executed in step S902 of the management process (Figure 23).

[0317] Step S1301 determines whether the setting value update signal input to the 15th buffer 122o of input port 121 has switched from a LOW level to a HI level. If a positive determination is made in step S1301, the value of the setting value recognition counter provided in the management RAM 114 is set to "1" (step S1302). The setting value recognition counter is a counter used by the management CPU 112 to identify the setting value of the pachinko machine 10. For example, if the value of the setting value recognition counter is "1", it means that the setting is "1", and if the value of the setting value recognition counter is "6", it means that the setting is "6".

[0318] Subsequently, it is determined whether the setting value update signal input to the 15th buffer 122o of input port 121 has switched back from LOW level to HI level (step S1303). If the determination in step S1303 is positive, the value of the setting value recognition counter in the management RAM 114 is incremented by 1 (step S1304). As a result, the setting value of the pachinko machine 10 identified by the management CPU 112 increases by one level.

[0319] If a negative determination is made in step S1303, or if the process in step S1304 is executed, it is determined whether or not a setting value identification completion command has been received from the main CPU 63 based on the input state of the first to eighth signals input to the first to eighth buffers 122a to 122h of the input port 121 (step S1305). If a negative determination is made in step S1305, the process returns to step S1303.

[0320] If a positive result is obtained in step S1305, the RTC information, which consists of date and time information, is read from the RTC 115 (step S1306). Then, the write process to the history memory 117 is executed (step S1307). In this write process, the pointer information of the history area 124 currently being written to is identified by referring to the pointer area 126 of the history memory 117, and the RTC information read in step S1306 is written to the history information storage area 125 of the history area 124 corresponding to the pointer information being written to. In addition, both information to identify that it is a set value and information about the value of the set value recognition counter are written to the history information storage area 125 corresponding to the pointer information being written to. As a result, the combination of information indicating that the setting state of the pachinko machine 10 has been newly set, the RTC information corresponding to the date and time when the setting was made, and the setting value information when the setting was made is stored as history information.

[0321] Subsequently, the update process for the target pointer is executed (step S1308). In this update process, the numerical information stored in the pointer area 126 of the history memory 117 is read and incremented by 1. It is then determined whether the pointer information after the increment exceeds the maximum value of the pointer information in the history area 124. If it does not exceed the maximum value, the pointer information after the increment is overwritten in the pointer area 126 as the new pointer information to be written. If it exceeds the maximum value, the pointer area 126 is cleared to "0" so that the pointer information to be written becomes the first pointer information.

[0322] As described above, when the setting update recognition process is executed and the setting state of the pachinko machine 10 is newly set, the fact that the setting was made, the date and time the setting was made, and the combination of the setting value at the time the setting was made are stored as history information in the history area 124. This makes it possible to read and analyze the information stored in the history memory 117 using an external device connected to the reading terminal 68d to determine the date and time the setting state of the pachinko machine 10 was newly set and the content of the setting value at the time the setting was made.

[0323] Here, even if the settings of the pachinko machine 10 are newly set, the information stored in the history memory 117 remains unchanged. This prevents the history information in the history memory 117 from being erased even if the settings of the pachinko machine 10 are newly set, and the various parameters described later are calculated using the history information that exists before and after the timing of the change in the settings of the pachinko machine 10. In this case, as described above, the date and time when the settings of the pachinko machine 10 are newly set are stored in the history memory 117, so by connecting an external device to the reading terminal 68d and reading the information stored in the history memory 117, it becomes possible to calculate various parameters for the period after the timing when the settings of the pachinko machine 10 are newly set and while that setting is maintained.

[0324] Next, the display output processing performed by the management CPU 112 will be explained with reference to the flowchart in Figure 30. Note that the display output processing is performed in step S909 of the management processing (Figure 23).

[0325] First, it is determined whether or not it is the timing for calculation (step S1401). If 51 seconds have elapsed since the supply of operating power to the management CPU 112 began, or if 51 seconds have elapsed since the last affirmative determination in step S1401, an affirmative determination is made in step S1401. If an affirmative determination is made in step S1401, the number of balls that enter each category under normal circumstances is calculated (step S1402). Specifically, first, the number of balls that enter the exit port 24a is calculated by counting the number of history information storage areas 125 in the history area 124 of the history memory 117, where correspondence information indicating that it is the exit port 24a is stored. Also, the number of balls that enter the general prize port 31 is calculated by counting the number of history information storage areas 125 in the history area 124 of the history memory 117, where correspondence information indicating that it is the general prize port 31 is stored. Furthermore, the number of balls that enter the special electric prize winning device 32 is calculated by counting the number of history information storage areas 125 in the history area 124 of the history memory 117 that store correspondence information indicating that it is the special electric prize winning device 32. Furthermore, the number of balls that enter the first operating port 33 is calculated by counting the number of history information storage areas 125 in the history area 124 of the history memory 117 that store correspondence information indicating that it is the first operating port 33. Furthermore, the number of balls that enter the second operating port 34 is calculated by counting the number of history information storage areas 125 in the history area 124 of the history memory 117 that store correspondence information indicating that it is the second operating port 34.

[0326] Subsequently, the number of balls that entered each of the out-out opening 24a, general prize-winning opening 31, special electric prize-winning device 32, first operation opening 33, and second operation opening 34 when the front door frame 14 was open is calculated by referring to the history information storage area 125 in the history area 124 of the history memory 117 that is in the period between the history information storage area 125 in which correspondence relationship information and start information indicating that it is the front door frame 14 are stored and the history information storage area 125 in which correspondence relationship information and end information indicating that it is the front door frame 14 are stored (step S1403). Furthermore, if there are multiple intervals in the entire sequence of pointer information between the history information storage area 125 where correspondence information and start information indicating that it is the front door frame 14 are stored and the history information storage area 125 where correspondence information and end information indicating that it is the front door frame 14 are stored, the total number of balls that enter each interval is calculated. Also, if there is a history information storage area 125 where correspondence information and start information indicating that it is the front door frame 14 are stored, but the history information storage area 125 where RTC information corresponding to a later time than the history information storage area 125 is stored does not contain correspondence information and end information indicating that it is the front door frame 14, then the history information in the history information storage area 125 where RTC information corresponding to a later time than the history information storage area 125 where correspondence information and start information indicating that it is the front door frame 14 are stored is treated as if the front door frame 14 was in an open state.

[0327] Subsequently, various parameters are calculated using the calculation results from steps S1402 and S1403 (step S1404). Specifically, first, the number of balls that entered while the front door frame 14 was open, calculated in step S1403, is subtracted from the number of balls that entered each step, calculated in step S1402. Then, the following 1st to 8th parameters are calculated using the number of balls that entered each step after this subtraction. Note that the difference between the number of balls that entered the out port 24a calculated in step S1402 and the number of balls that entered the out port 24a calculated in step S1403 is defined as the number of balls that entered, and the difference between the number of balls that entered the general prize port 31 calculated in step S1402 and the number of balls that entered the general prize port 31 calculated in step S1403 is defined as the number of balls that entered, and the difference between the number of balls that entered the special electric prize device 32 calculated in step S1402 is defined as the number of balls that entered, calculated in step S1402. The difference in the number of balls that enter the special electric prize device 32 calculated in step S1403 is defined as the number of balls entered K3, the difference in the number of balls that enter the first operating port 33 calculated in step S1403 compared to the number of balls that enter the first operating port 33 calculated in step S1402 is defined as the number of balls entered K4, and the difference in the number of balls that enter the second operating port 34 calculated in step S1403 compared to the number of balls that enter the second operating port 34 calculated in step S1402 is defined as the number of balls entered K5. • Parameter 1: Total number of game balls dispensed (K2 × "Number of prize balls for entry into general prize slot 31" + K3 × "Number of prize balls for entry into special electric prize device 32" + K4 × "Number of prize balls for entry into first operation slot 33" + K5 × "Number of prize balls for entry into second operation slot 34") / Ratio of the total number of game balls discharged from the game area PA (K1 + K2 + K3 + K4 + K5) (Hereafter, this ratio will be referred to as "D1") • Second parameter: The ratio of the total number of game balls entered into the general prize slot 31 (K2) to the total number of game balls discharged from the game area PA (K1 + K2 + K3 + K4 + K5). • Third parameter: The ratio of the total number of game balls entered into the special prize-winning device 32 (K3) to the total number of game balls discharged from the game area PA (K1 + K2 + K3 + K4 + K5). • Fourth parameter: The ratio of the total number of game balls entered into the first operating port 33 (K4) to the total number of game balls discharged from the game area PA (K1 + K2 + K3 + K4 + K5) (hereinafter, this ratio will be referred to as "D2"). • Fifth parameter: The ratio of the total number of game balls entered into the second operating port 34 (K5) to the total number of game balls discharged from the game area PA (K1 + K2 + K3 + K4 + K5) (hereinafter, this ratio will be referred to as "D3"). • Parameter 6: D1 - (D2 × "Number of prize balls awarded for winning in the first operating slot 33" + D3 × "Number of prize balls awarded for winning in the second operating slot 34") • Parameter 7: (K3 × "Number of prize balls awarded for winning into the special electric prize device 32" + K5 × "Number of prize balls awarded for winning into the second operating port 34") / Ratio of the total number of game balls dispensed (K2 × "Number of prize balls awarded for winning into the general prize port 31" + K3 × "Number of prize balls awarded for winning into the special electric prize device 32" + K4 × "Number of prize balls awarded for winning into the first operating port 33" + K5 × "Number of prize balls awarded for winning into the second operating port 34") • Parameter 8: K3 × "Number of prize balls awarded for winning in the special electric prize winning device 32" / Total number of game balls dispensed (K2 × "Number of prize balls awarded for winning in the general prize winning slot 31" + K3 × "Number of prize balls awarded for winning in the special electric prize winning device 32" + K4 × "Number of prize balls awarded for winning in the first operating slot 33" + K5 × "Number of prize balls awarded for winning in the second operating slot 34") In step S1404, the calculation results of the first to eighth parameters are stored in the normal operation storage area of ​​the calculation result memory 131. The first to eighth parameters stored in this normal operation storage area are retained until the next execution of step S1404. In other words, when the next execution of step S1404 calculates the first to eighth parameters, the newly calculated first to eighth parameters are stored in the normal operation storage area, overwriting the previous calculation results of the first to eighth parameters that were previously stored in the normal operation storage area.

[0328] Subsequently, the number of balls that entered each of the out gate 24a, general prize gate 31, special electric prize device 32, first operation gate 33, and second operation gate 34 while in the open / close execution mode is calculated by referring to the history information storage area 125 that exists during the period between the history information storage area 125 in the history area 124 of the history memory 117, which stores correspondence relationship information and start information indicating that it is in the open / close execution mode, and the history information storage area 125 that stores correspondence relationship information and end information indicating that it is in the open / close execution mode (step S1405). The period between the history information storage area 125 in the history area 124 of the history memory 117, which stores correspondence relationship information and start information indicating that it is in the open / close execution mode, and the history information storage area 125 that stores correspondence relationship information and end information indicating that it is in the open / close execution mode is calculated from the RTC information stored in these history information storage areas 125. Furthermore, if there are multiple intervals in the entire sequence of pointer information between the history information storage area 125 where correspondence relationship information and start information indicating that it is in open / close execution mode are stored and the history information storage area 125 where correspondence relationship information and end information indicating that it is in open / close execution mode are stored, the total number of balls entered for each interval is calculated. Also, if there is a history information storage area 125 where correspondence relationship information and start information indicating that it is in open / close execution mode are stored, but the history information storage area 125 where RTC information corresponding to a later time than the history information storage area 125 where correspondence relationship information and start information indicating that it is in open / close execution mode is stored does not contain correspondence relationship information and end information indicating that it is in open / close execution mode, then all the history information in the history information storage area 125 where RTC information corresponding to a later time than the history information storage area 125 where correspondence relationship information and start information indicating that it is in open / close execution mode is treated as being in open / close execution mode.

[0329] Subsequently, during the period of the opening / closing execution mode identified in step S1405, the number of balls that entered each of the out-out opening 24a, general prize-winning opening 31, special electric prize-winning device 32, first operating opening 33, and second operating opening 34 while the front door frame 14 was in the open state is calculated (step S1406). The method for calculating these ball entry numbers is the same as in step S1403, except that it assumes the period of the opening / closing execution mode identified in step S1405.

[0330] Subsequently, various parameters are calculated using the calculation results from steps S1405 and S1406 (step S1407). Specifically, first, the number of balls that entered while the front door frame 14 was open, calculated in step S1406, is subtracted from the number of balls that entered each step, calculated in step S1405. Then, the following 11th to 18th parameters are calculated using the number of balls that entered each step after this subtraction. Note that the difference between the number of balls that entered the out-out opening 24a calculated in step S1405 and the number of balls that entered the out-out opening 24a calculated in step S1406 is defined as the number of balls entered, the difference between the number of balls that entered the general prize-winning opening 31 calculated in step S1405 and the number of balls that entered the general prize-winning opening 31 calculated in step S1406 is defined as the number of balls entered, and the step of the number of balls that entered the special electric prize-winning device 32 calculated in step S1405 is defined as the number of balls entered. The difference in the number of balls that enter the special electric prize device 32 calculated in step S1406 is defined as the number of balls entered K13, the difference in the number of balls that enter the first operating port 33 calculated in step S1406 compared to the number of balls that enter the first operating port 33 calculated in step S1405 is defined as the number of balls entered K14, and the difference in the number of balls that enter the second operating port 34 calculated in step S1406 compared to the number of balls that enter the second operating port 34 calculated in step S1405 is defined as the number of balls entered K15. • Parameter 11: Total number of game balls dispensed (K12 × "Number of prize balls for winning at the general prize slot 31" + K13 × "Number of prize balls for winning at the special electric prize device 32" + K14 × "Number of prize balls for winning at the first operating slot 33" + K15 × "Number of prize balls for winning at the second operating slot 34") / Ratio of the total number of game balls discharged from the game area PA (K11 + K12 + K13 + K14 + K15) (Hereafter, this ratio will be referred to as "D11") • Parameter 12: The ratio of the total number of game balls entered into the general prize slot 31 (K12) to the total number of game balls discharged from the game area PA (K11 + K12 + K13 + K14 + K15). • Parameter 13: The ratio of the total number of game balls entered into the special prize-winning device 32 (K13) to the total number of game balls discharged from the game area PA (K11 + K12 + K13 + K14 + K15). • Parameter 14: The ratio of the total number of game balls entered into the first operating port 33 (K14) to the total number of game balls discharged from the game area PA (K11 + K12 + K13 + K14 + K15) (hereinafter, this ratio will be referred to as "D12"). • Parameter 15: The ratio of the total number of game balls entered into the second operating port 34 (K15) to the total number of game balls discharged from the game area PA (K11 + K12 + K13 + K14 + K15) (hereinafter, this ratio will be referred to as "D13"). • Parameter 16: D11 - (D12 × "Number of prize balls awarded for winning in the first operating slot 33" + D13 × "Number of prize balls awarded for winning in the second operating slot 34") • Parameter 17: (K13 × "Number of prize balls awarded for winning into the special electric prize device 32" + K15 × "Number of prize balls awarded for winning into the second operating port 34") / Ratio of the total number of game balls dispensed (K12 × "Number of prize balls awarded for winning into the general prize port 31" + K13 × "Number of prize balls awarded for winning into the special electric prize device 32" + K14 × "Number of prize balls awarded for winning into the first operating port 33" + K15 × "Number of prize balls awarded for winning into the second operating port 34") • Parameter 18: K13 × "Number of prize balls awarded for winning in the special electric prize winning device 32" / Ratio of total number of game balls dispensed (K12 × "Number of prize balls awarded for winning in the general prize winning slot 31" + K13 × "Number of prize balls awarded for winning in the special electric prize winning device 32" + K14 × "Number of prize balls awarded for winning in the first operating slot 33" + K15 × "Number of prize balls awarded for winning in the second operating slot 34") In step S1407, the calculation results of the 11th to 18th parameters are stored in the storage area for the opening / closing execution mode in the calculation result memory 131. The 11th to 18th parameters stored in the storage area for the opening / closing execution mode are retained until the next step S1407 is executed. In other words, when the next step S1407 is executed and the 11th to 18th parameters are calculated, the newly calculated 11th to 18th parameters are stored in the storage area for the opening / closing execution mode, overwriting the previous calculation results of the 11th to 18th parameters that were previously stored in the storage area for the opening / closing execution mode.

[0331] Subsequently, the number of balls that entered each of the out gate 24a, general prize gate 31, special electric prize device 32, first operation gate 33, and second operation gate 34 while in high-frequency support mode is calculated by referring to the history information storage area 125 in the history area 124 of the history memory 117 that is in the period between the history information storage area 125 in which correspondence relationship information and start information indicating that it is in high-frequency support mode is stored and the history information storage area 125 in which correspondence relationship information and end information indicating that it is in high-frequency support mode is stored (step S1408). The period between the history information storage area 125 in the history area 124 of the history memory 117 that is in high-frequency support mode and the history information storage area 125 in which correspondence relationship information and end information indicating that it is in high-frequency support mode is stored is calculated from the RTC information stored in these history information storage areas 125. Furthermore, if there are multiple intervals in the entire sequence of pointer information between the history information storage area 125 where correspondence relationship information and start information indicating high-frequency support mode are stored and the history information storage area 125 where correspondence relationship information and end information indicating high-frequency support mode are stored, the total number of balls entered for each interval is calculated. Also, if there is a history information storage area 125 where correspondence relationship information and start information indicating high-frequency support mode are stored, but the history information storage area 125 where RTC information corresponding to a later time than the history information storage area 125 is stored does not contain correspondence relationship information and end information indicating high-frequency support mode, then all the history information in the history information storage area 125 where RTC information corresponding to a later time than the history information storage area 125 where correspondence relationship information and start information indicating high-frequency support mode are stored is treated as being in high-frequency support mode.

[0332] Subsequently, during the period of high-frequency support mode identified in step S1408, the number of balls that entered each of the out-port 24a, general-purpose entry port 31, special-purpose entry device 32, first-operation port 33, and second-operation port 34 while the front door frame 14 was open is calculated (step S1409). The method for calculating these ball entry numbers is the same as in step S1403, except that it assumes the period of high-frequency support mode identified in step S1408.

[0333] Subsequently, various parameters are calculated using the calculation results from steps S1408 and S1409 (step S1410). Specifically, first, the number of balls that entered while the front door frame 14 was open, calculated in step S1409, is subtracted from the number of balls that entered each way, calculated in step S1408. Then, the following 21st to 26th parameters are calculated using the number of balls that entered each way after this subtraction. Note that the difference between the number of balls that entered the out-out opening 24a calculated in step S1408 and the number of balls that entered the out-out opening 24a calculated in step S1409 is defined as the number of balls that entered, K21; the difference between the number of balls that entered the general prize-winning opening 31 calculated in step S1408 and the number of balls that entered the general prize-winning opening 31 calculated in step S1409 is defined as the number of balls that entered, K22; and the difference between the number of balls that entered the special electric prize-winning device 32 calculated in step S1408 and the step... The difference in the number of balls that enter the special electric prize device 32 calculated in step S1409 is defined as the number of balls entered K23, the difference in the number of balls that enter the first operating port 33 calculated in step S1408 and the number of balls that enter the first operating port 33 calculated in step S1409 is defined as the number of balls entered K24, and the difference in the number of balls that enter the second operating port 34 calculated in step S1409 and the number of balls that enter the second operating port 34 calculated in step S1408 is defined as the number of balls entered K25. • Parameter 21: Total number of game balls dispensed (K22 × "Number of prize balls for entry into general prize slot 31" + K23 × "Number of prize balls for entry into special electric prize device 32" + K24 × "Number of prize balls for entry into first operation slot 33" + K25 × "Number of prize balls for entry into second operation slot 34") / Ratio of the total number of game balls discharged from the game area PA (K21 + K22 + K23 + K24 + K25) (Hereafter, this ratio will be referred to as "D11") • Parameter 22: The ratio of the total number of game balls entered into the general prize slot 31 (K22) to the total number of game balls discharged from the game area PA (K21 + K22 + K23 + K24 + K25). • Parameter 23: The ratio of the total number of game balls entered into the special prize-winning device 32 (K23) to the total number of game balls discharged from the game area PA (K21 + K22 + K23 + K24 + K25). • Parameter 24: The ratio of the total number of game balls entered into the first operating port 33 (K24) to the total number of game balls discharged from the game area PA (K21 + K22 + K23 + K24 + K25) (hereinafter, this ratio will be referred to as "D22"). • Parameter 25: The ratio of the total number of game balls entered into the second operating port 34 (K25) to the total number of game balls discharged from the game area PA (K21 + K22 + K23 + K24 + K25) (hereinafter, this ratio will be referred to as "D23"). • Parameter 26: D21 - (D22 × "Number of prize balls awarded for winning in the first operating slot 33" + D23 × "Number of prize balls awarded for winning in the second operating slot 34") In step S1410, the calculation results of the 21st to 26th parameters are stored in the high-frequency support mode storage area of ​​the calculation result memory 131. The 21st to 26th parameters stored in the high-frequency support mode storage area are retained until the next step S1410 is executed. In other words, when the next step S1410 is executed and the 21st to 26th parameters are calculated, the newly calculated 21st to 26th parameters are stored in the high-frequency support mode storage area, overwriting the previous calculation results of the 21st to 26th parameters that were previously stored in the high-frequency support mode storage area.

[0334] Subsequently, the frequency of the opening / closing execution mode is calculated and stored (step S1411). Specifically, the number of times the opening / closing execution mode occurs is calculated by counting the number of history information storage areas 125 in the history area 124 of the history memory 117, where correspondence information indicating that the opening / closing execution mode is in operation and start information are stored. The number of times a game round occurs is calculated by counting the number of history information storage areas 125 in the history area 124 of the history memory 117, where correspondence information indicating that a game round has started is stored. Then, the number of times the opening / closing execution mode occurs per unit game round is calculated. The number of times the opening / closing execution mode occurs is denoted as the occurrence count K31, and the number of times a game round occurs is denoted as the occurrence count K32. • Parameter 31: K31 / K32 In step S1411, the calculation result of the 31st parameter is stored in the opening / closing execution mode frequency storage area in the calculation result memory 131. The 31st parameter stored in the opening / closing execution mode frequency storage area is retained until the next step S1411 is executed. In other words, when the next step S1411 is executed and the 31st parameter is calculated, the newly calculated 31st parameter is stored in the opening / closing execution mode frequency storage area, overwriting the previous calculation result of the 31st parameter that was stored in the opening / closing execution mode frequency storage area.

[0335] Subsequently, the frequency of occurrence of the high-frequency support mode is calculated and stored (step S1412). Specifically, the number of times the high-frequency support mode occurs is calculated by counting the number of history information storage areas 125 in the history area 124 of the history memory 117, where correspondence information and start information indicating that it is the high-frequency support mode are stored. The number of times a game round occurs is calculated by counting the number of history information storage areas 125 in the history area 124 of the history memory 117, where correspondence information indicating that it is the start of a game round is stored. Then, the number of times the high-frequency support mode occurs per unit game round, and the ratio of the number of times the high-frequency support mode occurs to the number of times the open / close execution mode occurs are calculated. The number of times the high-frequency support mode occurs is denoted as occurrence count K41, the number of times a game round occurs as occurrence count K42, and the number of times the open / close execution mode occurs calculated in step S1411 as occurrence count K43. • Parameter 41: K41 / K42 • Parameter 42: K41 / K43 In step S1412, the calculation results of the 41st and 42nd parameters are stored in the high-frequency support mode frequency storage area in the calculation result memory 131. The 41st and 42nd parameters stored in the high-frequency support mode frequency storage area are retained until the next step S1412 is executed. In other words, when the next step S1412 is executed and the 41st and 42nd parameters are calculated, the newly calculated 41st and 42nd parameters are stored in the high-frequency support mode frequency storage area, overwriting the previous calculation results of the 41st and 42nd parameters that were previously stored in the high-frequency support mode frequency storage area.

[0336] If a negative result is obtained in step S1401, or if the process in step S1412 is executed, the display process is executed (step S1413). Figure 31 is a flowchart of the display process.

[0337] First, the value of the update timing counter in the management RAM 114 is decremented by 1 (step S1501). The update timing counter is a counter used by the management CPU 112 to identify that it is time to update the display content of the game history management results on the first to third notification display devices 69a to 69c. The management CPU 112 controls the display on the first to third notification display devices 69a to 69c to announce the calculation results of the first to eighth parameters, the eleventh to eighteenth parameters, the twenty-first to twenty-sixth parameters, the thirtieth parameter, and the fortieth to fortieth parameters. In this case, the first notification display device 69a displays information corresponding to the type of parameter to be announced. In addition, of the value obtained by multiplying the parameter to be announced by 100, the digit corresponding to the tens place is displayed on the second notification display device 69b, and the digit corresponding to the ones place is displayed on the third notification display device 69c. In the first to third notification display devices 69a to 69c, the displays corresponding to the calculation results of the first to eighth parameters, the eleventh to eighteenth parameters, the twenty-first to twenty-sixth parameters, the thirty-first parameter, and the forty-first to forty-two parameters are switched sequentially according to a predetermined order. After the calculation result of the forty-second parameter, which is the last item to be displayed, is shown, the calculation result of the first parameter, which is the first item to be displayed, is shown. In this case, the period during which the calculation result of one parameter is continuously displayed is two seconds.

[0338] Here, the calculation cycle for the various parameters in the management CPU 112 is 51 seconds. In contrast, there are 25 parameters, and the period during which the calculation result of one parameter is continuously displayed is 2 seconds. Therefore, the various parameters calculated by the management CPU 112 will be displayed at least once on the first to third notification display devices 69a to 69c.

[0339] If the process in step S1501 is executed, it is determined whether it is time to update the display content of the first to third notification display devices 69a to 69c by checking whether the value of the update timing counter after subtracting 1 is "0" (step S1502). If the result in step S1502 is positive, the value of the display target counter in the management RAM 114 is incremented by 1 (step S1503). If the value of the display target counter after incrementing by 1 exceeds the maximum value of "24" (step S1504: YES), the value of the display target counter is cleared to "0" (step S1505).

[0340] The display target counter is a counter used by the management CPU 112 to identify the type of parameter being displayed in the first to third notification display devices 69a to 69c. There is a one-to-one correspondence between the first to eighth parameters, the eleventh to eighteenth parameters, the twenty-twoth parameters, the thirty-first parameter, and the possible values ​​of the display target counter from "0" to "24". For example, if the value of the display target counter is "0", the first parameter, which is the first to be displayed, becomes the parameter to be displayed in the first to third notification display devices 69a to 69c. If the value of the display target counter is "24", the forty-second parameter, which is the last to be displayed, becomes the parameter to be displayed in the first to third notification display devices 69a to 69c.

[0341] If a negative determination is made in step S1504, or if the process in step S1505 is executed, the display control of the first notification display device 69a is performed so that information corresponding to the type of parameter corresponding to the value of the target counter is displayed (step S1506). In addition, the parameter corresponding to the value of the target counter is read from the calculation result memory 131, and the read parameter is multiplied by 100 so that the digit corresponding to the tens place is displayed on the second notification display device 69b and the digit corresponding to the units place is displayed on the third notification display device 69c (step S1507). The contents displayed on the first to third notification display devices 69a to 69c in steps S1506 and S1507 are retained until the next update timing or until the supply of operating power to the management CPU 112 is stopped. After that, the update timing counter in the management RAM 114 is set to a value corresponding to 2 seconds as the value corresponding to the next update timing (step S1508).

[0342] As described above, once the display processing is executed and power is supplied to the management CPU 112, the game history management results are displayed on the first to third notification display devices 69a to 69c. This display of the game history management results is performed regardless of whether the game is continuing or not, and regardless of whether the game machine body 12 is opened from the outer frame 11 and the main control device 60 is visible from the front of the pachinko machine 10. By performing the display control of the first to third notification display devices 69a to 69c regardless of the game status or the state of the pachinko machine 10 in this way, it is possible to simplify the processing configuration for controlling the display of the first to third notification display devices 69a to 69c.

[0343] The display of the game history management results in the first to third notification display devices 69a to 69c begins after the supply of operating power to the management CPU 112 has started and after the identification termination command has been received from the main CPU 63. In this case, the information stored in the calculation result memory 131 is retained even when the supply of operating power to the pachinko machine 10 is stopped, just like the information stored in the history memory 117. Therefore, when the supply of operating power to the management CPU 112 is started, the game history management results calculated before the supply of operating power to the management CPU 112 was stopped are displayed.

[0344] When the setting state of the pachinko machine 10 is set when power is supplied to the main CPU 63, information corresponding to the setting value being changed is displayed on the third notification display device 69c. However, the display of this information corresponding to the setting value is performed before the identification end command is sent from the main CPU 63, whereas the display of the game history management results on the first to third notification display devices 69a to 69c starts after the identification end command is sent from the main CPU 63. This makes it possible to prevent the display periods of these displays from overlapping, even if the third notification display device 69c is used as both a display device for displaying information corresponding to the setting value and a display for displaying the game history management results.

[0345] Furthermore, when information corresponding to the set value is displayed, the first notification display device 69a and the second notification display device 69b are hidden. Conversely, when the results of game history management are displayed, the first notification display device 69a and the second notification display device 69b are not hidden. This makes it possible to distinguish whether the third notification display device 69c is displaying information corresponding to the set value or the results of game history management.

[0346] Next, we will describe a processing configuration for outputting history information stored in the history memory 117 and various parameters stored in the calculation result memory 131 to an external device electrically connected to the read terminal 68d of the MPU 62. Figure 32(a) is a flowchart showing the data output processing executed by the main CPU 63. The data output processing is executed in step S112 of the main processing (Figure 9).

[0347] In the data ou...

Claims

[Claim 1] A history storage execution means that stores in a history storage means the history information of a game corresponding to a predetermined event that occurs as a result of the execution of a game, Information deriving means for deriving behavioral information corresponding to the result of the game using the history information stored in the history storage means, A configuration information storage means for storing the configuration information derived by the information derivation means, A manner information display control means that controls the display of manner information corresponding to the manner information stored in the manner information storage means to be displayed by the information display means, A predetermined corresponding display control means that controls the information display means to ensure that a predetermined corresponding display is performed before a new display corresponding to the aspect information is initiated, based on the occurrence of a predetermined display trigger. A setting means for setting a value corresponding to the player's advantage, A condition generating means that creates a condition in which the setting value can be set by the setting means, Equipped with, The aforementioned aspect information storage means includes a plurality of specific storage areas that enable the storage of each of the plurality of aspect information, The aspect information display control means controls the information display means to sequentially execute displays corresponding to each of the multiple aspect information stored in the multiple specific storage areas according to a predetermined display order, and when the information display means is to be made to perform a display corresponding to the aspect information after the predetermined corresponding display has been performed, it starts with the display corresponding to the aspect information corresponding to the first order in the predetermined display order. The information derivation means derives the aspect information using the historical information during a predetermined advantageous period. This gaming machine is equipped with control means for performing various processes, The control means is An in-area processing execution means that executes in-area processing, which is processing that uses a program stored in a predetermined address range storage area of ​​a program storage means, An out-of-bounds processing execution means for executing out-of-bounds processing, which is processing that utilizes a program stored in a storage area of ​​an address range outside the predetermined address range of the program storage means, Equipped with, This gaming machine is When processing within the aforementioned region is performed, information can be written to and read from the corresponding storage area within the region, while when processing outside the aforementioned region is performed, information can be read but information cannot be written to the corresponding storage area within the region. When the aforementioned out-of-area processing is performed, information can be written to and read from the out-of-area corresponding storage area, while when the aforementioned in-area processing is performed, information can be read but information cannot be written to the out-of-area corresponding storage area, Equipped with, The gaming machine is characterized in that the domain-based processing execution means includes means capable of executing as domain-based processing a process that can determine whether or not the setting value set as the target for use is normal.

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