Semiconductor optical array

Abstract

To provide a semiconductor optical element array superior in optical characteristics.SOLUTION: A semiconductor optical element array 10 comprises a semiconductor substrate 1, a mask layer 2 arranged on a main surface of the semiconductor substrate and having an opening, a nano-column 3 extending in a thickness direction through the opening from the semiconductor substrate and serving as a column crystal of a group III nitride semiconductor, a luminescent layer 4 arranged at a tip end of the nano-column, and a coating semiconductor layer 5 coating the luminescent layer and including a semiconductor. The semiconductor optical element array has a pixel including a plurality of nano-columns, and, in the pixel, a size of the nano-column increases gradually or continuously or decreases gradually or continuously from a center to a circumference.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] This disclosure relates to semiconductor optical arrays. [Background technology]

[0002] In recent years, group III nitride semiconductors such as gallium nitride (GaN) have attracted attention as useful semiconductor materials for light-emitting diodes such as light-emitting diodes and laser diodes. Light-emitting diodes are fabricated by forming a layered structure of group III nitride semiconductors on a substrate using crystal growth techniques such as metal-organic chemical vapor deposition (MOCVD) and molecular beam epitaxy (MBE).

[0003] For example, Patent Document 1 discloses a semiconductor optical array comprising fine columnar crystals containing a group III nitride semiconductor grown from a semiconductor substrate through openings arranged in a mask pattern. One objective of this technology is to control the position and shape of the fine columnar crystals formed on the substrate with high precision. [Prior art documents] [Patent Documents]

[0004] [Patent Document 1] International Publication No. 2010 / 023921 [Overview of the Initiative] [Problems that the invention aims to solve]

[0005] Semiconductor optical arrays are used, for example, in light-emitting devices. From the viewpoint of improving the performance of light-emitting devices, there is a desire to improve the optical properties of semiconductor optical arrays. This disclosure has been made in view of the above circumstances, and its main objective is to provide a semiconductor optical array having good optical properties. [Means for solving the problem]

[0006] This disclosure provides a semiconductor optical array comprising: a semiconductor substrate; a mask layer disposed on the main surface of the semiconductor substrate and having an opening; nanocolumns extending in the thickness direction from the semiconductor substrate through the opening and being columnar crystals of a group III nitride semiconductor; an emissive layer disposed at the tip of the nanocolumns; and a covering semiconductor layer covering the emissive layer and containing a semiconductor, wherein the semiconductor optical array has a plurality of pixels comprising the nanocolumns, and in the pixels, the size of the nanocolumns increases stepwise or continuously from the center to the outer edge, or decreases stepwise or continuously. [Effects of the Invention]

[0007] The semiconductor optical array in this disclosure has the effect of having good optical properties. [Brief explanation of the drawing]

[0008] [Figure 1] This is a schematic cross-sectional view illustrating a semiconductor optical array in this disclosure. [Figure 2] This is a schematic plan view illustrating the mask layer and nanocolumn in this disclosure. [Figure 3] This is a schematic plan view illustrating the pixels in this disclosure. [Figure 4] This is a schematic plan view illustrating the pixels in this disclosure. [Figure 5] This is an explanatory diagram illustrating the pixels in this disclosure. [Figure 6] This is an explanatory diagram illustrating the pixels in this disclosure. [Figure 7] This is a schematic cross-sectional view illustrating a nanocolumn in this disclosure. [Figure 8] This is a schematic plan view illustrating the pixels in this disclosure. [Figure 9] This is a schematic perspective view illustrating a semiconductor optical element array in this disclosure. [Figure 10] This is a schematic perspective view illustrating the method for manufacturing a semiconductor optical array in this disclosure. [Figure 11] It is an explanatory diagram for explaining the pixels used in Comparative Example 1 and Examples 1 and 2. [Figure 12] It is the emission spectrum of the pixels obtained in Comparative Example 1 and Examples 1 and 2. [Figure 13] It is an explanatory diagram for explaining the pixels used in Comparative Example 2 and Examples 3 and 4. [Figure 14] It is the emission spectrum of the pixels obtained in Comparative Example 2 and Examples 3 and 4.

Mode for Carrying Out the Invention

[0009] Hereinafter, the semiconductor optical element array in the present disclosure will be described in detail. In each of the following figures, for ease of understanding, the sizes and shapes of each part are exaggerated as appropriate. Further, in each figure, for convenience, hatching or reference signs may be omitted. Also, in the present disclosure, "another member is disposed on the surface (main surface) of one member" includes both a case where another member is disposed so as to contact the surface (main surface) of one member and a case where another member is disposed above the surface (main surface) of one member via another member.

[0010] FIG. 1 is a schematic cross-sectional view illustrating a semiconductor optical element array in the present disclosure. The semiconductor optical element array 10 shown in FIG. 1 includes a semiconductor substrate 1, a mask layer 2, a nanocolumn 3, a light-emitting layer 4, and a covering semiconductor layer 5. The semiconductor substrate 1 includes a base substrate 1a and a semiconductor layer 1b. The mask layer 2 is disposed on the main surface m of the semiconductor substrate 1 (semiconductor layer 1b) and has an opening 2x. The nanocolumn 3 extends in the thickness direction D , <o000001>,

[0011] , from the semiconductor substrate 1 (semiconductor layer 1b) through the opening 2x of the mask layer 2 and is a columnar crystal of a group III nitride semiconductor. The light-emitting layer 4 is disposed at the tip of the nanocolumn 3. The covering semiconductor layer 5 covers at least a part of the light-emitting layer 4 and contains a semiconductor.

[0011] FIG. 2 is a schematic plan view illustrating a mask layer and nanocolumns in the present disclosure. As shown in FIG. 2(a), the mask layer 2 has patterned openings 2x. Through the openings 2x, a crystal of a group-III nitride semiconductor is epitaxially grown. Thereby, nanocolumns 3 as shown in FIGS. 1 and 2(b) are obtained.

[0012] The semiconductor optical element array in the present disclosure has pixels including a plurality of nanocolumns. Specifically, one pixel is constituted by arranging a plurality of nanocolumns in a pattern. Usually, the above-described light-emitting layer and covering semiconductor layer are disposed in each nanocolumn. FIGS. 3 and 4 are schematic plan views respectively illustrating pixels in the present disclosure. As shown in FIGS. 3 and 4, the pixel P includes a plurality of nanocolumns 3. In the pixel P shown in FIG. 3, the size of the nanocolumn 3 continuously increases from the center C toward the outer periphery X. On the other hand, in the pixel P shown in FIG. 4, the size of the nanocolumn 3 continuously decreases from the center C toward the outer periphery X.

[0013] According to the present disclosure, in a pixel including a plurality of nanocolumns, by increasing or decreasing the size of the nanocolumns stepwise or continuously from the center toward the outer periphery, a semiconductor optical element array having good optical characteristics is obtained. Here, as described in Patent Document 1, the light-emitting characteristics of the light emitted from the light-emitting layer change depending on the size of the nanocolumns. Specifically, the peak wavelength of the light emitted from the light-emitting layer shifts to the longer wavelength side as the size of the nanocolumns increases, and shifts to the shorter wavelength side as the size of the nanocolumns decreases.

[0014] Therefore, it is expected that pixels containing multiple nanocolumns of non-uniform size will have inferior monochromaticity compared to pixels containing multiple nanocolumns of uniform size. However, when the size of the nanocolumns was varied from the center of the pixel towards the outer edge, no decrease in monochromaticity was observed, at least near the center of the pixel. Even more surprisingly, when the size of the nanocolumns was varied from the center of the pixel towards the outer edge, an improvement in luminescence intensity was observed, at least near the center of the pixel. The reason for this is not entirely clear, but it is presumed that the nanocolumns positioned near the outer edge of the pixel acted like lenses or reflectors, improving the efficiency of light extraction near the center of the pixel.

[0015] 1. Pixel In this disclosure, each pixel includes multiple nanocolumns. Details of the nanocolumns are described below in "2. Nanocolumns". In this disclosure, the size of the nanocolumns increases or decreases in a stepwise or continuous manner from the center of the pixel towards the outer edge.

[0016] In this disclosure, the center of a pixel refers to the centroid of the planar shape of the pixel when viewed in a plan view along the thickness direction. On the other hand, the outer perimeter of a pixel refers to the outer perimeter of the planar shape of the pixel when viewed in a plan view along the thickness direction. Furthermore, "size of the nanocolumn" refers to the size of the columnar portion of the nanocolumn (the columnar portion 3a exemplified in Figure 7, described later). The size of the columnar portion refers to the length of the line that passes through the centroid (center) of the planar shape of the columnar portion when viewed in a plan view along the thickness direction, and intersects the columnar portion at two points, with the longest distance between the intersection points.

[0017] The size of the nanocolumn at the center of a pixel is, for example, between 10 nm and 1000 nm. "Nanocolumn at the center of a pixel" refers to the nanocolumn at the center of the pixel when viewed in a planar view along the thickness direction, if one exists at the center of the pixel; if no nanocolumn exists at the center of the pixel, it refers to the nanocolumn closest to the center of the pixel. The size of the nanocolumn may be, for example, 700 nm or less, 650 nm or less, or 600 nm or less. Making the nanocolumn size 700 nm or less makes it easier to suppress the generation of threading dislocations.

[0018] In this disclosure, the size of the nanocolumns may increase in steps or continuously from the center of the pixel towards the outer edge. This case will be explained using Figure 5. In the pixel P shown in Figure 5(a), the size of the nanocolumns 3 increases continuously from the center C towards the outer edge X. Also, in the pixel P shown in Figure 5(a), the size of the nanocolumns 3 changes concentrically from the center C towards the outer edge X. As shown in Figure 5(b), the size of the nanocolumns may increase linearly from the center C towards the outer edge X. On the other hand, although not shown in particular, the size of the nanocolumns may increase curvilinearly (for example, in a quadratic function) from the center C towards the outer edge X.

[0019] Figure 5(c) shows nanocolumns 3 near the center of a pixel, and Figure 5(d) shows nanocolumns 3 near the outer edge of a pixel. Let S1 be the size of the nanocolumns at the center of the pixel, and S2 be the size of the nanocolumns at the outer edge of the pixel. The "nanocolumns at the center of the pixel" are as described above. On the other hand, "nanocolumns at the outer edge of a pixel" refers to the nanocolumns that constitute the outer edge of a pixel when the pixel is viewed in a planar view along the thickness direction.

[0020] S1 is, for example, 10 nm or more, may be 20 nm or more, or 30 nm or more. On the other hand, S1 is, for example, 300 nm or less, may be 200 nm or less, or 100 nm or less. Also, S2 is not particularly limited as long as it is greater than S1, but for example, 20 nm or more, may be 50 nm or more, or 100 nm or more. On the other hand, S2 is, for example, 1000 nm or less, may be 500 nm or less, or 300 nm or less. Furthermore, the ratio of S2 to S1 (S2 / S1) may be, for example, 1.5 or more, 6.0 or less, or 2.0 or more, or 4.0 or less.

[0021] Furthermore, in this disclosure, the size of the nanocolumns may increase in steps from the center of the pixel towards the outer edge of the pixel. In this case, the size of the nanocolumns may increase in two or more steps, five or more steps, or ten or more steps from the center of the pixel towards the outer edge of the pixel.

[0022] On the other hand, in this disclosure, the size of the nanocolumns may decrease in steps or continuously from the center of the pixel towards the outer edge. This case will be explained using Figure 6. In the pixel P shown in Figure 6(a), the size of the nanocolumns 3 decreases continuously from the center C towards the outer edge X. Also, in the pixel P shown in Figure 6(a), the size of the nanocolumns 3 changes concentrically from the center C towards the outer edge X. As shown in Figure 6(b), the size of the nanocolumns may decrease linearly from the center C towards the outer edge X. On the other hand, although not shown in particular, the size of the nanocolumns may decrease curvilinearly (for example, in a quadratic function) from the center C towards the outer edge X.

[0023] Figure 6(c) shows nanocolumn 3 near the center of the pixel, and Figure 6(d) shows nanocolumn 3 near the outer edge of the pixel. Let S3 be the size of the nanocolumn at the center of the pixel, and S4 be the size of the nanocolumn at the outer edge of the pixel. The "nanocolumn at the center of the pixel" and the "nanocolumn at the outer edge of the pixel" are as described above.

[0024] S3 is, for example, 100 nm or more, may be 150 nm or more, or 200 nm or more. On the other hand, S3 is, for example, 1000 nm or less, may be 500 nm or less, or 400 nm or less. Also, S4 is not particularly limited as long as it is smaller than S3, but for example, 10 nm or more, may be 100 nm or more, or 150 nm or more. On the other hand, S4 is, for example, 300 nm or less, or 250 nm or less. Furthermore, the ratio of S4 to S3 (S4 / S3) may be, for example, 0.4 or more, 0.8 or less, or 0.45 or more, or 0.6 or less.

[0025] Furthermore, in this disclosure, the size of the nanocolumns may decrease in steps from the center of the pixel towards the outer edge of the pixel. In this case, the size of the nanocolumns may decrease in two or more steps, five or more steps, or ten or more steps from the center of the pixel towards the outer edge of the pixel.

[0026] In the direction from the center of a pixel toward the outer edge of the pixel, the difference in size between adjacent nanocolumns may be, for example, 5 nm or less, 3 nm or less, or 1 nm or less. If the distance from the center of the pixel toward the outer edge of the pixel is L, the difference in size between adjacent nanocolumns in the region from the center of the pixel to 1 / 2 L may all be within the above range. Similarly, the difference in size between adjacent nanocolumns in the region from the center of the pixel to 3 / 4 L may all be within the above range. Note that if the size of the nanocolumns changes continuously from the center of the pixel toward the outer edge of the pixel, the difference in size between adjacent nanocolumns is usually greater than 0.

[0027] The arrangement of nanocolumns is not particularly limited, but may be arranged in a triangular lattice or a square lattice. In Figure 2 above, the openings 2x of the mask layer 2 are arranged in a triangular lattice, and the nanocolumns 3 growing from the openings 2x are also arranged in a triangular lattice. Also, as shown in Figure 5(c), the distance between the centers of adjacent nanocolumns is called the pitch. The pitch may be, for example, 200 nm or more, or 300 nm or more. On the other hand, the pitch may be, for example, 600 nm or less, or 500 nm or less. Also, adjacent nanocolumns are usually arranged so that they do not come into contact with each other. The gap between adjacent nanocolumns is preferably, for example, 1 nm or more. The pitch of nanocolumns in a pixel may be the same or different. The pitch is the same if the difference between the maximum and minimum pitch of the nanocolumns in the pixel is 5 nm or less. On the other hand, the pitch is different if the difference between the maximum and minimum pitch of the nanocolumns in the pixel is greater than 5 nm.

[0028] The planar shape of a pixel in this disclosure is not particularly limited, but examples include polygons such as triangular, quadrilateral (e.g., square, rectangular, rhombus), and hexagonal shapes. The size of a pixel is, for example, 10 μm or more, and may be 50 μm or more. On the other hand, the size of a pixel is, for example, 500 μm or less, and may be 100 μm or less. In this disclosure, "size of a pixel" means the length of the straight line that passes through the centroid (center) of the planar shape of the pixel when viewed in plan along the thickness direction, and intersects the pixel at two points, with the longest distance between the intersection points.

[0029] 2. Nanocolumn The nanocolumns in this disclosure extend in the thickness direction from the semiconductor substrate through openings in the mask layer and are columnar crystals of a group III nitride semiconductor. The nanocolumns may also be composed of single crystals of a group III nitride semiconductor. It is preferable that the nanocolumns have few crystal defects.

[0030] Group III nitride semiconductors contain Group III elements and N elements. A typical example of a Group III nitride semiconductor is gallium nitride (GaN). Another example of a Group III nitride semiconductor is Al, which has the general formula: x Ga y In 1-x-y Examples of materials are those represented by N(0≦x≦1, 0≦y≦1, 0≦x+y≦1). x may be greater than 0. x may be less than 1. y may be greater than 0. y may be less than 1. x+y may be greater than 0 and less than 1. The group III nitride semiconductor represented by the above general formula preferably has a band gap of 0.63 eV or more and 6.2 eV or less at room temperature. Another example of a group III nitride semiconductor is boron nitride. Furthermore, from the viewpoint of manufacturing stability, the group III nitride semiconductor is preferably a material with a hexagonal crystal structure.

[0031] A nanocolumn may have a columnar portion and a faceted structure portion located on the tip side of the columnar portion (opposite the semiconductor substrate). The faceted structure portion refers to a polyhedral structure whose sides are faceted surfaces located diagonally with respect to the direction perpendicular to the thickness direction. The shape of the columnar portion is not particularly limited, but examples include a cylindrical shape, a rectangular prism shape, and a hexagonal prism shape.

[0032] For example, when a group III nitride semiconductor with a wurtzite crystal structure is grown in the direction of the c-plane (= (0001) plane, polar plane) to form nanocolumns, the planar shape of the nanocolumns is hexagonal, as shown in Figure 2(b). Figures 7(a) and (b) are schematic cross-sectional views showing the cross-section when a nanocolumn is cut along its central axis. Both nanocolumns 3 shown in Figures 7(a) and (b) have a columnar portion 3a and a faceted structure portion 3b located on the tip side of the columnar portion 3a (opposite the semiconductor substrate).

[0033] The faceted structure 3b shown in Figure 7(a) has facet surfaces 31 (semipolar surfaces of the wurtzite crystal structure) and its shape is a hexagonal pyramidal shape. Examples of semipolar surfaces include the (10-1-1) plane, (10-1-3) plane, (11-22) plane, (11-24) plane, and (10-12) plane. On the other hand, the faceted structure 3b shown in Figure 7(b) has facet surfaces 31 (semipolar surfaces of the wurtzite crystal structure) and further has a flat surface 32 (polar surface of the wurtzite crystal structure) parallel to the direction perpendicular to the thickness direction. Depending on the crystal growth conditions, for example, the faceted structure shown in Figure 7(a) or Figure 7(b) may be formed.

[0034] When the nanocolumn size is small, a faceted structure with a hexagonal pyramidal shape, as shown in Figure 7(a), is easily formed, while when the nanocolumn size is large, a faceted structure like that shown in Figure 7(b) is easily formed. Depending on the crystal growth conditions, when the nanocolumn size is about 300 nm or larger, flat surfaces (polar surfaces) like those shown in Figure 7(b) are more likely to appear. Furthermore, as the nanocolumn size increases beyond about 300 nm, the area of ​​the flat surfaces (polar surfaces) tends to increase.

[0035] The height of the nanocolumn is not particularly limited, but may be, for example, 200 nm or more, and may also be 500 nm or more. On the other hand, the height of the nanocolumn may be, for example, 5 μm or less. The height of the nanocolumn refers to the distance (distance in the thickness direction) from the surface of the mask layer 2 opposite to the semiconductor substrate to the tip of the nanocolumn.

[0036] 3. Emitting layer In this disclosure, the light-emitting layer is positioned at the tip of the nanocolumn. That is, the light-emitting layer is positioned on the side opposite to the semiconductor substrate. Preferably, the light-emitting layer is provided so as to cover the facet structure of the nanocolumn.

[0037] The light-emitting layer preferably has a multiple quantum well (MQW) structure or a single quantum well (SQW) structure. The quantum well structure refers to a structure including a quantum well layer and a barrier layer sandwiching the quantum well layer. The bandgap of the barrier layer is usually larger than that of the quantum well layer. Examples of the light-emitting layer include InGaN, GaN, AlGaN, AlInGaN, InGaAsN, and InN. More specifically, the light-emitting layer is, for example, InGaN / GaN (barrier layer: InGaN, well layer: GaN), In x Ga 1-x N / In y Ga 1-y N (0 ≤ x ≤ 1, 0 ≤ y ≤ 1), GaN / AlGaN (barrier layer: AlGaN, well layer: GaN), and Al x Ga 1-x N / Al y Ga 1-y N (0 ≤ x ≤ 1, 0 ≤ y ≤ 1).

[0038] The peak wavelength of the light emitted from the light-emitting layer depends on the size of the nanocolumn immediately before the light-emitting layer is formed. Specifically, the peak wavelength of the light emitted from the light-emitting layer shifts toward the longer wavelength side as the size of the nanocolumn increases, and shifts toward the shorter wavelength side as the size of the nanocolumn decreases. That is, the peak wavelength of the light emitted from the light-emitting layer can be controlled based on the size of the nanocolumn. The size of the nanocolumn can be controlled based on the size of the opening in the mask layer.

[0039] The peak wavelength of the light emitted from the light-emitting layer depends on the surface area of the facet structure portion of the nanocolumn. Specifically, the peak wavelength of the light emitted from the light-emitting layer shifts toward the longer wavelength side as the surface area of the facet structure portion increases, and shifts toward the shorter wavelength side as the surface area of the facet structure portion decreases. That is, the peak wavelength of the light emitted from the light-emitting layer can be controlled based on the surface area of the facet structure portion of the nanocolumn.

[0040] 4. Coating semiconductor layer The coated semiconductor layer in this disclosure is a layer that covers the light-emitting layer and contains a semiconductor. The coated semiconductor layer preferably contains a semiconductor crystal, and more preferably contains a group III nitride semiconductor crystal. The coated semiconductor layer may be composed of a single crystal of a group III nitride semiconductor. It is preferable that the coated semiconductor layer has few crystal defects. The group III nitride semiconductor is the same as described in "2. Nano Column" above, so the description is omitted here.

[0041] The coated semiconductor layer 5 only needs to cover at least a portion of the light-emitting layer 4. In particular, it is preferable that the coated semiconductor layer 5 covers the light-emitting layer 4 so as to encompass the entire circumference of the light-emitting layer 4 in a plan view along the thickness direction, because better optical properties can be obtained. Alternatively, as shown in Figure 1, the coated semiconductor layer 5 may completely cover the light-emitting layer 4. That is, the coated semiconductor layer 5 may cover the light-emitting layer 4 so that the light-emitting layer 4 has no exposed portion to the external space. By suppressing the formation of non-luminescent recombination levels caused by exposed portions, a high internal quantum efficiency can be achieved.

[0042] Furthermore, the conductivity type of the nanocolumn and the conductivity type of the coating semiconductor layer are usually inversely related. When the conductivity type of the nanocolumn is n-type, the conductivity type of the coating semiconductor layer is usually p-type. In this case, the light-emitting layer emits light when electrons supplied from the nanocolumn combine with holes supplied from the coating semiconductor layer. On the other hand, when the conductivity type of the nanocolumn is p-type, the conductivity type of the coating semiconductor layer is usually n-type.

[0043] 5. Semiconductor substrates The semiconductor substrate in this disclosure supports nanocolumns. The semiconductor substrate also has, for example, a base substrate and a semiconductor layer. Examples of base substrates include sapphire substrates, silicon substrates, and SiC substrates.

[0044] The semiconductor layer preferably contains a group III nitride semiconductor as the semiconductor. The semiconductor layer may be composed of a single crystal of the group III nitride semiconductor. It is preferable that the semiconductor layer has few crystal defects. The group III nitride semiconductor is the same as described in "2. Nanocolumn" above. The group III nitride semiconductor in the semiconductor layer and the group III nitride semiconductor in the nanocolumn may have the same composition.

[0045] As shown in Figure 1, the semiconductor layer 1b has a thickness direction D T In a plan view along the line, the mask layer 2 may have a recess 1x at a position that at least overlaps with the opening 2x. The depth of the recess 1x is not particularly limited, but for example, it is between 1 nm and 250 nm.

[0046] A buffer layer may be placed between the underlying substrate and the semiconductor layer. Providing a buffer layer improves the crystal quality of the semiconductor layer (e.g., the flatness of the layer surface). Examples of buffer layers include group III nitride semiconductors such as gallium nitride and aluminum nitride. Furthermore, the semiconductor substrate does not necessarily have an underlying substrate. That is, the semiconductor substrate may be a self-supporting semiconductor layer (e.g., a GaN substrate).

[0047] 6. Mask layer The mask layer in this disclosure has openings. Examples of plan view shapes of the openings include square, circular, and polygonal shapes. The plan view shape of the openings is preferably axially symmetric. The density of the nanocolumns can be controlled by adjusting the pattern of the openings. Similarly, the size of the nanocolumns can be controlled by adjusting the size of the openings. The pattern and size of the openings are adjusted to obtain the nanocolumns described above.

[0048] The mask layer is preferably a metal mask layer containing a metal. Examples of metal elements to be included in the metal mask layer include titanium (Ti), tantalum (Ta), iron (Fe), nickel (Ni), platinum (Pt), gold (Au), cobalt (Co), tungsten (W), and molybdenum (Mo). The metal mask layer may contain only one metal element or two or more metal elements. The metal mask layer preferably contains at least Ti. The metal mask layer may be a layer having an oxide on its surface, or it may be a metal oxide layer. The thickness of the mask layer is not particularly limited, but for example, it is 2 nm to 100 nm.

[0049] 7. Semiconductor optical array In the semiconductor optical array of this disclosure, the entire pixel may be an emission region, or only a part of the pixel may be an emission region. For example, in the pixel P shown in Figure 8, a part is an emission region α. ​​The emission region α preferably includes the center C of the pixel P. In addition, the planar shape of the emission region may be, for example, a square, a circle, or a polygon. The planar shape of the emission region may be axially symmetric. Furthermore, the planar shape of the emission region may be similar to that of the pixel, or it may not be similar.

[0050] The size of the light-emitting region may be, for example, 5 μm or more, or 50 μm or more. On the other hand, the size of the light-emitting region may be, for example, 300 μm or less, or 100 μm or less. In this disclosure, "size of the light-emitting region" means the length of the straight line that passes through the centroid (center) of the planar shape of the light-emitting region viewed in the thickness direction, and intersects the light-emitting region at two points, with the longest distance between the intersection points.

[0051] When a portion of a pixel is a light-emitting region, the area ratio of the light-emitting region to the pixel may be, for example, 5% or more, or 10% or more. On the other hand, the above area ratio may be, for example, 80% or less, or 60% or less. As a method for forming the light-emitting region, for example, a method of adjusting the shape of the electrode electrically connected to the coating semiconductor layer can be mentioned.

[0052] The emission spectrum in the emission region may have a peak wavelength at a position between 430 nm and less than 500 nm. In this case, blue emission is obtained. The peak wavelength refers to the wavelength at which the highest emission intensity is obtained in the emission spectrum. Alternatively, the emission spectrum in the emission region may have a peak wavelength at a position between 500 nm and less than 580 nm. In this case, green emission is obtained. Alternatively, the emission spectrum in the emission region may have a peak wavelength at a position between 580 nm and less than 780 nm. In this case, red emission is obtained.

[0053] In the emission spectrum of the emission region, the number of peaks observed in the visible light region between 380 nm and 780 nm is preferably 2 or less, and more preferably 1. Furthermore, if the number of peaks observed in the visible light region between 380 nm and 780 nm is 2 or more, the highest emission intensity is preferably at least twice, and more preferably at least four times, the second highest emission intensity.

[0054] Furthermore, a light-emitting region in which the size of all nanocolumns in the light-emitting region is changed to the size of the nanocolumn at the center of the pixel is defined as a comparative light-emitting region. In this case, it is preferable that the emission intensity at the peak wavelength in the light-emitting region is greater than the emission intensity at the peak wavelength in the comparative light-emitting region.

[0055] The semiconductor optical array in this disclosure preferably has a plurality of pixels. For example, as shown in Figure 9, the semiconductor optical array preferably has a plurality of pixels (P1, P2, P3). The luminescence characteristics of the nanocolumns in this disclosure vary depending on their size. Therefore, by adjusting the size of the nanocolumns, for example, pixels P1, P2, and P3 can be made to emit light at wavelengths of the three primary colors R (red), G (green), and B (blue), respectively.

[0056] The applications of the semiconductor optical array in this disclosure are not particularly limited. Examples of applications for the semiconductor optical array include light-emitting elements such as light-emitting diodes and laser diodes.

[0057] The method for manufacturing a semiconductor optical array in this disclosure is not particularly limited. Figure 10 is a schematic perspective view illustrating a method for manufacturing a semiconductor optical array in this disclosure. In the method for manufacturing a semiconductor optical array shown in Figure 10, first, a base substrate 1a is prepared (Figure 10(a)). Next, a buffer layer (not shown) containing a group III nitride semiconductor is formed on the base substrate 1a under low temperature conditions by MOCVD or MBE, and a crystal of the group III nitride semiconductor is grown on the buffer layer under high temperature conditions to form a semiconductor layer 1b (Figure 10(b)). This gives a semiconductor substrate 1 having a base substrate 1a and a semiconductor layer 1b.

[0058] Subsequently, a mask layer 2 containing titanium (Ti) is formed on the main surface of the semiconductor layer 1b by vacuum deposition (Figure 10(c)). Next, a resist layer 6 is formed on the mask layer 2, and electron beam lithography and development are performed to form an aperture 6x (Figure 10(d)). At this time, the drawing pattern of the aperture 6x is set so that the pixels described above are obtained. Next, the mask layer 2 exposed from the aperture 6x is removed by etching to form an aperture 2x (Figure 10(e)). At this time, if not only the mask layer 2 but also the semiconductor layer 1b is etched, a recess 1x as shown in Figure 1 is formed.

[0059] Subsequently, a crystal of a group III nitride semiconductor is grown from the semiconductor layer 1b through the opening 2x using the MOCVD method or the MBE method. This forms a nanocolumn 3 (Figure 10(f)). At this time, the light-emitting layer 4 and the coating semiconductor layer 5 may be formed continuously. For example, when forming a nanocolumn using the MBE method, a source gas containing activated nitrogen generated by high-frequency plasma excitation and a group III metal is introduced onto the semiconductor layer to grow a crystal of a group III nitride semiconductor. The crystal growth temperature is, for example, 350°C or higher and 1200°C or lower. For example, when growing a GaN crystal, the crystal growth temperature is preferably 400°C or higher and 1000°C or lower. Also, when the crystal of the group III nitride semiconductor grows, it may grow in the thickness direction and simultaneously in a direction perpendicular to the thickness direction (in-plane direction). In that case, as shown in Figure 1, the size of the nanocolumn 3 is usually larger than the size of the opening 2x and the size of the recess 1x. In this way, a semiconductor optical element array 10 is obtained as shown in Figure 10(f). Subsequently, as shown in Figure 10(g), electrodes 11 may be placed on the coated semiconductor layer 5 and the mask layer 2, respectively.

[0060] This disclosure is not limited to the embodiments described above. The embodiments described above are illustrative, and any configuration that is substantially identical to the technical idea described in the claims of this disclosure and achieves similar effects is included within the technical scope of this disclosure. [Examples]

[0061] [Comparative Example 1] A GaN layer (semiconductor layer, thickness: approximately 3.5 μm) was formed on the (0001) surface of a sapphire substrate (underlying substrate) by MOCVD. Next, a titanium thin film (mask layer, thickness: approximately 5 nm) was deposited on the GaN layer by vacuum deposition. Then, a resist layer was formed on the titanium thin film, electron beam lithography was performed, and development was carried out to form a resist pattern with openings. Next, the mask layer exposed from the openings in the resist pattern was removed by etching, forming patterned openings in the mask layer. Finally, the resist pattern was peeled off.

[0062] Subsequently, using the RF MBE method, GaN columnar crystals were grown from the semiconductor substrate through openings in the mask layer under a temperature of 900°C to form nanocolumns (height: 2.5 μm). This resulted in the pixels shown in Figure 11(a) and below. • Pixel's planar shape: Hexagonal • Pixel size: 150μm • Pitch between the centers of adjacent nanocolumns: 350nm • Size of nanocolumns at the center of the pixel: 60nm • Size of nanocolumns at the outer edge of the pixel: 60nm

[0063] Next, an emissive layer having a multiple quantum well structure containing an InGaN film (thickness: 1 nm) was formed at the tip of the nanocolumn. Subsequently, a GaN crystal was grown on the emissive layer to form a coating semiconductor layer (thickness: 10 nm). This resulted in obtaining a semiconductor optical array.

[0064] Furthermore, after performing the same procedure as described above and forming nanocolumns, the nanocolumns were observed using a scanning electron microscope (SEM). The results are shown in Figures 11(b) and 11(c). As shown in Figures 11(b) and 11(c), the size of the nanocolumns at the center of the pixel and the size of the nanocolumns at the outer edge of the pixel were identical.

[0065] [Example 1] A semiconductor optical array was obtained in the same manner as in Comparative Example 1, except for the changes made to the pixel formation shown in Figure 11(d) and below. • Pixel's planar shape: Hexagonal • Pixel size (maximum length between opposite corners): 150 μm • Pitch between the centers of adjacent nanocolumns: 350nm • Size of nanocolumns at the center of the pixel: 60nm • Size of nanocolumns at the outer edge of the pixel: 100 nm

[0066] The results of SEM observation of the nanocolumns are shown in Figures 11(e) and 11(f). As shown in Figures 11(e) and 11(f), the size of the nanocolumns increased continuously from the center to the outer edge in the pixel.

[0067] [Example 2] A semiconductor optical array was obtained in the same manner as in Comparative Example 1, except that the pixels shown in Figure 11(g) and below were formed. • Pixel's planar shape: Hexagonal • Pixel size (maximum length between opposite corners): 150 μm • Pitch between the centers of adjacent nanocolumns: 350nm • Size of nanocolumns at the center of the pixel: 60nm • Size of nanocolumns at the outer edge of the pixel: 350nm

[0068] The results of SEM observation of the nanocolumns are shown in Figures 11(h) and 11(i). As shown in Figures 11(h) and 11(i), the size of the nanocolumns increased continuously from the center to the outer edge in the pixel.

[0069] [evaluation] The same procedure as in Comparative Example 1 and Examples 1 and 2 was followed to form the light-emitting layer. At this stage, the light-emitting layer was irradiated with a laser, and the light emission intensity was measured. The measurement area was a 30 μm diameter region including the center of the pixel, as indicated by the black circles in Figures 11(a), (d), and (g). The results are shown in Figure 12. As shown in Figure 12, Examples 1 and 2 showed higher light emission intensities compared to Comparative Example 1. More specifically, it was confirmed that high light emission intensity could be obtained by increasing the size of the nanocolumns around the measurement area, without increasing the size of the nanocolumns in the measurement area itself.

[0070] Furthermore, in Example 1, the size of the nanocolumns at the center of the measurement area was 50 nm, and the size of the nanocolumns at the outer periphery of the measurement area was 60 nm. Comparing the area occupied by the nanocolumns in the measurement area, Example 1 was 1.21 times larger than Comparative Example 1. In Example 2, the size of the nanocolumns at the center of the measurement area was 50 nm, and the size of the nanocolumns at the outer periphery of the measurement area was 100 nm. Comparing the area occupied by the nanocolumns in the measurement area, Example 2 was 2.25 times larger than Comparative Example 1. Since these increases are smaller than the increase in luminescence intensity shown in Figure 12, it was confirmed that in Examples 1 and 2, the improvement in luminescence intensity was due to factors other than the increase in area.

[0071] Furthermore, when the full width at half maximum (FWHM) of the peaks shown in Figure 12 was measured, it was 82 nm for Comparative Example 1, 47.6 nm for Example 1, and 55.4 nm for Example 2. In Examples 1 and 2, an increase in FWHM (decreased monochromaticity) was expected because the size of the nanocolumns was varied even within the measurement area. However, surprisingly, a decrease in FWHM (improved monochromaticity) was confirmed.

[0072] [Comparative Example 2] A semiconductor optical array was obtained in the same manner as in Comparative Example 1, except that the pixels shown in Figure 13(a) and below were formed. • Pixel's planar shape: Hexagonal • Pixel size (maximum length between opposite corners): 150 μm • Pitch between the centers of adjacent nanocolumns: 450nm • Size of nanocolumns at the center of the pixel: 200nm • Size of nanocolumns at the outer edge of the pixel: 200nm

[0073] The results of SEM observation of the nanocolumns are shown in Figures 13(b) and 13(c). As shown in Figures 13(b) and 13(c), the size of the nanocolumns at the center of the pixel and the size of the nanocolumns at the outer edge of the pixel were identical.

[0074] [Example 3] A semiconductor optical array was obtained in the same manner as in Comparative Example 1, except that the pixels shown in Figure 13(d) and below were formed. • Pixel's planar shape: Hexagonal • Pixel size (maximum length between opposite corners): 150 μm • Pitch between the centers of adjacent nanocolumns: 450nm • Size of nanocolumns at the center of the pixel: 200nm • Size of nanocolumns at the outer edge of the pixel: 150nm

[0075] The results of SEM observation of the nanocolumns are shown in Figures 13(e) and 13(f). As shown in Figures 13(e) and 13(f), the size of the nanocolumns decreased continuously from the center to the outer edge in the pixel.

[0076] [Example 4] A semiconductor optical array was obtained in the same manner as in Comparative Example 1, except that the pixels shown in Figure 13(g) and below were formed. • Pixel's planar shape: Hexagonal • Pixel size (maximum length between opposite corners): 150 μm • Pitch between the centers of adjacent nanocolumns: 450nm • Size of nanocolumns at the center of the pixel: 200nm • Size of nanocolumns at the outer edge of the pixel: 100 nm

[0077] The results of SEM observation of the nanocolumns are shown in Figures 13(h) and 13(i). As shown in Figures 13(h) and 13(i), the size of the nanocolumns decreased continuously from the center to the outer edge in the pixel.

[0078] [evaluation] The same procedure as in Comparative Example 2 and Examples 3 and 4 was followed to form the light-emitting layer. At this stage, the light-emitting layer was irradiated with a laser, and the light emission intensity was measured in the same manner as described above. The results are shown in Figure 14. As shown in Figure 14, Examples 3 and 4 showed higher light emission intensities compared to Comparative Example 2. Furthermore, when the full width at half maximum of the peaks shown in Figure 14 was measured, it was 61.2 nm for Comparative Example 2, 57.5 nm for Example 3, and 53.9 nm for Example 4.

[0079] Thus, the present disclosure provides, for example, the following inventions.

[0080] [1] Semiconductor substrate and A mask layer having an opening is placed on the main surface of the above semiconductor substrate, A nanocolumn, which is a columnar crystal of a group III nitride semiconductor, extends in the thickness direction from the above semiconductor substrate through the above opening, The light-emitting layer positioned at the tip of the above nanocolumn, The above-mentioned light-emitting layer is covered with a coating semiconductor layer containing a semiconductor, A semiconductor optical array having, The above semiconductor optical array has pixels that include a plurality of the above nanocolumns, A semiconductor optical array in which, in the above-mentioned pixels, the size of the nanocolumns increases stepwise or continuously from the center toward the outer edge, or decreases stepwise or continuously.

[0081] [2] The semiconductor optical array according to [1], wherein the size of the nanocolumn at the center of the above pixel is 10 nm or more and 1000 nm or less.

[0082] [3] A semiconductor optical array according to [1] or [2], wherein in the above-mentioned pixels, the size of the nanocolumns increases stepwise or continuously from the center toward the outer edge.

[0083] [4] The semiconductor optical array according to [3], wherein when the size of the nanocolumn at the center of the pixel is S1 [nm] and the size of the nanocolumn at the outer periphery of the pixel is S2 [nm], the ratio of S2 to S1 (S2 / S1) is 1.5 or more and 6.0 or less.

[0084] [5] The semiconductor optical array according to [1] or [2], wherein in the above-mentioned pixel, the size of the nanocolumn decreases in steps or continuously from the center toward the outer edge.

[0085] [6] The semiconductor optical array according to [5], wherein when the size of the nanocolumn at the center of the pixel is S3 [nm] and the size of the nanocolumn at the outer periphery of the pixel is S4 [nm], the ratio of S4 to S3 (S4 / S3) is 0.4 or more and 0.8 or less.

[0086] [7] A semiconductor optical array according to any one of [1] to [6], wherein the difference in size between adjacent nanocolumns in the direction from the center toward the outer periphery is 5 nm or less.

[0087] [8] A semiconductor optical array as described in any of [1] to [7], wherein the nanocolumns are columnar crystals of GaN.

[0088] [9] A semiconductor optical array according to any one of [1] to [8], wherein the light-emitting layer comprises InGaN.

[0089]

[10] A semiconductor optical array according to any one of [1] to [9], wherein a portion of the above pixels is an emission region, and the emission region includes the above center. [Explanation of Symbols]

[0090] 1… Semiconductor substrate 1a ... Substrate 1b ... Semiconductor layer 2… Mask layer 3… Nanocolumn 4… Light-emitting layer 5 … Covering semiconductor layer 10 ... Semiconductor optical array

Claims

1. Semiconductor substrate and A mask layer having an opening is disposed on the main surface of the semiconductor substrate, A nanocolumn, which is a columnar crystal of a group III nitride semiconductor, extends in the thickness direction from the semiconductor substrate through the opening, A light-emitting layer positioned at the tip of the nanocolumn, A coating semiconductor layer comprising a semiconductor covering the aforementioned light-emitting layer, A semiconductor optical array having, The semiconductor optical array has pixels that include a plurality of the nanocolumns, In the aforementioned pixel, the size of the nanocolumn increases stepwise or continuously from the center toward the outer edge. A semiconductor optical array in which, when the size of the nanocolumn at the center of the pixel is S1 [nm] and the size of the nanocolumn at the outer periphery of the pixel is S2 [nm], the ratio of S2 to S1 (S2 / S1) is 1.5 or more and 6.0 or less.

2. The semiconductor optical array according to claim 1, wherein the size of the nanocolumn at the center of the pixel is 10 nm or more and 1000 nm or less.

3. The semiconductor optical array according to claim 1 or claim 2, wherein the difference in size between adjacent nanocolumns in the direction from the center toward the outer periphery is 5 nm or less.

4. The semiconductor optical array according to claim 1 or claim 2, wherein the nanocolumn is a columnar crystal of GaN.

5. The semiconductor optical array according to claim 1 or claim 2, wherein the light-emitting layer includes InGaN.

6. The semiconductor optical array according to claim 1 or claim 2, wherein a portion of the pixel is a light-emitting region, and the light-emitting region includes the center.

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