Semiconductor memory

Abstract

To provide a semiconductor memory device capable of suppressing an increase in time required for an erase operation.SOLUTION: A semiconductor memory device 30 of one embodiment includes: a memory cell MC including a transistor; wiring CPWELL; and a first circuit 36. The first circuit performs an erase operation including an erase voltage application operation for applying an erase voltage VERA between a gate of the transistor and a channel of the transistor via the wiring and an erase verify operation for determining a threshold voltage of the memory cell. When the first circuit receives a first command FFh during the erase operation, it executes a first interruption process to interrupt the erase operation. The first circuit executes an erase voltage application operation or an erase verify operation when resuming the erase operation interrupted in the first interruption process based on a voltage value VERA1 of the wiring in receiving the first command.SELECTED DRAWING: Figure 9

Description

[Technical Field]

[0001] Embodiments of the present invention relate to semiconductor memory devices. [Background technology]

[0002] NAND flash memory is a well-known type of semiconductor memory device. [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] U.S. Patent Application Publication No. 2021 / 0303172 [Patent Document 2] U.S. Patent Application Publication No. 2022 / 0197560 [Patent Document 3] U.S. Patent No. 11402996 [Overview of the Initiative] [Problems that the invention aims to solve]

[0004] To provide a semiconductor memory device that can suppress the increase in the time required for erasure operations. [Means for solving the problem]

[0005] The semiconductor memory device according to the embodiment includes a memory cell including a transistor, wiring, and a first circuit. The first circuit performs an erase operation which includes an erase voltage application operation that applies an erase voltage between the gate and channel of the transistor via the wiring, and an erase verify operation that determines the threshold voltage of the memory cell. When the first circuit receives a first command during the erase operation, it performs a first interruption process that interrupts the erase operation. Based on the voltage value of the wiring when the first command was received, the first circuit performs either the erase voltage application operation or the erase verify operation when the erase operation interrupted by the first interruption process is resumed. [Brief explanation of the drawing]

[0006] [Figure 1] This is a block diagram showing an example of a memory system including a semiconductor memory device according to the first embodiment. [Figure 2] This block diagram shows an example of the configuration of a semiconductor memory device according to the first embodiment. [Figure 3] This is a circuit diagram of a memory cell array in a semiconductor memory device according to the first embodiment. [Figure 4] This is a cross-sectional view showing an example of the cross-sectional structure of a memory cell array in a semiconductor storage device according to the first embodiment. [Figure 5] This is a cross-sectional view showing an example of the cross-sectional structure of a memory pillar in a semiconductor memory device according to the first embodiment. [Figure 6] This figure illustrates an example of the sequence of erasure operations for a semiconductor memory device according to the first embodiment. [Figure 7] This is a timing chart showing an example of the erase operation of a semiconductor memory device according to the first embodiment. [Figure 8] This figure illustrates an example of the relationship between the timing at which an interruption instruction is received during the erase operation of a semiconductor memory device according to the first embodiment, and the operation when the erase operation is resumed. [Figure 9] This flowchart shows an example of the erasure operation of a semiconductor memory device according to the first embodiment. [Figure 10] This is a timing chart showing an example of the erase operation of a semiconductor memory device according to the first embodiment. [Figure 11] This timing chart shows another example of the erase operation of a semiconductor memory device according to the first embodiment. [Figure 12] This flowchart shows an example of the erasure operation of a semiconductor memory device according to the second embodiment. [Figure 13] This is a timing chart showing an example of the erase operation of a semiconductor memory device according to the second embodiment. [Figure 14] This timing chart shows another example of the erase operation of a semiconductor memory device according to the second embodiment. [Figure 15]It is a timing chart showing another example of the erasure operation of the semiconductor memory device according to the second embodiment. [Figure 16] It is a flowchart showing an example of the erasure operation of the semiconductor memory device according to the third embodiment. [Figure 17] It is a timing chart showing an example of the erasure operation of the semiconductor memory device according to the third embodiment. [Figure 18] It is a timing chart showing another example of the erasure operation of the semiconductor memory device according to the third embodiment. [Figure 19] It is a flowchart showing an example of the erasure operation of the semiconductor memory device according to the first modification of the third embodiment. [Figure 20] It is a timing chart showing an example of the erasure operation of the semiconductor memory device according to the first modification of the third embodiment. [Figure 21] It is a flowchart showing an example of the erasure operation of the semiconductor memory device according to the second modification of the third embodiment.

Mode for Carrying Out the Invention

[0007] Hereinafter, embodiments will be described with reference to the drawings. In this description, common reference numerals are given to common parts throughout the drawings.

[0008] Each functional block does not necessarily need to be distinguished as in the following examples. For example, some functions may be realized by functional blocks different from the exemplified functional blocks. Further, the exemplified functional blocks may be further divided into finer functional sub-blocks. The embodiments are not limited by which functional block realizes the function.

[0009] Also, each functional block can be realized as either hardware, computer software, or a combination of both.

[0010] 1. First Embodiment A semiconductor memory device according to the first embodiment will be described below. In the following description, NAND flash memory will be used as an example of a semiconductor memory device.

[0011] 1.1 Configuration 1.1.1 Memory System Configuration The configuration of the memory system including the semiconductor storage device according to this embodiment will be described with reference to Figure 1. Figure 1 is a block diagram showing an example of the memory system including the semiconductor storage device according to this embodiment.

[0012] Memory system 1 is a device that stores data. Memory system 1 may be, for example, an SSD (solid state drive), a UFS (Universal Flash Storage) device, a USB (Universal Serial Bus) memory, an MMC (Multi-Media Card), or an SD card. TM It is a card. Memory system 1 is connectable to host 2 via a host bus. Memory system 1 performs processing based on request signals or spontaneous processing requests received from host 2. Request signals are requests for various operations. Various operations include, for example, write operations, read operations, and erase operations. Spontaneous processing requests include, for example, wear leveling, compaction, and refresh.

[0013] Host 2 is a device that controls memory system 1. Host 2 may be, for example, a personal computer, a server system, a mobile device, an in-vehicle device, or a digital camera.

[0014] Next, we will describe the internal configuration of memory system 1.

[0015] The memory system 1 includes a memory controller 10 and a semiconductor memory device 30 as functional blocks. The semiconductor memory device 30 is a non-volatile memory, such as a NAND flash memory. Hereinafter, the semiconductor memory device 30 will be referred to as a NAND flash memory 30.

[0016] The memory controller 10 is a device that controls the NAND flash memory 30. The memory controller 10 is, for example, a System On a Chip (SoC). The memory controller 10 is connected to the host 2 via a host bus. The memory controller 10 receives request signals from the host 2 via the host bus. The memory controller 10 also transmits information to the host 2 via the host bus. The type of host bus depends on the application applied to the memory system 1. If the memory system 1 is an SSD, the host bus could be, for example, SAS (Serial Attached SCSI), SATA (Serial ATA), or PCIe. TM The Peripheral Component Interconnect Express (CPC) interface is used. If memory system 1 is a UFS device, the M-PHY interface is used as the host bus. If memory system 1 is a USB memory device, the USB interface is used as the host bus. If memory system 1 is an MMC, the eMMC (Embedded Multi Media Card) interface is used as the host bus. TM If it is a card, the host bus is SD TM A standard interface is used.

[0017] The memory controller 10 controls the NAND flash memory 30 via the NAND bus based on a request signal received from the host 2 or a spontaneous processing request. The memory controller 10, for example, transmits and receives data, as well as commands and addresses, to and from the NAND flash memory 30. The NAND bus transmits and receives signals according to the NAND interface.

[0018] The NAND flash memory 30 is a data storage device. The NAND flash memory 30 includes a plurality of memory cell transistors. Each of the plurality of memory cell transistors stores data nonvolatilously. The NAND flash memory 30 performs write, read, and erase operations based on a request signal received from the host 2. A write operation is, for example, an operation to write data to the plurality of memory cell transistors. A read operation is, for example, an operation to read data from the plurality of memory cell transistors. An erase operation is, for example, an operation to erase the data written to the plurality of memory cell transistors. Therefore, in a write operation, the NAND flash memory 30 stores the data received from the memory controller 10 nonvolatilously in the plurality of memory cell transistors. In a read operation, the NAND flash memory 30 outputs the data read from the plurality of memory cell transistors to the memory controller 10.

[0019] Next, we will describe the internal configuration of the memory controller 10.

[0020] The memory controller 10 includes, as functional blocks, a host interface (I / F) circuit 11, a processor (CPU: Central Processing Unit) 12, a buffer memory 13, an ECC (Error Checking and Correcting) circuit 14, a ROM (Read-only memory) 15, a RAM (Random Access Memory) 16, and a NAND interface (I / F) circuit 17.

[0021] The host interface circuit 11 is responsible for communication between the memory controller 10 and the host 2. The host interface circuit 11 is connected to the host 2 via the host bus.

[0022] The processor 12 is the control circuit for the memory controller 10. The processor 12 controls the operation of the entire memory controller 10 by executing the program (firmware) stored in the ROM 15. For example, when the processor 12 receives a write operation request signal from the host 2, it controls the write operation based on that signal. The same applies to read and erase operations.

[0023] Buffer memory 13 is memory that temporarily stores data. Buffer memory 13 is, for example, SRAM (Static Random Access Memory). Buffer memory 13 temporarily stores written data and read data, etc. Written data is data written to NAND flash memory 30. Read data is data read from NAND flash memory 30.

[0024] The ECC circuit 14 is a circuit that performs data error correction (ECC) processing. Specifically, the ECC circuit 14 generates error correction codes based on the data to be written during a data writing operation. Then, during a data reading operation, the ECC circuit 14 generates syndromes based on the error correction codes in predetermined units to detect errors and correct the detected errors.

[0025] ROM15 is a non-volatile memory. ROM15 is, for example, an EEPROM. TM It is (Electrically Erasable Programmable Read-Only Memory). ROM15 stores programs such as firmware.

[0026] RAM16 is volatile memory. RAM16 is, for example, SRAM. RAM16 is used as a workspace for processor 12. RAM16 stores firmware for managing NAND flash memory 30 and various management information.

[0027] The NAND interface circuit 17 is a circuit that manages communication between the memory controller 10 and the NAND flash memory 30. The NAND interface circuit 17 is connected to the NAND flash memory 30 via a NAND bus. For example, the NAND interface circuit 17 controls the transfer of data, commands, and addresses between the memory controller 10 and the NAND flash memory 30.

[0028] 1.1.2 Configuration of NAND flash memory The configuration of the NAND flash memory 30 will be explained using Figure 2. Figure 2 is a block diagram showing an example of the configuration of the NAND flash memory 30. The NAND flash memory 30 includes, as functional blocks, a memory cell array 31, an input / output circuit 32, a logic control circuit 33, a ready / busy circuit 34, a register 35, a sequencer 36, a driver module 37, a raw decoder module 38, and a sense amplifier module 39.

[0029] The memory cell array 31 includes multiple blocks BLK0 to BLKn (where n is an integer greater than or equal to 1). Hereafter, when blocks BLK0 to BLKn are not distinguished, they will simply be referred to as block BLK. A block BLK is, for example, a collection of multiple memory cell transistors whose data is erased collectively. For example, a block BLK is used as the unit of data erasure operation. The memory cell array 31 is provided with multiple bit lines and multiple word lines. Each memory cell transistor is associated with, for example, one bit line and one word line. Details of the memory cell array 31 will be described later.

[0030] The input / output circuit 32 is a circuit that sends and receives signals and information to and from the memory controller 10. The input / output circuit 32 sends and receives input / output signals DQ (for example, 8-bit signals DQ0 to DQ7), as well as data strobe signals DQS and DQSn (inverted signals of signal DQS) to and from the memory controller 10. Signal DQ is data that is sent and received between the NAND flash memory 30 and the memory controller 10. Signal DQ includes, for example, the command CMD, address ADD, status information STS, and data DAT. Signals DQS and DQSn are signals for controlling the timing of sending and receiving signal DQ. For example, during a data write operation, signals DQS and DQSn are sent from the memory controller 10 to the NAND flash memory 30 along with signal DQ containing the data to be written. The NAND flash memory 30 receives signal DQ containing the data to be written in synchronization with signals DQS and DQSn. Furthermore, during data read operations, signals DQS and DQSn are transmitted from the NAND flash memory 30 to the memory controller 10 along with signal DQ containing the read data. The memory controller 10 receives signal DQ containing the read data in synchronization with signals DQS and DQSn. The input / output circuit 32 may also receive signals DQS and DQSn from the memory controller 10 via the logic control circuit 33.

[0031] The logic control circuit 33 is a circuit that controls the input / output circuit 32 and the sequencer 36 based on control signals. The logic control circuit 33 receives the following control signals from the memory controller 10: the chip enable signal CEn, the command latch enable signal CLE, the address latch enable signal ALE, the write enable signal WEn, and the read enable signal REn. Signal CEn is a signal for enabling the NAND flash memory 30. Signal CLE is a signal that indicates that the signal DQ received by the NAND flash memory 30 is the command CMD. Signal ALE is a signal that indicates that the signal DQ received by the NAND flash memory 30 is the address ADD. Signal WEn is a signal that enables the input of signal DQ to the NAND flash memory 30, for example, during a write operation. Signal REn is a signal that enables the output of signal DQ from the NAND flash memory 30, for example, during a read operation. The NAND flash memory 30 generates signals DQS and DQSn based on signal REn. The NAND flash memory 30 outputs the signal DQ to the memory controller 10 based on the generated signals DQS and DQSn.

[0032] The ready / busy circuit 34 is a circuit that informs the memory controller 10 of the operating status of the sequencer 36. Based on the operating status of the sequencer 36, the ready / busy circuit 34 sends a ready / busy signal RBn to the memory controller 10. Signal RBn is a signal that indicates whether the NAND flash memory 30 is in a ready state or a busy state. For example, when the NAND flash memory 30 is in a ready state, the signal RBn is at a "High" level (hereinafter also referred to as "H level"). The ready state is when the NAND flash memory 30 is able to accept commands from the memory controller 10. For example, when the NAND flash memory 30 is in a busy state, the signal RBn is at a "Low" level (hereinafter also referred to as "L level"). The busy state is when the NAND flash memory 30 is unable to accept commands from the memory controller 10.

[0033] Register 35 is a circuit for temporarily storing information. Register 35 includes the command register 35A, the address register 35B, and the status register 35C.

[0034] Command register 35A is a circuit that stores the command CMD contained in signal DQ. Command CMD is received from input / output circuit 32. Command CMD includes, for example, instructions that cause the sequencer 36 to perform read, write, and erase operations.

[0035] The address register 35B is a circuit that stores the address ADD contained in the signal DQ. The address ADD is received from the input / output circuit 32. The address ADD includes, for example, the block address BAd, the page address PAAd, and the column address CAD. The block address BAd, page address PAAd, and column address CAD are used, for example, for selecting the block BLK, word line, and bit line, respectively.

[0036] The status register 35C is a circuit that temporarily stores status information STS, for example, during read, write, and erase operations. The status information STS is used to notify the memory controller 10 whether or not the operation has been completed successfully. Therefore, the input / output circuit 32 receives the status information STS from the status register 35C.

[0037] The sequencer 36 controls the operation of the entire NAND flash memory 30. For example, based on the command CMD stored in the command register 35A, the sequencer 36 controls the ready / busy circuit 34, the driver module 37, the raw decoder module 38, and the sense amplifier module 39 to perform various operations of the NAND flash memory 30.

[0038] The sequencer 36 includes a timer circuit 40 and a latch circuit 41. The sequencer 36 may include two or more latch circuits 41.

[0039] The timer circuit 40 measures, for example, the time during which the erase voltage VERA is applied during the erase operation.

[0040] The latch circuit 41 temporarily stores information used in the erase operation, for example. The information used in the erase operation includes, for example, application time information Iat, restart operation information Iar, and erase verify operation information Ivfy.

[0041] The driver module 37 is a circuit that generates voltages used in read, write, and erase operations. Based on the page address PAd stored in the address register 35B, the driver module 37 applies the generated voltage to the selected word line.

[0042] The row decoder module 38 is a circuit that selects one block BLK in the memory cell array 31 based on the block address BAd stored in the address register 35B.

[0043] The sense amplifier module 39 transmits and receives data DAT within signal DQ to and from the input / output circuit 32. During a write operation, the sense amplifier module 39 applies a voltage to the bit line based on the write data DAT received from the input / output circuit 32. During a read operation, the sense amplifier module 39 determines the data stored in the memory cell transistor based on the voltage of the bit line. The sense amplifier module 39 transfers the determination result to the input / output circuit 32 as read data DAT.

[0044] 1.1.3 Circuit configuration of memory cell array The circuit configuration of the memory cell array 31 will be explained using Figure 3. Figure 3 is a circuit diagram of the memory cell array 31. Figure 3 shows the circuit configuration of block BLK0 included in the memory cell array 31 as an example of the circuit configuration of the memory cell array 31. The other blocks BLK1 to BLKn have the same configuration as shown in Figure 3.

[0045] Block BLK includes, for example, four string units SU0 to SU3. Hereafter, if string units SU0 to SU3 are not distinguished, they will simply be referred to as string unit SU. String unit SU is, for example, a collection of multiple NAND strings NS that are selected collectively in a write or read operation. String unit SU includes multiple NAND strings NS associated with bit lines BL0 to BLm (where m is an integer greater than or equal to 1). Hereafter, if bit lines BL0 to BLm are not distinguished, they will simply be referred to as bit line BL. NAND string NS is a collection of multiple transistors connected in series. Multiple transistors connected in series include, for example, memory cell transistors MC0 to MC7, and selection transistors ST1 and ST2. Hereafter, if memory cell transistors MC0 to MC7 are not distinguished, they will simply be referred to as memory cell transistors MC. Memory cell transistors MC store data non-volatilely. Memory cell transistors MC include a control gate and a charge storage layer. Selection transistors ST1 and ST2 are switching elements. The selection transistors ST1 and ST2 are used to select the string unit SU during various operations.

[0046] In the NAND string NS, memory cell transistors MC0 to MC7 are connected in series. The drain of selection transistor ST1 is connected to the associated bit line BL. The source of selection transistor ST1 is connected to one end of memory cell transistors MC0 to MC7. The drain of selection transistor ST2 is connected to the other end of memory cell transistors MC0 to MC7. The source of selection transistor ST2 is connected to the source line CELSRC.

[0047] Within the same block BLK, the control gates of memory cell transistors MC0 to MC7 are commonly connected to word lines WL0 to WL7, respectively. Hereafter, when word lines WL0 to WL7 are not distinguished, they will simply be referred to as word line WL. The gates of each selection transistor ST1 within string units SU0 to SU3 are commonly connected to selection gate lines SGD0 to SGD3, respectively. Hereafter, when selection gate lines SGD0 to SGD3 are not distinguished, they will simply be referred to as selection gate line SGD. The gates of selection transistor ST2 included in the same block BLK are commonly connected to selection gate line SGS.

[0048] In the circuit configuration of the memory cell array 31 described above, the bit line BL is shared, for example, by multiple NAND strings NS to which the same column address CAd is assigned in multiple string units SU. The source line SL is shared, for example, between multiple blocks BLK.

[0049] A collection of multiple memory cell transistors MC connected to a common word line WL within a string unit SU is referred to, for example, as a cell unit CU. A block BLK contains multiple cell unit CUs. The data stored in a cell unit CU, each containing multiple memory cell transistors MC that store 1 bit of data according to a threshold voltage, corresponds to one page of data. A cell unit CU can store two or more pages of data, based on the number of bits of data stored in the memory cell transistors MC.

[0050] Furthermore, the circuit configuration of the memory cell array 31 is not limited to the configuration described above. For example, the number of string units SU included in block BLK, and the number of memory cell transistors MC and selection transistors ST1 and ST2 included in NAND string NS, can each be any number. Hereafter, the memory cell transistor MC will also be referred to as memory cell MC.

[0051] 1.1.4 Structure of a memory cell array The cross-sectional structure of the memory cell array 31 will be explained using Figure 4. Figure 4 is a cross-sectional view showing an example of the cross-sectional structure of the memory cell array 31. Figure 4 shows the region corresponding to block BLK. In Figure 4, the X direction corresponds to the extension direction of the word line WL. The Y direction corresponds to the extension direction of the bit line BL. The Z direction corresponds to the direction perpendicular to the surface of the semiconductor substrate. Note that in the example of Figure 4, a part of the insulating layer has been omitted for the sake of simplicity.

[0052] A p-well region 50 is provided within the semiconductor substrate. Above the well region 50, a wiring layer 51 functioning as a select gate line SGS, eight wiring layers 52 functioning as word lines WL0 to WL7, and a wiring layer 53 functioning as select gate lines SGD (SGD0 to SGD3) are stacked in that order, spaced apart from each other. That is, above the well region 50, the wiring layer 51, eight wiring layers 52, and wiring layer 53 are stacked in that order, each separated by an insulating layer (not shown). The select gate lines SGD0 to SGD3 are arranged in the Y direction in the order of SGD0, SGD1, SGD2, and SGD3, spaced apart from each other. The wiring layers 51 to 53 are made of a conductive material, for example, tungsten.

[0053] Furthermore, above the well region 50, a memory pillar MP is provided, which is a structure that forms the selection transistors ST1 and ST2, and the memory cell transistors MC0 to MC7. The memory pillar MP is formed in a columnar shape that extends along the Z direction. The memory pillar MP corresponds to the NAND string NS. The memory pillar MP penetrates, for example, the wiring layer 51, the eight-layer wiring layer 52, and the wiring layer 53, and its bottom surface reaches the p-type well region 50.

[0054] Here, an example is shown in which a memory pillar MP is connected to a p-type well region 50 in a semiconductor substrate, but the semiconductor substrate and the memory pillar MP may be formed separately. When the semiconductor substrate and the memory pillar MP are separated, the memory pillar MP is connected to, for example, an n-type semiconductor layer, and the n-type semiconductor layer is connected to, for example, a metal layer having a tungsten silicide and titanium nitride laminate or aluminum.

[0055] Furthermore, the memory pillar MP includes, for example, a core member 54, a semiconductor layer 55, insulating layers 56-58, and a conductor 59.

[0056] The core member 54 is formed in the central part of the memory pillar MP in a columnar shape that extends along the Z direction.

[0057] The sides and bottom of the core member 54 are covered by a semiconductor layer 55. The semiconductor layer 55 functions as the channels for the memory cell transistor MC and the selection transistors ST1 and ST2, respectively.

[0058] The sides of the semiconductor layer 55 are covered by a laminate of insulating layers 56-58.

[0059] Figure 5 is a cross-sectional view along the SS line in Figure 4, showing an example of the cross-sectional structure of a memory pillar MP. Specifically, Figure 5 shows the cross-sectional structure of a memory pillar MP in a layer parallel to the surface of a semiconductor substrate and including a wiring layer 52.

[0060] As shown in Figure 5, the insulating layer 56 surrounds the semiconductor layer 55. The insulating layer 56 functions as a tunnel insulating layer of the memory cell transistor MC. The insulating layer 56 is made of an insulating material, including, for example, silicon oxide and silicon oxynitride. The insulating layer 57 surrounds the insulating layer 56. The insulating layer 57 functions as a charge storage layer of the memory cell transistor MC. The insulating layer 57 is made of an insulating material, including, for example, silicon nitride. The insulating layer 58 surrounds the insulating layer 57. The insulating layer 58 functions as a block insulating layer of the memory cell transistor MC. The insulating layer 58 is made of an insulating material, including, for example, silicon oxide and aluminum oxide. The wiring layer 52 surrounds the insulating layer 58.

[0061] As shown in Figure 4, a conductor 59 is formed on the upper part of the core member 54 and the semiconductor layer 55. The conductor 59 is electrically connected to the semiconductor layer 55. The sides of the conductor 59 are covered, for example, by a laminate of insulating layers 56-58. The conductor 59 may be formed integrally with the semiconductor layer 55.

[0062] In the memory pillar MP configuration described above, for example, the portion where the memory pillar MP intersects with the wiring layer 51 functions as a selection transistor ST2. The portions where the memory pillar MP intersects with each of the eight wiring layers 52 function as memory cell transistors MC0 to MC7, respectively. The portion where the memory pillar MP intersects with the wiring layer 53 functions as a selection transistor ST1.

[0063] The upper end of the memory pillar MP is connected via a contact plug 60 to a wiring layer 61 which functions as a bit line BL. The wiring layer 61 is made of a conductive material, including, for example, copper.

[0064] n-type impurities are introduced into the surface region of well area 50. +A p-type diffusion region 62 is provided. A contact plug 63 is provided on the diffusion region 62, and the contact plug 63 is connected to a wiring layer 64 that functions as a source line CELSRC. Furthermore, p-type impurities are introduced into the surface region of the well region 50. + A type diffusion region 65 is provided. A contact plug 66 is provided on the diffusion region 65, and the contact plug 66 is connected to a wiring layer 67 that functions as a well wire CPWELL. The well wire CPWELL is wiring for applying voltage to the memory pillar MP through the well region 50.

[0065] Multiple such configurations are arranged in the depth direction (X direction) of the page in Figure 4, and a string unit SU is formed by a collection of multiple NAND strings NS aligned in the X direction.

[0066] 1.2 Erase Operation First, let's explain the overview of the erase operation.

[0067] The erase operation includes an erase voltage application operation and an erase verify operation. The erase voltage application operation is an operation to lower the threshold voltage of the memory cell MC by applying a voltage VERA to the memory cell MC to be erased. Voltage VERA is a higher voltage than, for example, the voltage used in the read operation. Voltage VERA is applied to the memory cell MC via wiring (e.g., well line CPWELL, source line CELSRC, or bit line 61). The erase verify operation is an operation to determine whether the threshold voltage of the memory cell MC is lower than the target voltage. Hereinafter, if the threshold voltage of the memory cell MC is less than the target voltage, it will be written as "the erase verify operation passed". On the other hand, if the threshold voltage of the memory cell MC is equal to or greater than the target voltage, it will be written as "the erase verify operation failed". The erase voltage application operation is typically performed on a block BLK basis. The erase verify operation is performed on a string unit SU basis.

[0068] The memory controller 10 can separately command the NAND flash memory 30 to perform an erase voltage application operation and an erase verify operation. For example, another operation such as a write operation or a read operation may be performed between the erase voltage application operation and the erase verify operation. Also, for example, the block BLK selected in the erase voltage application operation and the block BLK (string unit SU) selected in the erase verify operation may be different.

[0069] During the erase operation, the combination of erase voltage application and erase verification (hereinafter referred to as the "erase loop") is repeatedly executed until the threshold voltage of the memory cell MC falls below the target voltage. With each repetition of the erase loop, the set value of the voltage VERA in the erase voltage application operation is stepped up. For example, the set value of voltage VERA is stepped up by dVERA. By gradually increasing voltage VERA to the final set value in this way, the stress on the erase operation can be reduced compared to raising voltage VERA to the final set value all at once. Note that the erase verification operation may be omitted in the erase loop.

[0070] Figure 6 illustrates an example of an erase operation sequence. In the example in Figure 6, the erase operation is completed when the erase loop is repeated k times (where k is an integer greater than or equal to 2).

[0071] As shown in Figure 6, in the first erase loop (hereinafter also referred to as the "first loop"), the sequencer 36 performs an erase voltage application operation. After the erase voltage application operation is performed, the sequencer 36 skips the erase verify operation Evfy (does not perform the erase verify operation). The set value of voltage VERA in the first erase loop is lower than the set value of voltage VERA in the second and subsequent erase loops. Therefore, in the first erase loop, the possibility of the threshold voltage of the memory cell MC falling below the target voltage is lower compared to the second and subsequent erase loops. In other words, in the first erase loop, the possibility of passing the erase verify operation is lower compared to the second and subsequent erase loops. Therefore, it is possible to skip the erase verify operation in the first erase loop. By skipping the erase verify operation in this way, the increase in the overall time required for the erase operation can be suppressed. Note that the sequencer 36 may also perform the erase verify operation in the first erase loop.

[0072] Next, in the second erase loop (hereinafter also referred to as the "second loop"), the sequencer 36 performs an erase voltage application operation. The set value of voltage VERA is stepped up from the set value of voltage VERA in the erase voltage application operation of the first erase loop. After the erase voltage application operation is performed, the sequencer 36 performs an erase verify operation Evfy.

[0073] From the third erase loop (hereinafter also referred to as the "third loop") onward, the process is the same as the second erase loop.

[0074] Next, we will explain the details of the erase operation.

[0075] (Timing chart) Figure 7 is a timing chart showing an example of the erase operation of the NAND flash memory 30. The example in Figure 7 shows an example of the erase voltage application operation in the i-th erase loop (where i is an integer greater than or equal to 1).

[0076] In this embodiment, before the erase voltage application operation is performed, the voltages of the well line CPWELL, source line CELSRC, bit line BL, selection gate lines SGD and SGS, and word line WL are all VSS (0V).

[0077] During the erase operation, the memory controller 10 sends, for example, a command set CS1 to the NAND flash memory 30 as a signal DQ. Command set CS1 is a set of commands and addresses, including, for example, the command "60h", the address "ADD", and the command "D0h". The command "60h" is a command to select a block BLK, etc., based on the address ADD. The command "D0h" is a command to instruct the execution of the erase operation based on the address ADD.

[0078] As shown in Figure 7, the NAND flash memory 30 receives command set CS1 from the memory controller 10. At time t1, upon receiving command set CS1 from the memory controller 10, the sequencer 36 transitions the ready / busy signal RBn from high level to low level. The sequencer 36 also starts the erase voltage application operation based on the received command set CS1.

[0079] The erase voltage application operation includes, for example, a setup period pES, an erase execution period pEW, and a recovery period pER.

[0080] The setup period pES is the period during which the erase voltage application operation is set up. The setup period pES further includes a first setup period pES1 and a second setup period pES2. The first setup period pES1 is the period during which the voltages of the selection gate lines SGD and SGS, and the word line WL are raised (boosted). The second setup period pES2 is the period during which the voltages of the well line CPWELL, source line CELSRC, bit line BL, and the selection gate lines SGD and SGS are raised (boosted).

[0081] The erase execution period pEW is the period during which the voltages of the well line CPWELL, source line CELSRC, and bit line BL are raised to voltage VERA (the boosting is completed) and the threshold voltage of the memory cell MC decreases. For example, in the i-th erase loop, the timer circuit 40 measures the time during which voltage VERA is applied and increments a count value at regular intervals. When the count value reaches a predetermined set value (for example, 10), the timer circuit 40 stops measuring and counting up. The application of voltage VERA continues until the count value reaches 10, that is, until 10 periods of equal length (hereinafter referred to as "the first period", "the second period", ..., "the tenth period") have elapsed. The sum of the periods from the first to the tenth period is, for example, the time during which it can be inferred that the threshold voltage of the memory cell MC has become sufficiently low. Note that it is sufficient to infer that the threshold voltage of the memory cell MC has become sufficiently low, and the set value of the count value, i.e., the number of periods during which voltage VERA is applied, is not limited to 10.

[0082] The recovery period pER is the period during which the voltages of the well line CPWELL, source line CELSRC, bit line BL, selection gate lines SGD and SGS, and word line WL are lowered (stepped down).

[0083] (Setup period pES) The setup period pES corresponds to the period from time t1 to t3. The first setup period pES1 corresponds to the period from time t1 to t2. The second setup period pES2 corresponds to the period from time t2 to t3.

[0084] At time t1, the row decoder module 38 applies voltage VERA_SG1 to the selected gate lines SGD and SGS, and voltage VERA_WL to the word line WL. Voltage VERA_SG1 is higher than voltage VSS and lower than voltage VCC. Voltage VERA_WL is higher than voltage VSS and lower than voltage VERA_SG1. Voltage VERA_SG1 is, for example, about 2V. Voltage VERA_WL is, for example, 0.5V. The application of voltage VERA_SG1 increases the voltages of the selected gate lines SGD and SGS. The application of voltage VERA_WL increases the voltage of the word line WL.

[0085] At time t2, the voltages of the selected gate lines SGD and SGS become voltage VERA_SG1. The voltage of the word line WL becomes voltage VERA_WL. At time t2, the driver module 37 applies voltage VERA to the well line CPWELL and the source line CELSRC. The sense amplifier module 39 applies voltage VERA to the bit line BL. Voltage VERA is a higher voltage than voltage VCC. The final setting value of voltage VERA is, for example, 20V. Upon application of voltage VERA, the voltages of the well line CPWELL, the source line CELSRC, and the bit line BL increase. The voltages of the selected gate lines SGD and SGS also increase due to coupling. Note that the voltages of the selected gate lines SGD and SGS may also increase when the row decoder module 38 applies voltage VERA_SG2, described later, to the selected gate lines SGD and SGS.

[0086] (Erasure execution period pEW) The erasure execution period pEW corresponds to the period from time t3 to t4.

[0087] At time t3, the voltages of the well line CPWELL, source line CELSRC, and bit line BL are each voltage VERA. The voltages of the selection gate lines SGD and SGS are each voltage VERA_SG2. Voltage VERA_SG2 is higher than voltage VERA_SG1 and lower than voltage VERA. Voltage VERA_SG2 is, for example, between voltage VERA-10V and voltage VERA-5V. During the period from time t3 to t4 (from the 1st period to the 10th period), voltage VERA is applied to the well line CPWELL, source line CELSRC, and bit line BL. Voltage VERA_SG2 is applied to the selection gate lines SGD and SGS. Voltage VERA_WL is applied to the word line WL. This lowers the threshold voltage of the memory cell MC.

[0088] When the erasure execution period pEW begins, the sequencer 36 instructs the timer circuit 40 to measure the time during which the voltage VERA is applied to the well line CPWELL (hereinafter also referred to as "voltage VERA application time"). Based on the instruction received from the sequencer 36, the timer circuit 40 begins measuring the voltage VERA application time. When the 10th period ends, the recovery period pER begins.

[0089] (Recovery period pER) The recovery period (pER) corresponds to the period from time t4 to t5.

[0090] At time t4, the driver module 37 applies voltage VSS to the well line CPWELL and the source line CELSRC. The sense amplifier module 39 applies voltage VSS to the bit line BL. The row decoder module 38 applies voltage VSS to the selection gate lines SGD and SGS, and the word line WL. As a result, the voltages of the well line CPWELL, the source line CELSRC, the bit line BL, the selection gate lines SGD and SGS, and the word line WL decrease.

[0091] When the recovery period pER begins, the timer circuit 40 stops measuring the voltage VERA application time. The timer circuit 40 transmits the measured time (hereinafter also referred to as "measured time") to the sequencer 36. The sequencer 36 stores the measured time received from the timer circuit 40 as application time information Iat in the latch circuit 41.

[0092] At time t5, the voltages of the well line CPWELL, source line CELSRC, bit line BL, selection gate lines SGD and SGS, and word line WL all become voltage VSS. This completes the erase voltage application operation.

[0093] 1.3 Erase operation (when an interruption instruction is received) If the memory controller 10 receives an interrupt request (for example, a write operation or a read operation) from the host 2 during the erase operation, the memory controller 10 sends an instruction to the NAND flash memory 30 to interrupt the erase operation. Below, we will first describe the overview of the erase operation when the sequencer 36 receives an interruption instruction during the erase operation.

[0094] If the sequencer 36 receives a command, for example, "FFh," from the memory controller 10 during the erase operation, it interrupts the erase operation. The command "FFh" is a command that instructs the NAND flash memory 30 to interrupt the operation in progress. After the interruption of the erase operation, the sequencer 36 starts interrupt processing. When the interrupt processing is completed, the sequencer 36 resumes the erase operation. The operation at the time of resumption is determined based on when the interruption instruction was received during the erase operation (the timing of receiving the command "FFh").

[0095] Figure 8 illustrates an example of the relationship between the timing of receiving an interruption instruction during an erase operation and the operation when the erase operation is resumed. The sequence of the erase operation is the same as in Figure 6. Hereinafter, the period including the setup period pES, erase execution period pEW, and recovery period pER of the first erase voltage application operation, as well as the setup period pES and erase execution period pEW of the second erase voltage application operation, in two consecutively executed erase voltage application operations, will be referred to as the "verify skip period pVS". In this embodiment, the verify skip period pVS is from the start of the first loop to the erase execution period pEW of the second loop. Note that the verify skip period pVS may be provided in the third loop or later. Furthermore, the period including the setup period pES and erase execution period pEW of the erase voltage application operation other than the verify skip period pVS will be referred to as the "boost period pSU".

[0096] As shown in Figure 8, if the command "FFh" is received during the verify skip period pVS, the PLC 36 performs an erase voltage application operation as the operation upon restart. If the command "FFh" is received during the recovery period pER or the erase verify operation Evfy, the PLC 36 performs an erase verify operation as the operation upon restart. If the command "FFh" is received during the boost period pSU, the PLC 36 performs either an erase voltage application operation or an erase verify operation as the operation upon restart.

[0097] Next, we will describe the details of the erase operation when the sequencer 36 receives an interruption instruction during the erase operation.

[0098] (flowchart) Figure 9 is a flowchart showing an example of the erase operation of the NAND flash memory 30. In the example in Figure 9, the sequencer 36 receives the command "FFh" during the erase operation. In this embodiment, the erase operation shown below is given as an example when it is performed by the sequencer 36, but the erase operation shown below may also be performed by the memory controller 10. The same applies to other embodiments and modifications.

[0099] When the sequencer 36 receives command set CS1 from the memory controller 10, it starts the erase operation. After the erase operation has started, when the sequencer 36 receives the command "FFh" from the memory controller 10, it interrupts the erase operation (S100).

[0100] Next, the sequencer 36 determines whether the timing of receiving the command "FFh" is during the verify skip period pVS (S101).

[0101] If the verify skip period pVS is in progress (S101_Yes), the PLC 36 reserves the erase voltage application operation as the operation to be performed when the process resumes (S104). For example, the PLC 36 stores the "erase voltage application operation" (meaning that the operation to be performed when the process resumes is to apply an erase voltage), the voltage of the well line CPWELL at the time of interruption (when the command "FFh" is received), the interruption time, the boost start voltage (the set value of voltage VERA), and the boost method as restart operation information Iar in the latch circuit 41. When the interrupt processing is completed, the PLC 36 resumes the erase operation (S106). That is, the PLC 36 executes the reserved erase voltage application operation. For example, the PLC 36 obtains the restart operation information Iar from the latch circuit 41 and executes the erase voltage application operation based on the obtained restart operation information Iar.

[0102] On the other hand, if it is not during the verify skip period pVS (S101_No), the sequencer 36 determines whether the timing of receiving the command "FFh" is during the boost period pSU (S102).

[0103] If the boost period pSU is not active (S102_No), the PLC 36 reserves an erase verify operation as the operation to be performed upon restart (S105). If the boost period pSU is not active, for example, it is active during the recovery period pER or during an erase verify operation. The PLC 36 stores "erase verify operation," which means that the operation to be performed upon restart is an erase verify operation, as restart operation information Iar in the latch circuit 41. When the interrupt processing is completed, the PLC 36 restarts the erase operation (S106). That is, the PLC 36 executes the reserved erase verify operation. For example, the PLC 36 obtains the restart operation information Iar from the latch circuit 41 and executes the erase verify operation based on the obtained restart operation information Iar. When the erase verify operation is completed, the PLC 36 stores the completion time of the erase verify operation as erase verify operation information Ivfy in the latch circuit 41.

[0104] On the other hand, if the boost period pSU is in progress (S102_Yes), the sequencer 36 determines whether the voltage of the well line CPWELL (hereinafter referred to as "voltage VERA1") when the command "FFh" is received is higher than the first threshold Vth1 (S103). The first threshold Vth1 is a voltage that is higher than voltage VSS and lower than voltage VERA. The first threshold Vth1 is determined, for example, by empirical rules as a voltage that is relatively likely not to lower the threshold voltage of the memory cell MC. For example, the first threshold Vth1 is 10V or more and less than 15V.

[0105] If the voltage VERA1 is higher than the first threshold Vth1 (S103_Yes), the PLC 36 reserves an erase verify operation as the operation to be performed upon restart (S105). When the interrupt processing is completed, the PLC 36 resumes the erase operation (S106). In other words, the PLC 36 executes the reserved erase verify operation.

[0106] On the other hand, if the voltage VERA1 is less than or equal to the first threshold Vth1 (S103_No), the PLC 36 reserves the erase voltage application operation as the operation to be performed when the system is restarted (S104). When the interrupt processing is completed, the PLC 36 restarts the erase operation (S106). That is, the PLC 36 executes the reserved erase voltage application operation.

[0107] Thus, when the interrupted erase operation is resumed, the sequencer 36 performs either an erase voltage application operation or an erase verify operation based on the value of the well line CPWELL voltage VERA1 when it receives the command "FFh". The command "FFh" is not invalidated.

[0108] If voltage VERA1 is less than or equal to the first threshold Vth1, there is a relatively high probability that the threshold voltage of the memory cell MC will not decrease. Therefore, in this case, the sequencer 36 performs an erase voltage application operation when restarting. On the other hand, if voltage VERA1 is higher than the first threshold Vth1, there is a higher probability that the threshold voltage of the memory cell MC will decrease compared to the case where voltage VERA1 is less than or equal to the first threshold Vth1. Therefore, in this case, the sequencer 36 performs an erase verify operation when restarting.

[0109] (Timing chart) Figure 10 is a timing chart showing an example of the erase operation of the NAND flash memory 30. Figure 10 shows the case where, during one erase loop period other than the verify skip period pVS, the command "FFh" is received during the boost period pSU, and the voltage VERA1 of the well line CPWELL at the time of receiving the command "FFh" is less than or equal to the first threshold Vth1. In Figure 10, the interrupt processing is, for example, a read operation. Note that in Figure 10, the voltages of the source line CELSRC, bit line BL, selection gate lines SGD and SGS, and word line WL are omitted. The waveforms of the source line CELSRC and bit line BL are substantially the same as the waveform of the well line CPWELL, as shown in Figure 7.

[0110] As shown in Figure 10, at time t11, when the sequencer 36 receives command set CS1 from the memory controller 10, the ready / busy signal RBn transitions from high level to low level. When the ready / busy signal RBn transitions to low level, the sequencer 36 starts the erase voltage application operation based on the received command set CS1.

[0111] The operation during the period from time t11 to t12 is the same as the operation during the period from time t1 to t2 in Figure 7.

[0112] At time t12, the driver module 37 applies voltage VERA to the well line CPWELL and the source line CELSRC. The sense amplifier module 39 applies voltage VERA to the bit line BL. Upon application of voltage VERA, the voltages of the well line CPWELL, the source line CELSRC, and the bit line BL each increase.

[0113] Now, suppose that during the period from time t12 to t13, for example, the memory controller 10 receives a request from the host 2 for an interrupt processing for a read operation. In this case, the memory controller 10 sends the command "FFh" as signal DQ to the NAND flash memory 30.

[0114] At time t13 (during the boost period pSU), when the sequencer 36 receives the command "FFh" from the memory controller 10, it terminates the processing of the setup period pES and starts the processing of the recovery period pER. At this time, the voltage VERA1 of the well line CPWELL is less than or equal to the first threshold Vth1.

[0115] At time t13, the driver module 37 applies voltage VSS to the well line CPWELL and the source line CELSRC. The sense amplifier module 39 applies voltage VSS to the bit line BL. Upon application of voltage VSS, the voltages of the well line CPWELL, the source line CELSRC, and the bit line BL decrease.

[0116] At time t14, when the voltages of the well line CPWELL, source line CELSRC, bit line BL, selection gate lines SGD and SGS, and word line WL are stepped down to voltage VSS, the sequencer 36 transitions the ready / busy signal RBn from L level to H level. This interrupts the erase voltage application operation and triggers interrupt processing.

[0117] After the interrupt processing is completed, during the period until time t15, the memory controller 10 sends, for example, a command set CS2 as a signal DQ to the NAND flash memory 30. Command set CS2 is a set of commands and addresses, including, for example, the command "27h", the command "60h", the address "ADD", and the command "D0h". The command "27h" is a command that instructs the NAND flash memory 30 to resume the interrupted operation.

[0118] At time t15, when the PLC 36 receives command set CS2 from the memory controller 10, the ready / busy signal RBn transitions from high level to low level. The PLC 36 resumes the erase operation based on the received command set CS2. If the voltage VERA1 of the well line CPWELL when the command "FFh" is received is less than or equal to the first threshold Vth1, the PLC 36 performs an erase voltage application operation as the operation upon resumption.

[0119] The operation during the period from time t15 to t19 is the same as the operation during the period from time t1 to t5 in Figure 7. When the 10th period ends, the sequencer 36 deletes, for example, the restart operation information Iar and the applied time information Iat from the latch circuit 41.

[0120] Figure 11 is a timing chart showing another example of the erase operation of the NAND flash memory 30. Figure 11 shows the case where, during a period within one erase loop other than the verify skip period pVS, the command "FFh" is received during the boost period pSU, and the voltage VERA1 of the well line CPWELL at the time of receiving the command "FFh" is higher than the first threshold Vth1. In Figure 11, the interrupt processing is, for example, a read operation. Note that in Figure 11, the voltages of the source line CELSRC, bit line BL, selection gate lines SGD and SGS, and word line WL are omitted. The waveforms of the source line CELSRC and bit line BL are substantially the same as the waveform of the well line CPWELL, as shown in Figure 7.

[0121] As shown in Figure 11, at time t21, when the sequencer 36 receives command set CS1 from the memory controller 10, the ready / busy signal RBn transitions from high level to low level. When the ready / busy signal RBn transitions to low level, the sequencer 36 starts the erase voltage application operation based on the received command set CS1.

[0122] The operation during the period from time t21 to t24 is the same as the operation during the period from time t1 to t4 in Figure 7.

[0123] Now, suppose that during the period from time t23 to t24, for example, the memory controller 10 receives a request from the host 2 for an interrupt processing of a read operation. In this case, the memory controller 10 sends, for example, the command "FFh" as the signal DQ to the NAND flash memory 30.

[0124] At time t24 (during the boost period pSU), when the timer circuit 40 receives the command "FFh" from the memory controller 10, it terminates the measurement of the voltage VERA application time. The timer circuit 40 transmits the measured time to the sequencer 36. The sequencer 36 stores the measured time received from the timer circuit 40 as application time information Iat in the latch circuit 41. Also at time t24, the sequencer 36 terminates the processing of the erase execution period pEW and starts the processing of the recovery period pER. In Figure 11, processing is terminated in the middle of the 6th period of the erase execution period pEW. At this time, the voltage VERA1 of the well line CPWELL is higher than the first threshold Vth1 and equal to the voltage VERA.

[0125] The operation during the period from time t24 to t25 is the same as the operation during the period from time t4 to t5 in Figure 7.

[0126] At time t25, when the voltages of the well line CPWELL, source line CELSRC, bit line BL, selection gate lines SGD and SGS, and word line WL are stepped down to voltage VSS, the ready / busy signal RBn transitions from L level to H level. This interrupts the erase voltage application operation and triggers interrupt processing.

[0127] After the interrupt processing is completed, during the period until time t26, the memory controller 10 sends, for example, the command set CS2 as the signal DQ to the NAND flash memory 30.

[0128] At time t26, when the PLC 36 receives command set CS2 from the memory controller 10, the ready / busy signal RBn transitions from high level to low level. The PLC 36 resumes the erase operation based on the received command set CS2. If the voltage VERA1 of the well line CPWELL when the command "FFh" is received is higher than the first threshold Vth1, the PLC 36 performs an erase verify operation as the operation upon resumption.

[0129] During the period from time t26 to t27, the sequencer 36 performs an erase and verify operation.

[0130] The operation during the period from time t27 to t29 is the same as the operation during the period from time t1 to t3 in Figure 7.

[0131] During the period from time t29 to t30, the voltage VERA is applied to the well line CPWELL, the source line CELSRC, and the bit line BL, similar to the period from time t3 to t4 in Figure 7.

[0132] At time t29, the PLC 36 obtains the application time information Iat from the latch circuit 41 and executes the erase execution period pEW processing based on the obtained application time information Iat. In the example in Figure 11, since the processing ended in the middle of the 6th period during the erase execution period pEW from time t23 to t24, the PLC 36 executes the erase execution period pEW processing from the 6th period to the 10th period. That is, the voltage VERA is applied to the well line CPWELL from the 6th period to the 10th period. In other words, if the erase operation is interrupted in the 6th period of the erase execution period pEW during the erase voltage application operation, after the erase operation is resumed, the erase execution period pEW will start from the 6th period during the erase voltage application operation. When the 10th period ends, the PLC 36 deletes the restart operation information Iar and the application time information Iat from the latch circuit 41, for example. Furthermore, if the 10th period has not yet been completed, the sequencer 36 will not delete the restart operation information Iar and the applied time information Iat from, for example, the latch circuit 41.

[0133] The operation during the period from time t30 to t31 is the same as the operation during the period from time t4 to t5 in Figure 7.

[0134] 1.4 Effects of this embodiment According to the first embodiment, the increase in the time required for the erase operation can be suppressed. If an interruption command is received during the erase operation, interrupting the erase operation, and then the erase verification operation and erase voltage application operation are performed in that order upon resumption, the time from resumption until the start of the erase execution period pEW may be longer compared to when the erase voltage application operation is performed without the erase verification operation upon resumption. Therefore, the overall time required for the erase operation may be longer compared to when the erase voltage application operation is performed without the erase verification operation upon resumption.

[0135] Furthermore, if the erase operation is frequently interrupted by receiving interruption commands, and the erase verification operation and the erase voltage application operation are performed in that order each time the erase operation is resumed, the erase operation may not progress smoothly. In particular, if interruption commands are frequently received during the setup period (pES), the erase operation is highly likely to not progress.

[0136] In contrast, in this embodiment, the sequencer 36 controls whether or not to perform the erase verify operation based on the voltage VERA1 of the well line CPWELL when it receives the command "FFh" during the boost period pSU of the erase voltage application operation.

[0137] Specifically, if the voltage VERA1 is less than or equal to the first threshold Vth1 (a voltage higher than voltage VSS and lower than voltage VERA), the sequencer 36 performs an erase voltage application operation as the operation upon restart. On the other hand, if the voltage VERA1 is higher than the first threshold Vth1, the sequencer 36 performs an erase verify operation as the operation upon restart. Therefore, compared to the case where the erase verify operation and the erase voltage application operation are performed in that order each time the erase operation is restarted, the number of times the erase verify operation is performed upon restart is reduced. In other words, the time from restart until the erase execution period pEW starts can be shortened. As a result, according to this embodiment, the increase in the overall time required for the erase operation can be suppressed compared to the case where the erase verify operation and the erase voltage application operation are performed in that order each time the erase operation is restarted. Furthermore, according to this embodiment, even if the erase operation is interrupted by frequently receiving interruption commands and then restarted, the situation in which the erase operation does not progress smoothly can be improved. Therefore, even if the command "FFh" is frequently received, it is not necessary to disable the command "FFh".

[0138] 2. Second Embodiment A semiconductor memory device according to the second embodiment will now be described. In the semiconductor memory device according to the second embodiment, the erase operation differs from that of the first embodiment. The following description will focus on the differences from the first embodiment.

[0139] 2.1 Erase operation (when an interruption instruction is received) This section describes the details of the erase operation when the sequencer 36 receives an interruption instruction during the erase operation.

[0140] (flowchart) Figure 12 is a flowchart illustrating an example of the erase operation of the NAND flash memory 30. As an example of the erase operation, Figure 12 shows the case where the sequencer 36 receives the command "FFh" during the erase operation. In Figure 12, step S103 in Figure 9, shown in the first embodiment, is replaced with step S107, and steps S108 and S109 are added.

[0141] If the boost period pSU is in progress (S102_Yes), the sequencer 36 determines whether the voltage of the well line CPWELL (hereinafter referred to as "voltage VERA2") when the command "FFh" is received is higher than the second threshold Vth2 (S107). The second threshold Vth2 is a voltage that is higher than the first threshold Vth1 and lower than voltage VERA. The second threshold Vth2 is determined, for example, by empirical rules as a voltage that is relatively likely to lower the threshold voltage of the memory cell MC below the target voltage. For example, the second threshold Vth2 is 15V or more and less than voltage VERA.

[0142] If the voltage VERA2 is higher than the second threshold Vth2 (S107_Yes), the PLC 36 reserves an erase verify operation as the operation to be performed upon restart (S105). For example, the PLC 36 stores "erase verify operation," which means that the operation to be performed upon restart is an erase verify operation, as restart operation information Iar in the latch circuit 41. When the interrupt processing is completed, the PLC 36 restarts the erase operation (S106). That is, the PLC 36 executes the reserved erase verify operation.

[0143] On the other hand, if the voltage VERA2 is less than or equal to the second threshold Vth2 (S107_No), the sequencer 36 determines whether the erase operation was interrupted within a single erase loop when the voltage VERA2 was less than or equal to the second threshold Vth2 before the current interruption (hereinafter also referred to as the "first interruption process") (S108). For example, the sequencer 36 determines whether the voltage of the well line CPWELL at the time of interruption of the restart operation information Iar stored in the latch circuit 41 is less than or equal to the second threshold Vth2. If the voltage of the well line CPWELL at the time of interruption of the restart operation information Iar is less than or equal to the second threshold Vth2, the sequencer 36 determines that the erase operation was interrupted (hereinafter also referred to as the "second interruption process") within a single erase loop before the current interruption (first interruption process) when the voltage VERA2 was less than or equal to the second threshold Vth2. If the voltage of the well line CPWELL at the time of the interruption of the restart operation information Iar is higher than the second threshold Vth2, the sequencer 36 determines that, within a single erase loop, the erase operation interruption (second interruption process) was not performed before the current interruption when the voltage VERA2 was less than or equal to the second threshold Vth2.

[0144] If, within a single erase loop, the erase operation was not interrupted before the current interruption when the voltage VERA2 was below the second threshold Vth2 (S108_No), the PLC 36 reserves an erase voltage application operation as the operation to be performed when the operation is resumed (when the erase operation interrupted in the first interruption process is resumed) (S104). For example, the PLC 36 stores the "erasure voltage application operation" (meaning that the operation to be performed when the operation is resumed), the voltage of the well line CPWELL at the time of the interruption (voltage VERA2), the interruption time, the boost start voltage (the set value of voltage VERA), and the boost method as restart operation information Iar in the latch circuit 41. When the interrupt processing is completed, the PLC 36 resumes the erase operation (S106). That is, the PLC 36 executes the reserved erase voltage application operation.

[0145] On the other hand, if, within a single erase loop, the erase operation was interrupted before the current interruption when the voltage VERA2 was below the second threshold Vth2 (S108_Yes), the sequencer 36 determines whether or not the erase verify operation was performed at the time of the previous restart (when the erase operation interrupted by the second interruption process was restarted) (S109). For example, the sequencer 36 obtains restart operation information Iar from the latch circuit 41 and determines whether or not the erase verify operation was performed at the time of the previous restart based on the obtained restart operation information Iar.

[0146] If the erase verification operation was performed during the previous restart (S109_Yes), the PLC 36 reserves the erase voltage application operation as the operation for the current restart (S104). When the interrupt processing is completed, the PLC 36 resumes the erase operation (S106). In other words, the PLC 36 executes the reserved erase voltage application operation.

[0147] On the other hand, if the erase verification operation was not performed during the previous restart (S109_No), the PLC 36 reserves the erase verification operation as the operation for the current restart (S105). In other words, if, during a period within one erase loop other than the verify skip period pVS, the voltage VERA2 of the well line CPWELL when the PLC 36 receives the command "FFh" during the boost period pSU is less than or equal to the second threshold Vth2, and this condition is repeated twice, and the erase verification operation has not been performed, the PLC 36 reserves the erase verification operation as the operation for the current restart. When the interrupt processing is completed, the PLC 36 resumes the erase operation (S106). That is, the PLC 36 performs the reserved erase verification operation.

[0148] Thus, the sequencer 36 performs an erase voltage application operation or an erase verify operation when an interrupted erase operation is resumed, based on the value of the well line voltage VERA2 when it receives the command "FFh", and the number of times the voltage VERA2 has been interrupted within a single erase loop while being less than or equal to the second threshold Vth2. The command "FFh" is not invalidated.

[0149] If voltage VERA2 is higher than the second threshold Vth2, there is a relatively high probability that the threshold voltage of the memory cell MC will fall below the target voltage. Therefore, in this case, the sequencer 36 performs an erase verification operation upon restart.

[0150] When voltage VERA2 is below the second threshold Vth2, the likelihood of the memory cell MC's threshold voltage falling below the target voltage is lower compared to when voltage VERA2 is higher than the second threshold Vth2. However, if the erase operation is interrupted twice consecutively within a single erase loop when voltage VERA2 is below the second threshold Vth2, and the erase verification operation is not performed when the operation resumes after the previous interruption, it may not be possible to detect if the memory cell MC's threshold voltage falls below the target voltage during the erase voltage application operation at the time of the resumed operation after the previous interruption. In this case, the memory cell MC's threshold voltage may fall too low. Therefore, if the erase operation is not interrupted twice consecutively within a single erase loop when voltage VERA2 is below the second threshold Vth2, the sequencer 36 performs the erase voltage application operation when the operation resumes. If the erase operation is interrupted twice consecutively within a single erase loop when voltage VERA2 is below the second threshold Vth2, and the erase verification operation is performed when the operation resumes after the previous interruption, the sequencer 36 performs the erase voltage application operation when the operation resumes. Within a single erase loop, if the erase operation is interrupted twice consecutively when the voltage VERA2 is below the second threshold Vth2, and the erase verification operation was not performed when the operation resumed after the previous interruption, the sequencer 36 will perform the erase verification operation when the operation resumes.

[0151] Furthermore, if the voltage VERA2 of the well line CPWELL is less than or equal to the second threshold Vth2, and within a single erase loop, before the first interruption process, the second interruption process (where p is an integer greater than or equal to 2) has been executed p times when the erase operation is interrupted and the voltage VERA2 is less than or equal to the second threshold Vth2, then the erase voltage application operation or the erase verify operation may be executed when the erase operation interrupted by the first interruption process is resumed. Alternatively, within a single erase loop, if the second interruption process has not been executed p times before the first interruption process, and the voltage VERA2 is less than or equal to the second threshold Vth2, then the erase voltage application operation may be executed when the erase operation interrupted by the first interruption process is resumed.

[0152] (Timing chart) Figure 13 is a timing chart showing an example of the erase operation of the NAND flash memory 30. Figure 13 shows the case where, during one erase loop period other than the verify skip period pVS, the command "FFh" is received during the boost period pSU, and the well line voltage VERA2 at the time of receiving the command "FFh" is less than or equal to the second threshold Vth2. In Figure 13, the interrupt processing is, for example, a read operation. Note that in Figure 13, the voltages of the source line CELSRC, bit line BL, selection gate lines SGD and SGS, and word line WL are omitted. The waveforms of the source line CELSRC and bit line BL are substantially the same as the waveform of the well line CPWELL, as shown in Figure 7.

[0153] As shown in Figure 13, at time t41, when the sequencer 36 receives command set CS1 from the memory controller 10, the ready / busy signal RBn transitions from high level to low level. Based on the received command set CS1, the sequencer 36 starts the erase voltage application operation.

[0154] The operation during the period from time t41 to t42 is the same as the operation during the period from time t1 to t2 in Figure 7.

[0155] At time t42, the driver module 37 applies voltage VERA to the well line CPWELL and the source line CELSRC. The sense amplifier module 39 applies voltage VERA to the bit line BL. Upon application of voltage VERA, the voltages of the well line CPWELL, the source line CELSRC, and the bit line BL each increase.

[0156] Now, suppose that during the period from time t42 to t43, for example, the memory controller 10 receives a request from the host 2 for an interrupt processing of a read operation. In this case, the memory controller 10 sends, for example, the command "FFh" as the signal DQ to the NAND flash memory 30.

[0157] At time t43 (during the boost period pSU), when the sequencer 36 receives the command "FFh" from the memory controller 10, it terminates the processing of the setup period pES and starts the processing of the recovery period pER. At this time, the voltage VERA2 of the well line CPWELL is less than or equal to the second threshold Vth2.

[0158] At time t43, the driver module 37 applies voltage VSS to the well line CPWELL and the source line CELSRC. The sense amplifier module 39 applies voltage VSS to the bit line BL. Upon application of voltage VSS, the voltages of the well line CPWELL, the source line CELSRC, and the bit line BL decrease.

[0159] At time t44, when the voltages of the well line CPWELL, source line CELSRC, bit line BL, selection gate lines SGD and SGS, and word line WL are stepped down to voltage VSS, the ready / busy signal RBn transitions from L level to H level. This interrupts the erase voltage application operation and triggers interrupt processing.

[0160] After the interrupt processing is completed, during the period until time t45, the memory controller 10 sends, for example, command set CS2 as signal DQ to the NAND flash memory 30.

[0161] At time t45, when the sequencer 36 receives command set CS2 from the memory controller 10, the ready / busy signal RBn transitions from high level to low level. The sequencer 36 resumes the erase operation based on the received command set CS2. If the well line voltage VERA2 at the time of receiving the command "FFh" is less than or equal to the second threshold Vth2, the sequencer 36 performs an erase voltage application operation as the operation upon resumption.

[0162] The operation during the period from time t45 to t49 is the same as the operation during the period from time t1 to t5 in Figure 7. When the 10th period ends, the sequencer 36 deletes, for example, the restart operation information Iar and the applied time information Iat from the latch circuit 41.

[0163] Figure 14 is a timing chart showing another example of the erase operation of the NAND flash memory 30. Figure 14 shows the case where, during a period within one erase loop other than the verify skip period pVS, the command "FFh" is received during the boost period pSU, and the voltage VERA2 of the well line CPWELL at the time of receiving the command "FFh" is higher than the second threshold Vth2. In Figure 14, the interrupt processing is, for example, a read operation. Note that in Figure 14, the voltages of the source line CELSRC, bit line BL, selection gate lines SGD and SGS, and word line WL are omitted. The waveforms of the source line CELSRC and bit line BL are substantially the same as the waveform of the well line CPWELL, as shown in Figure 7.

[0164] As shown in Figure 14, at time t51, when the sequencer 36 receives command set CS1 from the memory controller 10, the ready / busy signal RBn transitions from high level to low level. When the ready / busy signal RBn transitions to low level, the sequencer 36 starts the erase voltage application operation based on the received command set CS1.

[0165] The operation during the period from time t51 to t54 is the same as the operation during the period from time t21 to t24 in Figure 11.

[0166] Now, suppose that during the period from time t53 to t54, for example, the memory controller 10 receives a request from the host 2 for an interrupt processing of a read operation. In this case, the memory controller 10 sends, for example, the command "FFh" as the signal DQ to the NAND flash memory 30.

[0167] At time t54 (during the boost period pSU), when the sequencer 36 receives the command "FFh" from the memory controller 10, it terminates the processing of the erase execution period pEW and starts the processing of the recovery period pER. At this time, the voltage VERA2 of the well line CPWELL is higher than the second threshold Vth2 and equal to the voltage VERA.

[0168] The operation during the period from time t54 to t55 is the same as the operation during the period from time t4 to t5 in Figure 7.

[0169] At time t55, when the voltages of the well line CPWELL, source line CELSRC, bit line BL, selection gate lines SGD and SGS, and word line WL are stepped down to voltage VSS, the ready / busy signal RBn transitions from L level to H level. This interrupts the erase voltage application operation and triggers interrupt processing.

[0170] After the interrupt processing is completed, during the period until time t56, the memory controller 10 sends, for example, the command set CS2 as the signal DQ to the NAND flash memory 30.

[0171] At time t56, when the PLC 36 receives command set CS2 from the memory controller 10, the ready / busy signal RBn transitions from high level to low level. The PLC 36 resumes the erase operation based on the received command set CS2. If the voltage VERA2 of the well line CPWELL when the command "FFh" is received is higher than the second threshold Vth2, the PLC 36 performs an erase verify operation as the operation upon resumption.

[0172] During the period from time t56 to t57, the sequencer 36 performs an erase and verify operation.

[0173] The operation during the period from time t57 to t61 is the same as the operation during the period from time t27 to t31 in Figure 11. After the 10th period ends, the sequencer 36 deletes, for example, the restart operation information Iar and the applied time information Iat from the latch circuit 41.

[0174] Figure 15 is a timing chart showing another example of the erase operation of the NAND flash memory 30. Figure 15 shows a case in which, during a period within one erase loop other than the verify skip period pVS, the erase operation is interrupted by receiving the command "FFh" during a boost period pSU, and then the command "FFh" is received again during the boost period pSU after the erase operation has resumed. In Figure 15, the interrupt processing is, for example, a read operation. Note that in Figure 15, the voltages of the source line CELSRC, bit line BL, selection gate lines SGD and SGS, and word line WL are omitted. The waveforms of the source line CELSRC and bit line BL are substantially the same as the waveform of the well line CPWELL, as shown in Figure 7.

[0175] As shown in Figure 15, at time t71, when the sequencer 36 receives command set CS1 from the memory controller 10, the ready / busy signal RBn transitions from the high level to the low level. Based on the received command set CS1, the sequencer 36 starts the erase voltage application operation.

[0176] The operation during the period from time t71 to t72 is the same as the operation during the period from time t1 to t2 in Figure 7.

[0177] At time t72, the driver module 37 applies voltage VERA to the well line CPWELL and the source line CELSRC. The sense amplifier module 39 applies voltage VERA to the bit line BL. Upon application of voltage VERA, the voltages of the well line CPWELL, the source line CELSRC, and the bit line BL each increase.

[0178] Now, suppose that during the period from time t72 to t73, for example, the memory controller 10 receives a request from the host 2 for an interrupt processing of a read operation. In this case, the memory controller 10 sends, for example, the command "FFh" as the signal DQ to the NAND flash memory 30.

[0179] At time t73 (during the boost period pSU), when the sequencer 36 receives the command "FFh" from the memory controller 10, it terminates the processing of the setup period pES and starts the processing of the recovery period pER. At this time, the voltage VERA2 of the well line CPWELL (hereinafter also referred to as "voltage VERA2a") is less than or equal to the second threshold Vth2.

[0180] At time t73, the driver module 37 applies voltage VSS to the well line CPWELL and the source line CELSRC. The sense amplifier module 39 applies voltage VSS to the bit line BL. Upon application of voltage VSS, the voltages of the well line CPWELL, the source line CELSRC, and the bit line BL decrease.

[0181] At time t74, when the voltages of the well line CPWELL, source line CELSRC, bit line BL, selection gate lines SGD and SGS, and word line WL are stepped down to voltage VSS, the ready / busy signal RBn transitions from L level to H level. This interrupts the erase voltage application operation and triggers interrupt processing.

[0182] After the interrupt processing is completed, during the period until time t75, the memory controller 10 sends, for example, command set CS2 as signal DQ to the NAND flash memory 30.

[0183] At time t75, when the PLC 36 receives command set CS2 from the memory controller 10, the ready / busy signal RBn transitions from high level to low level. The PLC 36 resumes the erase operation based on the received command set CS2. If the well line voltage VERA2 (VERA2a) at the time of receiving the command "FFh" is less than or equal to the second threshold Vth2, the PLC 36 performs an erase voltage application operation as the operation upon resumption.

[0184] The operation during the period from time t75 to t76 is the same as the operation during the period from time t1 to t2 in Figure 7.

[0185] At time t76, the driver module 37 applies voltage VERA to the well line CPWELL and the source line CELSRC. The sense amplifier module 39 applies voltage VERA to the bit line BL. Upon application of voltage VERA, the voltages of the well line CPWELL, the source line CELSRC, and the bit line BL each increase.

[0186] Now, suppose that during the period from time t76 to t77, for example, the memory controller 10 receives a request from the host 2 for an interrupt processing of a read operation. In this case, the memory controller 10 sends, for example, the command "FFh" as the signal DQ to the NAND flash memory 30.

[0187] At time t77 (during the boost period pSU), when the sequencer 36 receives the command "FFh" from the memory controller 10, it terminates the setup pES process and starts the recovery period pER process. At this time, the voltage VERA2 (hereinafter also referred to as "voltage VERA2b") of the well line CPWELL is less than or equal to the second threshold Vth2.

[0188] At time t77, the driver module 37 applies voltage VSS to the well line CPWELL and the source line CELSRC. The sense amplifier module 39 applies voltage VSS to the bit line BL. Upon application of voltage VSS, the voltages of the well line CPWELL, the source line CELSRC, and the bit line BL decrease.

[0189] At time t78, when the voltages of the well line CPWELL, source line CELSRC, bit line BL, selection gate lines SGD and SGS, and word line WL are stepped down to voltage VSS, the ready / busy signal RBn transitions from L level to H level. This interrupts the erase voltage application operation and triggers interrupt processing.

[0190] After the interrupt processing is completed, during the period until time t79, the memory controller 10 sends, for example, command set CS2 as signal DQ to the NAND flash memory 30.

[0191] At time t79, when the sequencer 36 receives command set CS2 from the memory controller 10, the ready / busy signal RBn transitions from H level to L level. The sequencer 36 resumes the erase operation based on the received command set CS2. If, during a period within one erase loop other than the verify skip period pVS, the well line voltage VERA2 at the time the sequencer 36 receives the command "FFh" during the boost period pSU is less than or equal to the second threshold Vth2, this condition is repeated twice, the sequencer 36 performs an erase verify operation as the restart operation. Alternatively, if, during a period within one erase loop other than the verify skip period pVS, the well line voltage VERA2 at the time the sequencer 36 receives the command "FFh" during the boost period pSU is less than or equal to the second threshold Vth2, this condition is repeated three or more times, the erase verify operation may be performed as the restart operation.

[0192] During the period from time t79 to t80, the sequencer 36 performs an erase-verify operation.

[0193] The operation during the period from time t80 to t84 is the same as the operation during the period from time t1 to t5 in Figure 7. When the 10th period ends, the sequencer 36 deletes, for example, the restart operation information Iar and the applied time information Iat from the latch circuit 41.

[0194] 2.2 Effects according to this embodiment According to the second embodiment, the same effects as the first embodiment are achieved.

[0195] Furthermore, in this embodiment, if the voltage VERA2 is less than or equal to the second threshold Vth2 (a voltage higher than the first threshold Vth1 and lower than the voltage VERA), the sequencer 36 performs an erase voltage application operation as an operation upon restart. If the voltage VERA2 is higher than the second threshold Vth2, the sequencer 36 performs an erase verify operation as an operation upon restart. Even if the voltage VERA2 is less than or equal to the second threshold Vth2, if the voltage VERA2 is less than or equal to the second threshold Vth2 twice during a period within one erase loop other than the verify skip period pVS, the sequencer 36 performs an erase verify operation as an operation upon restart. Therefore, according to this embodiment, it is possible to suppress the threshold voltage of the memory cell MC from dropping too low.

[0196] 3. Third Embodiment A semiconductor memory device according to the third embodiment will now be described. In the semiconductor memory device according to the third embodiment, the erase operation differs from that of the second embodiment. The following description will focus on the differences from the second embodiment.

[0197] 3.1 Erase operation (when an interruption instruction is received) This section describes the details of the erase operation when the sequencer 36 receives an interruption instruction during the erase operation.

[0198] (flowchart) Figure 16 is a flowchart illustrating an example of the erase operation of the NAND flash memory 30. As an example of the erase operation, Figure 16 shows the case where the sequencer 36 receives the command "FFh" during the erase operation. In Figure 16, steps S108 and S109 of Figure 12 shown in the second embodiment are replaced with steps S110 to S112.

[0199] If the voltage VERA2 is less than or equal to the second threshold Vth2 (S107_No), the sequencer 36 determines whether the voltage VERA2 is higher than the first threshold Vth1 (S110). The first threshold Vth1 is the same value as the first threshold Vth1 shown in the first embodiment. The second threshold Vth2 is the same value as the second threshold Vth2 shown in the second embodiment.

[0200] If the voltage VERA2 is high, less than or equal to the first threshold Vth1 (S110_No), the sequencer 36 reserves the operation to apply the erase voltage as the operation to restart (S104).

[0201] On the other hand, if the voltage VERA2 is higher than the first threshold Vth1 (S110_Yes), the sequencer 36 determines whether the erase operation was interrupted twice consecutively within a single erase loop at a voltage VERA2 that satisfies the condition Vth1 < voltage VERA2 ≤ second threshold Vth2 (S111). The determination method is, for example, the same as in the second embodiment.

[0202] If the erase operation has not been interrupted twice in a row within a single erase loop (S111_No), the sequencer 36 reserves the operation to apply the erase voltage as the operation to resume (S104).

[0203] On the other hand, if the erase operation is interrupted twice in a row within a single erase loop (S111_Yes), the PLC 36 determines whether or not the erase verify operation was performed between the previous interruption (second interruption process) and the current interruption (first interruption process) (S112). For example, the PLC 36 determines whether the end time of the erase verify operation information Ivfy stored in the latch circuit 41 is between the interruption time of the restart operation information Iar stored in the latch circuit 41 and the current time. If the end time of the erase verify operation information Ivfy is between the interruption time of the restart operation information Iar and the current time, the PLC 36 determines that the erase verify operation was performed between the previous interruption and the current interruption. If the end time of the erase verify operation information Ivfy is not between the interruption time of the restart operation information Iar and the current time, the PLC 36 determines that the erase verify operation was not performed between the previous interruption and the current interruption.

[0204] If an erase verification operation has been performed between the previous interruption and the current interruption (S112_Yes), the sequencer 36 reserves an erase voltage application operation as the operation to be performed when the system is restarted (S104).

[0205] On the other hand, if the erase verify operation has not been performed between the previous interruption and the current interruption (S112_No), the sequencer 36 reserves the erase verify operation as the operation to be performed when the system is resumed (S105).

[0206] Thus, the sequencer 36 performs an erase voltage application operation or an erase verify operation when an interrupted erase operation is resumed, based on the value of the well line CPWELL voltage VERA2 when it receives the command "FFh", the number of times the erase loop has been interrupted at a voltage VERA2 that satisfies the first threshold Vth1 < voltage VERA2 ≤ second threshold Vth2, and whether or not an erase verify operation was performed between the previous interruption and the current interruption. The command "FFh" is not invalidated.

[0207] If voltage VERA2 is higher than the second threshold Vth2, there is a relatively high probability that the threshold voltage of the memory cell MC will fall below the target voltage. Therefore, in this case, the sequencer 36 performs an erase verification operation upon restart.

[0208] When voltage VERA2 is higher than the first threshold Vth1 and less than or equal to the second threshold Vth2, the likelihood of the memory cell MC's threshold voltage falling below the target voltage is lower compared to when voltage VERA2 is higher than the second threshold Vth2. However, if the erase operation is interrupted twice consecutively within a single erase loop with first threshold Vth1 < voltage VERA2 ≤ second threshold Vth2, and the erase verification operation is not performed between the previous interruption and the current interruption, it may not be possible to detect if the memory cell MC's threshold voltage falls below the target voltage during the erase voltage application operation upon resumption after the previous interruption. In this case, the memory cell MC's threshold voltage may fall too low. Therefore, if the erase operation has not been interrupted twice consecutively within a single erase loop with first threshold Vth1 < voltage VERA2 ≤ second threshold Vth2, the sequencer 36 performs the erase voltage application operation upon resumption. If, within a single erase loop, the erase operation is interrupted twice consecutively when the first threshold Vth1 < voltage VERA2 ≤ second threshold Vth2, and the erase verification operation has been performed between the previous interruption and the current interruption, the sequencer 36 will perform the erase voltage application operation when the operation is resumed. If, within a single erase loop, the erase operation is interrupted twice consecutively when the first threshold Vth1 < voltage VERA2 ≤ second threshold Vth2, and the erase verification operation has not been performed between the previous interruption and the current interruption, the sequencer 36 will perform the erase verification operation when the operation is resumed.

[0209] If the voltage VERA2 is less than or equal to the first threshold Vth1, there is a relatively high probability that the threshold voltage of the memory cell MC will not decrease. Therefore, in this case, the sequencer 36 performs the erase voltage application operation when restarting.

[0210] Furthermore, if the voltage VERA2 of the well line CPWELL is higher than the first threshold Vth1 and less than or equal to the second threshold Vth2, and within a single erase loop, before the first interruption process, the second interruption process (where p is an integer greater than or equal to 2) has been executed p times when the erase operation is interrupted while the voltage VERA2 is higher than the first threshold Vth1 and less than or equal to the second threshold Vth2, then the erase voltage application operation or the erase verify operation may be executed when the erase operation interrupted by the first interruption process is resumed. Within a single erase loop, if the second interruption process has not been executed p times before the first interruption process, while the voltage VERA2 is higher than the first threshold Vth1 and less than or equal to the second threshold Vth2, then the erase voltage application operation may be executed when the erase operation interrupted by the first interruption process is resumed.

[0211] (Timing chart) Figure 17 is a timing chart showing an example of the erase operation of the NAND flash memory 30. Figure 17 shows a case in which, within one erase loop period other than the verify skip period pVS, the command "FFh" is received during the boost period pSU, and the well line voltage VERA2 at the time of receiving the command "FFh" is higher than the second threshold Vth2, and this is repeated twice. In Figure 17, the interrupt processing is, for example, a read operation. Note that in Figure 17, the voltages of the source line CELSRC, bit line BL, selection gate lines SGD and SGS, and word line WL are omitted. The waveforms of the source line CELSRC and bit line BL are substantially the same as the waveform of the well line CPWELL, as shown in Figure 7.

[0212] As shown in Figure 17, at time t91, when the sequencer 36 receives command set CS1 from the memory controller 10, the ready / busy signal RBn transitions from the high level to the low level. Based on the received command set CS1, the sequencer 36 starts the erase voltage application operation.

[0213] The operation during the period from time t91 to t92 is the same as the operation during the period from time t41 to t42 in Figure 13.

[0214] At time t92, the driver module 37 applies voltage VERA to the well line CPWELL and the source line CELSRC. The sense amplifier module 39 applies voltage VERA to the bit line BL. Upon application of voltage VERA, the voltages of the well line CPWELL, the source line CELSRC, and the bit line BL each increase.

[0215] Now, suppose that during the period from time t92 to t93, for example, the memory controller 10 receives a request from the host 2 for an interrupt processing of a read operation. In this case, the memory controller 10 sends, for example, the command "FFh" as the signal DQ to the NAND flash memory 30.

[0216] At time t93 (during the boost period pSU), when the sequencer 36 receives the command "FFh" from the memory controller 10, it terminates the processing of the setup period pES and starts the processing of the recovery period pER. At this time, the voltage VERA2 (voltage VERA2a) of the well line CPWELL is higher than the second threshold Vth2.

[0217] At time t93, the driver module 37 applies voltage VSS to the well line CPWELL and the source line CELSRC. The sense amplifier module 39 applies voltage VSS to the bit line BL. Upon application of voltage VSS, the voltages of the well line CPWELL, the source line CELSRC, and the bit line BL decrease.

[0218] At time t94, when the voltages of the well line CPWELL, source line CELSRC, bit line BL, selection gate lines SGD and SGS, and word line WL are stepped down to voltage VSS, the ready / busy signal RBn transitions from L level to H level. This interrupts the erase voltage application operation and triggers interrupt processing.

[0219] After the interrupt processing is completed, during the period until time t95, the memory controller 10 sends, for example, the command set CS2 as the signal DQ to the NAND flash memory 30.

[0220] At time t95, when the PLC 36 receives command set CS2 from the memory controller 10, the ready / busy signal RBn transitions from high level to low level. The PLC 36 resumes the erase operation based on the received command set CS2. If the well line voltage VERA2 at the time of receiving the command "FFh" is higher than the second threshold Vth2, the PLC 36 performs an erase verify operation as the operation upon resumption.

[0221] During the period from time t95 to t96, the sequencer 36 performs an erase-verify operation.

[0222] The operation during the period from time t96 to t101 is the same as the operation during the period from time t91 to t96.

[0223] Figure 18 is a timing chart showing another example of the erase operation of the NAND flash memory 30. Figure 18 shows a case in which, within one erase loop period other than the verify skip period pVS, the command "FFh" is received during the boost period pSU, and the well line voltage VERA2 at the time of receiving the command "FFh" is higher than the first threshold Vth1 and less than or equal to the second threshold Vth2, and this is repeated four times. In Figure 18, the interrupt processing is, for example, a read operation. Note that in Figure 18, the voltages of the source line CELSRC, bit line BL, selection gate lines SGD and SGS, and word line WL are omitted. The waveforms of the source line CELSRC and bit line BL are substantially the same as the waveform of the well line CPWELL, as shown in Figure 7.

[0224] As shown in Figure 18, at time t111, when the sequencer 36 receives command set CS1 from the memory controller 10, the ready / busy signal RBn transitions from high level to low level. When the ready / busy signal RBn transitions to low level, the sequencer 36 starts the erase voltage application operation based on the received command set CS1.

[0225] The operation during the period from time t111 to t112 is the same as the operation during the period from time t91 to t92 in Figure 17.

[0226] At time t112, the driver module 37 applies voltage VERA to the well line CPWELL and the source line CELSRC. The sense amplifier module 39 applies voltage VERA to the bit line BL. Upon application of voltage VERA, the voltages of the well line CPWELL, the source line CELSRC, and the bit line BL each increase.

[0227] Now, suppose that during the period from time t112 to t113, for example, the memory controller 10 receives a request from the host 2 for an interrupt processing of a read operation. In this case, the memory controller 10 sends, for example, the command "FFh" as the signal DQ to the NAND flash memory 30.

[0228] At time t113 (during the boost period pSU), when the sequencer 36 receives the command "FFh" from the memory controller 10, it terminates the processing of the erase execution period pEW and starts the processing of the recovery period pER. At this time, the voltage VERA2 (VERA2a) of the well line CPWELL is higher than the first threshold Vth1 and less than or equal to the second threshold Vth2.

[0229] At time t113, the driver module 37 applies voltage VSS to the well line CPWELL and the source line CELSRC. The sense amplifier module 39 applies voltage VSS to the bit line BL. Upon application of voltage VSS, the voltages of the well line CPWELL, the source line CELSRC, and the bit line BL decrease.

[0230] At time t114, when the voltages of the well line CPWELL, source line CELSRC, bit line BL, selection gate lines SGD and SGS, and word line WL are stepped down to voltage VSS, the ready / busy signal RBn transitions from L level to H level. This interrupts the erase voltage application operation and triggers interrupt processing.

[0231] After the interrupt processing is completed, during the period until time t115, the memory controller 10 sends, for example, command set CS2 as signal DQ to the NAND flash memory 30.

[0232] At time t115, when the sequencer 36 receives command set CS2 from the memory controller 10, the ready / busy signal RBn transitions from high level to low level. The sequencer 36 resumes the erase operation based on the received command set CS2. When the command "FFh" is received, the voltage VERA2 (voltage VERA2a) of the well line CPWELL is higher than the first threshold Vth1 and less than or equal to the second threshold Vth2, and within one erase loop, if the erase operation has not been interrupted twice consecutively with first threshold Vth1 < voltage VERA2 ≤ second threshold Vth2, the sequencer 36 performs the erase voltage application operation as the operation upon resumption.

[0233] The operation during the period from time t115 to t119 is the same as the operation during the period from time t111 to t115.

[0234] At time t119, when the PLC 36 receives command set CS2 from the memory controller 10, the ready / busy signal RBn transitions from H level to L level. The PLC 36 resumes the erase operation based on the received command set CS2. When the command "FFh" is received, the voltage VERA2 (voltage VERA2b) of the well line CPWELL is higher than the first threshold Vth1 and less than or equal to the second threshold Vth2, and within one erase loop, the erase operation has been interrupted twice consecutively with first threshold Vth1 < voltage VERA2 ≤ second threshold Vth2, and the erase verify operation has not been performed since the previous interruption, the PLC 36 performs the erase verify operation as the operation upon resumption.

[0235] During the period from time t119 to t120, the sequencer 36 performs an erase-verify operation.

[0236] The operation during the period from time t120 to t124 is the same as the operation during the period from time t111 to t115.

[0237] At time t124, when the sequencer 36 receives command set CS2 from the memory controller 10, the ready / busy signal RBn transitions from H level to L level. The sequencer 36 resumes the erase operation based on the received command set CS2. When the command "FFh" is received, the voltage VERA2 (voltage VERA2c) of the well line CPWELL is higher than the first threshold Vth1 and less than or equal to the second threshold Vth2, and within one erase loop, the erase operation has been interrupted twice consecutively with first threshold Vth1 < voltage VERA2 ≤ second threshold Vth2, and an erase verify operation has been performed since the previous interruption, the sequencer 36 performs an erase voltage application operation as the operation upon resumption.

[0238] The operation during the period from time t124 to t128 is the same as the operation during the period from time t111 to t115.

[0239] At time t128, when the sequencer 36 receives command set CS2 from the memory controller 10, the ready / busy signal RBn transitions from high level to low level. The sequencer 36 resumes the erase operation based on the received command set CS2. When the command "FFh" is received, the voltage VERA2 (voltage VERA2d) of the well line CPWELL is higher than the first threshold Vth1 and less than or equal to the second threshold Vth2, and within one erase loop, the erase operation has been interrupted twice consecutively with first threshold Vth1 < voltage VERA2 ≤ second threshold Vth2, and the erase verify operation has not been performed since the previous interruption, the sequencer 36 performs the erase verify operation as the operation upon resumption.

[0240] During the period from time t128 to t129, the sequencer 36 performs an erase and verify operation.

[0241] 3.2 Effects according to this embodiment According to the third embodiment, the same effects as the first embodiment are achieved.

[0242] Furthermore, in this embodiment, if the voltage VERA2 is higher than the second threshold Vth2, the sequencer 36 performs an erase verification operation as the operation upon restart. If the voltage VERA2 is less than or equal to the first threshold Vth1 (a voltage lower than the second threshold Vth2), the sequencer 36 performs an erase voltage application operation as the operation upon restart. If the voltage VERA2 is higher than the first threshold Vth1 and less than or equal to the second threshold Vth2, the following operations are performed: Within a single erase loop, if the erase operation has not been interrupted twice consecutively with the first threshold Vth1 < voltage VERA2 ≤ second threshold Vth2, the sequencer 36 performs an erase voltage application operation upon restart. Within a single erase loop, if the erase operation has been interrupted twice consecutively with the first threshold Vth1 < voltage VERA2 ≤ second threshold Vth2, and an erase verification operation has been performed between the previous interruption and the current interruption, the sequencer 36 performs an erase voltage application operation upon the current restart. Within a single erase loop, if the erase operation is interrupted twice consecutively when the first threshold Vth1 < voltage VERA2 ≤ second threshold Vth2, and the erase verification operation has not been performed between the previous interruption and the current interruption, the sequencer 36 performs the erase verification operation when the operation is resumed. Therefore, according to this embodiment, it is possible to suppress the threshold voltage of the memory cell MC from dropping too low while suppressing the number of erase verification operations.

[0243] 3.3 First Variation A semiconductor memory device according to the first modification of the third embodiment will be described. In the semiconductor memory device according to the first modification of the third embodiment, the erase operation differs from that of the third embodiment. The following description will focus on the differences from the third embodiment.

[0244] 3.3.1 Erase operation (when an interruption instruction is received) This section describes the details of the erase operation when the sequencer 36 receives an interruption instruction during the erase operation.

[0245] (flowchart) Figure 19 is a flowchart illustrating an example of the erase operation of the NAND flash memory 30. As an example of the erase operation, Figure 19 shows the case where the sequencer 36 receives the command "FFh" during the erase operation. In Figure 19, steps S111 and S112 in Figure 16, shown in the third embodiment, are replaced with steps S108 and S109 in Figure 12, shown in the second embodiment.

[0246] If the voltage VERA2 is less than or equal to the second threshold Vth2 (S107_No), the sequencer 36 determines whether the voltage VERA2 is higher than the first threshold Vth1 (S110).

[0247] If the voltage VERA2 is higher than the first threshold Vth1 (S110_Yes), the sequencer 36 determines whether the erase operation was interrupted within a single erase loop before the current interruption when the voltage VERA2 was between the first threshold Vth1 and the second threshold Vth2 (S108). The determination method is the same as in the second embodiment, for example.

[0248] Within a single erase loop, if the voltage VERA2 was not interrupted before the current interruption when the first threshold Vth1 < voltage VERA2 ≤ second threshold Vth2 (S108_No), the sequencer 36 reserves the erase voltage application operation as the operation to be performed when the operation is resumed (when the erase operation interrupted by the first interruption process is resumed) (S104).

[0249] On the other hand, if, within a single erase loop, the erase operation was interrupted before the current interruption when the voltage VERA2 was at the first threshold Vth1 < voltage VERA2 ≤ second threshold Vth2 (S108_Yes), the sequencer 36 determines whether or not the erase verification operation was performed at the time of the previous restart (when the erase operation interrupted in the second interruption process was restarted) (S109).

[0250] If the erase verification operation was performed during the previous restart (S109_Yes), the sequencer 36 reserves the erase voltage application operation as the operation for the current restart (S104).

[0251] On the other hand, if the erase verify operation was not performed during the previous restart (S109_No), the PLC 36 reserves the erase verify operation as the operation for the current restart (S105). In other words, if, during a period within one erase loop other than the verify skip period pVS, the voltage VERA2 of the well line CPWELL when the PLC 36 receives the command "FFh" during the boost period pSU is twice equal to the first threshold Vth1 < voltage VERA2 ≤ second threshold Vth2, and the erase verify operation has not been performed, the PLC 36 reserves the erase verify operation as the operation for the current restart.

[0252] Thus, the sequencer 36 performs an erase voltage application operation or an erase verify operation when an interrupted erase operation is resumed, based on the value of the well line voltage VERA2 when it receives the command "FFh", and the number of times the voltage VERA2 has been interrupted within a single erase loop where the first threshold Vth1 < voltage VERA2 ≤ second threshold Vth2. The command "FFh" is not invalidated.

[0253] If voltage VERA2 is higher than the second threshold Vth2, there is a relatively high probability that the threshold voltage of the memory cell MC will fall below the target voltage. Therefore, in this case, the sequencer 36 performs an erase verification operation upon restart.

[0254] When voltage VERA2 is higher than the first threshold Vth1 and less than or equal to the second threshold Vth2, the likelihood of the memory cell MC's threshold voltage falling below the target voltage is lower compared to when voltage VERA2 is higher than the second threshold Vth2. However, if the erase operation is interrupted twice consecutively within a single erase loop with first threshold Vth1 < voltage VERA2 ≤ second threshold Vth2, and the erase verification operation is not performed between the previous interruption and the current interruption, it may not be possible to detect if the memory cell MC's threshold voltage falls below the target voltage during the erase voltage application operation upon resumption after the previous interruption. In this case, the memory cell MC's threshold voltage may fall too low. Therefore, within a single erase loop, if voltage VERA2 is not interrupted twice consecutively with first threshold Vth1 < voltage VERA2 ≤ second threshold Vth2, the sequencer 36 performs the erase voltage application operation upon resumption. If, within a single erase loop, the erase operation is interrupted twice consecutively when the voltage VERA2 is between the first threshold Vth1 < voltage VERA2 ≤ second threshold Vth2, and the erase verification operation was performed when the operation resumed after the previous interruption, the sequencer 36 will perform the erase voltage application operation when the operation resumes. If, within a single erase loop, the erase operation is interrupted twice consecutively when the voltage VERA2 is between the first threshold Vth1 < voltage VERA2 ≤ second threshold Vth2, and the erase verification operation was not performed when the operation resumed after the previous interruption, the sequencer 36 will perform the erase verification operation when the operation resumes.

[0255] If the voltage VERA2 is less than or equal to the first threshold Vth1, there is a relatively high probability that the threshold voltage of the memory cell MC will not decrease. Therefore, in this case, the sequencer 36 performs the erase voltage application operation when restarting.

[0256] Furthermore, if the voltage VERA2 of the well line CPWELL is higher than the first threshold Vth1 and less than or equal to the second threshold Vth2, and within a single erase loop, before the first interruption process, the second interruption process (where p is an integer greater than or equal to 2) has been executed p times when the erase operation is interrupted while the voltage VERA2 is higher than the first threshold Vth1 and less than or equal to the second threshold Vth2, then the erase voltage application operation or the erase verify operation may be executed when the erase operation interrupted by the first interruption process is resumed. Within a single erase loop, if the second interruption process has not been executed p times before the first interruption process, while the voltage VERA2 is higher than the first threshold Vth1 and less than or equal to the second threshold Vth2, then the erase voltage application operation may be executed when the erase operation interrupted by the first interruption process is resumed.

[0257] (Timing chart) Figure 20 is a timing chart showing an example of the erase operation of the NAND flash memory 30. Figure 20 shows the case where, during one erase loop period other than the verify skip period pVS, the command "FFh" is received during the boost period pSU, and the well line voltage VERA2 at the time of receiving the command "FFh" is higher than the first threshold Vth1 and less than or equal to the second threshold Vth2. In Figure 20, the interrupt processing is, for example, a read operation. Note that in Figure 20, the voltages of the source line CELSRC, bit line BL, selection gate lines SGD and SGS, and word line WL are omitted. The waveforms of the source line CELSRC and bit line BL are substantially the same as the waveform of the well line CPWELL, as shown in Figure 7.

[0258] As shown in Figure 20, at time t131, when the sequencer 36 receives command set CS1 from the memory controller 10, the ready / busy signal RBn transitions from the high level to the low level. Based on the received command set CS1, the sequencer 36 starts the erase voltage application operation.

[0259] The operation during the period from time t131 to t135 is the same as the operation during the period from time t111 to t115 in Figure 18.

[0260] At time t135, when the sequencer 36 receives command set CS2 from the memory controller 10, the ready / busy signal RBn transitions from the high level to the low level. The sequencer 36 resumes the erase operation based on the received command set CS2. When the command "FFh" is received, the voltage VERA2 (VERA2a) of the well line CPWELL is higher than the first threshold Vth1 and less than or equal to the second threshold Vth2, and within one erase loop, if the erase operation has not been interrupted twice consecutively with the first threshold Vth1 < voltage VERA2 ≤ second threshold Vth2, the sequencer 36 performs the erase voltage application operation as the operation upon resumption.

[0261] The operation during the period from time t135 to t139 is the same as the operation during the period from time t45 to t49 in Figure 13.

[0262] During the period from time t139 to t140, the sequencer 36 performs an erase-verify operation. When the erase-verify operation is completed, the ready / busy signal RBn transitions from the low level to the high level.

[0263] At time t141, when the sequencer 36 receives command set CS1 from the memory controller 10, the ready / busy signal RBn transitions from high level to low level. Based on the received command set CS1, the sequencer 36 starts the erase voltage application operation.

[0264] The operation during the period from time t141 to t145 is the same as the operation during the period from time t131 to t135.

[0265] At time t145, when the sequencer 36 receives the command set CS2 from the memory controller 10, the ready / busy signal RBn transitions from the H level to the L level. The sequencer 36 resumes the erasing operation based on the received command set CS2. When the voltage VERA2 (VERA2c) of the well line CPWELL when receiving the command "FFh" is higher than the first threshold value Vth1 and not more than the second threshold value Vth2, and within one erasing loop, when the erasing operation has not been interrupted twice continuously with the first threshold value Vth1 < voltage VERA2 ≤ the second threshold value Vth2, the sequencer 36 executes the erase voltage application operation as the operation at the time of resumption.

[0266] 3.3.2 Effects according to this modification According to this modification, the same effects as those of the first embodiment are achieved.

[0267] Also, in this modification, when the voltage VERA2 is higher than the second threshold value Vth2, the sequencer 36 executes the erase verification operation as the operation at the time of resumption. When the voltage VERA2 is not more than the first threshold value Vth1 (a voltage lower than the second threshold value Vth2), the sequencer 36 executes the erase voltage application operation as the operation at the time of resumption. When the voltage VERA2 is higher than the first threshold value Vth1 and not more than the second threshold value Vth2, the sequencer 36 executes the erase voltage application operation as the operation at the time of resumption. Even when the voltage VERA2 is higher than the first threshold value Vth1 and not more than the second threshold value Vth2, if the case where the voltage VERA2 is higher than the first threshold value Vth1 and not more than the second threshold value Vth2 is repeated twice in a period within one erasing loop other than the verification skip period pVS, the sequencer 36 executes the erase verification operation as the operation at the time of resumption. Therefore, according to this modification, it is possible to suppress the number of erase verification operations and suppress the threshold voltage of the memory cell MC from decreasing too much.

[0268] 3.4 Second modification A semiconductor memory device according to the second modification of the third embodiment will be described. In the semiconductor memory device according to the second modification of the third embodiment, the erasing operation is different from that of the third embodiment. In the following description, the differences from the third embodiment will be mainly described.

[0269] 3.4.1 Erase operation (when an interruption instruction is received) This section describes the details of the erase operation when the sequencer 36 receives an interruption instruction during the erase operation.

[0270] (flowchart) Figure 21 is a flowchart illustrating an example of the erase operation of the NAND flash memory 30. As an example of the erase operation, Figure 21 shows the case where the sequencer 36 receives the command "FFh" during the erase operation. In Figure 21, steps S107 and S110 in Figure 16, shown in the third embodiment, are omitted, and steps S111 and S112 in Figure 16 are replaced by steps S108 and S109 in Figure 12, shown in the second embodiment.

[0271] If the boost period pSU is in progress (S102_Yes), the PLC 36 determines whether the erase operation was interrupted before the current interruption (first interruption process) within a single erase loop (S108). For example, the PLC 36 determines whether the restart operation information Iar is stored in the latch circuit 41. If the restart operation information Iar is stored, the PLC 36 determines that the erase operation interruption (second interruption process) was performed before the current interruption (first interruption process) within a single erase loop. If the restart operation information Iar is not stored, the PLC 36 determines that the erase operation interruption (second interruption process) was not performed before the current interruption (first interruption process) within a single erase loop.

[0272] If the erase operation has not been interrupted within a single erase loop prior to the current interruption (S108_No), the PLC 36 reserves an erase voltage application operation as the operation to be performed when the erase operation interrupted in the first interruption process is resumed (S104). For example, the PLC 36 stores the "erasure voltage application operation" (meaning that the operation to be performed when the operation is resumed), the voltage of the well line CPWELL at the time of interruption (voltage VERA2), the interruption time, the boost start voltage (the set value of voltage VERA), and the boost method as restart operation information Iar in the latch circuit 41. When the interrupt processing is completed, the PLC 36 resumes the erase operation (S106). That is, the PLC 36 executes the reserved erase voltage application operation.

[0273] On the other hand, if an erase operation was interrupted within a single erase loop prior to the current interruption (S108_Yes), the sequencer 36 determines whether or not an erase verify operation was performed at the time of the previous restart (when the erase operation interrupted in the second interruption process was restarted) (S109). For example, the sequencer 36 obtains restart operation information Iar from the latch circuit 41 and determines whether or not an erase verify operation was performed at the time of the previous restart based on the obtained restart operation information Iar.

[0274] If the erase verification operation was performed during the previous restart (S109_Yes), the PLC 36 reserves the erase voltage application operation as the operation for the current restart (S104). When the interrupt processing is completed, the PLC 36 resumes the erase operation (S106). In other words, the PLC 36 executes the reserved erase voltage application operation.

[0275] On the other hand, if the erase verify operation was not performed during the previous restart (S109_No), the PLC 36 reserves the erase verify operation as the operation for the current restart (S105). In other words, if the PLC 36 receives the command "FFh" during the boost period pSU twice during a period within one erase loop other than the verify skip period pVS, the PLC 36 reserves the erase verify operation as the operation for the current restart. For example, the PLC 36 stores "erase verify operation," which means that the operation for the restart is an erase verify operation, as restart operation information Iar in the latch circuit 41. When the interrupt processing is completed, the PLC 36 restarts the erase operation (S106). That is, the PLC 36 executes the reserved erase verify operation.

[0276] In this way, the sequencer 36 performs either an erase voltage application operation or an erase verify operation when an interrupted erase operation is resumed, based on the number of times it was interrupted within a single erase loop. The command "FFh" is not disabled.

[0277] If the erase operation is interrupted twice consecutively within a single erase loop, and the erase verification operation is not performed when the operation resumes after the previous interruption, it may not be possible to detect if the threshold voltage of the memory cell MC falls below the target voltage during the erase voltage application operation when the operation resumes after the previous interruption. In this case, the threshold voltage of the memory cell MC may fall too low. Therefore, if the erase operation is not interrupted twice consecutively within a single erase loop, the PLC 36 performs the erase voltage application operation when the operation resumes. If the erase operation is interrupted twice consecutively within a single erase loop, and the erase verification operation is performed when the operation resumes after the previous interruption, the PLC 36 performs the erase voltage application operation when the operation resumes. If the erase operation is interrupted twice consecutively within a single erase loop, and the erase verification operation is not performed when the operation resumes after the previous interruption, the PLC 36 performs the erase verification operation when the operation resumes.

[0278] Furthermore, if a second interruption process (where p is an integer greater than or equal to 2) has been executed p times before the first interruption process to interrupt the erase operation, the erase voltage application operation or the erase verification operation may be executed when the erase operation interrupted by the first interruption process is resumed. If the second interruption process has not been executed p times before the first interruption process, the erase voltage application operation may be executed when the erase operation interrupted by the first interruption process is resumed.

[0279] (Timing chart) The timing chart showing an example of the erase operation of the NAND flash memory 30 according to this modified example is the same as that shown in Figures 13 to 15 in the second embodiment. In this modified example, if the sequencer 36 receives the command "FFh" during the boost period pSU twice during a period within one erase loop other than the verify skip period pVS, the sequencer 36 performs an erase verify operation as the operation upon restart. Alternatively, the erase verify operation may be performed as the operation upon restart if the sequencer 36 receives the command "FFh" during the boost period pSU three or more times during a period within one erase loop other than the verify skip period pVS.

[0280] 3.4.2 Effects of this modified example This modified version achieves the same effects as the first embodiment.

[0281] Furthermore, in this modified example, if the sequencer 36 receives the command "FFh" during the boost period pSU twice within one erase loop period other than the verify skip period pVS, the sequencer 36 performs an erase verify operation as the operation upon restart. Therefore, according to this embodiment, it is possible to suppress the threshold voltage of the memory cell MC from dropping too low.

[0282] 4. Variations, etc. As described above, the semiconductor memory device according to the embodiment includes a memory cell (MC) including a transistor, a wiring (CPWELL), and a first circuit (36). The first circuit (36) executes an erasing operation including an erasing voltage application operation of applying an erasing voltage (VERA) between the gate of the transistor and the channel of the transistor via the wiring (CPWELL), and an erasing verification operation of determining the threshold voltage of the memory cell (MC). During the erasing operation, when the first circuit (36) receives a first command (FFh), it executes a first interruption process of interrupting the erasing operation. The first circuit (36) executes an erasing voltage application operation or an erasing verification operation at the restart of the erasing operation interrupted by the first interruption process based on the voltage value (VERA1 / VERA2) of the wiring (CPWELL) when the first command (FFh) is received.

[0283] Note that the embodiment is not limited to the form described above, and various modifications are possible.

[0284] Also, the order of the processes in the flowchart described in the above embodiment can be changed as much as possible.

[0285] Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the gist of the invention. These embodiments and their modifications are included in the scope and gist of the invention, and are also included in the invention described in the claims and the equivalent scope thereof.

Description of Reference Numerals

[0286] 1... Memory system, 2... Host, 10... Memory controller, 11... Host interface circuit, 12... Processor, 13... Buffer memory, 14... ECC circuit, 15... ROM, 16... RAM, 17... NAND interface circuit, 30... NAND type flash memory, 31... Memory cell array, 32... Input / output circuit, 33... Logic control circuit, 34... Ready / Busy circuit, 35... Register, 35A... Command register, 35B... Address register, 35C... Status register, 36... Sequencer, 37... Driver module, 38... Row decoder module, 39... Sense amplifier module, 50... p-type well region, 51 - 53... Wiring layers, 54... Core member, 55... Semiconductor layer, 56 - 58... Insulation layers, 59... Conductor, 60... Contact plug, 61... Wiring layer, 62... n + -type diffusion region, 63... Contact plug, 64... Wiring layer, 65... p + -type diffusion region, 66... Contact plug, 67... Wiring layer

Claims

1. A memory cell containing a transistor, Wiring and, A first circuit that performs an erase operation, which includes an erase voltage application operation that applies an erase voltage between the gate and channel of the transistor via the aforementioned wiring, and an erase verify operation that determines the threshold voltage of the memory cell. Equipped with, The first circuit is, If a first command is received during the erase operation, a first interruption process is executed to interrupt the erase operation. Based on the voltage value of the wiring when the first command is received, the erase voltage application operation or the erase verification operation is executed when the erase operation interrupted in the first interruption process is resumed. Semiconductor memory device.

2. The semiconductor memory device according to claim 1, wherein the timing of receiving the first command is during the erase voltage application operation.

3. The first circuit is, If the voltage value of the wiring is higher than the first threshold, the erase verification operation is executed when the erase operation that was interrupted in the first interruption process is resumed. If the voltage value of the wiring is less than or equal to the first threshold, the erase voltage application operation is executed when the erase operation, which was interrupted in the first interruption process, is resumed. The semiconductor memory device according to claim 1.

4. The first circuit is, If the voltage value of the wiring is higher than the second threshold, the erase verification operation is executed when the erase operation, which was interrupted in the first interruption process, is resumed. If the voltage value of the wiring is less than or equal to the second threshold, If a second interruption process is performed before the first interruption process and the voltage value of the wiring is less than or equal to the second threshold, the erase voltage application operation or the erase verification operation is performed when the erase operation interrupted by the first interruption process is resumed. If the first interruption process has not yet occurred and the voltage value of the wiring is less than or equal to the second threshold, the erase voltage application operation will be performed when the erase operation interrupted by the first interruption process is resumed. The semiconductor memory device according to claim 1.

5. The first circuit is, If the voltage value of the wiring is less than or equal to the second threshold, If the second interruption process is performed before the first interruption process and the voltage value of the wiring is less than or equal to the second threshold, and the erase verification operation is performed when the erase operation interrupted by the second interruption process is resumed, then the erase voltage application operation is performed when the erase operation interrupted by the first interruption process is resumed. The second interruption process is performed when it is before the first interruption process and the voltage value of the wiring is less than or equal to the second threshold, and if the erase verification operation is not performed when the erase operation interrupted by the second interruption process is resumed, the erase verification operation is performed when the erase operation interrupted by the first interruption process is resumed. The semiconductor memory device according to claim 4.

6. The first circuit is, If the voltage value of the wiring is less than or equal to the first threshold, the erase voltage application operation is executed when the erase operation that was interrupted in the first interruption process is resumed. If the voltage value of the wiring is higher than the first threshold and less than or equal to the second threshold, If a second interruption process is performed before the first interruption process, and the voltage value of the wiring is higher than the first threshold and less than or equal to the second threshold, then the erase voltage application operation or the erase verification operation is performed when the erase operation interrupted by the first interruption process is resumed. If the second interruption process has not been performed before the first interruption process, and the voltage value of the wiring is higher than the first threshold and less than or equal to the second threshold, then the erase voltage application operation will be performed when the erase operation interrupted by the first interruption process is resumed. If the voltage value of the wiring is higher than the second threshold, the erase verify operation is executed when the erase operation, which was interrupted in the first interruption process, is resumed. The semiconductor memory device according to claim 1.

7. The first circuit is, If the voltage value of the wiring is higher than the first threshold and less than or equal to the second threshold, If the first interruption process has not yet occurred and the voltage value of the wiring is higher than the first threshold and less than or equal to the second threshold, the second interruption process is executed. If the erase verification operation has been performed between the second interruption process and the first interruption process, the erase voltage application operation is executed when the erase operation, which was interrupted by the first interruption process, is resumed. The second interruption process is performed when it is before the first interruption process and the voltage value of the wiring is higher than the first threshold and less than or equal to the second threshold. If the erase verification operation has not been performed between the second interruption process and the first interruption process, the erase verification operation is performed when the erase operation, which was interrupted by the first interruption process, is resumed. The semiconductor memory device according to claim 6.

8. The first circuit is, If the voltage value of the wiring is higher than the first threshold and less than or equal to the second threshold, If the first interruption process has not yet occurred and the voltage value of the wiring is higher than the first threshold and less than or equal to the second threshold, the second interruption process is executed. If the erase verification operation is being performed when the erase operation interrupted by the second interruption process is resumed, the erase voltage application operation is being executed when the erase operation interrupted by the first interruption process is resumed. The second interruption process is performed when it is before the first interruption process and the voltage value of the wiring is higher than the first threshold and less than or equal to the second threshold; if the erase verification operation is not performed when the erase operation interrupted by the second interruption process is resumed, the erase verification operation is performed when the erase operation interrupted by the first interruption process is resumed. The semiconductor memory device according to claim 6.

9. A memory cell containing a transistor, Wiring and, A first circuit that performs an erase operation, which includes an erase voltage application operation that applies an erase voltage between the gate and channel of the transistor via the aforementioned wiring, and an erase verify operation that determines the threshold voltage of the memory cell. Equipped with, The first circuit is, If a first command is received during the erase operation, a first interruption process is executed to interrupt the erase operation. If a second interruption process is performed to interrupt the erase operation before the first interruption process, the erase voltage application operation or the erase verification operation is performed when the erase operation interrupted by the first interruption process is resumed. If the second interruption process is not performed before the first interruption process, the erase voltage application operation is performed when the erase operation interrupted by the first interruption process is resumed. Semiconductor memory device.

10. The first circuit is, If the second interruption process is performed before the first interruption process, and the erase verification operation is performed when the erase operation interrupted by the second interruption process is resumed, then the erase voltage application operation is performed when the erase operation interrupted by the first interruption process is resumed. If the second interruption process is executed before the first interruption process, and the erase verification operation is not executed when the erase operation interrupted by the second interruption process is resumed, then the erase verification operation is executed when the erase operation interrupted by the first interruption process is resumed. The semiconductor memory device according to claim 9.

11. The first circuit is, If the voltage value of the wiring is higher than the second threshold, the erase verification operation is executed when the erase operation, which was interrupted in the first interruption process, is resumed. If the voltage value of the wiring is less than or equal to the second threshold, If the second interruption process, which interrupts the erase operation, has been executed n times (where n is an integer of 2 or more) before the first interruption process and when the voltage value of the wiring is less than or equal to the second threshold, then when the erase operation interrupted by the first interruption process is resumed, the erase voltage application operation or the erase verification operation is executed. If the first interruption process has not yet occurred and the voltage value of the wiring is less than or equal to the second threshold, the erase voltage application operation will be executed when the erase operation interrupted by the first interruption process is resumed. The semiconductor memory device according to claim 1.

12. The first circuit is, If the voltage value of the wiring is less than or equal to the first threshold, the erase voltage application operation is executed when the erase operation that was interrupted in the first interruption process is resumed. If the voltage value of the wiring is higher than the first threshold and less than or equal to the second threshold, If the second interruption process, which interrupts the erase operation, has been executed n times (where n is an integer of 2 or more) before the first interruption process, and the voltage value of the wiring is higher than the first threshold and less than or equal to the second threshold, then the erase voltage application operation or the erase verification operation is executed when the erase operation interrupted by the first interruption process is resumed. If the second interruption process has not been performed n times while the voltage value of the wiring is higher than the first threshold and less than or equal to the second threshold, the erase voltage application operation is performed when the erase operation interrupted by the first interruption process is resumed. If the voltage value of the wiring is higher than the second threshold, the erase verify operation is executed when the erase operation, which was interrupted in the first interruption process, is resumed. The semiconductor memory device according to claim 1.

13. The first circuit is, If a second interruption process (where n is an integer of 2 or more) that interrupts the erase operation is performed n times before the first interruption process, the erase voltage application operation or the erase verification operation is performed when the erase operation interrupted by the first interruption process is resumed. If the second interruption process has not been executed n times prior to the first interruption process, the erase voltage application operation is executed when the erase operation interrupted by the first interruption process is resumed. The semiconductor memory device according to claim 9.

14. The first command is not invalidated. The semiconductor memory device according to claim 1.

15. If the erase operation is interrupted during the first period of the erase execution period in which the erase voltage is applied in the erase voltage application operation, After the erase operation is resumed, in the erase voltage application operation, the erase execution period starts from the first period. The semiconductor memory device according to claim 1.

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