Data Fabric Clock Switching

Abstract

The memory controller couples to a data fabric clock domain and to a physical layer interface circuit PHY clock domain. A first interface circuit adapts transfers between the data fabric clock domain (FCLK) and the memory controller clock domain, and a second interface circuit couples the memory controller to the PHY clock domain. The power controller responds to the power state change request by sending a command to the second interface circuit to change parameters of the memory system and update a set of timing parameters of the memory controller according to a selected power state of a plurality of power states. The power controller responds to the request to synchronize to a new frequency of the FCLK domain by changing a set of timing parameters of the clock interface circuit without changing the set of timing parameters of the memory system or the selected power state.

Description

Background Art

[0001] Computer systems generally use inexpensive and high-density dynamic random access memory (DRAM) chips for main memory. Most DRAM chips sold today are compatible with various double data rate (DDR) DRAM standards promulgated by the Joint Electron Devices Engineering Council (JEDEC).

[0002] A memory controller is a digital circuit that manages the flow of data going in and out of DRAM via a memory bus. Known memory controllers receive memory access requests from a host system, queue them, and dispatch them to DRAM in the order selected by an arbiter. Memory controllers are typically instructed to change their power states according to a defined group of power states in order to meet the memory usage requirements of a computer system while saving power as much as possible. In many cases, the power state is controlled according to specifications such as the Advanced Configuration and Power Interface (ACPI) specification, which is a power management and configuration standard for computers such as personal computers (PCs) and servers. ACPI enables a computer operating system to manage the power consumed in various devices by changing the operating mode of the device from a limited set of modes that may include different operating frequencies, different supply voltages, and different operating modes.

Brief Description of the Drawings

[0003] [Figure 1] It is a block diagram of an accelerated processing unit (APU) and a memory system known in the prior art. [Figure 2] It is a block diagram of a memory controller suitable for use in an APU similar to FIG. 1 according to some embodiments. [Figure 3] This is a block diagram of several elements of the APU for providing clock domain signals and synchronization across clock domains in the memory channel controller. [Figure 4] This is a flowchart of a process for changing the power state in a memory controller according to several embodiments. [Figure 5] This is a flowchart of a process for responding to a power state command, according to several embodiments. [Modes for carrying out the invention]

[0004] In the following description, the use of the same reference numerals in different drawings indicates the same or identical items. Unless otherwise noted, the word “combined” and its associated verb forms include both direct and indirect electrical connections by means known in the art, and unless otherwise noted, any description of a direct connection also means an alternative embodiment using a preferred form of indirect electrical connection.

[0005] The memory controller includes a memory channel controller and a power controller. The memory channel controller has a first interface circuit adapted to connect to a data fabric operating in a first clock domain, and a second interface circuit adapted to connect to a physical layer interface circuit (PHY) operating in a third clock domain. The memory channel controller operates in the second clock domain according to a set of timing parameters. The first interface circuit includes a clock interface circuit for adapting transfers between the first and second clock domains. The power controller is coupled to the memory channel controller and, in response to a power state change request, sends a command to the second interface circuit to change the parameters of the memory system and updates the set of timing parameters of the memory channel controller according to a selected power state from among several power states. Furthermore, the power controller responds to a request to synchronize the first interface circuit to a new frequency of only the first clock signal in the first clock domain in order to change the set of timing parameters of the clock interface circuit without changing the set of timing parameters of the memory system or the selected power state.

[0006] The method includes receiving a power state command in the memory controller and, in response to changing the operating frequency of at least one of the memory controller clock domain and the memory clock domain, resynchronizing the memory controller bus interface with the data fabric clock domain and resynchronizing the PHY with the memory controller. The method also includes receiving a request to resynchronize the memory controller to the frequency of only the first clock signal of the data fabric clock domain and, in response, changing a set of timing parameters for the clock interface circuit between the data fabric clock domain and the memory controller clock domain and changing a set of timing parameters for the memory or memory controller, without resynchronizing the PHY with the memory controller.

[0007] The data processing system includes a data fabric, memory channels, a memory channel controller, and a power controller. The data fabric operates on a data fabric clock. The memory channels include a PHY operating on a memory clock domain for coupling to DRAM memory. The memory channel controller also includes a first interface circuit adapted to connect to the data fabric and a second interface circuit adapted to connect to the PHY. The memory channel controller operates in the second clock domain according to a set of timing parameters. The first interface circuit includes a clock interface circuit for adapting transfers between the first and second clock domains. The power controller is connected to the memory channel controller and, in response to a power state change request, sends commands to the second interface circuit to change the parameters of the memory system and updates the set of timing parameters of the memory channel controller according to a selected power state from among several power states. Furthermore, the power controller responds to a request to synchronize the interface circuit to a new frequency of only the first clock signal of the data fabric clock domain (FCLK) in order to change the set of timing parameters of the clock interface circuit without changing the set of timing parameters of the memory system or the selected power state.

[0008] Figure 1 is a block diagram of a conventionally known accelerated processing unit (APU) 100 and memory system 130. The APU 100 is an integrated circuit suitable for use as a processor in a host data processing system and generally includes a central processing unit (CPU) core complex 110, a set of graphics cores 120 and display engines 122, a data fabric 125, a memory management hub 140, a set of peripheral controllers 160 and peripheral bus controllers 170, and a system management unit (SMU) 180.

[0009] The CPU core complex 110 includes CPU cores 112 and 114. In this example, the CPU core complex 110 includes two CPU cores, but in other embodiments, the CPU core complex 110 may include any number of CPU cores. Each of the CPU cores 112 and 114 is bidirectionally connected to a system management network (SMN) and a data fabric 125 that form a control fabric, and can provide memory access requests to the data fabric 125. Each of the CPU cores 112 and 114 may be a single core, or a core complex having two or more single cores that share a specific resource such as a cache.

[0010] The graphics core 120 is a high-performance graphics processing unit (GPU) capable of performing graphics processing such as vertex processing, fragment processing, shading, and texture blending in a highly integrated parallel manner. The graphics core 120 is bidirectionally connected to the SMN and the data fabric 125 and can provide memory access requests to the data fabric 125. In this regard, the APU 100 can support either an integrated memory architecture in which the CPU core complex 110 and the graphics core 120 share the same memory space, or a memory architecture in which the CPU core complex 110 and the graphics core 120 share a portion of the memory space, while the graphics core 120 also uses private graphics memory that is not accessible by the CPU core complex 110.

[0011] The display engine 122 renders and rasterizes objects generated by the graphics core 120 for display on the monitor. The graphics core 120 and the display engine 122 are bidirectionally connected to a common memory management hub 140 via a data fabric 125 for uniform translation to appropriate addresses in the memory system 130.

[0012] The data fabric 125 includes a crossbar switch for routing memory access requests and memory responses between any memory access agent and the memory management hub 140. The data fabric also includes a system memory map defined by the basic input / output system (BIOS) and buffers for each virtual connection to determine the destination of memory accesses based on the system configuration.

[0013] The peripheral controller 160 includes a universal serial bus (USB) controller 162 and a Serial Advanced Technology Attachment (SATA) interface controller 164, each of which is bidirectionally connected to the system hub 166 and the SMN bus. These two controllers are merely typical examples of peripheral controllers that may be used with the APU 100.

[0014] The peripheral bus controller 170 includes a system controller or "Southbridge" (SB) 172 and a Peripheral Component Interconnect Express (PCIe) controller 174, each of which is bidirectionally connected to an input / output (I / O) hub 176 and the SMN bus. The I / O hub 176 is also bidirectionally connected to a system hub 166 and a data fabric 125. Therefore, for example, a CPU core can program registers in the USB controller 162, SATA interface controller 164, SB 172, or PCIe controller 174 via access routed by the data fabric 125 through the I / O hub 176. Software and firmware for the APU 100 are stored in a system data drive or system BIOS memory (not shown), which may be any of various non-volatile memory types such as read-only memory (ROM) or electrically erasable programmable ROM (EEPROM). Generally, BIOS memory is accessed via the PCIe bus, and system data drives are accessed via the SATA interface.

[0015] The SMU180 is a local controller that controls the operation of resources on the APU100 and synchronizes communication between them. The SMU180 manages the power-up sequencing of various processors on the APU100 and controls multiple off-chip devices via reset, enable, and other signals. The SMU180 includes one or more clock sources (not shown), such as a phase-locked loop (PLL), to provide clock signals to each of the components of the APU100. The SMU180 can also manage power for various processors and other functional blocks and receive power consumption values ​​measured from the CPU cores 112, 114 and the graphics core 120 to determine appropriate power states.

[0016] The memory management hub 140 and its associated physical interfaces (PHYs) 151 and 152 are integrated with the APU 100 in this embodiment. The memory management hub 140 includes memory channels 141 and 142 and a power engine 149. Memory channel 141 includes a host interface 145, a memory channel controller 143, and a physical interface 147. The host interface 145 connects the memory channel controller 143 bidirectionally to the data fabric 125 via a serial presence detect link (SDP). The physical interface 147 connects the memory channel controller 143 bidirectionally to the PHY 151 and conforms to the DDR PHY Interface (DFI) specification. Memory channel 142 includes a host interface 146, a memory channel controller 144, and a physical interface 148. The host interface 146 connects the memory channel controller 144 bidirectionally to the data fabric 125 via another SDP. The physical interface 148 connects the memory channel controller 144 to the PHY 152 bidirectionally and complies with the DFI specification. The power engine 149 is connected bidirectionally to the SMU 180 via the SMN bus, to the PHYs 151 and 152 via the Advanced Peripheral Bus (APB) interface 254, and also bidirectionally to the memory channel controllers 143 and 144. The PHY 151 has a bidirectional connection to the memory channel 131. The PHY 152 has a bidirectionally connected memory channel 133.

[0017] The memory management hub 140 is an instantiation of a memory controller having two memory channel controllers, and uses a shared power engine 149 to control the operation of both memory channel controllers 143 and 144 in a manner further described below. Each of the memory channels 141 and 142 can be connected to state-of-the-art DDR memory such as DDR version 5 (DDR5), DDR version 4 (DDR4), low-power DDR4 (LPDDR4), graphics DDR version 5 (GDDR5), and high-bandwidth memory (HBM), and can be adapted to future memory technologies. These memories provide high bus bandwidth and high-speed operation. At the same time, these memories provide a low-power mode to conserve power for battery-powered applications such as laptop computers, and also perform built-in thermal monitoring.

[0018] The memory system 130 includes memory channels 131 and 133. Memory channel 131 includes a set of dual inline memory modules (DIMMs) connected to the DDRx bus 132, which in this embodiment include representative DIMMs 134, 136, and 138 corresponding to individual ranks. Similarly, memory channel 133 includes a set of DIMMs connected to the DDRx bus 129, including representative DIMMs 135, 137, and 139.

[0019] The APU100 acts as the central processing unit (CPU) of a host data processing system, providing a variety of buses and interfaces useful in modern computer systems. These interfaces include two double data rate (DDRx) memory channels, a PCIe root complex for connecting to PCIe links, a USB controller for connecting to USB networks, and an interface to SATA mass storage devices.

[0020] Furthermore, the APU100 also implements various system monitoring and power saving functions. In particular, one system monitoring function is thermal monitoring. For example, if the APU100 becomes hot, the SMU180 can reduce the frequency and voltage of CPU cores 112, 114 and / or graphics core 120. If the APU100 becomes too hot, the SMU can be completely shut down. The SMU180 can also receive thermal events from external sensors via the SMN bus, and the SMU180 can reduce the clock frequency and / or power supply voltage accordingly.

[0021] Figure 2 is a block diagram of a memory controller 200 suitable for use in an APU like the one in Figure 1. The memory controller 200 generally includes a memory channel controller 210 and a power controller 250. The memory channel controller 210 generally includes an interface 212, a memory interface queue 214, a command queue 220, an address generator 222, a content-addressable memory (CAM) 224, a replay control logic 231 including a replay queue 230, a refresh control logic block 232, a timing block 234, a page table 236, an arbiter 238, an error correction code (ECC) check circuit 242, an ECC generation block 244, a data buffer 246, and a refresh control logic 232.

[0022] Interface 212 has a first bidirectional connection to the data fabric via an external bus and has an output. In the memory controller 200, this external bus conforms to the highly extensible interface version 4 specified by ARM Holdings, PLC of Cambridge, UK, known as "AXI4," although in other embodiments it may be a different type of interface. Interface 212 translates memory access requests from a first clock domain known as the "FCLK" domain to a second clock domain inside the memory controller 200 known as the "UCLK" domain. Similarly, the memory interface queue 214 grants memory access from the UCLK domain to the "DFICLK" domain associated with the DFI interface.

[0023] The address generator 222 decodes the address of a memory access request received from the data fabric via the AXI4 bus. The memory access request includes an access address within a physical address space represented in a normalized format. The address generator 222 converts the normalized address into a format that can be used to address the actual memory devices within the memory system 130 and to efficiently schedule the associated accesses. This format includes a region identifier that associates the memory access request with a specific rank, row address, column address, bank address, and bank group. At startup, the system BIOS queries the memory devices within the memory system 130 to determine their sizes and configurations, and programs a set of configuration registers associated with the address generator 222. The address generator 222 uses the configuration stored in the configuration registers to convert the normalized address into an appropriate format. The command queue 220 is a queue of memory access requests received from memory access agents within the APU 100, such as the CPU cores 112, 114 and the graphics core 120. The command queue 220 stores the address field decoded by the address generator 222, as well as other address information that enables the arbiter 238 to efficiently select a memory access that includes an access type and a quality of service (QoS) identifier. The CAM 224 includes information for implementing ordering rules, such as write after write (WAW) and read after write (RAW) ordering rules.

[0024] The error correction code (ECC) generation block 244 determines the ECC for the write data sent to the memory. This ECC data is then added to the write data within the data buffer 246. The ECC check circuit 242 checks the received ECC by comparing it with the incoming ECC.

[0025] The replay queue 230 is a temporary queue for storing memory accesses selected by the arbiter 238 waiting for responses such as addresses and command parity responses. The replay control logic 231 accesses the ECC check circuit 242 to determine whether the returned ECC is correct or indicates an error. The playback control logic 231 starts and controls a playback sequence in which accesses are replayed in the case of parity or ECC errors in any of these cycles. The replayed command is placed in the memory interface queue 214.

[0026] The refresh control logic 232 includes state machines for various power-off, refresh, and termination resistance (ZQ) calibration cycles generated separately from normal read and write memory access requests received from the memory access agent. For example, when a memory rank is in precharge power-down, the refresh control logic must be periodically activated to execute a refresh cycle. The refresh control logic 232 periodically generates a refresh command according to defined conditions to prevent data errors caused by charge leakage from the storage capacitors of the memory cells in the DRAM chip. The refresh control logic 232 includes an activation counter 248. In this embodiment, the activation counter 248 has a counter for each memory region that counts the rolling number of activation commands transmitted to the memory region via the memory channel. The memory region is, in some embodiments, a memory bank and, in other embodiments, a memory sub-bank, as further described below. Further, the refresh control logic 232 periodically calibrates the ZQ to prevent mismatches in the on-die termination resistance due to thermal changes in the system.

[0027] The arbiter 238 is bidirectionally connected to the command queue 220 and is the heart of the memory channel controller 210, performing intelligent scheduling of accesses to improve memory bus usage. In this embodiment, the arbiter 238 includes a bank group tracking circuit 235 for tracking the bank group numbers of several recently issued write commands and “masking” them by preventing the dispatch of commands to those bank groups for a specified time period under certain conditions, as will be further described below. The arbiter 238 implements appropriate timing relationships by using a timing block 234 to determine whether a particular access in the command queue 220 is eligible to be issued based on DRAM timing parameters. For example, each DRAM is “t RC It has a minimum specified time between activation commands, known as "". Timing block 234 maintains a set of counters that determine eligibility based on this timing parameter and other timing parameters defined in the JEDEC specification and is bidirectionally connected to replay queue 230. Page table 236 maintains state information about active pages in each bank and rank of the memory channel for arbiter 238 and is bidirectionally connected to replay queue 230.

[0028] The ECC generation block 244 calculates the ECC according to the write data in response to a write memory access request received from interface 212. The data buffer 246 stores the write data and ECC related to the received memory access request. When the arbiter 238 selects the corresponding write access for dispatch to the memory channel, the data buffer outputs the combined write data / ECC to the memory interface queue 214.

[0029] The memory channel controller 210 includes circuitry that enables the selection of memory accesses for dispatch to the relevant memory channel. To make the desired arbitration decision, the address generator 222 decodes the address information into pre-decoded information, including the rank, row address, column address, bank address, and bank group in the memory system, and the command queue 220 stores the pre-decoded information. The configuration register 262 stores configuration information for determining how the address generator 222 decodes the received address information. The arbiter 238 uses the decoded address information, timing eligibility information indicated by the timing block 234, and active page information indicated by the page table 236 to efficiently schedule memory accesses while complying with other criteria such as quality of service (QoS) requirements. For example, the arbiter 238 implements priority for access to open pages to avoid the overhead of precharge and activation commands required to modify memory pages, and hides overhead access to one bank by interleaving read and write access to another bank. In particular, during normal operation, the arbiter 238 typically keeps pages open in different banks until these pages need to be precharged before they can select different pages. In some embodiments, the arbiter 238 determines the eligibility of a command selection based on at least the respective values ​​of the activation counter 248 with respect to the target memory region of each command.

[0030] The power controller 250 generally includes an interface 252 to an Advanced Extensible Interface, Version 1 (AXI), an Advanced Peripheral Bus (APB) interface 254, a power engine 260, and a set of power state control logic blocks 270. Interface 252 has a first bidirectional connection to the SMN and an output. The APB interface 254 has an input connected to the output of interface 252 and an output for connecting to the PHY via the APB.

[0031] The power engine 260 has an input connected to the output of interface 252 and an output connected to the input of memory interface queue 214. The power engine 260 includes a set of configuration registers 262, a microcontroller (μC) 264, a self-refresh controller (SLFREF / PE) 266, a reliable read / write timing engine (RRW / TE) 268, and a memory controller clock domain state change circuit ("CLKARB") 271, which includes a UCLK control logic block 272, a DFICLK synchronous logic block 274, and an FCLK synchronous logic block 276. The configuration registers 262 are programmed via the AXI bus and store configuration information for controlling the operation of various blocks in the memory controller 200 in a selected power state from four different power states via the power state control logic block 270. Thus, the power state control logic block 270 has outputs connected to various blocks in the memory controller 200, which are not shown in detail in Figure 2. SLFREF / PE266 is an engine that enables manual generation of refreshes in addition to automatic generation of refreshes by refresh control logic 232. The reliable read / write timing engine 268 provides a continuous memory access stream to memory or I / O devices for purposes such as DDR interface maximum read latency (MRL) training and loopback testing.

[0032] During operation, the power controller 250 receives power state commands from the SMU 180 (Figure 1) via the data fabric's power management control interface and, accordingly, changes the power state of the memory controller 200 and the mounted DRAM to enter a new power state, typically including different clock speeds for the DFICLK and UCLK domains. Each of the power state control logic blocks 270 implements its respective power state by controlling various blocks of the memory controller 200 to operate according to its respective power state according to configuration values ​​set in the configuration register 262. The configuration values ​​include a set of timing parameters and other configuration parameters for configuring the memory channel controller to operate in each power state.

[0033] When the power state of the memory controller 200 changes, the UCLK control logic block 272 sends the necessary signals to control and adjust the various blocks of the memory channel controller 210 when changing to the new power state specified by the power state command from the SMU 180. The UCLK control logic block 272 includes circuitry that adjusts the operation of various logic blocks within the memory channel controller 210, adjusts the UCLK frequency if necessary, and adjusts the memory channel controller 210 to operate for the new configuration register values ​​via its respective power state control logic block 270.

[0034] The DFICLK synchronization logic block 274 is used whenever there is a change in either UCLK or DFICLK. It includes circuitry for controlling synchronization between these two clock domains in the memory interface queue 214, which typically includes pausing the interface, applying a new clock frequency, and instructing the interface to synchronize across the new clock frequency. In some embodiments, the contents of the memory interface queue 214 or the various queues within it are temporarily stored in local RAM to complete the synchronization. The DFICLK synchronization logic block 274 is activated by μC264 for each power state change, except for those provided herein that relate only to FCLK changes, as will be further described below.

[0035] The FCLK synchronization logic block 276 is used whenever there is a change in the UCLK or FCLK frequency. The FCLK synchronization logic block 276 includes circuitry that controls the synchronization between these two clock domains within interface 212. The synchronization process typically involves pausing interface 212, allowing the SMU 180 to adjust the frequency of FCLK in the FCLK clock domain of the data fabric 125, instructing interface 212 to synchronize across the new clock frequency, and then re-establishing the connection to the data fabric.

[0036] Figure 3 is a block diagram of some elements of the APU 300 for providing clock domain signals and synchronization across clock domains in the memory channel controller 210. In this embodiment, the APU 300 includes a memory controller 200 similar to that in Figure 2, but only the relevant elements are shown. The APU 300 includes a data fabric 125, an SMU 180, a memory controller 200, an FCLK PLL 302, an UCLK PLL 304, and a PHY 320.

[0037] The SMU180 has an output connected to the FCLK PLL302, a bidirectional connection to the data fabric 125, and a bidirectional connection to the SMN. Generally, the SMU180 implements power state control decisions from the operating system kernel and, in some embodiments, makes additional decisions regarding the power state of various parts of the APU300 based on various conditions across the APU300. The SMU exposes power state control defined in system power state specifications such as the Advanced Configuration and Power Interface (ACPI), a power management and configuration specification for computers such as personal computers (PCs) and servers, to the APU300 operating system. ACPI allows computer operating systems to manage the power consumed by various devices by changing the device operating mode from a limited set of power states that may include different operating frequencies, different supply voltages, and other differences. In particular, the SMU180 selects the power state of the data fabric 125, memory controller 200, and PHY320, along with the associated DRAM memory. Other power state adjustments can also be performed by other system elements.

[0038] As described with respect to Figure 1, the data fabric 125 is a scalable data fabric that connects the system processing core to various subsystems, and has bidirectional connections to the SMU 180, bidirectional connections to the memory controller 200, and inputs connected to the output of the FCLK PLL 302. The data fabric 125 operates in the FCLK clock domain based on the FCLK signal provided by the FCLK PLL 302.

[0039] The memory controller 200 includes a memory channel controller 210 and a power controller 250, as described with respect to Figure 2. The power controller 250 is connected to the memory channel controller to control its various parts and has an output connected to the UCLK PLL 304, a bidirectional connection to the SMN via an AXI interface, and a bidirectional connection to the PHY 320. The memory channel controller includes an interface 212 for connecting to the data fabric 125, a memory interface queue 214 for connecting to the PHY 320, and an input for receiving the UCLK signal from the UCLK PLL 304. As described with respect to Figure 2, the memory channel controller 210 operates in the UCLK clock domain, interfaces to the FCLK domain via interface 212, and interfaces to the DFICLK domain of the PHY 320 via the memory interface queue 214 and its associated PHY interface. Figure 3 shows the voltage domain crossing interface (VDCI) 310 within interface 212 of the memory channel controller 210, which connects the FCLK clock domain and the UCLK clock domain.

[0040] The PHY320 has bidirectional connections to a power controller 250, bidirectional connections to a memory channel controller 210, and an input connected to the memory channel controller 210 for receiving a DFICLK clock signal, typically having FCLK / 2. DFICLK and UCLK are equal when UCLK is set to FCLK / 2, and DFICLK is half the frequency of UCLK when UCLK is set to FCLK. The PHY320 includes a memory clock PLL322 for generating a clock signal for signaling on the memory bus. The PLL322 uses DFICLK as a reference. The PHY320 includes a group of configuration registers 324 for holding many configuration values ​​required to interface with DDRx memory in its various supported modes and power states. The PHY320 also includes a set of four power state control logic blocks 326, each connected to the respective set of configuration registers 324, to control the PHY circuitry to implement four supported power states. While some embodiments support more than four power states, the four power states defined by the ACPI interface are typically used. Adding more power states typically requires adding more configuration registers with associated power state control logic to implement the additional power states. The configuration values ​​include timing parameters and other configuration parameters for configuring the PHY to operate in each power state. The configuration register 324 is configurable on the SMN via the power controller 250.

[0041] The APU300 enables the data fabric, operating on the FCLK domain, to operate at frequencies different from the typical 1:1 or 1:2 relationship with the memory controller clock domain and the DFICLK clock domain. The VDCI310 provides an asynchronous clock interface circuit including an asynchronous first-in, first-out (FIFO) buffer, enabling the data fabric to operate at frequencies lower than UCLK (e.g., to conserve power in signaling during low-traffic operation) or higher than UCLK (e.g., when the data fabric has a high traffic load among other system components). To support configurations where FCLK is less than UCLK, the memory controller 200 suppresses read responses and buffers transfers to the data fabric to prevent overflow of the slower FCLK interface.

[0042] The memory controller 200 supports changing the FCLK domain frequency in an efficient manner that does not require resynchronizing UFCLK to the interface of the memory interface queue 214, or resetting the PHY and flushing the queues associated with the PHY, as is typically done when changing the power state according to the process in Figure 4, for example.

[0043] In operation, the power controller 250 responds to a power state change request by updating the set of timing parameters of the memory channel controller, sending a command to the DFI interface circuit of the memory interface queue 214 to change the parameters of the memory system to a selected memory power state from among the supported power states, and activating the circuit to achieve adjustment in the memory controller 200. An example of this process is illustrated with reference to Figure 4. Furthermore, the power controller 250 responds to a request to synchronize the memory controller to a new frequency of only the FCLK signal in the FCLK clock domain, known herein as an F-clock-only power state change, by changing the set of timing parameters of the VDCI 310 and resynchronizing the VDCI across the FCLK and UCLK domains without changing the set of timing parameters or the selected power state in which the memory channel controller 210 and PHY 320 are operating. An example of this process is illustrated with reference to Figure 5.

[0044] Figure 4 shows a flowchart 400 of a process for changing the power state in a memory controller according to several embodiments. This process is suitable for use with the memory controllers of Figures 2 and 3, as well as other memory controllers that include data fabric synchronization circuits and PHY synchronization circuits for changing power state adjustments. This process is an example of a complete power state transition that includes resynchronizing both interfaces of the memory controller. A power state command is typically a command that changes to another ACPI exposed power state defined for the memory system and may include changes to any combination of UCLK, DFICLK, and FCLK. This process is described to provide an example of the complexity and latency involved in performing a power state transition.

[0045] The process begins in block 402, when a power status command is received by the power controller 250. Typically, the power status command is received from a system management controller such as the SMU 180. In block 404, the power controller 250 signals the data fabric to suspend memory access requests to the memory controller 200. This signal typically goes to a coherent slave controller on the data fabric, but in other embodiments, the signal may go to another system element such as the SMU 180 that instructs the data fabric to suspend memory access requests to the memory controller 200.

[0046] In block 406, the power controller instructs the memory controller to flush its various queues and put the PHY into configuration mode. This flush step is optional as the PHY is not powered down. In block 408, the power controller 250 puts the memory controller 200 and its associated DRAM into self-refresh mode and turns off clock gating of the UCLK signal to the memory controller 200. In the embodiment of Figure 2, blocks 406 and 408 are performed using the UCLK control logic block 272. In other embodiments, other suitable memory clock domain control circuits are used.

[0047] In block 410, the power controller 250 adjusts the frequencies of the UCLK and / or DFICLK PLLs to the required frequencies specified by the power state command, typically by writing to designated control registers. This block includes a period for the PLL frequencies to ramp up or ramp down to their new operating frequencies. Next, in block 412, the power controller turns on clock gating of the UCLK signal to the memory controller 200 and selects a set of power state control registers in configuration register 262 to control operation in the new power state. This block includes a period for the logic blocks in the memory controller 200 to initialize.

[0048] In block 414, the power controller 250 exits the configuration mode and resynchronizes the memory controller 200 with the PHY. In the embodiment shown in Figure 2, block 414 is achieved using the DFICLK synchronization logic block 274 to resynchronize the DFI interface of the memory interface queue 214 with the PHY. In other embodiments, other suitable memory clock domain state change circuits are used.

[0049] In block 416, the power controller 250 resynchronizes the memory controller interface with the data fabric using a new frequency relationship between FCLK and UCLK. In the embodiment shown in Figure 2, block 416 is achieved using the FCLK synchronous logic block 274, but in other embodiments, other clock synchronization circuits are used.

[0050] As can be understood, the power state change process generally introduces an operational delay of several microseconds and requires the contents of various queues to be unloaded or flushed and reloaded after the power state change. Therefore, a memory power state change request can introduce very long latency to any new memory access requests generated during the power state change.

[0051] Figure 5 shows a flowchart 500 of a process for responding to power state commands according to several embodiments. The process shown allows for adjustment of the data fabric frequency in combination with power state commands implemented in the memory controller in order to resynchronize the memory controller with the data fabric. This process has the advantage of supporting specific adjustments in the memory controller power state without interrupting the memory controller operation shown by the process in Figure 4. This process also has the advantage of supporting more variability than that provided by ACPI power state commands when adjusting the data fabric clock.

[0052] The process begins in block 502, when a power state command override signal is received by the power controller 250. The power state override command indicates to the power controller that subsequent or accompanying power state commands will not change the UCLK clock frequency or the DFICLK clock frequency. In the illustrated embodiment, the power state override command is sent from the SMU 180 to the power controller 250. In some embodiments, the decision to send power state override commands and FCLK-only power state commands is made by the operating system kernel and implemented by a command to the SMU 180. In some other embodiments, the SMU 180 may not expose this functionality to the operating system and instead make the decision itself. Further embodiments may allow either the SMU 180 or the operating system kernel to control this functionality. This decision is generally made to enable the data fabric to handle its workload demands while improving the power efficiency of the data fabric and minimizing the impact on memory channel throughput and latency. Using power state commands to achieve such changes has the advantage of leveraging the existing ACPI power state framework while providing extended capabilities within that framework.

[0053] In block 504, the power controller 250 receives a power state command consisting only of FCLK that follows or is associated with the power state command override signal received in block 502. In some embodiments, the command override signal may be included in the power state command, while in other embodiments, the command override signal is separate, indicating that a single subsequent power state command is subject to the override condition.

[0054] In block 506, the process implements overrides by disabling or deactivating the memory controller clock domain state change circuit, which in this embodiment is the UCLK control logic block 272, and the memory clock domain state change circuit, which in this embodiment is the DFICLK synchronization logic block 274. The circuits are disabled to prevent the state change circuits from changing the memory controller clock domain (UCLK) and the memory clock domain (DFICLK), and to prevent the memory controller interface from being resynchronized to the PHY. This avoids executing blocks 406, 408, 410, 412, and 414 in Figure 4 when responding to power state commands relating only to data fabric clock frequency changes. The circuits for executing these blocks are preferably disabled or deactivated by setting control bits or activating control gates in response to power state override commands. This setting may be performed immediately after receiving the power state override signal in block 502, so that when a power state command is received in block 504, the associated circuits are disabled. In this way, the same circuitry used to switch between the limited number of power states supported by ACPI is used to support the extended functionality when switching data fabric clock domain clock frequencies. This approach has the advantage of supporting more data fabric clock domain frequency values ​​than are available in the limited number of power states supported by the memory controller and control registers in the PHY.

[0055] In block 508, the power controller 250 signals the data fabric to pause memory access requests. In other embodiments, as described with reference to Figure 4, this is achieved by the SMU signaling the SMU to request that it stop memory access requests to the memory controller via the data fabric.

[0056] In block 520, the SMU 180 adjusts the data fabric clock (FCLK) frequency to a new desired operating frequency by adjusting the FCLK PLL 302 (Figure 3). The new operating frequency is preferably specified in a power state command in block 504 so that the power controller 250 can utilize it. In this embodiment, the SMU 180 controls the FCLK PLL 302, but other embodiments may use other control methods to adjust the data fabric clock frequency. The new data fabric clock frequency can be selected from frequencies specified in any of the limited number of power states provided in the power state control logic block 270 (Figure 2), or from frequencies not specified in those power states. The new data fabric clock frequency may be higher or lower than the memory controller clock domain (UCLK) frequency.

[0057] Once the data fabric clock frequency slopes or transitions to a new value and stabilizes, the memory controller resynchronizes its interface with the data fabric in block 512. In this embodiment, the power controller 250 controls the resynchronization by activating the FCLK synchronous logic block 276, which controls the VDCI 310 (Figure 3) in interface 212 to resynchronize with the data fabric via the asynchronous FIFO architecture. At this point, the power state change has been achieved, and the power controller can signal the data fabric to resume sending memory access requests to the memory controller 200.

[0058] As can be understood, the use of F-clock-only power state commands allows the power state command framework to be used for the additional capability of FCLK changes, along with modifications to improve the speed of power state switching in the memory controller. Another advantage is that FCLK changes beyond those specified within a defined power state can be made in systems that support only a limited number of power states, such as 4, which is a typical number supported at the time of filing. The data fabric may run at a clock frequency slower or faster than the clock frequency specified in a defined set of power states. This allows for efficient adjustments to the data fabric to handle workload demands that may be irrelevant to the particular memory controller(s) to which the F-clock-only power state commands apply. In embodiments where the F-clock-only power state commands are not exposed to the operating system, the process in Figure 5 is preferably transparent to the operating system so that the operating system kernel power state control process can treat the current power state as if there were no FCLK change, and the operating system can use the data fabric at the new operating frequency of the data fabric clock domain.

[0059] Any part of the memory controller 200 or power controller 250 and the FCLK synchronous logic block 274 in Figure 2 may be described or represented by a computer-accessible data structure in the form of a database or other data structure that can be read by a program and used directly or indirectly to manufacture the integrated circuit. For example, this data structure may be a behavioral-level description or register-transfer-level (RTL) description of hardware functions in a high-level design language (HDL) such as Verilog or VHDL. The description may be read by a synthesis tool that can synthesize the description to generate a netlist containing a list of gates from a synthesis library. The netlist contains a set of gates that also represent the functions of the hardware, including the integrated circuit. The netlist may then be arranged and routed to generate a dataset that describes the geometric shapes applied to a mask. The mask can then be used in various semiconductor manufacturing processes to manufacture the integrated circuit. Alternatively, the database on a computer-accessible storage medium may, as desired, be a netlist (with or without a synthesis library) or a dataset, or Graphic Data System (GDS) II data.

[0060] While specific embodiments have been described, various modifications to these embodiments will be apparent to those skilled in the art. For example, the internal architecture of the memory channel controller 210 and / or power controller 250 may differ in different embodiments. The memory controller 200 may interface with other types of memory besides DDRx, such as high-bandwidth memory (HBM), RAMbus DRAM (RAMbus DRAM, RDRAM), etc. The illustrated embodiments show each rank of memory corresponding to individual DIMMs or SIMMs, but in other embodiments, each module may support multiple ranks. Further other embodiments may include other types of DRAM modules or DRAM not included in the specific module, such as DRAM mounted on a host motherboard. Accordingly, the appended claims are intended to cover all modifications of the disclosed embodiments that fall within the scope of the disclosed embodiments.

Claims

1. It is a memory controller, A memory channel controller comprising: a first interface circuit adapted to couple to a data fabric operating in a first clock domain; and a second interface circuit adapted to couple to a physical layer interface circuit (PHY) operating in a third clock domain, wherein the memory channel controller operates in the second clock domain according to a set of timing parameters, and the first interface circuit includes a clock interface circuit for couple transfers between the first clock domain and the second clock domain. A power controller coupled to the memory channel controller, which transmits a command to the second interface circuit to change the parameters of the memory system, including the memory channel and memory, in response to a power state change request, and updates a set of timing parameters of the memory channel controller according to a power state selected from a plurality of power states, The power controller responds to a request to synchronize the first interface circuit with a new frequency only for the first clock signal of the first clock domain in order to change the set of timing parameters of the clock interface circuit without changing the set of timing parameters of the memory system or the selected power state. Memory controller.

2. A request to synchronize only the first clock signal of the first clock domain with a new frequency includes a power state override signal and a subsequent power state command, the power state override signal causing the power controller to disable selected memory controller clock domain state change circuits and memory clock domain state change circuits in response to a subsequent power state command associated with the change of the first clock domain. A memory controller according to claim 1.

3. The aforementioned power controller When responding to a power state command that is not accompanied by a previous power state command override signal, a new set of power state control registers is selected from several sets of power state control registers of the memory controller, including the operating parameters of the memory controller. It is possible to operate in a way that does not select a new set of power state control registers when responding to a power state command accompanied by a previous power state command override signal. The memory controller according to claim 2.

4. The aforementioned power controller When responding to a power state command that does not include a previous power state command override signal, a new set of power state control registers for the PHY is selected from several sets of power state control registers for the PHY, including the operating parameters of the PHY. When responding to a power state command accompanied by a previous power state command override signal, the PHY can be operated not to select a new set of power state control registers. The memory controller according to claim 2.

5. Each of the set of power state control registers of the PHY is connected to the PHY and corresponds to a supported power state of the dynamic random access memory (DRAM) associated with the memory controller. The memory controller according to claim 4.

6. A clock signal is supplied to the second clock domain, and a phase-locked loop (PLL) is coupled to the power controller, A memory controller according to claim 1.

7. The memory controller is embodied in a data processing system that includes the data fabric operating in the first clock domain and a memory channel operating in the clock domain for coupling to a DRAM memory. A memory controller according to any one of claims 1 to 6.

8. In the memory controller, upon receiving a power state command and changing the operating frequency of at least one of the memory controller clock domain and memory clock domain, the memory controller bus interface is resynchronized with the data fabric clock domain, and the physical layer interface (PHY) is resynchronized with the memory controller. The memory controller receives a request to resynchronize with the frequency of only the first clock signal of the data fabric clock domain, and in response, modifies the set of timing parameters of the clock interface circuit between the data fabric clock domain and the memory controller clock domain without resynchronizing the PHY with the memory controller, and modifies the set of timing parameters of the memory or the memory controller in addition to the timing parameters of the clock interface circuit. method.

9. The request to resynchronize the memory controller includes a power state command override signal and a subsequent power state command. The method includes disabling a selected memory controller clock domain state change circuit and a memory clock domain state change circuit in response to a subsequent power state command associated with a change in the data fabric clock domain. The method of claim 8.

10. When responding to a power state command that does not include a previous power state command override signal, a new set of power state control registers is selected from several sets of power state control registers of the memory controller, including the operating parameters of the memory controller. This includes not selecting a new set of power state control registers when responding to a power state command accompanied by a previous power state command override signal, The method of claim 8.

11. When responding to a power state command that does not involve a previous power state command override signal, a new set of power state control registers for the PHY is selected from several sets of power state control registers for the PHY, including the operating parameters of the PHY. This includes not selecting a new set of power state control registers for PHY when responding to a power state command accompanied by a previous power state command override signal, The method of claim 8.

12. Each of the set of power state control registers of the PHY is connected to the PHY and corresponds to a supported power state of the dynamic random access memory (DRAM) associated with the memory controller. The method according to claim 11.

13. This includes adjusting the phase-locked loop (PLL) that supplies the clock signal to the memory controller clock domain in response to a power state command that does not have a previous power state command override signal. The method of claim 8.

14. The system management unit controller includes determining that the data fabric clock domain should change its operating frequency, then sending the power state command override signal to the memory controller to cause the data fabric clock domain to change its operating frequency, and then sending the subsequent power state command to the memory controller. The method of claim 9.

15. The subsequent power state command includes power state data indicating the current memory controller clock domain operating frequency, the current memory clock domain operating frequency, and the regulated data fabric clock domain operating frequency. The method according to claim 14.

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