Semiconductor equipment

Abstract

To propose a storage device capable of enhancing storage capacity per unit area while ensuring a data retention period.SOLUTION: A storage device includes: a storage element; a transistor including an oxide semiconductor in an active layer for controlling accumulation, retention, and release of charges in the storage element; and a capacitive element connected to the storage element. At least one of a pair of electrodes of the capacitive element has light-blocking properties. In addition, the storage device has a conduction film or an insulation film having light-blocking properties. The active layer is located between the electrode having light-blocking properties and the conduction film or the insulation film having light-blocking properties.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] This relates to a memory device and a semiconductor device that uses said memory device. [Background technology]

[0002] In recent years, high mobility has been obtained from polysilicon and microcrystalline silicon, and amorphous silicon As a new semiconductor material that combines uniform device characteristics obtained by the process, oxide semiconductors Metal oxides, which exhibit semiconductor properties and are called conductors, are attracting attention. It is used in various applications; for example, indium oxide, a well-known metal oxide, is used in liquid It is used as a transparent electrode material in crystal display devices, etc. It is a metal oxide exhibiting semiconductor properties. For example, there are tungsten oxide, tin oxide, indium oxide, zinc oxide, and this Insulated gate field-effect type that uses a metal oxide exhibiting semiconductor properties in the channel formation region A transistor (hereinafter simply referred to as a transistor) is already known.

[0003] The above-mentioned transistors using oxide semiconductors have wavelengths shorter than visible light, especially ultraviolet light. Light in the side region can cause degradation of characteristics such as a shift in threshold voltage and an increase in off-current. It is known that transistors used in semiconductor devices have small changes in their characteristics. It is desirable that the variation caused by changes in characteristics be small. As disclosed in Reference No. 1 or Patent Document No. 2, the degradation of transistor characteristics due to light is prevented. Technologies aimed at achieving this are being researched and developed. [Prior art documents] [Patent Documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2010-021520 [Patent Document 2] Japanese Patent Application Laid-Open No. 2009-277701 [Summary of the Invention] [Problems to be Solved by the Invention]

[0005] In the case of a semiconductor memory device (hereinafter simply referred to as a memory device) using a transistor including the above oxide semiconductor in a channel formation region as a switching element, due to the threshold voltage of the above transistor shifting or the off-current increasing, the charge to be held in the memory element becomes easily released, and the period during which data can be held tends to be shortened. Therefore, in order to ensure a longer period during which accurate data is held in the memory device, it is important to prevent deterioration of the characteristics of the transistor caused by light irradiation.

[0006] In addition, the smaller the area occupied by each memory cell in the above memory device, the higher the storage capacity per unit area can be increased. However, when the area occupied by the memory cell becomes smaller, the exclusive area of the capacitive element provided in each memory cell for holding the charge of the memory element also has to be reduced. Therefore, it becomes difficult for the capacitive element to secure a capacitance value large enough to hold data in the memory device for a long time.

[0007] In view of the above problems, an object of one aspect of the present invention is to propose a memory device capable of increasing the storage capacity per unit area while ensuring the period during which data is held. Alternatively, an object of one aspect of the present invention is to propose a semiconductor device using the above memory device. [Means for Solving the Problems]

[0008] ​​​​​​​​ A memory device according to one aspect of the present invention includes a transistor that functions as a memory element, and a transistor including an oxide semiconductor in an active layer for controlling the accumulation, retention, and release of charges in the memory element. and a capacitor element connected to the memory element. Alternatively, a memory device according to one aspect of the present invention includes a capacitor element that functions as a memory element, and a transistor including an oxide semiconductor in a channel formation region for controlling the accumulation, retention, and release of charges in the memory element. has. And at least one of a pair of electrodes of the capacitor element has a light-shielding property. Further, a memory device according to one aspect of the present invention has a light-shielding layer such as a light-shielding conductive film or insulating film, and is characterized in that it is located between an electrode having a light-shielding property and the light-shielding layer with respect to the active layer.

[0009] The active layer of the transistor that functions as a memory element may also contain an oxide semiconductor.

[0010]

[0011] The oxide semiconductor has a band gap about three times as large as that of silicon and a lower intrinsic carrier density than silicon. By including a semiconductor material having the above-described characteristics in the channel formation region, a transistor with an extremely low off-current can be realized. By using the transistor having the above configuration as a switching element for holding the charges stored in the memory element, leakage of charges from the memory element can be prevented.

[0012] Note that the oxide semiconductor has a mobility as high as that obtained by microcrystalline silicon or polycrystalline silicon and uniform device characteristics obtained by amorphous silicon. ​ It is a metal oxide showing conductor characteristics. And impurities such as moisture or hydrogen that act as electron donors are reduced and highly purified, and the oxide semiconductor (puri fied OS) with reduced oxygen deficiency is of type i (intrinsic semiconductor) or extremely close to type i. Therefore, a transistor using the above oxide semiconductor has the characteristic that the off-current is extremely low. Specifically , an oxide semiconductor that is highly purified and has reduced oxygen deficiency has a measured hydrogen concentration by secondary ion mass spectrometry (SIM S:Secondary Ion Mass Spectrometry) of 5×10 / cm 19 or less, preferably 5×10 3 / cm 18 or less, more 3 preferably 5×10 / cm 17 or less, even more preferably 1×10 3 / cm 16 or less, and is made 3 as follows. Also, the carrier density of the oxide semiconductor film that can be measured by Hall effect measurement is 1×10 14 / cm 3 less than, preferably 1×10 12 / cm 3 less than, even more preferably 1×10 1 1 / cm 3 less than. Also, the band gap of the oxide semiconductor is 2 eV or more, preferably 2.5 eV or more, more preferably 3 eV or more. By using an oxide semiconductor film in which the impurity concentration of moisture or hydrogen is sufficiently reduced and highly purified and the oxygen deficiency is reduced, the off-current and leakage current of the transistor can be reduced. <**********>

[0013] Here, the analysis of the hydrogen concentration in the oxide semiconductor film will be mentioned. In and The hydrogen concentration in the conductive film is measured using SIMS. Due to its principle, SIMS measures the area near the sample surface and It is known that it is difficult to accurately obtain data near the lamination interface between films made of different materials. Therefore, when analyzing the distribution of hydrogen concentration in the thickness direction within a membrane using SIMS, Within the range where the membrane in question exists, there is no extreme fluctuation in the value, and a nearly constant value is obtained. The average value in the region will be adopted as the hydrogen concentration. Also, the thickness of the film being measured is small. In this case, a region was found where a nearly constant value could be obtained, influenced by the hydrogen concentration in the adjacent membrane. In some cases, this may not be possible. In this case, the maximum value of hydrogen concentration in the region where the film exists or The minimum value is adopted as the hydrogen concentration in the membrane. Furthermore, in the region where the membrane exists... If there is no bell-shaped peak with a local maximum or a trough-shaped peak with a local minimum, then the inflection point The value of will be adopted as the hydrogen concentration.

[0014] Specifically, a highly purified oxide semiconductor film with reduced oxygen deficiency is used as the active layer. The low off-current of a transistor can be proven through various experiments. For example, channel The width is 1 x 10 6 Even with a device that is μm in size and has a channel length of 10 μm, the source electrode and drain When the voltage between the electrodes (drain voltage) is in the range of 1V to 10V, the off-current (gate electrode) The drain current when the voltage between the source electrode and the source electrode is set to 0V or less is measured by a semiconductor parameter analyzer. Below the measurement limit of the riser, i.e., 1 × 10⁻⁶ -13 It is possible to obtain the characteristic of being A or less. In this case, the off-current density, which corresponds to the value obtained by dividing the off-current by the channel width of the transistor, is It can be seen that it is less than 100 Hz / μm. Also, the capacitive element and the transistor (gate insulating The edge film thickness is 100 nm) and connects to allow electricity to flow into or out of the capacitive element. In an experiment using a circuit that controls the load with the transistor, the transistor was high When a purified oxide semiconductor film with reduced oxygen vacancies is used in the channel formation region, The off-current density of the transistor was measured from the change in the amount of charge per unit time of the element. However, when the voltage between the source and drain electrodes of the transistor is 3V, 10zA / It was found that even lower off-current densities, ranging from μm to 100 zA / μm, can be obtained. Therefore, in a semiconductor device according to one aspect of the present invention, the purity is increased and oxygen deficiency is reduced. The off-current density of a transistor using an oxide semiconductor film as the active layer is measured between the source electrode and the electrode. Depending on the voltage between the rain electrodes, it may be 10 zA / μm or less, preferably 1 zA / μm or less, and Preferably, the oxygen deficiency can be reduced to 1 yA / μm or less. Therefore, the purity is increased and the oxygen deficiency is reduced. In transistors using a reduced oxide semiconductor film as the active layer, the off-current is crystalline. It is significantly lower compared to transistors using silicon.

[0015] Furthermore, oxide semiconductors are quaternary metal oxides, specifically In-Sn-Ga-Zn-O system oxide semiconductors. Conductors, and ternary metal oxides such as In-Ga-Zn-O oxide semiconductors and In-Sn-Z nO-based oxide semiconductors, In-Al-Zn-O-based oxide semiconductors, Sn-Ga-Zn-O-based Oxide semiconductors, Al-Ga-Zn-O based oxide semiconductors, Sn-Al-Zn-O based oxide semiconductors Conductors, and binary metal oxides such as In-Zn-O oxide semiconductors and Sn-Zn-O oxide semiconductors. Monocrystalline semiconductors, Al-Zn-O oxide semiconductors, Zn-Mg-O oxide semiconductors, Sn-Mg -O-based oxide semiconductors, In-Mg-O-based oxide semiconductors, In-Ga-O-based oxide semiconductors and Using In-O-based oxide semiconductors, Sn-O-based oxide semiconductors, Zn-O-based oxide semiconductors, etc. It is possible to be. In this specification, for example, In-Sn-Ga-Zn-O system Oxide semiconductors include indium (In), tin (Sn), gallium (Ga), and zinc (Zn). This means a metal oxide containing [a certain compound], and its stoichiometric composition ratio is not particularly specified. The above oxide semiconductor may contain silicon.

[0016] Alternatively, oxide semiconductors have the chemical formula InMO3(ZnO). m (If m > 0, m is a natural number) It can be expressed as (not necessarily) where M is Zn, Ga, Al, Mn and C It represents one or more metallic elements selected from o. For example, M may be Ga, Ga and Al. Examples include Ga and Mn, or Ga and Co. [Effects of the Invention]

[0017] In one aspect of the present invention, a transistor containing an oxide semiconductor as an active layer is used as an electrical memory element. By using it as a switching element to control the holding of the load, the charge from the memory element Leakage can be prevented. In addition, the electrode, conductive film, and insulating film have light-shielding properties, and the active layer By inserting this, it is possible to prevent the characteristics of the above transistor from degrading due to light. In terms of structure, it can suppress the threshold voltage shift and prevent the off-current from rising. In one aspect of the present invention, the above-mentioned light-shielding electrode is used as the electrode of a capacitive element. Therefore, because the capacitive elements and transistors are arranged within the memory cell so that they overlap, the capacitive elements The goal is to reduce the area occupied by memory cells while maintaining the required surface area or capacity. can.

[0018] Therefore, a storage device according to one aspect of the present invention ensures a period for retaining data, The storage capacity per unit area can be increased. Alternatively, the present invention relates to the above storage device being semiconductor By using it in body devices, the reliability of semiconductor devices can be improved and their functionality enhanced. [Brief explanation of the drawing]

[0019] [Figure 1] Circuit diagram and cross-sectional view of a memory cell. [Figure 2] Circuit diagram of a memory cell. [Figure 3] Top view of a memory cell. [Figure 4] Cross-sectional view of a memory cell. [Figure 5] Cross-sectional view of a memory cell. [Figure 6] Circuit diagram of the memory unit. [Figure 7] Circuit diagram of the memory unit. [Figure 8] Timing chart for the memory unit. [Figure 9] Block diagram of a memory device. [Figure 10] Block diagram of a memory device. [Figure 11] Circuit diagram of the readout circuit. [Figure 12] Circuit diagram of the characteristic evaluation circuit. [Figure 13] Timing chart for the characteristic evaluation circuit. [Figure 14] This diagram shows the relationship between the elapsed time (Time) and the output signal potential (Vout) in a characteristic evaluation circuit. [Figure 15] This figure shows the relationship between the elapsed time (Time) in the characteristic evaluation circuit and the leakage current calculated by the measurement. [Figure 16] This diagram shows the relationship between the potential at node A and the leakage current in the characteristic evaluation circuit. [Figure 17] Block diagram of an RF tag. [Figure 18] A diagram showing the configuration of a storage medium. [Figure 19] A diagram of an electronic device. [Modes for carrying out the invention]

[0020] The embodiments of the present invention will be described in detail below with reference to the drawings. However, the present invention is... Not limited to the following description, the present invention may have forms and characteristics that do not depart from the spirit and scope of the invention. Those skilled in the art will readily understand that the details can be modified in various ways. Therefore, the present invention This shall not be interpreted as being limited to the contents of the embodiments described below.

[0021] Furthermore, integrated circuits such as microprocessors and image processing circuits, as well as RF tags, storage media, and semiconductors. Any semiconductor device that can use a memory device, such as a body display device, is subject to the present invention. It falls under the category. Furthermore, semiconductor display devices include liquid crystal displays and organic light-emitting diodes (OLEDs). Light-emitting devices equipped with light-emitting elements in each pixel, such as electronic paper and DMD (Digital Media Display), are representative of this type of device. l Micromirror Device), PDP (Plasma Display) Semiconductors such as Panels, FEDs (Field Emission Displays), etc. A semiconductor display device having a circuit element using a body membrane in the pixel or driving circuit falls into this category. It is included in.

[0022] (Embodiment 1) Figure 1(A) shows a circuit diagram illustrating the configuration of a memory cell of a storage device according to one aspect of the present invention, as an example. As shown in Figure 1(A), the memory cell 101 functions as a memory element. A transistor 102, a transistor 103 that functions as a switching element, and a capacitive element. It has 104. Transistor 102, which functions as a memory element, has a gate electrode and an active layer Data is stored by accumulating electric charge in the gate capacitance formed between the two.

[0023] Memory cell 101 may include transistors, diodes, resistors, and capacitive elements as needed. It may also have other circuit elements such as inductors.

[0024] Furthermore, the source and drain electrodes of a transistor are related to the polarity of the transistor and each electrode The name changes depending on the difference in potential applied to the poles. Generally, n-channel In a transistor, the electrode to which a low potential is applied is called the source electrode, and the electrode to which a high potential is applied is called the source electrode. The electrode that is subjected to low potential is called the drain electrode. Also, in a p-channel transistor, the potential is low. The electrode to which a current is applied is called the drain electrode, and the electrode to which a high potential is applied is called the source electrode. It will be discovered. Below, one of the source electrode and the drain electrode will be the first terminal, and the other the second terminal. The memory cell 101 has transistors 102, 103, and capacitive elements 10 Let's explain the connection relationships in section 4.

[0025] In the memory cell 101 shown in Figure 1(A), the first terminal of the transistor 103 is connected The potential of the signal containing the data is applied to the node. Also, the number of transistors 103 Terminal 2 is connected to the gate electrode of transistor 102. Capacitive element 104 has A pair of electrodes are connected, one of which is connected to the gate electrode of transistor 102, and the other is at a predetermined potential. It is connected to the given node.

[0026] Furthermore, Figure 1(B) shows a circuit diagram illustrating a memory cell configuration different from that of Figure 1(A) as an example. In the circuit diagram shown in Figure 1(B), the memory cell 101 functions as a memory element. It has a child 105 and a transistor 103 that functions as a switching element. Data is stored by accumulating electric charge in the capacitive element 105, which functions as a capacitor.

[0027] In the memory cell 101 shown in Figure 1(B), the first terminal of the transistor 103 is connected The potential of the signal containing the data is applied to the node. Also, the capacitive element 105 has One of the pair of electrodes is connected to the second terminal of transistor 103, and the other is subjected to a predetermined potential. It is connected to the node that is being accessed.

[0028] In this specification, "connection" means an electrical connection, and current, voltage, or potential is... This corresponds to a state where it can be supplied or transmitted. Therefore, a connected state is a state where it is directly connected. It does not necessarily refer to a state in which current, voltage, or potential is available or To enable transmission, circuit elements such as wiring, resistors, diodes, and transistors are used. This category also includes situations where the connection is indirect.

[0029] Furthermore, even if components that appear independent on the circuit diagram are connected to each other, in reality For example, when a part of the wiring functions as an electrode, one conductive film can function as an electrode for multiple components. It may also have multiple functions. In this specification, connection means a single conductive film. However, this category also includes cases where a component possesses the functions of multiple other components.

[0030] In one aspect of the present invention, the switching element shown in Figure 1(A) or Figure 1(B) is used as In the channel formation region of the functional transistor 103, the band gap is greater than that of silicon semiconductors. It is characterized by containing oxide semiconductors with a broad carrier range and a lower intrinsic carrier density than silicon. By including an oxide semiconductor having the above-described characteristics in the channel formation region, the off-current A transistor 103 with extremely low performance can be realized. The data 103 is stored in the transistor 102 or the capacitive element 105, which functions as a memory element. By using it as a switching element to hold the stored charge, the leakage of the above charge is prevented. It is possible to do so.

[0031] Unless otherwise specified, in this specification, off-current refers to the off-current of an n-channel transistor. In this state, the drain electrode is at a higher potential than the source electrode and gate electrode, When the potential of the gate electrode is 0 or less relative to the potential of the source electrode, the source electrode and This refers to the current flowing between the drain electrodes. Alternatively, in this specification, off-current means p In channel transistors, the drain electrode is lower than the source electrode and gate electrode. In a state where the potential is such that the potential of the gate electrode is 0 or less when the potential of the source electrode is used as a reference. This refers to the current flowing between the source electrode and the drain electrode when the voltage is above.

[0032] Semiconductors have a wider band gap and a lower intrinsic carrier density than silicon. Examples of conductive materials include, in addition to oxide semiconductors, silicon carbide (SiC), gallium nitride ( Examples of compound semiconductors include GaN, silicon carbide, and gallium nitride. Compound semiconductors must be single crystals, and in order to obtain single-crystal materials, oxide semiconductors Crystal growth at temperatures significantly higher than the process temperature, or epitaxy on special substrates. Silicon wafers that require scalar growth or have strict manufacturing conditions, but are not readily available. Deposition of films on glass substrates with low heat resistance temperatures is difficult. However, oxide semiconductors can be deposited using sputtering. It can be manufactured using methods such as the printing method or wet methods (printing method, etc.), and has advantages such as excellent mass production capabilities. Furthermore, since oxide semiconductors can be deposited even at room temperature, they can be deposited on glass substrates, or on semiconductors. It is possible to deposit thin films on integrated circuits using conductive elements, and it can also accommodate larger substrates. Therefore, among the wide-bandgap semiconductors mentioned above, oxide semiconductors in particular have high mass-producibility. It has the advantage of improving the performance of transistors (for example, field-effect mobility). Even when trying to obtain a crystalline oxide semiconductor for this purpose, heat treatment at 200°C to 800°C is required. This method allows us to obtain crystalline oxide semiconductors.

[0033] In Figure 1(A), the transistor 102, which functions as a memory element, has an active layer. An oxide semiconductor film may be used in the active layer of transistor 102. Silicon or gels, other than oxide semiconductors, in amorphous, microcrystalline, polycrystalline, or single-crystal forms. Semiconductors such as manium may be used. All transistors within memory cell 101 By using an oxide semiconductor film as the active layer, the process can be simplified. Furthermore, the active layer of transistor 102, which functions as a memory element, is, for example, polycrystalline or single-layered. By using semiconductor materials that can achieve higher mobility than oxide semiconductors, such as crystalline silicon This allows for high-speed reading of data from the memory cell 101.

[0034] Note that in Figure 1(A) or Figure 1(B), transistor 103 has a gate electrode on one side of the active layer. This shows the case where it is only on the side. Transistor 103 is present with the active layer in between. If there is a pair of gate electrodes, one of the gate electrodes controls the switching. A signal is given for this purpose, and the other gate electrode is in a floating state, electrically insulated. It can be in a state where it is in a state where it is receiving an electric potential from another source. In the latter case, The same potential may be applied to the paired electrodes, or only the other terminal electrode may be given a ground. A fixed potential such as a tumbler may be applied. The height of the potential applied to the other gate electrode can be controlled. By doing so, the threshold voltage of transistor 103 can be controlled.

[0035] Furthermore, in Figure 1(B), the memory cell 101 functions as a transistor that acts as a switching element. Although the present invention shows a configuration having only one Ta103, the present invention is not limited to this configuration. In one embodiment, a transistor that functions as a switching element is provided in each memory cell at a minimum level. One is sufficient, and the number of transistors mentioned above may be multiple. Memory cell 1 If 01 has multiple transistors that function as switching elements, then the above multiple Transistors can be connected in parallel, or in series, or in series. Parallel connections are also acceptable.

[0036] In this specification, the state in which transistors are connected in series means, for example, the first Only one of the first or second terminals of the first transistor is the first terminal of the second transistor. This means that only one of the terminals, the first or second terminal, is connected. The state in which the transistors are connected in parallel means that the first terminal of the first transistor is connected to the second transistor. The first terminal of the first transistor is connected to the second terminal of the second transistor. This means that it is connected to a child.

[0037] Next, Figure 1(C) shows the cross-section of the transistor 103 and the capacitive element 104 as shown in Figure 1(A). An example of a top view is shown. Note that Figure 1(C) shows the cross-sectional structure of the memory cell 101 shown in Figure 1(A). This shows that the transistor 103 and the capacitive element 105 in Figure 1(B) are also shown in Figure 1( A configuration similar to C) can be adopted.

[0038] In the cross-sectional view shown in Figure 1(C), a capacitive element 104 and a trap are placed on a substrate 110 having an insulating surface. A transistor 103 is formed, and the capacitive element 104 and the transistor 103 are insulated with an insulating film 11. They overlap with a 1 in between.

[0039] Specifically, the capacitive element 104 has electrodes 112 formed on a substrate 110 having an insulating surface and , an insulating film 113 on electrode 112, and electrode 1 that overlaps electrode 112 with the insulating film 113 in between. It has 14. The portion where electrode 112, insulating film 113, and electrode 114 overlap is capacitance It functions as element 104.

[0040] Furthermore, transistor 103 has a gate electrode 1 on the insulating film 111 that covers the electrode 114. 15, the insulating film 116 on the gate electrode 115, and the gate electrode 1 with the insulating film 116 in between. An active layer 117 containing an oxide semiconductor, overlapping with 15, and a source electrode 11 on the active layer 117. 8. It has a drain electrode 119. Furthermore, transistor 103 has an active layer 117. The component includes an insulating film 120 covering the source electrode 118 and the drain electrode 119. It is acceptable to have it. Transistor 103 is a bottom gate type, and also the source electrode 11 Between 8 and the drain electrode 119, a channel formed by etching a portion of the active layer 117. It has an erotic structure.

[0041] Note that Figure 1(C) illustrates the case where transistor 103 has a single-gate structure. However, transistor 103 has multiple electrically connected gate electrodes, It may also be a multi-gate structure having multiple channel-forming regions.

[0042] Furthermore, in one embodiment of the present invention, as shown in Figure 1(C), a light-shielding insulating film 1 21 is formed so as to cover transistor 103. Specifically, transistor 1 An insulating film 121, which functions as a light-shielding layer, is formed so as to overlap with the active layer 117 of 03.

[0043] Furthermore, light-shielding layers such as insulating films, wiring, or electrodes that have light-shielding properties are used in the active layer. The transmittance of light near the absorption edge wavelength of oxide semiconductors, or in the wavelength region shorter than this, is low. Specifically, if the absorption edge wavelength is λ0, the light-shielding layer is such that wavelengths of 100 nm or more are... The transmittance of light below λ0 + 100 nm shall be 50% or less, more preferably 30% or less. For example, the absorption edge wave of the active layer 117 formed using an In-Ga-Zn-O oxide semiconductor. When the wavelength is 393nm, the light-shielding layer has a transmittance of light between 100nm and 493nm. The amount should be 50% or less, more preferably 30% or less. Note that all light included in the above wavelength range is also included. However, it is not necessary to satisfy the above transmittance requirements; at least one wavelength included in the above wavelength range is required. The light must satisfy the above transmittance range. Furthermore, longer wavelengths than the above wavelength range are acceptable. The light transmittance on the side also meets the above range, which prevents the light degradation of the oxide semiconductor. It is desirable in that respect.

[0044] For example, insulating film 121 is a low-grade acid with a lower oxidation number than carbon black and titanium dioxide. A resin containing dispersed black pigments such as titanium dioxide and UV absorbers such as titanium dioxide and zinc oxide. It can be formed using fats. Examples of resins include acrylic resin, polyimide, and benzylamine. Organic resins such as zocyclobutene resin, polyamide, epoxy resin, and siloxane-based resins. It can be used. Siloxane resins are formed by the bonding of silicon (Si) and oxygen (O) to bone. It is a material in which a hierarchical structure is formed. Substituents include hydrogen, fluorine, fluorogroups, and organic groups. It may contain at least one of the following (e.g., alkyl groups, aromatic hydrocarbons).

[0045] Furthermore, when resin is used for the insulating film 121, impurities such as hydrogen and water contained in the resin may be activated. It enters the interface of the active layer 117, the insulating film 116, or the interface and its vicinity with the other insulating film. To prevent clogging, a highly barrier material is used between the insulating film 121 and the active layer 117. It is desirable to form an insulating film 122 with high barrier properties. For example, nitrogen Silicon oxide film, silicon nitride film, aluminum nitride film, or aluminum nitride film, etc. It can be mentioned that the active layer 117 and the insulating film 122 with a high nitrogen content are in direct contact. As a result, the characteristics of transistor 103 may deteriorate, so as shown in Figure 1(C), Between the protective layer 117 and the insulating film 122, there is a silicon oxide film and a silicon oxidnitride film with a low nitrogen content. It is desirable to form any insulating film 120.

[0046] Furthermore, by using an inorganic material containing oxygen in the insulating film 120 that is in contact with the active layer 117, water Oxygen deficiency occurs in the active layer 117 due to heat treatment to reduce the amount of hydrogen. Even so, oxygen is supplied to the active layer 117 from the insulating film 120, reducing the oxygen deficiency that would otherwise be the donor. It is possible to reduce the amount to achieve a configuration that satisfies the stoichiometric composition ratio. Therefore, the active layer 117 This makes it possible to approximate type i, and the variation in the electrical characteristics of transistor 103 due to oxygen deficiency can be reduced. This can reduce noise and improve electrical characteristics.

[0047] Furthermore, by heat-treating the active layer 117 under an oxygen atmosphere, oxygen is added to the oxide semiconductor. Furthermore, the oxygen deficiency that serves as a donor in the active layer 117 may be reduced. Heat treatment temperature This is carried out, for example, at a temperature of 100°C or higher but less than 350°C, preferably 150°C or higher but less than 250°C. The oxygen gas used in the heat treatment under an oxygen atmosphere does not contain water, hydrogen, etc. Preferably, the purity of the oxygen gas introduced into the heat treatment device is set to 6N (99.9999%). ) or higher, preferably 7N (99.99999%) or higher (i.e., the impurity concentration in oxygen is 1p It is preferable that the concentration be 0.1 ppm or less, preferably 0.1 ppm or less.

[0048] Alternatively, oxygen may be added to the active layer 117 using methods such as ion implantation or ion doping. By adding this, the oxygen deficiency of the donor may be reduced. For example, 2.45GHz The oxygen that has been plasma-generated by microwaves should be added to the active layer 117.

[0049] In this specification, an oxidized nitride is defined as a compound in which the oxygen content is higher than the nitrogen content. It is a substance, and nitride oxides have a higher nitrogen content than oxygen in their composition. It refers to a substance. For example, silicon oxidnitride contains 50 to 70 atomic percent oxygen, and nitrogen. Element is 0.5 atomic% to 15 atomic%, silicon is 25 atomic% to 35 atomic%, and hydrogen is 0 The substance may be included in an amount of 0.1 atomic% to 10 atomic%. Also, nitride acid. Silicon is a compound containing 5 to 30 atomic percent oxygen and 20 to 55 atomic percent nitrogen. , in the range of silicon at 25 atomic% to 35 atomic% and hydrogen at 10 atomic% to 30 atomic% It may be a substance that is included. However, the range of the above composition is determined by Rutherford backscattering method. RBS: Rutherford Backscattering Spectromet ry) and hydrogen forward scattering (HFS) This is the result when measured using a ring. Furthermore, the content ratio of the constituent elements is the sum of the elements. It takes a value that does not exceed 100 atomic percent.

[0050] Furthermore, in one embodiment of the present invention, as shown in Figure 1(C), the capacitive element 104 has At least one of electrode 112 or electrode 114 has light-shielding properties. The electrode 112 or electrode 114 is positioned to overlap with the active layer 117 of the transistor 103. It has been done.

[0051] With the above configuration, an electrode 112 or electrode 114 having light-shielding properties and a light-shielding insulating film are provided. Since the active layer 117 is sandwiched between 121 and the active layer, light near the absorption edge wavelength of the oxide semiconductor, if This prevents light in a shorter wavelength range from entering the active layer 117.

[0052] Next, Figure 1(D) shows the cross-section of the transistor 103 and the capacitive element 104 as shown in Figure 1(A). An example of a top view is shown. Note that Figure 1(D) shows the cross-sectional structure of the memory cell 101 shown in Figure 1(A). This shows that the transistor 103 and the capacitive element 105 in Figure 1(B) are also shown in Figure 1( A configuration similar to D) can be adopted.

[0053] In the cross-sectional view shown in Figure 1(D), similar to Figure 1(C), on the substrate 110 having an insulating surface, A capacitive element 104 and a transistor 103 are formed, and the capacitive element 104 and transistor 103 is superimposed with the insulating film 111 in between.

[0054] The specific configuration of the capacitive element 104 and the transistor 103 is the same as in Figure 1(C). In Figure 1(D), wiring 123 is formed with a light-shielding conductive film, and wiring 123 It covers transistor 103. Specifically, it overlaps with the active layer 117 of transistor 103. To achieve this, a light-shielding wiring 123 is formed.

[0055] The characteristics required for the light-shielding wiring 123 are as described above, and are used in the active layer. The transmittance of light in the vicinity of the absorption edge wavelength of oxide semiconductors, or in wavelengths shorter than that, is low. Therefore, a metal possessing both conductivity and light-shielding properties will be used for the wiring 123. For example For example, wiring 123 contains molybdenum, titanium, chromium, tantalum, tungsten, and aluminum. Metallic materials such as um, copper, neodymium, and scandium, and alloy materials that are mainly composed of these metallic materials. Conductive films using these materials, or nitrides of these metals, can be used in single layers or in multilayer configurations. .

[0056] Furthermore, in Figure 1(D), similar to Figure 1(C), the electrodes 112 or the capacitive element 104 At least one of the electrodes 114 is light-shielding. And the light-shielding electrode 112 or The electrode 114 is formed in a position that overlaps with the active layer 117 of the transistor 103.

[0057] With the above configuration, Figure 1(D) shows an electrode 112 or electrode 114 that has light-shielding properties, and Since the active layer 117 is sandwiched between the wiring 123 which has properties, the absorption edge wavelength of the oxide semiconductor This prevents nearby light, or light in a shorter wavelength range, from entering the active layer 117. It is possible.

[0058] In Figures 1(C) and 1(D), transistor 103 is on the insulating film 120. The back gate electrode may be located in a position that overlaps with the channel formation region of the active layer 117. When forming a back gate electrode, an insulating film is formed to cover the back gate electrode. The back gate electrode may be in an electrically insulated floating state, or It is also possible that the position is given. In the latter case, the back gate electrode has gate electrode 1 It is also acceptable for the same potential as 15 to be applied, or for a fixed potential such as ground to be applied. It is also acceptable to do so. By controlling the height of the potential applied to the back gate electrode, transistor 1 The threshold voltage of 03 can be controlled.

[0059] Note that in Figures 1(C) and 1(D), transistor 103 is a bottom-gate type. Furthermore, although the case having a channel etch structure has been shown, in one aspect of the present invention The structure of a transistor is not limited to this configuration.

[0060] In one aspect of the present invention, a transistor 103 containing an oxide semiconductor in its active layer 117 is used as a memory element Controlling the charge retention in the transistor 102 or capacitive element 105 used as a child. By using it as a switching element, the above-mentioned charge leakage can be prevented. Furthermore, by sandwiching the active layer 117 with layers such as light-shielding electrodes, conductive films, and insulating films, This prevents the characteristics of the transistor 103 from degrading due to light. Specifically, This suppresses the threshold voltage shift and prevents the off-current from rising. Furthermore, this development In one embodiment, the light-shielding electrode is connected to the electrical element 104 or 105. It is used as pole 112 or electrode 114. Therefore, capacitive element 104 or capacitive element 105 Since the transistor 103 is positioned within the memory cell 101 so as to overlap with the capacitive element While ensuring the occupied area or capacitance value of 104 or the capacitive element 105, memory cell 10 The area occupied by 1 can be reduced.

[0061] Therefore, a storage device according to one aspect of the present invention ensures a period for retaining data, The storage capacity per unit area can be increased. Alternatively, the present invention relates to the above storage device being semiconductor By using it in body devices, the reliability of semiconductor devices can be improved and their functionality enhanced.

[0062] Next, Figure 2 shows a more specific example of the connection configuration of various wirings in the memory cell 101. vinegar.

[0063] The memory cell 101 shown in Figure 2(A) is a transistor 1 that functions as a switching element. It has transistor 03 and a capacitive element 105 that functions as a memory element. The electrode is connected to the word line WL. Also, the first terminal of transistor 103 is data It is connected to the DL wire, and the second terminal is connected to one electrode of the capacitive element 105. The other electrode of the capacitive element 105 is in contact with a node to which a fixed potential such as ground is applied. It continues.

[0064] In the memory cell 101 shown in Figure 2(A), when data is written, the transistor 103 is The signal potential, including the data, is transmitted from the data line DL through transistor 103. The signal is applied to one electrode of the capacitance element 105. Then, according to the potential of the above signal, the capacitance element 1 The amount of charge stored in 05 is controlled, which allows data to be written to the capacitive element 105. It will take place.

[0065] Next, when data is being held, transistor 103 is turned off, and capacitive element 105 is... The charge is retained. As mentioned above, transistor 103 has an extremely low off-current. It has the characteristic of being less prone to leakage of charge stored in the capacitive element 105, and shielding If light is not used, or if semiconductor material such as silicon is used for transistor 103 Compared to other methods, it allows for data retention over a longer period.

[0066] When data is read, transistor 103 turns on, and capacitance is transmitted via the data line DL. The charge accumulated in element 105 is extracted. Then, the difference in the amount of charge is read. This allows the data to be read.

[0067] The memory cell 101 shown in Figure 2(B) is a transistor 1 that functions as a switching element. It has 03, a transistor 102 that functions as a memory element, and a capacitive element 104. The gate electrode of transistor 103 is connected to the first word line WLa. The first terminal of the ZISTA 103 is connected to the first data line DLa, and the second terminal is connected to the transistor It is connected to the gate electrode of transistor 102. The first terminal of transistor 102 is the second data line. A node connected to DLb, with the second terminal having a fixed potential such as ground. It is connected to the transistor 102. The pair of electrodes of the capacitive element 104 are connected such that one electrode is connected to the transistor 102. It is connected to the gate electrode, and the other end is connected to the second word line WLb.

[0068] In the memory cell 101 shown in Figure 2(B), when data is written, the transistor 103 is The potential of the signal containing data from the first data line DLa is transmitted through transistor 103. This is then applied to the gate electrode of transistor 102. Then, according to the potential of the above signal, The gate capacitance of transistor 102 and the amount of charge stored in capacitive element 104 are controlled. This allows data to be written to transistor 102 and capacitive element 104.

[0069] Next, when data is being held, transistor 103 turns off, and transistor 102 The gate capacitance and the charge stored in the capacitive element 104 are retained. As described above, The inverter 103 has the characteristic of having an extremely low off-current. Therefore, the accumulated The above charge is unlikely to leak, and if light shielding is not performed, or if silicon is connected to transistor 103 Compared to using semiconductor materials such as , it is possible to retain data for a longer period of time. Cut.

[0070] When reading data, the potential of the second word line WLb is changed. Capacitive element 104 is present. The potential difference between the pair of electrodes remains maintained by the law of conservation of charge, so the second word line WL The change in potential at b is applied to the gate electrode of transistor 102. Transistor 102 The threshold voltage changes depending on the amount of charge stored in its gate capacitance. Therefore, The potential of the gate electrode of transistor 102 changes, resulting in the following By reading the difference in the amount of charge stored from the magnitude of the drain current, data It can be read.

[0071] The memory cell 101 shown in Figure 2(C) has one data line DL, and the first data line DLa and the second In that it also has the functionality of a 2-data-line DLb, the memory cell 10 shown in Figure 2(B) It differs from 1. Specifically, the memory cell 101 shown in Figure 2(C) is a switching element A transistor 103 that functions as a memory element, and a transistor 102 that functions as a memory element, It has a capacitive element 104. The gate electrode of transistor 103 is connected to the first word line WLa. They are connected. Also, the first terminal of transistor 103 is connected to the data line DL. The second terminal is connected to the gate electrode of transistor 102. Terminal 1 is connected to the data line DL, and terminal 2 is supplied with a fixed potential such as ground. It is connected to the node that is being connected. The pair of electrodes of the capacitive element 104 are such that one is a trap It is connected to the gate electrode of inverter 102, and the other end is connected to the second word line WLb.

[0072] The memory cell 101 shown in Figure 2(C) performs operations such as writing, holding, and reading data. This can be done in the same manner as the memory cell 101 shown in Figure 2(B).

[0073] The memory cell 101 shown in Figure 2(D) is a transistor 1 that functions as a switching element. 03, a transistor 102 that functions as a memory element, a capacitive element 104, and data reading It has a transistor 106 that functions as a switching element to control the output. The gate electrode of transistor 103 is connected to the first word line WLa. The first terminal of sta103 is connected to the first data line DLa, and the second terminal is connected to a transistor. It is connected to the gate electrode of 102. The first terminal of transistor 102 is connected to the transistor It is connected to the second terminal of 106, and the second terminal is given a fixed potential such as ground. It is connected to the node. The first terminal of transistor 106 is connected to the second data line D It is connected to Lb. The gate electrode of transistor 106 is connected to the second word line WLb. The pair of electrodes of the capacitive element 104 are connected to the gate of the transistor 102. One end is connected to an electrode, and the other end is connected to a node to which a fixed potential is applied.

[0074] In the memory cell 101 shown in Figure 2(D), when data is written, the transistor 103 is The potential of the signal containing data from the first data line DLa is transmitted through transistor 103. This is then applied to the gate electrode of transistor 102. Then, according to the potential of the above signal, The gate capacitance of transistor 102 and the amount of charge stored in the capacitive element 104 are controlled. Then, data is written to transistor 102 and capacitive element 104.

[0075] Next, when data is being held, transistor 103 turns off, and transistor 102 The gate capacitance and the charge stored in the capacitive element 104 are retained. As described above, The STA103 has the characteristic of having an extremely low off-current. Therefore, the accumulated above Electric charge is less likely to leak, and if light shielding is not performed, or if semiconductor materials such as silicon are used... Compared to other methods, this allows for data retention over a longer period.

[0076] When data is read, the potential of the second word line WLb changes, causing transistor 10 6 turns on. When transistor 106 turns on, transistor 102 receives that signal. A drain current of a height commensurate with the amount of charge stored in the capacitor flows. Therefore, By reading the magnitude of the drain current of the converter 102, we can determine the difference in the amount of charge stored. This allows the data to be read.

[0077] (Embodiment 2) In this embodiment, the specific configuration of the memory cell in the storage device according to one aspect of the present invention is described. An example will be described. In this embodiment, the circuit configuration shown in Figure 2(C) is used. Let's take a memory cell as an example and explain its structure.

[0078] Figure 3 shows an example of a top view of a memory cell. Note that Figure 3 clearly shows the structure of the memory cell. Therefore, all insulating films other than those with light-shielding properties are omitted from the diagram. Figure 4 shows a cross-sectional view along the dashed line A1-A2 in section 3.

[0079] The memory cell shown in Figures 3 and 4 has a transistor 102 on a substrate 110 having an insulating surface. It has a transistor 103 and a capacitive element 104. And it is formed on a substrate 110. The capacitor element 104 is covered with an insulating film 111, and on the insulating film 111 there is a transistor 1 02 and transistor 103 are formed. And capacitive element 104 and transistor sta 102 and transistor 103 are stacked on top of each other with an insulating film 111 in between.

[0080] Specifically, the capacitive element 104 has electrodes 112 formed on a substrate 110 having an insulating surface and , an insulating film 113 on electrode 112, and electrode 1 that overlaps electrode 112 with the insulating film 113 in between. It has 14. The portion where electrode 112, insulating film 113, and electrode 114 overlap is capacitance It functions as element 104.

[0081] Furthermore, transistor 103 has a source electrode or drain electrode on the insulating film 111. Functional conductive films 130 and 131, and an acid in contact with conductive films 130 and 131. An active layer 132 containing a semiconductor, and a conductive film 130, a conductive film 131, and the active layer 132 covering it. The insulating film 133 and the gate electrode 13 which overlaps with the active layer 132 with the insulating film 133 in between. It has 4.

[0082] The transistor 103 shown in Figures 3 and 4 is a top-gate type and also has a source electrode. Alternatively, conductive films 130 and 131, which function as drain electrodes, are located beneath the active layer 132. It is a bottom contact structure where the parts are in contact on the sides.

[0083] Furthermore, transistor 102 has a source electrode or drain electrode on the insulating film 111. Functional conductive films 131 and 135, and an acid in contact with conductive films 131 and 135. An active layer 136 containing a semiconductor, and a conductive film 131, a conductive film 135, and the active layer 136 are covered The insulating film 133 and the gate electrode 13 which overlaps with the active layer 136 with the insulating film 133 in between. It has 7.

[0084] The transistor 102 shown in Figures 3 and 4 is a top-gate type, similar to transistor 103. The conductive film 131 and conductive film are present and also function as a source electrode or drain electrode. 135 is in contact with the underside of the active layer 136, forming a bottom contact structure.

[0085] Furthermore, in Figures 3 and 4, transistors 102 and 103 have a single-gate structure. The example given is that transistors 102 and 103 are electrically connected. Having multiple connected gate electrodes, it has multiple channel-forming regions, a multi-gate It may also be a T-structure.

[0086] Then, the conductive film 130, through the contact hole 138 formed in the insulating film 111, It is in contact with electrode 114.

[0087] Furthermore, an insulating film 139 is formed to cover transistors 102 and 103. And on the insulating film 139, there are contact holes 1 formed in the insulating film 139. A light-shielding conductive material connected to the gate electrode 137 of transistor 102 via 40. A film 141 is formed. Furthermore, the conductive film 141 is formed between the insulating film 139 and the insulating film 133. It is connected to the conductive film 130 through the formed contact hole 142. On the film 139, a transient is transmitted through a contact hole 143 formed in the insulating film 139. A light-shielding conductive film 144 is formed on the gate electrode 134 of the terminal 103. ru.

[0088] The light-shielding conductive film 141 is at least a part of the active layer 136 of the transistor 102 It is formed in an overlapping position. Furthermore, in order to further block light incident on the active layer 136, the active layer 1 It is desirable to completely cover the entire 36 with the conductive film 141.

[0089] Furthermore, the light-shielding conductive film 144 is at least on the active layer 132 of the transistor 103. It is formed in a position that overlaps with a part of it. Furthermore, in order to further block light from entering the active layer 132, It is desirable to completely cover the entire conductive layer 132 with the conductive film 144.

[0090] Furthermore, in one aspect of the present invention, the electrode 112 or electrode 114 of the capacitive element 104 is reduced At the very least, one of them has light-shielding properties. And the light-shielding electrode 112 or electrode 114 , a position that overlaps with the active layer 132 of transistor 103 and the active layer 136 of transistor 102. It is formed in such a way that at least a portion of the active layer 132 and the active layer 136 are connected to the electrode 11. 2 or it is sufficient if it overlaps with electrode 114. However, if the active layer 132 or active layer 136 To further block incoming light, the entire active layer 132, or the entire active layer 136, It is desirable to position it so that it overlaps with electrode 112 or electrode 114.

[0091] Required characteristics for light-shielding electrodes 112, 114, conductive film 141, and conductive film 144 As mentioned above, this is near the absorption edge wavelength of the oxide semiconductor used in the active layer, or The transmittance of light in a shorter wavelength range than this is assumed to be low. Therefore, electrode 112, electrode 11 4. Conductive films 141 and 144 use metals that possess both conductivity and light-shielding properties. For example Electrodes 112 and 114 are made of molybdenum, titanium, chromium, tantalum, and tungsten. Metal materials such as cellulose, neodymium, and scandium, and alloy materials that mainly consist of these metal materials are used. The conductive film, or nitrides of these metals, can be used as a single layer or in a multilayer structure. In addition to the materials mentioned above, aluminum or copper may be used for conductive films 141 and 144. It is also possible to use aluminum or copper for conductive film 141 and conductive film 144. To avoid problems with heat resistance and corrosion, it is best to use it in combination with high-melting-point metal materials. High melting point metal materials include molybdenum, titanium, chromium, tantalum, tungsten, and neodymium. Gymn, scandium, etc., can be used.

[0092] For example, the electrode 112, electrode 114, conductive film 141, and conductive film 144 are arranged in a two-layer laminated structure. In this case, a two-layer laminated structure is formed by laminating a molybdenum film on an aluminum film, and molybdenum is laminated on a copper film. A two-layer structure with a copper film, or a two-layer structure with a titanium nitride film or tantalum nitride film laminated on a copper film. It is preferable to have a structure, or a two-layer structure in which a titanium nitride film and a molybdenum film are stacked. When the electrode 112, electrode 114, conductive film 141, and conductive film 144 have a three-layer laminated structure. Aluminum film, aluminum-silicon alloy film, aluminum-titanium alloy film Alternatively, an aluminum-neodymium alloy film is used as an intermediate layer, with a tungsten film and tungsten nitride. It is preferable to have a structure in which a film, a titanium nitride film, or a titanium film is laminated as upper and lower layers.

[0093] The film thickness of electrode 112, electrode 114, conductive film 141, and conductive film 144 is, for example, 10 The wavelength is between 400 nm and 100 nm to 200 nm.

[0094] In one aspect of the present invention, the above configuration provides a light-shielding electrode 112 or electrode 114, Since the active layer 136 is sandwiched between the light-shielding conductive film 141, the absorption edge of the oxide semiconductor This prevents light near the wavelength, or light in the shorter wavelength range, from entering the active layer 136. It is possible to do so. In addition, an electrode 112 or electrode 114 that has light-shielding properties and Since the active layer 132 is sandwiched between the conductive films 144, light near the absorption edge wavelength of the oxide semiconductor, Alternatively, it is possible to prevent light in a shorter wavelength range from entering the active layer 132. .

[0095] In Figures 3 and 4, conductive films 141 and 144, which function as wiring, are used to activate Although the example given is a configuration in which layer 132 or the active layer 136 is shielded from light, the configuration shown in Figure 1(C) Similarly, an insulating film having light-shielding properties is used to shield the active layer 132 or the active layer 136 from light. That's fine.

[0096] Furthermore, in Figures 3 and 4, the transistor 102, which functions as a memory element, has its active layer 13 Although the example in 6 shows the case where an oxide semiconductor is included, transistor 102 is not necessarily an oxide semiconductor. The active layer does not necessarily have to contain a semiconductor material. For example, a semiconductor such as silicon or germanium. When forming the active layer of transistor 102 using a conductive material, the active layer is formed on one insulating surface. The capacitance layer and the capacitance element 104 can be formed together. Furthermore, the capacitance element 104 The electrode 112, like the active layer described above, also uses semiconductor materials such as silicon or germanium. It can be formed by [doing something].

[0097] Furthermore, electrode 112 also functions as the second word line WLb. Also, the conductive film 144, It also functions as the first word line WLa. Furthermore, the conductive film 131 also functions as a data line DL. The conductive film 135 functions as wiring to which a fixed potential such as ground is applied.

[0098] There are no major restrictions on the materials that can be used as the substrate 110, but at least, It is necessary to have sufficient heat resistance to withstand the heat treatment during the manufacturing process. For example The substrate 110 can be a glass substrate, a quartz substrate, or a substrate fabricated by the fusion method or the float method. Ceramic substrates and the like can be used. Glass substrates are suitable because the subsequent heat treatment temperature is high. In such cases, it is best to use materials with a strain point of 730°C or higher. Substrates made of synthetic resin generally tend to have a lower heat resistance temperature compared to the above substrates. It can be used if it can withstand the processing temperature during the manufacturing process.

[0099] Furthermore, the insulating film 133 is a silicon oxide film made using plasma CVD or sputtering. silicon nitride film, silicon oxide nitride film, silicon oxide nitride film, aluminum oxide film, aluminum nitride Aluminum film, aluminum oxide nitride film, aluminum nitride oxide film, hafnium oxide film or oxide The tantalum film can be formed as a single layer or by stacking layers. It functions as a gate insulating film. The insulating film 133 should preferably contain as few impurities as possible, such as water, hydrogen, and oxygen. When depositing a silicon oxide film using the tailing method, a silicon target is used as the target. Using a quartz or crystalline target, oxygen or a mixture of oxygen and argon is used as the sputtering gas. Use "su".

[0100] By removing impurities, an oxide semiconductor is made i-type or substantially i-type (high-purity) Because the oxide semiconductor (which has been purified) is extremely sensitive to interface states and interface charges, it is highly purified. The interface between the oxide semiconductor and the gate insulating film is important. Therefore, highly purified oxide semiconductor The gate insulating film (GI) that contacts the conductor requires high quality.

[0101] For example, high-density plasma CVD using μ-waves (frequency 2.45 GHz) produces dense and dielectric materials. Since it can form a high-pressure, high-quality insulating film, it is suitable as a method for forming the insulating film 133. The interface is formed by the close contact between the highly purified oxide semiconductor and the high-quality gate insulating film. This is because it reduces the energy levels and improves the interfacial properties.

[0102] Of course, if it can form a good quality insulating film 133 as a gate insulating film, sputtering Other film deposition methods such as the ring method and plasma CVD can be applied. Furthermore, after film deposition... The insulating film may also be one whose film quality and interface properties with oxide semiconductors are improved by heat treatment. In any case, it is essential that the film quality as a gate insulating film is good, as well as gate insulation Any solution that can reduce the interface state density between the film and the oxide semiconductor and form a good interface would be ideal. .

[0103] Furthermore, by using an inorganic material containing oxygen in the insulating film 133, moisture or hydrogen can be reduced. Even if oxygen deficiencies occur in the active layer 132 and active layer 136 due to the heat treatment for this purpose Oxygen is supplied from the insulating film 133 to the active layer 132 and the active layer 136, and oxygen deficiencies that serve as donors are eliminated. It is possible to reduce the amount and create a configuration that satisfies the stoichiometric composition ratio. Therefore, the active layer 13 2. The active layer 136 can be brought closer to type i, and the electrical characteristics of the transistor due to oxygen deficiency can be improved. This reduces variations and improves electrical characteristics.

[0104] Furthermore, the oxide semiconductor film used as the active layer 132 or active layer 136 has a thickness of 2 nm or more. Less than 200 nm, preferably a film thickness of 3 nm or more and 50 nm or less, more preferably a film thickness of 3 nm or more and 20 nm or less. The oxide semiconductor film is formed by using an oxide semiconductor as a target and a sputtering method. The oxide semiconductor film can also be formed by sputtering in an atmosphere of a noble gas (e.g., argon), an oxygen atmosphere, or a mixed atmosphere of a noble gas (e.g., argon) and oxygen. It can be formed by a sputtering method.

[0105] As described above, the oxide semiconductor film includes a quaternary metal oxide In-Sn-Ga-Zn -O-based oxide semiconductor, a ternary metal oxide In-Ga-Zn-O-based oxide semiconductor, In-Sn-Zn-O-based oxide semiconductor, In-Al-Zn-O-based oxide semiconductor, Sn-G a-Zn-O-based oxide semiconductor, Al-Ga-Zn-O-based oxide semiconductor, Sn-Al-Zn -O-based oxide semiconductor, a binary metal oxide In-Zn-O-based oxide semiconductor, Sn- Zn-O-based oxide semiconductor, Al-Zn-O-based oxide semiconductor, Zn-Mg-O-based oxide semiconductor, Sn-Mg-O-based oxide semiconductor, In-Mg-O-based oxide semiconductor, In-Ga-O-based oxide semiconductor, In-O-based oxide semiconductor, Sn-O-based oxide semiconductor, Zn-O-based oxide semiconductor, etc. can be used.

[0106] For example, when a thin film of an In-Ga-Zn-O-based oxide semiconductor obtained by a sputtering method is used as the oxide semiconductor film, as a target, for example, a target having a composition ratio of In2O3:Ga2O3:Z nO = 1:1:1 [mol ratio] is used. Also, a target having a composition ratio of In2O 3:Ga2O3:ZnO = 1:1:2 [mol ratio], and also a target having a composition ratio of In2O3:Ga2O3:ZnO = 1:1:4 [mol ratio] is used. It is possible. Also, the packing density of targets containing In, Ga, and Zn is 90% or more. The fill density is 100% or less, preferably 95% or more and less than 100%. A target with a high fill density is used. As a result, the deposited oxide semiconductor film becomes a dense film.

[0107] Furthermore, when using an In-Zn-O based material as the oxide semiconductor, the combination of targets used The ratio is an atomic ratio, where In:Zn = 50:1 to 1:2 (which translates to In2O3 in mole ratio). :ZnO=25:1~1:4), preferably In:Zn=20:1~1:1 (in terms of mole ratio) When converted, In2O3:ZnO = 10:1 to 2:1, and more preferably In:Zn = 1 0.5:1~15:1 (converted to a mole ratio of In2O3:ZnO=3:4~15:2) For example, the target used to form In-Zn-O oxide semiconductors has an atomic ratio of When In:Zn:O = X:Y:Z, assume Z > 1.5X + Y. Set the ratio of Zn within the above range. By storing them compactly, mobility can be improved.

[0108] Furthermore, in oxide semiconductor films formed by sputtering, etc., water or hydrogen may be present as impurities. It can be present in large quantities. Water or hydrogen readily forms donor levels, thus oxidizing Water is an impurity for semiconductors. Therefore, in one aspect of the present invention, water in an oxide semiconductor film To reduce impurities such as nitrogen or hydrogen, nitrogen, oxygen, and hydrogen are added to the oxide semiconductor film. Heat treatment is performed in a dry air or noble gas (argon, helium, etc.) atmosphere. The above gas has a water content of 20 ppm or less, preferably 1 ppm or less, preferably 1 It is desirable that the level be 0 ppb or less.

[0109] By applying heat treatment to the oxide semiconductor film, water or hydrogen is removed from the oxide semiconductor film. This is possible. Specifically, 300°C to 700°C, preferably 300°C to 50°C. Heat treatment should be performed at 0°C or below. For example, at 500°C for 3 to 6 minutes. Yes, that's fine. If the RTA method is used for heat treatment, dehydration or dehydrogenation can be performed in a short time, It can process even at temperatures exceeding the strain point of the glass substrate.

[0110] Heat treatment devices include electric furnaces, as well as heat conduction or thermal radiation from heat sources such as resistance heating elements. It may also be a device that heats the object to be processed. For example, GRTA (Gas Rapid T thermal annealing) equipment, LRTA (Lamp Rapid Thermal RTA (Rapid Thermal Anneal) devices such as Anneal devices It can be used. The LRTA device can use halogen lamps, metal halide lamps, xenon Examples include arc lamps, carbon arc lamps, high-pressure sodium lamps, and high-pressure mercury lamps. This device heats the object being processed by radiating light (electromagnetic waves) from a lamp. GRTA The apparatus is a device that performs heat treatment using high-temperature gas. The gas is a rare gas such as argon. An inert gas that does not react with the material being treated by heat treatment, such as sulfur or nitrogen, is used. ru.

[0111] The above-mentioned heat treatment reduces the hydrogen concentration in the oxide semiconductor film, thereby increasing its purity. Yes, it is possible. This allows for stabilization of the properties of oxide semiconductor films. Also, glass Heat treatment below the transition temperature results in a low carrier density due to hydrogen and a widening of the band gap. A large oxide semiconductor film can be formed. Therefore, transistors can be formed using a large-area substrate. 102. Transistors 103 can be fabricated, and mass productivity can be enhanced.

[0112] When heating the oxide semiconductor film, depending on the material and heating conditions of the oxide semiconductor film, plate-like crystals may be formed on the surface thereof. The plate-like crystals are preferably single crystals with a c-axis orientation substantially perpendicular to the surface of the oxide semiconductor film. Also, even if it is not a single crystal, it is preferable that each crystal is a polycrystal with a c-axis orientation substantially perpendicular to the surface of the oxide semiconductor film. Moreover, in addition to the c-axis orientation, it is preferable that the ab planes of each crystal coincide, or the a-axis or b-axis coincides. When there are irregularities on the underlying surface of the oxide semiconductor film, the plate-like crystals become polycrystals. Therefore, it is desired that the underlying surface is as flat as possible. In one aspect of the present invention, by using the transistor 103 including an oxide semiconductor in the active layer 132 as a switching element for controlling the charge retention in the transistor 102 or the capacitor element 104 used as a memory element, the leakage of the charge can be prevented. Also, by sandwiching the active layer 132 with a light-shielding layer such as an electrode having light-shielding properties, a conductive film, or an insulating film, deterioration of the characteristics of the transistor 103 due to light can be prevented. Specifically, a shift in the threshold voltage can be suppressed, and an increase in the off-current can be prevented. Furthermore, in one aspect of the present invention, the electrode having light-shielding properties is used as the electrode 112 or electrode 114 of the capacitor element 104. Therefore, since the capacitor element 104 and the transistor 103 are disposed in the memory cell 101 so as to overlap, the exclusive area or capacitance value of the capacitor element 104 can be secured.

[0113] In one aspect of the present invention, by using the transistor 103 including an oxide semiconductor in the active layer 132 as a switching element for controlling the charge retention in the transistor 102 or the capacitor element 104 used as a memory element, the leakage of the charge can be prevented. Also, by sandwiching the active layer 132 with a light-shielding layer such as an electrode having light-shielding properties, a conductive film, or an insulating film, deterioration of the characteristics of the transistor 103 due to light can be prevented. Specifically, a shift in the threshold voltage can be suppressed, and an increase in the off-current can be prevented. Furthermore, in one aspect of the present invention, the electrode having light-shielding properties is used as the electrode 112 or electrode 114 of the capacitor element 104. Therefore, since the capacitor element 1,04 and the transistor 103 are disposed in the memory cell 101 so as to overlap, the exclusive area or capacitance value of the capacitor element 104 can be secured. Specifically, a shift in the threshold voltage can be suppressed, and an increase in the off-current can be prevented. Furthermore, in one aspect of the present invention, the electrode having light-shielding properties is used as the electrode 112 or electrode 114 of the capacitor element 104. Therefore, since the capacitor element 104 and the transistor 103 are disposed in the memory cell 101 so as to overlap, the exclusive area or capacitance value of the capacitor element 104 can be secured. Therefore, since the capacitor element 104 and the transistor 103 are disposed in the memory cell 101 so as to overlap, the exclusive area or capacitance value of the capacitor element 104 can be secured. At the same time, the area occupied by the memory cell 101 can be reduced.

[0114] Therefore, a storage device according to one aspect of the present invention ensures a period for retaining data, The storage capacity per unit area can be increased. Alternatively, the present invention relates to the above storage device being semiconductor By using it in body devices, the reliability of semiconductor devices can be improved and their functionality enhanced.

[0115] This embodiment can be implemented in appropriate combination with the above embodiment.

[0116] (Embodiment 3) In this embodiment, the transistor 103, which functions as a switching element, is shown in Figure 1(D). Let's describe an example of a different configuration.

[0117] Figure 5(A) shows an example of a cross-sectional view of transistor 103 and capacitive element 104. Figure 5(A) shows the cross-sectional structure of the memory cell 101 shown in Figure 1(A), but Figure 1(B) The transistor 103 and the capacitive element 105 also employ the same configuration as in Figure 5(A). It is possible.

[0118] In the cross-sectional view shown in Figure 5(A), similar to Figure 1(D), on the substrate 110 having an insulating surface, A capacitive element 104 and a transistor 103 are formed, and the capacitive element 104 and transistor 103 is superimposed with the insulating film 111 in between.

[0119] The specific configuration of the capacitive element 104 is the same as in Figure 1(D). In Figure 5(A), the transient STA 103 differs from Figure 1(D) in that it has a channel protection structure.

[0120] The transistor 103 shown in Figure 5(A) has a gate electrode 150 on an insulating film 111 and a gate The insulating film 151 on the electrode 150, and the insulating film 151 overlapping with the gate electrode 150 The active layer 152 containing an oxide semiconductor and the gate electrode 150 are active at a position overlapping with the gate electrode 150. A channel protective film 153 formed on layer 152 and a source electric field formed on the active layer 152 It has an electrode 154 and a drain electrode 155. Furthermore, the transistor 103 has a source electrode An electrode 154, a drain electrode 155, a channel protective film 153, and an insulating film formed on the active layer 152 The border film 156 may also be included as a component.

[0121] By providing the channel protective film 153, the channel formation region of the active layer 152 is formed. In relation to the time, film reduction due to plasma and etching agent during subsequent etching processes. This can prevent damage. Therefore, the reliability of transistors can be improved. ru.

[0122] By using an inorganic material containing oxygen in the channel protective film 153, moisture or hydrogen can be reduced. Even if oxygen deficiency occurs in the active layer 152 due to the heat treatment for this purpose, Oxygen is supplied to channel 2 from the channel protection membrane 153, reducing the oxygen deficiency that would otherwise be the donor, thus stoichiometrically. It is possible to create a configuration that satisfies the desired composition ratio. Therefore, the active layer 152 is made closer to type i. This reduces variations in the electrical characteristics of transistors due to oxygen deficiency and provides high voltage resistance. This allows for improvements in electrical characteristics, such as lower off-current.

[0123] Furthermore, transistor 103 has a back gate electrode on the insulating film 156. This is also good. The back gate electrode is formed so as to overlap with the channel formation region of the active layer 152. The back gate electrode may be in an electrically insulated floating state. It is also acceptable for an electric potential to be applied. In the latter case, the back gate electrode is a gate electrode. It is also acceptable for the same potential as 150 to be applied, or for a fixed potential such as ground to be applied. It is acceptable even if it is. By controlling the height of the potential applied to the buck gate electrode, the transistor It can control the threshold voltage of 103.

[0124] Then, in Figure 5(A), wiring 123 is formed with a light-shielding conductive film, and wiring 123 It is the same as in Figure 1(D) in that it covers transistor 103. Specifically, Light-shielding wiring 123 is formed so as to overlap with the active layer 152 of transistor 103. ru.

[0125] Furthermore, in Figure 5(A), similar to Figure 1(D), the electrodes 112 or the capacitive element 104 At least one of the electrodes 114 is light-shielding. And the light-shielding electrode 112 or The electrode 114 is formed in a position that overlaps with the active layer 152 of the transistor 103.

[0126] With the above configuration, Figure 5(A) shows an electrode 112 or electrode 114 that has light-shielding properties, and Since the active layer 152 is sandwiched between the wiring 123 which has properties, the absorption edge wavelength of the oxide semiconductor This prevents light from nearby or from light in a shorter wavelength range from entering the active layer 152. It is possible.

[0127] Furthermore, the transistor 103, which functions as a switching element, has a different configuration from that shown in Figure 1(D). Let me explain another example.

[0128] Figure 5(B) shows an example of a cross-sectional view of transistor 103 and capacitive element 104. Figure 5(B) shows the cross-sectional structure of the memory cell 101 shown in Figure 1(A), but Figure 1(B) The transistor 103 and the capacitive element 105 also employ the same configuration as in Figure 5(B). It is possible.

[0129] In the cross-sectional view shown in Figure 5(B), similar to Figure 1(D), on the substrate 110 having an insulating surface, A capacitive element 104 and a transistor 103 are formed, and the capacitive element 104 and transistor 103 is superimposed with the insulating film 111 in between.

[0130] The specific configuration of the capacitive element 104 is the same as in Figure 1(D). In Figure 5(B), the transient The sta103 is a bottom-gate type, and the source electrode or drain electrode is the active layer. It differs from Figure 1(D) in that it has a bottom contact structure that is in contact with the lower side.

[0131] The transistor 103 shown in Figure 5(B) has a gate electrode 160 on an insulating film 111 and a gate An insulating film 161 on electrode 160, and a source electrode 164 formed on the insulating film 161, An electrode 165 and a gate electrode 160 are formed on the insulating film 161 at a position overlapping with the gate electrode 160. Furthermore, the source electrode 164 and drain electrode 165 are in contact with an active oxide semiconductor. It has a layer 162 and a drain electrode. Furthermore, the transistor 103 has a source electrode 164 and a drain electrode. The electrode 165 and the insulating film 166 formed on the active layer 162 may also be included as components.

[0132] Furthermore, by using an inorganic material containing oxygen in the insulating film 166 that is in contact with the active layer 162, water Oxygen deficiency occurs in the active layer 162 due to heat treatment to reduce the amount of hydrogen. Even so, oxygen is supplied to the active layer 162 from the insulating film 166, reducing the oxygen deficiency that would otherwise be the donor. It is possible to reduce the amount to achieve a configuration that satisfies the stoichiometric composition ratio. Therefore, the active layer 162 This makes it possible to approximate type i, and the variation in the electrical characteristics of transistor 103 due to oxygen deficiency can be reduced. This can reduce noise and improve electrical characteristics.

[0133] Furthermore, transistor 103 has a back gate electrode on the insulating film 166. This is also good. The back gate electrode is formed so as to overlap with the channel formation region of the active layer 162. The back gate electrode may be in an electrically insulated floating state. It is also acceptable for an electric potential to be applied. In the latter case, the back gate electrode is a gate electrode. It is also acceptable for the same potential as 160 to be applied, or for a fixed potential such as ground to be applied. It is acceptable even if it is. By controlling the height of the potential applied to the buck gate electrode, the transistor It can control the threshold voltage of 103.

[0134] Then, in Figure 5(B), wiring 123 is formed with a light-shielding conductive film, and wiring 123 It is the same as in Figure 1(D) in that it covers transistor 103. Specifically, Light-shielding wiring 123 is formed so as to overlap with the active layer 162 of transistor 103. ru.

[0135] Furthermore, in Figure 5(B), similar to Figure 1(D), the electrodes 112 or the capacitive element 104 At least one of the electrodes 114 is light-shielding. And the light-shielding electrode 112 or The electrode 114 is formed in a position that overlaps with the active layer 162 of the transistor 103.

[0136] With the above configuration, Figure 5(B) shows an electrode 112 or electrode 114 that has light-shielding properties, and Since the active layer 162 is sandwiched between the wiring 123 which has properties, the absorption edge wavelength of the oxide semiconductor This prevents nearby light, or light in a shorter wavelength range, from entering the active layer 162. It is possible.

[0137] Note that in Figures 5(A) and 5(B), the wiring 123 is used for the active layer 152 or the active layer 1 Although a configuration that blocks light from 62 is given as an example, the configuration that blocks light from light is similar to the configuration shown in Figure 1(C). The insulating film may be used to shield the active layer 152 or the active layer 162 from light.

[0138] Furthermore, in Figures 5(A) and 5(B), transistor 103 has a single-gate structure. Although this is an example, transistor 103 has multiple electrically connected gate electrodes By having this feature, it may also be a multi-gate structure having multiple channel-forming regions.

[0139] This embodiment can be implemented in appropriate combination with the above embodiment.

[0140] (Embodiment 4) In this embodiment, the specific configuration of the memory unit and its operation will be described.

[0141] Figure 6 shows one of the circuit diagrams of a storage unit 200 having multiple memory cells 101 as shown in Figure 2(A). This is an example. For the configuration of the memory cell 101, please refer to the content described in Embodiment 1. It is possible to pour drinks.

[0142] The memory unit 200 shown in Figure 6 has various wiring configurations, including multiple word lines WL and multiple data lines DL. A circuit is provided, and signals or fixed potentials from the drive circuit are transmitted to each memory via these wires. It is supplied to cell 101. The number of the above wirings is determined by the number and arrangement of memory cells 101. It is possible.

[0143] Specifically, in the case of the memory unit 200 shown in Figure 6, 3 rows x 4 columns of memory cells are connected in a matrix. The word lines WL1-WL3 and data lines DL1-DL4 are connected within the storage unit 200. This illustrates an example of how they are arranged.

[0144] Next, the operation of the memory unit 200 shown in Figure 6 will be explained.

[0145] First, let's explain the operation of the storage unit 200 when writing data. When a signal with a pulse is input to the word line WL1, the potential of the pulse, specifically In terms of potential, a high level of potential is present in the gateway of transistor 103 connected to word line WL1. It is applied to the electrode. Therefore, the transistor to which the gate electrode is connected to the word line WL1 All functions of the TA103 will be turned on.

[0146] Next, signals containing data as information are input to data lines DL1-DL4. The potential level of the signals input to lines DL1 to DL4 will naturally differ depending on the data content. The potential input to data lines DL1~DL4 is transmitted via the ON transistor 103. The signal is applied to one electrode of the capacitive element 105. Then, according to the potential of the above signal, the capacitive element The amount of charge stored in sub-element 105 is controlled, thereby enabling the writing of data to the capacitive element 105. The process will be carried out.

[0147] When the input of a pulsed signal to word line WL1 ends, a gate is placed on word line WL1. All transistors 103 to which electrodes are connected turn off. Then, the word line WL2 A signal with pulses is sequentially input to word line WL3, and a memo is input to word line WL2. In a memory cell 101 having a recell 101 and a word line WL3, the above-described operation is similar. This is repeated.

[0148] Next, the operation of the storage unit 200 during data retention will be described. All word lines WL1 to WL3 have a potential at a level that turns off transistor 103. Specifically, a low potential is applied. Transistor 103 is turned off as described above. Because the current is extremely low, the charge stored in the capacitive element 105 is unlikely to leak, and light shielding is not required. In the absence of this feature, or compared to the case where semiconductor materials such as silicon are used in transistor 103 This allows for data retention over long periods of time.

[0149] Next, the operation of the storage unit 200 during data reading will be described. During output, as with writing, a signal with pulses sequentially is transmitted to word lines WL1 to WL3. The following is input. The potential of this pulse, specifically the high-level potential, is connected to the word line WL1. When applied to the gate electrode of the connected transistor 103, the transistor 103 All of them will be turned on.

[0150] When transistor 103 is turned on, the data stored in capacitive element 105 via data line DL Electric charge is extracted. Then, by reading the difference in the amount of charge, the data can be read. It is possible.

[0151] Each data line DL is connected to a readout circuit, and the output signal of the readout circuit However, it includes data that was actually read from the memory unit.

[0152] In this embodiment, the write, hold, and read operations are performed on multiple memory cells 101. Although the driving method described above is explained in order, the present invention is not limited to this configuration. The above operation may be performed only in the memory cell 101 with the specified address.

[0153] Furthermore, in the case of the storage unit 200 shown in Figure 6, each memory cell 101 has a data line DL and a power line. There are three wires: the do-wire WL and the wire for supplying a fixed potential to the electrodes of the capacitive element 105. Although the example shows the case where they are connected, in one aspect of the present invention, the wiring of each memory cell The number is not limited to this. Signals for controlling the switching of transistor 103, A signal to control the charge amount of the capacitive element 105 and a fixed potential are supplied to the memory cell 101. It can supply power, and moreover, the amount of charge stored in the capacitive element 105 is included as information. The number of wires and connection structure are appropriately determined so that the potential can be sent to the drive circuit. That's fine.

[0154] This embodiment can be implemented in appropriate combination with the above embodiment.

[0155] (Embodiment 5) In this embodiment, the specific configuration of the memory unit and its operation will be described.

[0156] Figure 7 shows one of the circuit diagrams of a storage unit 201 having multiple memory cells 101 as shown in Figure 2(C). This is an example. For the configuration of the memory cell 101, please refer to the content described in Embodiment 1. It is possible to pour drinks.

[0157] In the memory unit 201 shown in Figure 7, there are multiple first word lines WLa, multiple second word lines WLb, Multiple data lines (DL) and other types of wiring are provided, and signals from the drive circuit or fixed power The power is supplied to each memory cell 101 via these wires. The number of the above wires is the number of memory cells It can be determined by the number and arrangement of the 101s.

[0158] Specifically, in the case of the memory unit 201 shown in Figure 7, the memory cells are arranged in a matrix of 3 rows x 3 columns. It is continued, with the first word line WLa1~WLa3, the second word line WLb1~WLb3, and This example illustrates the case where data lines DL1 to DL3 are located within the memory unit 201.

[0159] Next, the operation of the memory unit 201 shown in Figure 7 will be explained. Figure 8 shows multiple first word lines. WLa1~WLa3, multiple second word lines WLb1~WLb3, multiple data lines DL1~ This is a timing chart showing the time variation of the signal potential input to DL3. (Figure 8) The timing chart shows that both transistor 102 and transistor 103 are n-channel type. The example illustrates the case where binary data is being handled.

[0160] Note that in the timing chart, the signal potential is such that the rising or falling edge is vertical. This is how it should be shown. However, the actual signal potential is affected by wiring load, noise, etc. Therefore, it is easy for anyone skilled in the art to understand that the waveform will be dulled.

[0161] First, let's explain the operation of the storage unit 201 when writing data. When a pulsed signal is input to the first word line WLa1, the potential of the pulse Specifically, a high potential is applied to the transistor connected to the first word line WLa1. It is applied to the gate electrode of 103. Therefore, the gate electrode is connected to the first word line WLa1. All transistors 103 that are connected turn on. Meanwhile, the second word lines WLb1~WLb A low potential is applied to point 3.

[0162] Next, signals containing data as information are input to data lines DL1-DL3. The potential level of the signals input to lines DL1 to DL3 will naturally differ depending on the content of the data. The potential input to data lines DL1~DL3 is transmitted via the ON transistor 103. This is applied to the gate electrode of transistor 102 and one electrode of capacitive element 104. Then, according to the potential of the above signal, the gate capacitance of transistor 102 and the capacitance element 104 By controlling the amount of charge accumulated, data is written to the memory cell 101. It can be done.

[0163] When the input of a pulsed signal to the first word line WLa1 ends, the first word line WL All transistors 103, whose gate electrode is connected to a1, turn off. And then, A pulsed signal is input sequentially to the first word line WLa2 and the first word line WLa3, Memory cell 101 having a first word line WLa2, memory cell having a first word line WLa3 In step 101, the above-described operation is repeated in the same manner.

[0164] Next, the operation of the storage unit 201 during data retention will be described. For all first word lines WLa1 to WLa3, there is a level at which transistor 103 turns off. A potential, specifically a low-level potential, is applied. Transistor 103 is as described above. Since the off-current is extremely low, the gate capacitance of transistor 102 and the capacitance element 104 The accumulated charge is less likely to leak, and if light shielding is not performed, or in semiconductors such as silicon... Compared to using the material in transistor 103, it allows for data retention over a longer period of time. It is possible.

[0165] Meanwhile, a low potential is continuously applied to the second word lines WLb1 to WLb3. .

[0166] Next, the operation of the storage unit 201 during data reading will be described. During the malfunction, a low-level potential is input to all first word lines WLa1 to WLa3. As a result, a low potential is applied to the gate electrode of transistor 103. Therefore, Transistor 103, whose gate electrode is connected to word lines WLa1~WLa3, It remains off.

[0167] On the other hand, a pulsed signal is input to the second word line WLb1, and the potential of the pulse, Specifically, a high potential is applied to the other electrode of the capacitive element 104. The potential difference between the pair of electrodes in 04 remains maintained by the law of conservation of charge, so the second power The change in potential across wire WLb1 is applied to the gate electrode of transistor 102. The threshold voltage of transistor 102 changes depending on the amount of charge stored in its gate capacitance. Therefore, transistor 102 has a charge that is commensurate with the amount of charge stored in its gate capacitance. A drain current of that height flows. Therefore, the magnitude of the drain current of transistor 102 By reading the difference in the amount of accumulated charge, the data can be read from the data line DL. It is possible to break out of it.

[0168] When the input of a pulsed signal to the second word line WLb1 ends, the second word line WL All transistors 102 of memory cell 101 having b1 are turned off. Then, the second wave A pulsed signal is sequentially input to the second word line WLb2 and the second word line WLb3, and the second word Memory cell 101 having a second word line WLb2, memory cell 1 having a second word line WLb3 In step 01, the above-described operation is repeated in the same manner.

[0169] Furthermore, a readout circuit is connected to the end of data lines DL1 to DL3, and the readout circuit The output signal contains the data actually read from the memory unit 201.

[0170] In this embodiment, the write, hold, and read operations are performed on multiple memory cells 101. Although the driving method described above is explained in order, the present invention is not limited to this configuration. The above operation may be performed only in the memory cell 101 with the specified address.

[0171] Furthermore, in the case of the memory unit 201 shown in Figure 7, each memory cell 101 has a first word line WLa and The second word line WLb, the data line DL, and the transistor 102 are supplied with a fixed potential. The example shows a case where four wires are connected to the main wire, but in one aspect of the present invention The number of wires each memory cell has is not limited to this. The signal to control the gate and the amount of charge stored in the gate capacitance of transistor 102 are controlled. It is possible to supply the memory cell 101 with a signal for that purpose and a fixed potential, and furthermore, The potential, which contains the amount of charge accumulated in the gate capacitance as information, is sent to the drive circuit. The number of wires and connection structure should be determined appropriately to achieve this.

[0172] This embodiment can be implemented in appropriate combination with the above embodiment.

[0173] (Embodiment 6) Figure 9 shows, as an example, the configuration of a storage device according to one aspect of the present invention, in a block diagram. The memory device 300 shown includes a storage unit 301 having multiple memory cells, and a storage unit 301 It has a drive circuit 302 that controls its operation.

[0174] The drive circuit 302 writes data to the storage unit 301 and reads data from the storage unit 301. The various operations, such as data retrieval and data retention in the memory unit 301, are performed according to signals from the control circuit. It can be controlled in that way.

[0175] In Figure 9, the control circuit that supplies signals to the drive circuit 302 is not included in the storage device 300. Furthermore, although it is assumed that the control circuit is located outside the memory device 300, the control circuit is located outside the memory device. It may be included as a component of [the group].

[0176] Next, an example of a specific configuration of the drive circuit of a storage device according to one aspect of the present invention will be described. do.

[0177] Figure 10 shows, as an example, a block diagram illustrating the specific configuration of a storage device according to one aspect of the present invention. In addition, the block diagram shown in Figure 10 classifies the circuits within the memory device according to their function, and they interact with each other. Although shown as independent blocks, the actual circuit can be completely separated by function. It's complex, and a single circuit can sometimes be involved in multiple functions.

[0178] The storage device 300 shown in Figure 10 has a storage unit 301 and a drive circuit 302. Circuit 302 generates a signal that contains the data read from the storage unit 301 as information. The output circuit 303 and the memory cells of the storage unit 301 are selected row by row by word line The dynamic circuit 304 and the data writing to the selected memory cell in the storage unit 301. It has a data line drive circuit 305 that controls the readout cycle. Control circuit that controls the operation of path 303, word line drive circuit 304, and data line drive circuit 305. It has 306.

[0179] Furthermore, in the memory device 300 shown in Figure 10, the word line drive circuit 304 is connected to the decoder 307. It has a level shifter 308 and a buffer 309. The data line drive circuit 305 is It has a decoder 310, a level shifter 311, and a selector 312.

[0180] Furthermore, a storage device 300 according to one aspect of the present invention includes at least a storage unit 301 in its configuration. That should be sufficient. Furthermore, the storage device 300 according to one aspect of the present invention is driven by the storage unit 301. This category includes memory modules to which part or all of circuit 302 is connected. The memory module is equipped with connection terminals that allow it to be mounted on a printed circuit board or the like. Furthermore, it is acceptable if the product is protected by resin or the like, in a so-called packaged state.

[0181] Also, the memory unit 301, read circuit 303, word line drive circuit 304, data line drive circuit 305 and the control circuit 306 may all be formed using a single substrate, or any one of them may be formed using a single substrate. One or all of the substrates may be different from each other.

[0182] When using different substrates, FPC (Flexible Printed Circuit) Electrical connection can be secured via (it), etc. In this case, the drive circuit 302 A portion of the FPC may be connected using the COF (Chip On Film) method. Alternatively, the COG (Chip On Glass) method can be used to ensure electrical connectivity. It is possible.

[0183] The memory device 300 receives a signal AD containing the addresses (Ax, Ay) of the memory unit 301 as information. When input is received, the control circuit 306 sends the column address Ax to the data line drive circuit 305. The row-direction address Ay is sent to the word line drive circuit 304. The control circuit 306 also... The signal DATA, which contains the data input to the storage device 300 as information, is transmitted to the data line drive circuit. Send to 305.

[0184] The control circuit 306 selects between data writing and reading operations in the memory unit 301. The supplied signals are RE (Read enable) and WE (Write enable). ) and so on are selected. Furthermore, if there are multiple memory units 301, the control circuit 306 The signal CE (Chip enable) for selecting the memory unit 301 is input. This is also acceptable. In this case, the operation selected by signals RE and WE is selected by signal CE. This is executed in the memory unit 301.

[0185] In the memory unit 301, when a write operation is selected by the signal WE, the control circuit 306 receives In accordance with the instructions, the decoder 307 of the word line drive circuit 304, address A A signal is generated to select the memory cell corresponding to y. This signal is used by the level shifter. After the amplitude is adjusted by 308, the waveform is processed in buffer 309 and stored in storage unit 3 It is input to 01. Meanwhile, the data line drive circuit 305 follows instructions from the control circuit 306. In decoder 310, among the memory cells selected, the one corresponding to address Ax A signal is generated for selecting the Morissel. This signal is then transmitted by the level shifter 311. After the amplitude is adjusted, it is input to selector 312. Selector 312 processes the input signal. The signal DATA is sampled according to the code, and the memory corresponding to the address (Ax, Ay) is selected. The sampled signal is input to the terminal.

[0186] Furthermore, in the memory unit 301, when a read operation is selected by the signal RE, the control circuit 30 In accordance with the instructions from 6, in the decoder 307 of the word line drive circuit 304, add A signal is generated to select the memory cell corresponding to LessAy. This signal is level After the amplitude is adjusted by the shifter 308, the waveform is processed in the buffer 309, and then recorded The data is input to the memory unit 301. Meanwhile, the readout circuit 303 receives instructions from the control circuit 306. Therefore, among the memory cells selected by the decoder 307, the one corresponding to address Ax Select a Moriscell. Then, it will be stored in the memory cell corresponding to the address (Ax, Ay). The system reads the data and generates a signal that includes the data as information.

[0187] This embodiment can be implemented in appropriate combination with the above embodiment.

[0188] (Embodiment 7) This embodiment describes an example of a specific configuration of the readout circuit.

[0189] The potential read from the memory unit is determined according to the data written to the memory cell. The bell is determined. Therefore, ideally, the same digital value data is stored in multiple memory cells. If that's the case, then the potential read from multiple memory cells should all be at the same level. Yes, but in reality, the transistor that functions as a memory element, or when reading... The characteristics of the transistor, which functions as a switching element, vary between memory cells. This can happen. In this case, even if all the data that should be read are the same digital value. Therefore, because there is variation in the actual read-out potential, its distribution has a range. Even if there is some variation in the potential read from the memory, accurate data can be used as information. The readout cycle includes and processes the amplitude and waveform to form a signal according to the desired specifications. It is desirable to provide the path within the drive circuit.

[0190] Figure 11 shows an example of a read circuit in a circuit diagram. The read circuit shown in Figure 11 is from the memory unit. Switching for controlling the input of the readout potential Vdata to the readout circuit. A transistor 260 that functions as an element and a transistor 261 that functions as a resistor It has. Furthermore, the readout circuit shown in Figure 11 includes an operational amplifier 262.

[0191] Specifically, transistor 261 has its gate electrode and drain electrode (or, The drain region is connected, and high levels are connected to the gate electrode and drain electrode. A power supply potential Vdd is provided. Also, transistor 261 has a source electrode that is optoelectronic. It is connected to the non-inverting input terminal (+) of amplifier 262. Therefore, transistor 261 is , the node to which the power supply potential Vdd is applied and the non-inverting input terminal (+) of the op-amp 262 It functions as a resistor connected between the gate electrode and the drain electrode. Although a transistor with connected electrodes was used as a resistor, the present invention is not limited to this, and the resistor and Any component that functions in that way can be substituted.

[0192] Furthermore, transistor 260, which functions as a switching element, has its gate electrode connected to bit line B It is connected to L1 to BL3 respectively. And according to the potential of the bit lines BL1 to BL3 The supply of potential Vdata to the source electrode of transistor 260 is controlled.

[0193] For example, when transistor 260 connected to bit line BL1 is turned on, the potential Vdat The voltage a and the power supply potential Vdd are separated by resistance using transistors 260 and 261. The resulting potential is applied to the non-inverting input terminal (+) of the operational amplifier 262. Since the power supply potential Vdd level is fixed, the potential level obtained by resistance division is... This reflects the level of the potential Vdata, i.e., the digital value of the read-out data. It is.

[0194] On the other hand, a reference potential Vref is applied to the inverting input terminal (-) of the operational amplifier 262. And, is the potential applied to the non-inverting input terminal (+) higher than the reference potential Vref? Depending on the value, the level of the output terminal potential Vout can be varied, thereby, It is possible to obtain a signal that indirectly contains data as information.

[0195] Furthermore, even among memory cells that store data with the same value, there may be variations in characteristics between memory cells. Due to the variability, the level of the read-out potential Vdata also varies, and its distribution is wide. It may have this. Therefore, the level of the reference potential Vref is important for accurately reading the data value. To achieve this, the variation in node potential Vdata is taken into consideration.

[0196] Furthermore, Figure 11 shows an example of a readout circuit when dealing with binary digital values, so data The operational amplifier used to read out the data is one for each node to which the potential Vdata is given. While several are used, the number of operational amplifiers is not limited to these. When dealing with data, the number of operational amplifiers for a given node with potential Vdata is n- Let's set it to 1.

[0197] This embodiment can be implemented in appropriate combination with the above embodiment.

[0198] (Embodiment 8) This embodiment describes an example of calculating the off-current of a transistor.

[0199] First, the configuration of the characteristic evaluation circuit used to calculate the off-current will be explained using Figure 12. In this embodiment, the characteristic evaluation circuit measures a plurality of measurement systems 801 connected in parallel with each other. To prepare. Specifically, in Figure 12, eight measurement systems 801 are connected in parallel for characteristic evaluation. This illustrates a road.

[0200] The measurement system 801 consists of transistor 811, transistor 812, capacitive element 813, and It includes transistor 814 and transistor 815.

[0201] Transistor 811 is a charge injection transistor. And transistor 811 is The first terminal is connected to a node to which a potential V1 is applied, and the second terminal is , is connected to the first terminal of transistor 812. The gate electrode of transistor 811 is It is connected to the node to which the potential Vext_a is given.

[0202] Transistor 812 is a transistor for evaluating leakage current. Leakage current includes the off-current of the transistor. And transistor 81 2 has its first terminal connected to the second terminal of transistor 811, and its second terminal However, it is connected to a node to which potential V2 is given. The gate voltage of transistor 812 The pole is connected to the node to which the potential Vext_b is given.

[0203] The first electrode of the capacitive element 813 is connected to the second terminal of transistor 811 and transistor 812 It is connected to the first terminal. The second electrode of the capacitive element 813 is given a potential V2. It is connected to a node.

[0204] The transistor 814 has its first terminal connected to a node to which a potential V3 is applied. Furthermore, its second terminal is connected to the first terminal of transistor 815. The gate electrode of 814 is the second terminal of transistor 811 and the first terminal of transistor 812. It is connected to the first electrode of the capacitive element 813. The point where the electrodes are connected is designated as node A.

[0205] The first terminal of transistor 815 is connected to the second terminal of transistor 814. Furthermore, its second terminal is connected to a node to which a potential V4 is applied. (Transistor) The gate electrode of the 815 is connected to the node to which the potential Vext_c is given.

[0206] The measurement system 801 then uses the second terminal of transistor 814 and the first terminal of transistor 815. The potential of the node to which the terminal is connected is output as the potential of the output signal, Vout.

[0207] In this embodiment, the transistor 811 includes an oxide semiconductor in its active layer. Furthermore, the size of the channel-forming region contained in the active layer is such that the channel length L = 10 μm, A transistor with a channel width W = 10 μm is used.

[0208] The channel formation region is the area in the semiconductor film between the source electrode and the drain electrode. This corresponds to the region that overlaps with the gate electrode, with the gate insulating film in between.

[0209] Furthermore, transistors 814 and 815 include an oxide semiconductor in their active layer. Furthermore, the size of the channel-forming region contained in the active layer is such that the channel length L = 3 μm, A transistor with a channel width W = 100 μm is used.

[0210] Furthermore, transistor 812 includes an oxide semiconductor in its active layer, with a source located on top of the active layer. The electrode and drain electrode are in contact, and the source electrode and drain electrode overlap with the gate electrode. A bottom gate structure without a lap region, having an offset region with a width of 1 μm. An inverter is used. By providing an offset region, parasitic capacity can be reduced. Furthermore, as transistor 812, the channel formation region included in the active layer is as follows: Transistors of different sizes are used, as shown in conditions 1 to 6 of Table 1.

[0211] [Table 1]

[0212] If the charge injection transistor 811 is not provided in the measurement system 801, the capacitive element 81 When injecting charge into 3, it is necessary to turn on the leakage current evaluation transistor 812 once. In this case, the leakage current evaluation transistor 812 will enter a steady state from on to off. If the element requires time to complete the process, the measurement will take time. As shown in Figure 12, charge The input transistor 811 and the leakage current evaluation transistor 812 are measured separately using the measurement system 80. By providing it at 1, the leakage current evaluation transistor 812 is always on during charge injection. It can be kept in a stable state. Therefore, the time required for measurement can be shortened.

[0213] Furthermore, the charge injection transistor 811 and the leakage current evaluation transistor 812 were measured. By providing them separately in system 801, each transistor can be made to an appropriate size. This can be done. Also, the channel width W of the leakage current evaluation transistor 812 is set for charge injection. By making the channel width W of the transistor 811 larger, the leakage current evaluation transistor To relatively reduce the leakage current components in the characteristic evaluation circuit other than the leakage current of the ZISTA 812. This allows for high precision in evaluating the leakage current of the transistor 812 used for leakage current evaluation. It can be measured in degrees. At the same time, during charge injection, a transistor 8 for evaluating leakage current is used. Since it is not necessary to turn on 12 once, some of the charge in the channel formation region flows to node A. There is no influence from potential fluctuations at node A due to the crowding.

[0214] On the other hand, the channel width W of the charge injection transistor 811 is used for the leakage current evaluation transistor By making the channel width W of 812 smaller, the charge injection transistor 811 The current can be made relatively smaller. Also, during charge injection, the channel formation region The influence of potential fluctuations at node A due to some of the charge flowing into node A is also small.

[0215] Furthermore, as shown in Figure 12, by creating a structure in which multiple measurement systems 801 are connected in parallel, This allows for a more accurate calculation of the leakage current in the characteristic evaluation circuit.

[0216] Next, we will describe a specific method for calculating the off-current of a transistor using the characteristic evaluation circuit shown in Figure 12. I will explain this.

[0217] First, the leakage current measurement method for the characteristic evaluation circuit shown in Figure 12 will be explained using Figure 13. Figure 13 illustrates a leakage current measurement method using the characteristic evaluation circuit shown in Figure 12. This is a timing chart.

[0218] The leakage current measurement method using the characteristic evaluation circuit shown in Figure 12 is performed during the write period and the hold period. It can be divided into sections. The operations during each period are explained below. Note that the writing period During both the interval and retention period, potentials V2 and V4 were set to 0V, potential V3 to 5V, and potential Set Vext_c to 0.5V.

[0219] First, during the writing period, the potential Vext_b is set so that transistor 812 is turned off. Set the potential to the eel height VL (-3V). Also, set the potential V1 to the write potential Vw. After that, the potential Vext_a is set to a potential such that transistor 811 is turned on for a certain period of time. Set to VH (5V). With the above configuration, charge accumulates at node A, and the potential of node A... This will be equivalent to the write potential Vw. Next, the potential Vext_a is set to transistor 8 Set the potential VL to a height such that 11 turns off. Then, set the potential V1 to potential VSS(0 Set to V).

[0220] Next, during the retention period, the change in the amount of charge held by node A results in the following changes in node A. The change in potential is measured. From the change in potential, the first and second terminals of transistor 812 are determined. The value of the current flowing between the nodes can be calculated. Therefore, the charge accumulation at node A and the node It is possible to measure the change in potential of line A.

[0221] The accumulation of charge at node A and the measurement of the change in potential at node A (also called the accumulation and measurement operation). This is repeated. First, the first accumulation and measurement operation is repeated 15 times. During the measurement operation, a potential of 5V is input as the write potential Vw during the write period, and the hold period... Hold for 1 hour. Next, repeat the second accumulation and measurement operation twice. Second accumulation In the measurement operation, the write potential Vw is set to 3.5V during the write period, and the hold period is set to 50 hours. Hold the interval. Next, perform the third accumulation and measurement operation once. The write voltage Vw is set to 4.5V during the write period, and the hold period is set to 10 hours. By repeatedly performing the accumulation and measurement operations, the measured current value is obtained from the steady-state value. This can be confirmed. In other words, the current I flowing through node A A Of these, Transient currents (current components that decrease over time from the start of measurement) can be excluded. As a result, leakage current can be measured with higher accuracy.

[0222] Generally, the potential V of node A A It can be expressed as a function of the output signal potential Vout as follows: It is possible.

[0223]

number

[0224] Also, the charge Q at node A. A The potential V of node A is A Capacity C connected to node A A , fixed Using a constant, it can be expressed as follows: Capacity C connected to node A A teeth, This is the sum of the capacitance value of the capacitive element 813 and the capacitance values ​​of the other capacitors besides the capacitive element 813.

[0225]

number

[0226] Current I at node A A This is the charge flowing into node A (or the charge flowing out of node A) Since it is a time derivative, the current I at node A A It can be expressed as follows:

[0227]

number

[0228] For example, let Δt be approximately 54,000 seconds. Capacity C connected to node A. A and output signal From the potential Vout, the current I at node A ASince it is possible to determine the characteristics of the evaluation circuit The current can be calculated.

[0229] Next, the measurement results of the output signal potential Vout using the measurement method with the above characteristic evaluation circuit and The leakage current value of the characteristic evaluation circuit calculated from the measurement results is shown.

[0230] Figure 14 shows, as an example, the above measurements under conditions 1, 2, and 3 (first accumulation and measurement). Figure 15 shows the relationship between the elapsed time (Time) during the constant operation and the potential (Vout) of the output signal. The relationship between the elapsed time (Time) related to the above measurement and the leakage current calculated by the measurement is As shown, the potential Vout of the output signal fluctuates from the start of measurement, and in order to reach a steady state... It appears that more than 10 hours will be needed.

[0231] Furthermore, Figure 16 shows the potential of node A under conditions 1 to 6, as estimated by the above measurements. The relationship between this and leakage current is shown. In Figure 16, for example, under condition 4, the potential of node A is 3. At 0V, the leakage current is 28yA / μm. The leakage current is measured by transistor 812. Since this includes the off-current, the off-current of transistor 812 is also considered to be 28 yA / μm or less. It is possible.

[0232] As described above, it contains a highly purified oxide semiconductor layer that functions as a channel-forming layer. In a characteristic evaluation circuit using a transistor, the leakage current is sufficiently low, It can be seen that the off-current of the inverter is sufficiently small.

[0233] (Embodiment 9) This embodiment describes an example of the configuration of an RF tag, which is one of the semiconductor devices of the present invention. I will reveal it.

[0234] Figure 17 is a block diagram showing one embodiment of the RF tag of the present invention. In Figure 17, RF tag 5 50 has an antenna circuit 551 and an integrated circuit 552. The integrated circuit 552 is electric Source circuit 553, demodulation circuit 554, modulation circuit 555, regulator 556, arithmetic circuit 557 It also has a storage device 558 and a boost circuit 559.

[0235] Next, we will explain an example of how the RF tag 550 operates. A radio wave is sent from the interrogator. Then, in the antenna circuit 551, the radio waves are converted into AC voltage. In the power supply circuit 553, The AC voltage from the antenna circuit 551 is rectified to generate the voltage for the power supply. Power supply circuit 553 The voltage for the power supply generated in this circuit is supplied to the arithmetic circuit 557 and the regulator 556. The regulator 556 stabilizes the voltage for the power supply from the power supply circuit 553, or After adjusting the height, the demodulation circuit 554, modulation circuit 555, and arithmetic circuit within the integrated circuit 552 It supplies power to various circuits such as 557, the storage device 558, or the boost circuit 559.

[0236] The demodulation circuit 554 demodulates the AC signal received by the antenna circuit 551 and then processes it into the subsequent calculation circuit. The output is sent to 557. The arithmetic circuit 557 performs calculations according to the signal input from the demodulation circuit 554. The calculation is performed and a separate signal is generated. When the above calculation is performed, the memory device 558 is a primary cache It can be used as a storage memory or secondary cache memory. Also, the arithmetic circuit 557 It analyzes the signal input from the demodulation circuit 554 and the content of the command sent from the interrogator. Therefore, the output of information in the storage device 558, or the contents of instructions in the storage device 558 Execution is performed. The signal output from the arithmetic circuit 557 is encoded and modulated by the modulation circuit 555. The modulation circuit 555 modulates the radio waves received by the antenna circuit 551 according to the signal. The radio waves modulated in antenna circuit 551 are received by the interrogator.

[0237] Thus, communication between the RF tag 550 and the interrogator uses radio waves as the carrier wave. This is done by modulation. The carriers are 125kHz, 13.56MHz, and 950MHz. The methods vary depending on the standard. Furthermore, the modulation method also differs depending on the standard, including amplitude modulation, frequency modulation, and phase modulation. There are various modulation methods, but any modulation method that conforms to the standard can be used. .

[0238] The signal transmission method is classified into electromagnetic coupling, electromagnetic induction, and microwave methods depending on the wavelength of the carrier. It can be classified into various types, such as formulas.

[0239] The boost circuit 559 boosts the voltage output from the regulator 556 and sends it to the memory device 558. They are supplying it.

[0240] In one aspect of the present invention, the storage device 558 has the configuration shown in the above embodiment, and This allows for increased storage capacity per unit area while ensuring a sufficient period for data retention. A key feature is that, therefore, the RF tag 550 according to one aspect of the present invention has the above-mentioned storage device 558 By using this, the reliability of the data can be improved. Also, by using the above storage device 558 This allows for miniaturization or enhancement of the RF tag 550's functionality.

[0241] In this embodiment, the configuration of the RF tag 550 having an antenna circuit 551 will be described. However, an RF tag according to one aspect of the present invention does not necessarily include an antenna circuit as one of its components. It is not necessary. Furthermore, an oscillator circuit or a secondary battery may be provided in the RF tag shown in Figure 17. .

[0242] This embodiment can be implemented in appropriate combination with the above embodiment.

[0243] (Embodiment 10) In this embodiment, one of the semiconductor devices using a storage device according to one aspect of the present invention is a portable An example of a strip-type storage medium will be described.

[0244] Figure 18(A) shows an example configuration of a storage medium according to one aspect of the present invention. The storage medium shown in A) is a storage device 701 according to one aspect of the present invention, and a drive device and a storage medium A connector 702 for electrical connection and various signals input and output via connector 702 The interface 703 performs signal processing according to the specifications, and also checks the operating status of the storage medium, etc. Therefore, the light-emitting diode 704 that lights up, the storage device 701, the interface 703, and Controls the operation of various circuits and semiconductor elements within the storage medium, such as the photodiode 704. Roller 705 is mounted on printed circuit board 706. In addition, there is a controller. A crystal oscillator used to generate the clock signal for controlling the operation of the 705, memory A regulator or similar device may be provided to control the power supply potential within the medium. stomach.

[0245] The printed circuit board 706 shown in Figure 18(A) has a connector 7 as shown in Figure 18(B). The 02 and the light-emitting diode 704 are partially exposed and covered with a cover material 707 made of resin or the like. It would be good to protect it.

[0246] A storage device 701 according to one aspect of the present invention ensures a period for retaining data, and on a unit surface A key feature is that the memory capacity per unit area can be increased. Therefore, in one aspect of the present invention, Such a storage medium can improve data reliability by using the above-mentioned storage device 701. Yes, it is possible. Furthermore, by using the above-mentioned storage device 701, the storage medium can be miniaturized. .

[0247] This embodiment can be implemented in appropriate combination with the above embodiment. [Examples]

[0248] By using a semiconductor device according to one aspect of the present invention, highly reliable electronic devices and high-performance electronic devices can be obtained. It is possible to provide electronic devices.

[0249] A semiconductor device according to one aspect of the present invention is a display device, a notebook personal computer, and a recording device. Image playback device equipped with a media (typically DVD: Digital Versatile) (A device that plays recording media such as discs and has a display capable of displaying the images thereof) It is possible to use a semiconductor device according to one aspect of the present invention. As sub-devices, mobile phones, portable game consoles, personal digital assistants, e-books, video cameras, etc. Digital still camera, goggle-type display (head-mounted display), navigation Audio systems, sound reproduction devices (car audio, digital audio players, etc.) , photocopiers, fax machines, printers, multifunction printers, ATMs (A Examples include electronic devices (TM), vending machines, etc. Specific examples of these electronic devices are shown in Figure 19.

[0250] Figure 19(A) shows a portable game console, comprising a casing 7031, casing 7032, display unit 7033, Display unit 7034, microphone 7035, speaker 7036, operation key 7037, stand It has illustrations 7038, etc. A semiconductor device according to one aspect of the present invention is a drive for a portable game console. It can be used in integrated circuits for controlling the operation of portable game consoles. By using a semiconductor device according to one aspect of the present invention in the integrated circuit, a highly reliable portable game This allows us to provide a portable game console with advanced functionality. The portable game console has two display units 7033 and 7034, but The number of display units in a game console is not limited to this.

[0251] Figure 19(B) is a mobile phone, comprising a housing 7041, a display unit 7042, an audio input unit 7043, It has an audio output unit 7044, an operation key 7045, a light receiving unit 7046, etc. By converting the light received into an electrical signal, external images can be captured. A semiconductor device according to one aspect of the invention is used in an integrated circuit for controlling the operation of a mobile phone. This can be done. A semiconductor device according to one aspect of the present invention can be used in an integrated circuit for controlling the operation of a mobile phone. By using this method, it is possible to provide highly reliable mobile phones and mobile phones with advanced functionality. Cut.

[0252] Figure 19(C) shows a portable information terminal, consisting of a housing 7051, a display unit 7052, and operation keys 7053. It has the following features. The portable information terminal shown in Figure 19(C) has the modem built into the housing 7051. It may also be done. A semiconductor device according to one aspect of the present invention is a collection for controlling the drive of a portable information terminal. It can be used in integrated circuits. The present invention is used in integrated circuits for controlling the operation of portable information terminals. By using a semiconductor device according to one embodiment, a highly reliable portable information terminal and a highly functional portable information terminal can be obtained. We can provide a mobile information terminal.

[0253] This embodiment can be implemented in appropriate combination with the above embodiment. [Explanation of Symbols]

[0254] 101 cell cells 102 transistors 103 Transistors 104 Capacitive element 105 Capacitive element 106 transistors 110 circuit boards 111 Insulating Film 112 Electrode 113 Insulating Film 114 Electrode 115 Gate Shuttle 116 Insulating film 117 Active layer 118 Source Electrode 119 Drain electrode 120 insulating film 121 Insulating film 122 Insulating film 123 Wiring 130 Conductive film 131 Conductive film 132 Active layer 133 Insulating film 134 gate 135 Conductive film 136 Active layer 137 gate 138 Contact Holes 139 Insulating film 140 contact holes 141 Conductive film 142 Contact Holes 143 Contact Holes 144 Conductive film 150 Guard signals 151 Insulating Film 152 Active layer 153 Channel protective film 154 Source electrodes 155 Drain electrode 156 Insulating film 160 Guard Station 161 Insulating film 162 Active layer 164 source electrodes 165 Drain electrode 166 Insulating film 200 Storage section 201 Storage section 260 transistors 261 transistors 262 Op-amps 300 storage device 301 Storage section 302 Drive Circuit 303 Readout Circuit 304 Word Line Drive Circuit 305 Data Line Drive Circuit 306 Control Circuit 307 Decoder 308 Level Shifter 309 buffers 310 Decoder 311 Level Shifter 312 Selector 550 RF tags 551 Antenna Circuit 552 Integrated Circuits 553 Power supply circuit 554 Demodulation Circuit 555 Modulation Circuit 556 Regulator 557 Arithmetic circuit 558 Storage device 559 Boost Circuit 701 Storage device 702 connector 703 Interface 704 Light-Emitting Diode 705 Controller 706 Printed Wiring Board 707 Cover material 801 Measurement System 811 Transistors 812 transistors 813 Capacitive element 814 Transistors 815 Transistors 7031 enclosure 7032 enclosure 7033 Display section 7034 Display section 7035 Microphone 7036 Speaker 7037 Operation Keys 7038 Stylus 7041 enclosure 7042 Display section 7043 Voice Input Section 7044 Audio output section 7045 Operation Keys 7046 Light receiving section 7051 enclosure 7052 Display section 7053 Operation Keys

Claims

1. It comprises a capacitive element, a first transistor, and a second transistor, The source electrode or drain electrode of the first transistor is always in electrical contact with the gate electrode of the second transistor. The source electrode or drain electrode of the first transistor, the other of which is always in electrical contact with the first wiring, The source electrode or drain electrode of the second transistor is always in electrical contact with the first wiring. The capacitive element comprises a first electrode, an insulating film having a region on the first electrode, and a second electrode having a region on the insulating film. The second electrode of the capacitive element has a region that is in contact with a first conductive film that functions as either the source electrode or the drain electrode of the first transistor. The channel formation region of the first transistor and the channel formation region of the second transistor are semiconductor devices having regions above and overlapping with the capacitive element, It comprises a first oxide semiconductor layer and a second oxide semiconductor layer, The first oxide semiconductor layer has a channel formation region for the first transistor. The second oxide semiconductor layer has a channel formation region for the second transistor. In a cross-sectional view of the first transistor in the channel length direction, the first oxide semiconductor layer has a bending point, In a cross-sectional view of the second transistor in the channel length direction, the second oxide semiconductor layer has a bending point, In a plan view, the first wiring is a semiconductor device having a region located between the channel formation region of the first transistor and the channel formation region of the second transistor.

2. It comprises a capacitive element, a first transistor, and a second transistor, The source electrode or drain electrode of the first transistor is always in electrical contact with the gate electrode of the second transistor. The source electrode or drain electrode of the first transistor, the other of which is always in electrical contact with the first wiring, The source electrode or drain electrode of the second transistor is always in electrical contact with the first wiring. The capacitive element comprises a first electrode, an insulating film having a region on the first electrode, and a second electrode having a region on the insulating film. The second electrode of the capacitive element has a region that is in contact with a first conductive film that functions as either the source electrode or the drain electrode of the first transistor. The channel formation region of the first transistor and the channel formation region of the second transistor are semiconductor devices having regions above and overlapping with the capacitive element, It comprises a first oxide semiconductor layer, a second oxide semiconductor layer, and a first insulating layer. The first oxide semiconductor layer has a channel formation region for the first transistor. The second oxide semiconductor layer has a channel formation region for the second transistor. The first insulating layer has a region in contact with the first oxide semiconductor layer and a region in contact with the second oxide semiconductor layer. The first insulating layer comprises silicon and oxygen, In a cross-sectional view of the first transistor in the channel length direction, the first oxide semiconductor layer has a bending point, In a cross-sectional view of the second transistor in the channel length direction, the second oxide semiconductor layer has a bending point, In a plan view, the first wiring is a semiconductor device having a region located between the channel formation region of the first transistor and the channel formation region of the second transistor.

3. It comprises a capacitive element, a first transistor, and a second transistor, The source electrode or drain electrode of the first transistor is always in electrical contact with the gate electrode of the second transistor. The source electrode or drain electrode of the first transistor, the other of which is always in electrical contact with the first wiring, The source electrode or drain electrode of the second transistor is always in electrical contact with the first wiring. The capacitive element comprises a first electrode, an insulating film having a region on the first electrode, and a second electrode having a region on the insulating film. The second electrode of the capacitive element has a region that is in contact with a first conductive film that functions as either the source electrode or the drain electrode of the first transistor. The channel formation region of the first transistor and the channel formation region of the second transistor are semiconductor devices having regions above and overlapping with the capacitive element, It comprises a first oxide semiconductor layer, a second oxide semiconductor layer, a first insulating layer, and a second insulating layer. The first oxide semiconductor layer has a channel formation region for the first transistor. The second oxide semiconductor layer has a channel formation region for the second transistor. The first insulating layer has a region between the first oxide semiconductor layer and the second insulating layer, and a region between the second oxide semiconductor layer and the second insulating layer. The first insulating layer comprises silicon and oxygen, The second insulating layer comprises silicon and nitrogen, In a cross-sectional view of the first transistor in the channel length direction, the first oxide semiconductor layer has a bending point, In a cross-sectional view of the second transistor in the channel length direction, the second oxide semiconductor layer has a bending point, In a plan view, the first wiring is a semiconductor device having a region located between the channel formation region of the first transistor and the channel formation region of the second transistor.

4. In any one of claims 1 to 3, The oxide semiconductor layer is a semiconductor device having In, Ga, and Zn.

5. It comprises a capacitive element, a first transistor, and a second transistor, The source electrode or drain electrode of the first transistor is always in electrical contact with the gate electrode of the second transistor. The source electrode or drain electrode of the first transistor, the other of which is always in electrical contact with the first wiring, The source electrode or drain electrode of the second transistor is always in electrical contact with the first wiring. The capacitive element comprises a first electrode, an insulating film having a region on the first electrode, and a second electrode having a region on the insulating film. The second electrode of the capacitive element has a region that is in contact with a first conductive film that functions as either the source electrode or the drain electrode of the first transistor. The channel formation region of the first transistor and the channel formation region of the second transistor are semiconductor devices having regions above and overlapping with the capacitive element, It comprises a first oxide semiconductor layer and a second oxide semiconductor layer, The first oxide semiconductor layer has a channel formation region for the first transistor. The second oxide semiconductor layer has a channel formation region for the second transistor. The first oxide semiconductor layer is In-O, The second oxide semiconductor layer is In-O, In a cross-sectional view of the first transistor in the channel length direction, the first oxide semiconductor layer has a bending point, In a cross-sectional view of the second transistor in the channel length direction, the second oxide semiconductor layer has a bending point, In a plan view, the first wiring is a semiconductor device having a region located between the channel formation region of the first transistor and the channel formation region of the second transistor.

6. It comprises a capacitive element, a first transistor, and a second transistor, The source electrode or drain electrode of the first transistor is always in electrical contact with the gate electrode of the second transistor. The source electrode or drain electrode of the first transistor, the other of which is always in electrical contact with the first wiring, The source electrode or drain electrode of the second transistor is always in electrical contact with the first wiring. The capacitive element comprises a first electrode, an insulating film having a region on the first electrode, and a second electrode having a region on the insulating film. The second electrode of the capacitive element has a region that is in contact with a first conductive film that functions as either the source electrode or the drain electrode of the first transistor. The channel formation region of the first transistor and the channel formation region of the second transistor are semiconductor devices having regions above and overlapping with the capacitive element, It comprises a first oxide semiconductor layer, a second oxide semiconductor layer, and a first insulating layer. The first oxide semiconductor layer has a channel formation region for the first transistor. The second oxide semiconductor layer has a channel formation region for the second transistor. The first oxide semiconductor layer is In-O, The second oxide semiconductor layer is In-O, The first insulating layer has a region in contact with the first oxide semiconductor layer and a region in contact with the second oxide semiconductor layer. The first insulating layer comprises silicon and oxygen, In a cross-sectional view of the first transistor in the channel length direction, the first oxide semiconductor layer has a bending point, In a cross-sectional view of the second transistor in the channel length direction, the second oxide semiconductor layer has a bending point, In a plan view, the first wiring is a semiconductor device having a region located between the channel formation region of the first transistor and the channel formation region of the second transistor.

7. It comprises a capacitive element, a first transistor, and a second transistor, The source electrode or drain electrode of the first transistor is always in electrical contact with the gate electrode of the second transistor. The source electrode or drain electrode of the first transistor, the other of which is always in electrical contact with the first wiring, The source electrode or drain electrode of the second transistor is always in electrical contact with the first wiring. The capacitive element comprises a first electrode, an insulating film having a region on the first electrode, and a second electrode having a region on the insulating film. The second electrode of the capacitive element has a region that is in contact with a first conductive film that functions as either the source electrode or the drain electrode of the first transistor. The channel formation region of the first transistor and the channel formation region of the second transistor are semiconductor devices having regions above and overlapping with the capacitive element, It comprises a first oxide semiconductor layer, a second oxide semiconductor layer, a first insulating layer, and a second insulating layer. The first oxide semiconductor layer has a channel formation region for the first transistor. The second oxide semiconductor layer has a channel formation region for the second transistor. The first oxide semiconductor layer is In-O, The second oxide semiconductor layer is In-O, The first insulating layer has a region between the first oxide semiconductor layer and the second insulating layer, and a region between the second oxide semiconductor layer and the second insulating layer. The first insulating layer comprises silicon and oxygen, The second insulating layer comprises silicon and nitrogen, In a cross-sectional view of the first transistor in the channel length direction, the first oxide semiconductor layer has a bending point, In a cross-sectional view of the second transistor in the channel length direction, the second oxide semiconductor layer has a bending point, In a plan view, the first wiring is a semiconductor device having a region located between the channel formation region of the first transistor and the channel formation region of the second transistor.

8. In any one of claims 1 to 7, A semiconductor device having an off-current density of 100 Hz / μm or less for the first transistor.

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