Self-aligned gate-end capping (SAGE) architecture with reduced capping

Abstract

To provide self-aligned gate endcap (SAGE) architectures with reduced or removed caps, and methods of manufacturing the same.SOLUTION: An integrated circuit structure 700 (720) includes a first gate electrode (708 on the left) over a first semiconductor fin 704 (one of a pair of fins 704 on the left). A second gate electrode (708 on the right) is over a second semiconductor fin (one of the pair of fins 704 on the right). A gate endcap isolation structure 722 is between the first gate electrode and the second gate electrode, the gate endcap isolation structure having higher-k dielectric cap layers 714, 724 on a lower-k dielectric wall 712. A local interconnect 726 is on the first gate electrode, on the higher-k dielectric cap layer, and on the second gate electrode, the local interconnect having a bottommost surface above an uppermost surface of the higher-k dielectric cap layer.SELECTED DRAWING: Figure 7A

Description

Technical Field

[0001] Embodiments of the present disclosure are in the field of semiconductor devices and processes, and more particularly, to a self-aligned gate end-cap (SAGE) architecture with reduced or removed caps, and a method of manufacturing a self-aligned gate end-cap (SAGE) architecture with reduced or removed caps.

Background Art

[0002] Over the past several decades, feature scaling in integrated circuits has been a driving force behind the continuously growing semiconductor industry. By scaling to even smaller features, it becomes possible to increase the density of functional units within the limited area of a semiconductor chip. For example, by reducing transistor dimensions, it becomes possible to incorporate more memory or logic devices on a chip, increasing the capacity of the manufactured product. However, aiming for more capacity than ever before is not without problems. The need to optimize the performance of each device is becoming increasingly important.

[0003] In the manufacture of integrated circuit devices, as device dimensions continue to shrink, multi-gate transistors such as tri-gate transistors have become more prevalent. In conventional processes, tri-gate transistors are generally manufactured on either a bulk silicon substrate or a silicon-on-insulator substrate. In some instances, the bulk silicon substrate is preferred due to its lower cost and the ability to enable a less complex tri-gate manufacturing process.

[0004] However, scaling multi-gate transistors without impact has not yet been achieved. As the dimensions of these basic building blocks in microelectronic circuits decrease, and as the number of these building blocks manufactured in a given area increases, the constraints on the lithography processes used to pattern these building blocks become enormous. In particular, there can be a trade-off between the minimum dimensions (critical dimensions) of patterned features in a semiconductor stack and the spacing between such features. [Brief explanation of the drawing]

[0005] [Figure 1] The diagram shows a plan view comparing adjacent integrated circuit structures of a conventional architecture with relatively wide spacing (left (a)) with adjacent integrated circuit structures of a self-aligned gate end cap (SAGE) architecture with relatively narrow spacing according to the embodiment of this disclosure (right (b)).

[0006] [Figure 2] A plan view of a conventional layout including a fin-based semiconductor device with end-to-end spacing is shown.

[0007] [Figure 3] The image shows a cross-sectional view through a fin, comparing a conventional architecture (left (a)) with a self-aligned gate end cap (SAGE) architecture according to the embodiment of this disclosure (right (b)).

[0008] [Figure 4A] This shows a cross-sectional view of key process steps in a conventional FinFET or tri-gate process manufacturing scheme. [Figure 4B] This shows a cross-sectional view of key process steps in a conventional FinFET or tri-gate process manufacturing scheme. [Figure 4C] This shows a cross-sectional view of key process steps in a conventional FinFET or tri-gate process manufacturing scheme. [Figure 4D] This shows a cross-sectional view of key process steps in a conventional FinFET or tri-gate process manufacturing scheme.

[0009] [Figure 5A] This disclosure shows cross-sectional views of key process steps in a self-aligned gate end cap (SAGE) process manufacturing scheme for a FinFET or tri-gate device according to the embodiments of this disclosure. [Figure 5B] This disclosure shows cross-sectional views of key process steps in a self-aligned gate end cap (SAGE) process manufacturing scheme for a FinFET or tri-gate device according to the embodiments of this disclosure. [Figure 5C] This disclosure shows cross-sectional views of key process steps in a self-aligned gate end cap (SAGE) process manufacturing scheme for a FinFET or tri-gate device according to the embodiments of this disclosure. [Figure 5D] This disclosure shows cross-sectional views of key process steps in a self-aligned gate end cap (SAGE) process manufacturing scheme for a FinFET or tri-gate device according to the embodiments of this disclosure.

[0010] [Figure 6] The layout of a 6T SRAM cell area having self-aligned gate end cap (SAGE) walls according to an embodiment of this disclosure is shown.

[0011] [Figure 7A] The images show cross-sectional views of the channel region of an integrated circuit structure without etched self-aligned gate end caps (SAGE) wall caps (left) and an integrated circuit structure with partially etched SAGE wall caps (right) according to the embodiments of this disclosure.

[0012] [Figure 7B] The images show cross-sectional views of the channel region of an integrated circuit structure without etched SAGE wall caps (left) and an integrated circuit structure with fully etched SAGE wall caps (right) according to the embodiments of this disclosure.

[0013] [Figure 7C] Cross-sectional views of a channel region of an integrated circuit structure without an etched SAGE wall cap (left side) and an integrated circuit structure having a combination of a partially etched SAGE wall cap and a fully etched SAGE wall cap (right side) according to an embodiment of the present disclosure are shown.

[0014] [Figure 7D] Cross-sectional views through a source or drain region of an integrated circuit structure without an etched SAGE wall cap (left side) and an integrated circuit structure having a partially etched SAGE wall cap (right side) according to an embodiment of the present disclosure are shown.

[0015] [Figure 8A] A cross-sectional view of a non-planar semiconductor device having a multi-self-aligned gate end cap (SAGE) isolation structure architecture according to an embodiment of the present disclosure is shown.

[0016] [Figure 8B] A plan view along the a-a' axis of the semiconductor device of FIG. 8A according to an embodiment of the present disclosure is shown.

[0017] [Figures 9A-9C] Cross-sectional views of important process steps in a self-aligned gate end cap (SAGE) process manufacturing scheme of another FinFET or trigate device according to an embodiment of the present disclosure are shown.

[0018] [Figure 10] A computing device according to one implementation of an embodiment of the present disclosure is shown.

[0019] [Figure 11] An interposer including one or more embodiments of the present disclosure is shown.

MODE FOR CARRYING OUT THE INVENTION

[0020] Self-aligned gate end cap (SAGE) architectures with reduced or eliminated caps, and methods for manufacturing self-aligned gate end cap (SAGE) architectures with reduced or eliminated caps are described. Many specific details, including specific integration and material configurations, are described in the following description to provide a full understanding of the embodiments of the disclosure. It will be apparent to those skilled in the art that embodiments of the disclosure can be carried out without these specific details. In other examples, well-known features, such as the design layout of integrated circuits, are not described in detail to avoid unnecessarily obscuring the embodiments of the disclosure. Furthermore, it should be understood that the various embodiments shown are illustrative and not necessarily drawn to actual size.

[0021] Certain terms may be used for reference purposes only in the following descriptions and are therefore not intended to be restrictive. For example, terms such as “top,” “bottom,” “upper,” and “downward” refer to the direction in the referenced drawing. Terms such as “front,” “rear,” “back,” and “side” describe the orientation and / or location of a part of a component, within a consistent but arbitrary frame of reference. This is made clear by the wording describing the component being described and the references to the relevant drawings. Such terms may include the words specifically mentioned above, their derivatives, and words with similar meanings.

[0022] The embodiments described herein may relate to semiconductor processes and structures of the substrate process (FEOL). FEOL is the first part of integrated circuit (IC) manufacturing, in which individual devices (e.g., transistors, capacitors, resistors, etc.) are patterned onto a semiconductor substrate or layer. FEOL generally encompasses everything up to (but not including) the deposition of a metal interconnect layer. After the final FEOL step, typically, a wafer with isolated transistors (e.g., without any wires) is produced.

[0023] The embodiments described herein may relate to semiconductor processes and structures in the wiring process (BEOL). BEOL is the second part of IC manufacturing where individual devices (e.g., transistors, capacitors, resistors, etc.) are interconnected with wiring on a wafer, e.g., one or more metallization layers. BEOL includes contacts, insulating layers (dielectrics), metal levels, and bonding sites for chip-package connections. In the BEOL portion of the manufacturing stage, contacts (pads), interconnect wires, vias, and dielectric structures are formed. In modern IC processes, more than 10 metal layers may be added in BEOL.

[0024] The embodiments described later may apply to FEOL processes and structures, BEOL processes and structures, or both FEOL and BEOL processes and structures. In particular, exemplary processing schemes may be shown using FEOL process scenarios, but such approaches may also be applicable to BEOL processes. Similarly, exemplary processing schemes may be shown using BEOL process scenarios, but such approaches may also be applicable to FEOL processes.

[0025] One or more embodiments of this disclosure relate to semiconductor structures or devices having one or more gate end cap structures. Furthermore, methods for fabricating gate end cap isolation structures by self-alignment techniques are also described. In one or more embodiments, reduction of self-aligned gate end cap (SAGE) caps is performed using a highly selective high-k dielectric material (HiK) etching process. Embodiments described herein may address problems associated with scaling end-to-end spacing of diffusion in ultra-scaling process techniques.

[0026] To provide a broader context, the latest technological approach relies on end-to-end (polycut) lithographic scaling of gates to define the diffusion overlap of minimum-technical gates. The diffusion overlap of minimum-technical gates is a key element in the end-to-end space of diffusion. The relevant gate line (polycut) process is typically limited by considering lithography, alignment, and etching biases, ultimately setting the minimum diffusion end-to-end distance. Other approaches, such as contact-over-active gate (COAG) architectures, have worked to improve the properties of such diffusion intervals. However, there is still considerable room for improvement in this field.

[0027] To provide a basis for highlighting the advantages of the embodiments of this disclosure, it should first be understood that the advantages of the self-aligned gate end cap (SAGE) architecture over non-SAGE approaches may include achieving higher layout density, particularly diffusion scaling to diffusion spacing. As an example, Figure 1 shows a plan view comparing adjacent integrated circuit structures of a conventional architecture with relatively wide spacing (left (a)) with adjacent integrated circuit structures of a SAGE architecture with relatively narrow spacing according to an embodiment of this disclosure (right (b)).

[0028] Referring to the left side (a) of Figure 1, layout 100 includes a first integrated circuit structure 102 and a second integrated circuit structure 104, which are based on semiconductor fins 106 and 108, respectively. Each device 102 and 104 has a gate electrode 110 or 112, respectively. Furthermore, each device 102 and 104 has trench contacts (TCNs) 114 or 116 in the source and drain regions of fins 106 and 108, respectively. Gate vias 118 and 120 and trench contact vias 119 and 121 are also shown.

[0029] Referring again to the left side (a) of Figure 1, the gate electrodes 110 and 112 each have relatively wide end cap regions 122 that are located away from the corresponding fins 106 and 108, respectively. The TCNs 114 and 116 each have relatively large end-to-end spacings 124, which are also located away from the corresponding fins 106 and 108, respectively.

[0030] On the other hand, referring to the right side (b) of Figure 1, layout 150 includes a first integrated circuit structure 152 and a second integrated circuit structure 154, which are based on semiconductor fins 156 and 158, respectively. Each device 152 and 154 has a gate electrode 160 or 162, respectively. Furthermore, each device 152 and 154 has trench contacts (TCNs) 164 or 166 in the source and drain regions of the fins 156 and 158, respectively. Gate vias 168 and 170 and trench contact vias 169 and 171 are also shown.

[0031] Referring again to the right side (b) of Figure 1, the gate electrodes 160 and 162 have relatively narrow end cap regions, which are located away from the corresponding fins 156 and 158, respectively. Each TCN 164 and 166 has a relatively narrow end-to-end spacing 174, which is also located away from the corresponding fins 156 and 158, respectively.

[0032] To provide further context, scaling of gate end cap and trench contact (TCN) end cap regions is a significant contributor to improving the area and density of transistor layouts. The gate and TCN end cap regions refer to the overlap of the gate and TCN in the diffusion region / fin of a semiconductor device. As an example, Figure 2 shows a plan view of a conventional layout 200 including a fin-based semiconductor device with end-to-end spacing.

[0033] Referring to Figure 2, the first semiconductor device 202 and the second semiconductor device 204 are based on semiconductor fins 206 and 208, respectively. Each device 202 and 204 has a gate electrode 210 or 212, respectively. Furthermore, each device 202 and 204 has trench contacts (TCNs) 214 or 216 in the source and drain regions of fins 206 and 208, respectively. The gate electrodes 210 and 212 and the TCNs 214 and 216 each have end cap regions, which are located away from the corresponding fins 206 and 208, respectively.

[0034] Referring again to Figure 2, typically, the dimensions of the gate and TCN end caps must include a margin for mask alignment error to ensure robust transistor operation against worst-case mask misalignment, leaving an end-to-end spacing of 218. Thus, another critical design rule for improving transistor layout density is the spacing between two adjacent end caps facing each other. However, the parameter "2 * end caps + end-to-end spacing" is becoming increasingly difficult to scale using lithography patterning and to meet the scaling requirements of newer technologies. In particular, the additional end cap length required to account for mask alignment error also increases the gate capacitance value due to the longer overlap length between the TCN and gate electrode, thereby increasing the dynamic power consumption of the product and degrading performance. Conventional solutions have focused on improving alignment margin and patterning or resolution to allow for reductions in both end cap dimensions and end cap-to-end cap spacing.

[0035] An approach is described that provides for the overlap of self-aligned gate end caps (SAGEs) and TCNs of semiconductor fins without requiring any consideration of mask alignment, according to embodiments of the present disclosure. In one such embodiment, a disposable spacer is manufactured on the sidewall of the semiconductor fin, which determines the overlap dimensions of the gate end caps and contacts. The end cap process defined by the spacer allows the gate and TCN end cap regions to self-align with the semiconductor fin, and therefore does not require an extra end cap length to account for mask misalignment. Furthermore, since the gate and TCN end cap / overlap dimensions remain fixed, the approach described herein does not necessarily require lithography patterning at the previously required stage, resulting in improved (i.e., reduced) inter-device variability of electrical parameters.

[0036] According to one or more embodiments of the present disclosure, scaling is achieved by constructing a SAGE wall, thereby reducing gate end cap overlap for diffusion. As an example, Figure 3 shows a cross-sectional view through a fin comparing a conventional architecture (left (a)) with a self-aligned gate end cap (SAGE) architecture according to an embodiment of the present disclosure (right (b)).

[0037] Referring to the left side (a) of Figure 3, the integrated circuit structure 300 includes a substrate 302 having a fin 304 protruding therefrom. The height (H) of the active portion of the fin 304 Si )306 is set by a separation structure 308 that laterally surrounds the lower part of the fin 304. Gate structures may be formed above the integrated circuit structure 300 for device manufacturing. However, the separation in such gate structures is addressed by increasing the spacing between the fins 304.

[0038] On the other hand, referring to the right side (b) of Figure 3, the integrated circuit structure 350 includes a substrate 352 having a fin 354 protruding therefrom. The height (H) of the active portion of the fin 354 Si)356 is defined by a separation structure 358 that laterally surrounds the lower part of the fin 354. Separation SAGE walls 360 (which may include a hard mask on top of them, as shown) are contained within the separation structure 358 between adjacent fins 354. The distance between the separation SAGE wall 360 and the nearest fin 354 defines the gate end cap spacing 362. Gate structures may be formed above the integrated circuit structure 350, between the separation SAGE walls 360, for the purpose of manufacturing the device. Such separation of gate structures is imposed by the separation SAGE walls 360. Since the separation SAGE walls 360 are self-aligned, constraints from conventional approaches can be minimized, and more aggressive diffusion into the diffusion spacing can be enabled. Furthermore, since the gate structures involve separation at all locations, individual gate structure portions may be layers connected by local interconnects formed above the separation SAGE walls 360.

[0039] To provide a comparative view, Figures 4A-4D show cross-sectional views of key process steps in a conventional FinFET or tri-gate process manufacturing scheme, and Figures 5A-5D show cross-sectional views of key process steps in a self-aligned gate end cap process manufacturing scheme for a FinFET or tri-gate device according to the embodiments of this disclosure.

[0040] Referring to Figures 4A and 5A, bulk semiconductor substrates 400 or 500, such as bulk single-crystal silicon substrates, are provided, each having etched fins 402 or 502 therein. In embodiments, the fins are formed directly on the bulk substrate 400 or 500 and are therefore formed in a continuous manner with the bulk substrate 400 or 500. It should be understood that within the substrate 400 or 500, shallow trench isolation structures may be formed between the fins. Referring to Figure 5A, a hard mask layer 504, such as a hard mask layer of silicon nitride, and a pad oxide layer 506, such as a silicon dioxide layer, remain on the fins 502 after patterning to form the fins 502. On the other hand, referring to Figure 4A, such hard mask layers and pad oxide layers have been removed.

[0041] Referring to Figure 4B, a dummy or permanent gate dielectric layer 410 is formed on the exposed surface of the semiconductor fin 402, and a dummy gate layer 412 is formed above the resulting structure. On the other hand, referring to Figure 5B, a dummy or permanent gate dielectric layer 510 is formed on the exposed surface of the semiconductor fin 502, and a dummy spacer 512 is formed adjacent to the resulting structure.

[0042] Referring to Figure 4C, patterning is performed to cut the gate end cap, and a separation region 414 is formed in the resulting patterned dummy gate end 416. In conventional process schemes, a larger gate end cap must be manufactured to account for gate mask misalignment, as illustrated by the arrowed region 418. On the other hand, referring to Figure 5C, a self-aligning separation region 514 is formed by providing a separation layer above the structure in Figure 5B, for example by deposition and planarization. In such one embodiment, the self-aligning gate end cap process does not require extra space for mask alignment, as can be compared in Figures 4C and 5C.

[0043] Referring to Figure 4D, the dummy gate electrode 412 in Figure 4C is replaced by a permanent gate electrode. If a dummy gate dielectric layer is used, such a dummy gate dielectric layer may also be replaced by a permanent gate dielectric layer in this process. In the specific example shown, a dual metal gate replacement process is performed to provide an N-type gate electrode 420 above the first semiconductor fin 402A and a P-type gate electrode 422 above the second semiconductor fin 402B. The N-type gate electrode 420 and the P-type gate electrode 422 are formed between the isolation regions 414, where they contact, forming a P / N junction 424. The exact location of the P / N junction 424 may vary depending on the alignment misalignment, as illustrated by the arrowed region 426.

[0044] On the other hand, referring to Figure 5D, the hard mask layer 504 and the pad oxide layer 506 are removed, and the dummy spacer 514 in Figure 5C is replaced with a permanent gate electrode. If a dummy gate dielectric layer is used, such a dummy gate dielectric layer may also be replaced by a permanent gate dielectric layer in this process. In the specific example shown, a dual metal gate replacement process is performed to provide an N-type gate electrode 520 above the first semiconductor fin 502A and a P-type gate electrode 522 above the second semiconductor fin 502B. The N-type gate electrode 520 and the P-type gate electrode 522 are formed between and separated by gate end cap isolation structures 514.

[0045] Referring again to Figure 4D, a local interconnect 440 may be fabricated to bring the N-type gate electrode 420 and the P-type gate electrode 422 into contact, providing a conductive path around the P / N junction 424. Similarly, referring to Figure 5D, a local interconnect 540 may be fabricated to bring the N-type gate electrode 520 and the P-type gate electrode 522 into contact, providing a conductive path above the isolation structure 514 interposed between them. Referring to both Figures 4D and 5D, a hard mask 442 or 542 may be formed on the local interconnect 440 or 540, respectively. Referring particularly to Figure 5D, in one embodiment, the conductivity of the local interconnect 540 is interrupted by a dielectric plug 550 when a break at an electrical contact along the gate line is required.

[0046] According to one or more embodiments of this disclosure, a self-aligning gate end cap (SAGE) process scheme involves forming a gate / trench contact end cap that self-aligns with the fins without requiring extra length to account for mask misalignment. Thus, the embodiments may be implemented to allow for area reduction of the transistor layout. Embodiments described herein may involve the fabrication of a gate end cap isolation structure, which may also be referred to as a gate wall, isolation gate wall, or SAGE wall.

[0047] In another embodiment, SAGE cap reduction, such as high-k cap etching, is performed to reduce or remove SAGE wall caps.

[0048] To provide context, the self-aligned gate edge (SAGE) architecture described above can be implemented for continuous cell height scaling while overcoming the limitations in edge placement errors in the lithography process. As an example, Figure 6 shows a layout of a 6T SRAM cell area having SAGE walls according to an embodiment of this disclosure.

[0049] Referring to Figure 6, the 6T SRAM layout 600 has a cell area within the SAGE wall 612, with a cell height 602 and a cell length 604. A pair of fins (or nanowire stacks) 606 are located within the cell area. The active gate 608 and the inactive gate 610 are located above the pair of fins (or nanowire stacks) 606.

[0050] As a benefit of the SAGE wall 612 in the 6T SRAM layout 600, the architecture can be implemented to eliminate an extra 10nm margin due to gate edge misalignment caused by the lower wall. However, the SAGE wall 612 may need to withstand many different process sequences. To minimize variations, extremely durable materials may be required, at least as caps for the SAGE wall. In one embodiment, such caps consist of high-k materials such as hafnium oxide (HfO2), zirconium oxide (ZrO2), hafnium-zirconium oxide, HfNO, ZrNO, or HfZrNO. Such materials may be essential for process controllability. However, high-k materials and the associated tall gate metal layers can add enormous costs in terms of capacitance margin tied to active power. Any high-k material surrounding the channel and gate can contribute to the total capacitance. Therefore, it is important to reduce high-k components in the SAGE wall to the extent possible, which can be a challenge to balance.

[0051] In conventional approaches, the lower part of the SAGE wall is replaced with a low-k material. However, the upper high-k cap remains a significant portion contributing to the capacitance near the device. According to one or more embodiments of the present disclosure, the unwanted high-k portion of the SAGE structure is reduced or removed after the gate and trench contact (TCN) metals have been formed. The high-k (HiK) portion can be reduced or removed using a HiK etching process selective for Si, SiGe, oxides, nitrides, and metals.

[0052] The advantages of implementing one or more embodiments described herein may include reducing capacity while retaining the advantages of scaling cell height using SAGE, thereby enabling optimal PPA (power, performance, and area). It should be understood that HiK etched in the SAGE post-metal gate (MG) process or trench contact (TCN) process is detectable by XSEM and / or TEM. In embodiments, at the channel location, after the metal gate process is completed, the HiK portion of the SAGE structure is etched out, reduced, or removed. Similarly, at the source or drain location, after the TCN metal process, the HiK portion of the SAGE structure is etched out, reduced, or removed. The etching process may be selective for the metal gate portion and / or trench contact portion.

[0053] In the first example, Figure 7A shows cross-sectional views of the channel region of an integrated circuit structure without etched SAGE wall caps (left) and an integrated circuit structure with partially etched SAGE wall caps (right) according to an embodiment of the present disclosure.

[0054] Referring to the left side of Figure 7A, the integrated circuit structure 700 without etched SAGE wall caps includes a substrate 702 having fins 704 on or above it. The lower part of the fins 704 is surrounded by a shallow trench isolation structure 706, and the upper part of the fins 704 protrudes above the shallow trench isolation structure 706. Gate stacks 708 are each located above one or more fins 704, for example, above each of a pair of fins 704. Each gate stack 708 may include a gate dielectric, such as a high-k gate dielectric, and a metal gate electrode with an exposed upper surface. SAGE walls 710 are located on and between the sides of the gate stacks 708. Each SAGE wall 710 has a high-k dielectric cap layer 714 on a low-k dielectric wall 712. The high-k dielectric cap layer 714 has an uppermost surface 715 and a lowermost surface 713. The local conductive interconnect 716 electrically couples the exposed upper surface of the metal gate electrode of the adjacent gate stack 708 and extends above the intervening SAGE wall (intermediate portion 710). The local conductive interconnect 716 has an uppermost surface 719 and a lowermost surface 717. The lowermost surface 717 of the local conductive interconnect 716 is below the uppermost surface 715 of the high-k dielectric capping layer 714 of the SAGE wall 710.

[0055] Referring to the right side of Figure 7A, the integrated circuit structure 720 having a partially etched SAGE wall cap includes a substrate 702 having fins 704 on or above it. The lower part of the fins 704 is surrounded by a shallow trench isolation structure 706, and the upper part of the fins 704 protrudes above the shallow trench isolation structure 706. Gate stacks 708 are each located above one or more fins 704, for example, above each of a pair of fins 704. Each gate stack 708 may include a gate dielectric, such as a high-k gate dielectric, and a metal gate electrode with an exposed upper surface. SAGE walls 722 are located on and between the sides of the gate stacks 708. Each SAGE wall 722 has a high-k dielectric cap layer 724 on a low-k dielectric wall 712. The high-k dielectric cap layer 724 has an uppermost surface 725.

[0056] Referring again to the right side of Figure 7A, according to embodiments of the present disclosure, the integrated circuit structure 720 includes a first gate electrode (left 708) above a first semiconductor fin (one of the pair of left fins 704). A second gate electrode (right 708) is above a second semiconductor fin (one of the pair of right fins 704). A gate end cap isolation structure (intermediate portion 722) is located between the first gate electrode (left 708) and the second gate electrode (right 708). The gate end cap isolation structure 722 has a high-k dielectric cap layer 724 on a low-k dielectric wall 712. A local interconnect 726 is located above the first gate electrode (left 708), above the high-k dielectric cap layer (intermediate portion 724), and above the second gate electrode (right 708). The local interconnect 726 has a bottom surface 727 above the top surface 725 of the high-k dielectric cap layer (intermediate portion 724).

[0057] In one embodiment, the first gate electrode (left 708) and the second gate electrode (right 708) each have a coplanar upper surface 725 of the high-k dielectric cap layer (intermediate portion 724) of the gate end cap isolation structure (intermediate portion 722). In one embodiment, the local interconnect 726 electrically connects the first gate electrode (left 708) and the second gate electrode (right 708). In one embodiment, the gate end cap isolation structure (intermediate portion 722) includes a vertical seam in the center of the low-k dielectric wall 712, as will be described later in relation to Figure 9C, for example.

[0058] In the second example, Figure 7B shows cross-sectional views of the channel region of an integrated circuit structure without etched SAGE wall caps (left) and an integrated circuit structure with fully etched SAGE wall caps (right) according to an embodiment of the present disclosure.

[0059] Referring to the left side of Figure 7B, the integrated circuit structure 700 without etched SAGE wall caps is as described above in relation to Figure 7A. Referring to the right side of Figure 7B, the integrated circuit structure 730 with completely etched / removed SAGE wall caps includes a substrate 702 having fins 704 on or above it. The lower part of the fins 704 is surrounded by a shallow trench isolation structure 706, and the upper part of the fins 704 protrudes above the shallow trench isolation structure 706. Gate stacks 708 are each located above one or more fins 704, for example, above each of a pair of fins 704. Each gate stack 708 may include a gate dielectric, such as a high-k gate dielectric, and a metal gate electrode with an exposed upper surface. SAGE walls 732 are located on and between the sides of the gate stacks 708. Each SAGE wall 732 includes only a low-k dielectric wall 734. The local conductive interconnect 736 electrically couples the exposed upper surface of the metal gate electrode of the adjacent gate stack 708 and extends above the intervening SAGE wall (intermediate section 732). In one embodiment, the bottom surface of the local conductive interconnect is planar throughout the local conductive interconnect 736, as shown in the figure.

[0060] In the third example, Figure 7C shows cross-sectional views of the channel region of an integrated circuit structure without etched SAGE wall caps according to an embodiment of the present disclosure (left side), and an integrated circuit structure having a combination of partially etched SAGE wall caps and fully etched SAGE wall caps (right side).

[0061] Referring to the left side of Figure 7C, the integrated circuit structure 700 without etched SAGE wall caps is as described above in relation to Figure 7A. Referring to the right side of Figure 7C, the integrated circuit structure 740 having both partially etched and fully etched SAGE wall caps includes a substrate 702 having fins 704 on or above it. The lower part of the fins 704 is surrounded by a shallow trench isolation structure 706, and the upper part of the fins 704 protrudes above the shallow trench isolation structure 706. Gate stacks 708 are each located above one or more fins 704, for example, above each of a pair of fins 704. Each gate stack 708 may include a gate dielectric such as a high-k gate dielectric and a metal gate electrode with an exposed upper surface. SAGE walls 742A are on the sides of the gate stacks 708, and SAGE walls 742B are located between the gate stacks 708. Each SAGE wall 742A has a high-k dielectric cap layer 744 on top of a low-k dielectric wall. The high-k dielectric cap layer 744 has an uppermost surface 745 and a lowermost surface 743. SAGE wall 742B has only a low-k dielectric wall 746. A local conductive interconnect 748 electrically couples the exposed upper surface of the metal gate electrode of the adjacent gate stack 708 and extends above the intervening SAGE wall 742B. The local conductive interconnect 748 has a lowermost surface 742 and an uppermost surface 749. The lowermost surface 742 of the local conductive interconnect 748 is coplanar with the lowermost surface 743 of the high-k dielectric cap layer 744. The uppermost surface 749 of the local conductive interconnect 748 is above the uppermost surface 745 of the high-k dielectric cap layer 744 of the SAGE wall 742A. In one embodiment, the bottom surface 742 of the local conductive interconnect 748 is planar as shown in the figure.

[0062] Figure 7D shows cross-sectional views through the source or drain region of an integrated circuit structure without an etched SAGE wall cap (left) and an integrated circuit structure with a partially etched SAGE wall cap (right) according to an embodiment of the present disclosure.

[0063] Referring to the left side of Figure 7D, the integrated circuit structure 750 without etched SAGE wall caps includes a substrate 702 having fins 704 on or above it. The lower part of the fins 704 is surrounded by a shallow trench isolation structure 706, and the upper part of the fins 704 protrudes above the shallow trench isolation structure 706. Conductive trench contacts 756 are located above one or more fins 704, for example, above each pair of fins 704, above epitaxial source or drain structures 752 / 754. The epitaxial source or drain structures 752 and 754 may have opposite conductivity. SAGE walls 710 are located on and between the conductive trench contacts 756. Each SAGE wall 710 has a high-k dielectric cap layer 714 on a low-k dielectric wall 712. The local conductive interconnect 758 electrically couples the exposed upper surface of the adjacent conductive trench contact 756 and extends above the intervening SAGE wall (intermediate portion 710). The local conductive interconnect 716 has its lowest surface below the uppermost surface of the high-k dielectric cap layer 714 of the SAGE wall 710.

[0064] Referring to the right side of Figure 7D, the integrated circuit structure 760 having a partially etched SAGE wall cap includes a substrate 702 having fins 704 on or above it. The lower part of the fins 704 is surrounded by a shallow trench isolation structure 706, and the upper part of the fins 704 protrudes above the shallow trench isolation structure 706. Conductive trench contacts 756 (which may be contained in dielectric 757) are located above one or more fins 704, for example, above each pair of fins 704, above epitaxial source or drain structures 752 / 754. The epitaxial source or drain structures 752 and 754 may have opposite conductivity. SAGE walls 722 are located on and between the conductive trench contacts 756. Each SAGE wall 722 has a high-k dielectric cap layer 724 on a low-k dielectric wall 712. The high-k dielectric cap layer 724 has an uppermost surface 725. The local conductive interconnect 762 electrically couples the exposed upper surface of the adjacent conductive trench contact 756 and extends above the intervening SAGE wall (intermediate portion 722). The local conductive interconnect 762 has a bottom surface 761 and an upper surface 763. The bottom surface 761 of the local conductive interconnect 762 is above the upper surface 725 of the high-k dielectric capping layer 724 of the SAGE wall 722. In one embodiment, the bottom surface 761 of the local conductive interconnect 762 is planar throughout the local conductive interconnect 762, as shown in the figure.

[0065] Referring again to the right side of Figure 7D, according to embodiments of the present disclosure, the integrated circuit structure 760 includes a first trench contact (left side 756) above a first epitaxial structure 752 above a first semiconductor fin (one of the pair of fins 704 on the left side). A second trench contact (right side 756) is located above a second epitaxial structure 754 above a second semiconductor fin (one of the pair of fins 704 on the right side). A gate end cap isolation structure (intermediate section 722) is located between the first trench contact (left side 756) and the second trench contact (right side 756). The gate end cap isolation structure (intermediate section 722) has a high-k dielectric cap layer 724 on a low-k dielectric wall 712. The local interconnect 756 rests on the first trench contact (left side 756), on the high-k dielectric cap layer 724, and on the second trench contact (right side 756). The local interconnect 762 has its lowest surface 761 above the uppermost surface 725 of the high-k dielectric cap layer 724.

[0066] In one embodiment, the first trench contact (left 756) and the second trench contact (right 756) each have a coplanar upper surface with the uppermost surface 725 of the high-k dielectric cap layer 724 of the gate end cap isolation structure (intermediate section 722). In one embodiment, the local interconnect 762 electrically connects the first trench contact (left 756) and the second trench contact (right 756). In one embodiment, the gate end cap isolation structure (intermediate section 722) includes a vertical seam in the center within the low-k dielectric wall 712, as will be described later in relation to Figure 9C, for example.

[0067] In another embodiment, the SAGE wall may vary in width, position, and function for different devices. In exemplary implementations, system-on-chip (SoC) process technology typically requires support for standard logic (e.g., low voltage, thin oxide) and I / O (e.g., high voltage, thick oxide) transistors. The distinction between standard logic and high voltage (HVI / O) devices may be achieved by a multi-oxide process sequence, where logic transistors receive thin, high-performance oxide and I / O devices receive thick oxide capable of withstanding higher voltages. As process technology scales, logic devices scale aggressively in dimensions, creating manufacturing challenges associated with the formation of dual oxides. According to one or more embodiments of this disclosure, a high-voltage end-cap process is combined with an ultra-scalable FinFET transistor architecture to provide a multi-self-aligned end-cap process in which at least some (if not all) of the SAGE structures are manufactured without fin end caps.

[0068] To provide context, as technology nodes scale down to smaller sizes, there is a growing lack of geometric space to accommodate defect-free dual-oxide processes that may be required for high-voltage transistor manufacturing in narrow-endcap logic devices. Current approaches rely on a single, unscaled end-cap space to accommodate a single logic oxide process. However, since the end-cap space may be insufficient to accommodate both oxides (gate dielectrics), such processes may not fit into the larger, scaled geometry required to support dual-oxide high-voltage SoC technology.

[0069] Embodiments of this disclosure address the scaling limitations imposed by the requirement to fill high-voltage gates with both high-voltage oxides and logic oxides. In particular, as logic dimensions decrease, the end cap space in high-voltage (HV) devices becomes too narrow to adequately fill both oxides. In embodiments, the different end cap spaces between logic transistors and high-voltage transistors are fabricated using the SAGE architecture, respectively. The end caps of logic transistors are ultrascaled by using a self-aligned end cap architecture, while high-voltage transistors have wider end caps to accommodate thicker gate dielectrics. One or both types of end caps can be fabricated without fin end caps according to embodiments described herein.

[0070] One or more embodiments described herein relate to, or may be referred to as, a multidirectional-unidirectional end capping process flow for ultra-scaling logic end caps. To provide context, in a typical SAGE flow, a single end cap spacer is deposited to form a self-aligning end cap that separates the fins from the SAGE wall. Embodiments described herein may include the formation of different sacrificial spacer thicknesses between the logic and the HV gate. A self-aligning end cap wall is then formed. The different spacer widths are selected to be thicker in the high-voltage area, while the standard thickness is used in the logic area. The different spacer widths may allow the high-voltage oxide to be successfully deposited without sacrificing density in the logic area. In embodiments, the different spacer thicknesses follow the intended HV oxide thickness.

[0071] As an example of a completed device, Figure 8A shows a cross-sectional view of a non-planar semiconductor device having a multi-self-aligned gate-end cap isolation structure architecture according to an embodiment of the present disclosure. Figure 8B shows a plan view along the a-a' axis of the structure of Figure 8A according to an embodiment of the present disclosure.

[0072] Referring to Figure 8A, the semiconductor structure 800 includes a non-planar active region formed within a trench isolation layer 806 from the substrate 802 (e.g., a fin structure including protruding fin portions 804 and sub-fin regions 805). In an embodiment, the fin structure is a plurality of fin lines forming a lattice structure such as a tight-pitch lattice structure. In such an embodiment, the tight pitch is not directly achievable by conventional lithography. For example, a pattern based on conventional lithography may be formed first, but the pitch may be divided into two using spacer mask patterning, as is known in the art. Furthermore, the original pitch may be divided into four by a second spacer mask patterning. Thus, the lattice fin pattern may have lines spaced at a constant pitch and having a constant width. The pattern may be manufactured by pitch division into two or four, or by other pitch division approaches. Each of the individual fins 804 shown may represent a corresponding individual fin, or a plurality of fins at a particular location.

[0073] The gate structure 808 is located above the protruding portion 804 of the non-planar active region and above the portion of the trench isolation layer 806. As shown, the gate structure 808 includes a gate electrode 850 and a gate dielectric layer 852. In one embodiment, although not shown, the gate structure 808 may include a dielectric cap layer.

[0074] The gate structure 808 is separated by narrow self-aligned gate end cap (SAGE) isolation structures or walls 820, 821A, or 821B. Each SAGE wall 820 has a width. In embodiments, SAGE wall 821A has a width greater than each of the SAGE walls 820, and SAGE wall 821B has a width less than each of the SAGE walls 820. SAGE walls of different widths may be associated with different device types, as described in the exemplary embodiments herein. It should be understood that the variation in SAGE wall widths is reconfigurable. In other embodiments, the widths are all the same. Each of the SAGE walls 820, 821A, or 821B may include one or more local interconnects 854 or dielectric plugs 899 formed thereon. In embodiments, each of the SAGE walls 820, 821A, or 821B is recessed below the uppermost surface 897 of the trench isolation layer 806, as shown in Figure 8A.

[0075] According to embodiments of this disclosure, the SAGE wall 821A is formed at the location of the cut fin. In certain embodiments, the SAGE wall 821A is formed above the cut portion 869 of the fin, as shown in the illustration. In embodiments, the SAGE walls 820, 821A and 821B are manufactured after the fin cutting process.

[0076] In an exemplary embodiment, the semiconductor structure 800 includes a first plurality of semiconductor fins (fins in region 870A or a plurality of fins 804) located above the substrate 802 and protruding through the uppermost surface 897 of the trench isolation layer 806, and a first gate structure (gate structure 808 in region 870A) located above the first plurality of semiconductor fins. A second plurality of semiconductor fins (fins in region 870B or a plurality of fins 804) are located above the substrate 802 and protruding through the uppermost surface 897 of the trench isolation layer 806, and a second gate structure (gate structure 808 in region 870B) is located above the second plurality of semiconductor fins. A gate end cap isolation structure (to the left of the SAGE wall 820) is located between the first gate structure and the second gate structure and is in contact with them. The semiconductor fins of the first group of semiconductor fins closest to the gate end cap separation structure (from region 870A) are further away from the gate end cap separation structure than the semiconductor fins of the second group of semiconductor fins closest to the gate end cap separation structure (from region 870B).

[0077] In one embodiment, region 870A is an I / O region and region 870B is a logic region. As shown in the illustration, in one such embodiment, a second logic region 870C is adjacent to logic region 870B and is electrically connected to logic region 870B by a local interconnect 854. Another region 870D may be a location where an additional logic or I / O region may be located. Embodiments described herein may include different spacings from the SAGE walls (e.g., wider spacing from SAGE wall 821B and the left-hand side 820 of region 870A), or SAGE walls of different widths (e.g., narrower 821B vs 820 vs wider 821A), or both different spacings from the SAGE walls and SAGE walls of different widths. In one embodiment, the I / O region has a larger spacing between SAGE walls than the logic region. In one embodiment, wider SAGE walls are between adjacent logic regions than between adjacent I / O regions.

[0078] The gate contact 814 and the gate contact via 816 located above it are also visible in this perspective view, along with the metal interconnect 860 located above it, all of which are located in the interlayer insulating film stack or layer 870. As can also be seen in the perspective view of Figure 8A, in one embodiment the gate contact 814 is above the non-planar active region. Also as shown in Figure 8A, a boundary 880 is present in the doping profile between the protruding fin portion 804 and the sub-fin region 805, but other embodiments do not include such a boundary in the doping profile between these regions.

[0079] Referring to Figure 8B, the gate structure 808 is shown to be located above the protruding fin portion 804 and separated by the self-aligning gate end cap separation structure 820. In one embodiment, the gate structure 808 forms one of several parallel gate lines that form a grid structure, such as a tight-pitch grid structure. In such an embodiment, the tight pitch is not directly achievable by conventional lithography. For example, a pattern based on conventional lithography may be formed first, but the pitch may be divided into two using spacer mask patterning, as is known in the art. Furthermore, the original pitch may be divided into four by a second spacer mask patterning. Thus, the grid-like gate pattern may have lines that are spaced at a constant pitch and have a constant width. The pattern may be manufactured by pitch division into two or four, or by other pitch division approaches.

[0080] Referring again to Figure 8B, the source and drain regions 804A and 804B of the protruding fin portion 804 are shown in this perspective view, and it should be understood that these regions overlap with the trench contact structure. In one embodiment, the source and drain regions 804A and 804B are doped portions of the raw material of the protruding fin portion 804. In another embodiment, the material of the protruding fin portion 804 is removed and replaced with another semiconductor material, for example by epitaxial growth. In either case, the source and drain regions 804A and 804B may extend below the height of the trench isolation layer 806, i.e., into the sub-fin region 805.

[0081] In embodiments, the semiconductor structure 800 includes, but is not limited to, a non-planar device such as a FinFET or a tri-gate device. In such embodiments, the corresponding semiconductor channel region consists of or is formed on a three-dimensional object. In one such embodiment, the gate structure 808 surrounds at least the top surface and a pair of side walls of the three-dimensional object.

[0082] The substrate 802 may consist of a semiconductor material that can withstand the manufacturing process and allows charge transfer. In embodiments, the substrate 802 is a bulk substrate consisting of crystalline silicon, silicon / germanium, or germanium layers doped with charge carriers such as phosphorus, arsenic, boron, or combinations thereof, in order to form the active region 804. In one embodiment, the silicon atom concentration of the bulk substrate 802 is greater than 97%. In another embodiment, the bulk substrate 802 consists of an epitaxial layer grown on a separate crystalline substrate, for example, a silicon epitaxial layer grown on a boron-doped bulk silicon single-crystal substrate. Alternatively, the bulk substrate 802 may consist of a group III-V material. In some embodiments, the bulk substrate 802 is made of a Group III-V material such as gallium nitride, gallium phosphide, gallium arsenide, indium phosphide, indium antimonide, indium gallium arsenide, aluminum gallium arsenide, indium gallium phosphide, or a combination thereof. In one embodiment, the bulk substrate 802 is made of a Group III-V material, and the charge carrier dopant impurity atoms are, but are not limited to, carbon, silicon, germanium, oxygen, sulfur, selenium, or tellurium.

[0083] The trench isolation layer 806 may ultimately consist of a suitable material for electrically isolating portions of the permanent gate structure from the underlying bulk substrate, or for contributing to such isolating active regions formed within the underlying bulk substrate, such as isolating the active regions of fins. For example, in one embodiment, the trench isolation layer 806 may consist of a dielectric material such as silicon dioxide, silicon oxynitride, silicon nitride, or carbon-doped silicon nitride, but is not limited to these materials.

[0084] The self-aligned gate end cap isolation structures 820, 821A, and 821B may consist of a suitable material or a combination of materials that ultimately electrically isolate portions of the permanent gate structure from each other or contribute to this isolation. Exemplary materials or combinations of materials include single-material structures such as silicon dioxide, silicon oxynitride, silicon nitride, or carbon-doped silicon nitride. Other exemplary materials or combinations of materials include multilayer stacks having a lower layer of silicon dioxide, silicon oxynitride, silicon nitride, or carbon-doped silicon nitride and an upper layer of a high dielectric constant material such as hafnium oxide. Additional examples are described later in relation to Figures 9A–9C.

[0085] The gate structure 808 may consist of a gate electrode stack including a gate dielectric layer 852 and a gate electrode layer 850. In an embodiment, the gate electrode of the gate electrode stack is made of a metal gate, and the gate dielectric layer contains a high-k material.

[0086] In an exemplary embodiment, the gate structure 808 in region 870A includes a first gate dielectric 852 conforming to a first plurality of semiconductor fins, adjacent to and in contact with the first side (left-hand 820) of the gate end cap isolation structure. The second gate stack in region 870B includes a second gate dielectric 852 conforming to a second plurality of semiconductor fins, adjacent to and in contact with the second side of the gate end cap isolation structure opposite to the first side of the gate end cap isolation structure. In one embodiment, the first gate dielectric is thicker than the second gate dielectric, as shown in Figure 8A. In one embodiment, the first gate dielectric has more dielectric layers (e.g., layers 852A and 852B) than the second gate dielectric (e.g., layer 852 only). In an embodiment, the gate dielectric in region 870A is an I / O gate dielectric, and the gate dielectric in region 870B is a logic gate dielectric.

[0087] In embodiments, the gate dielectric of region 870B consists of, but is not limited to, materials such as hafnium oxide, hafnium oxynitride, hafnium silicate, lanthanum oxide, zirconium oxide, zirconium silicate, tantalum oxide, barium strontium titanate, barium titanate, strontium titanate, yttrium oxide, aluminum oxide, tantalum scandium lead oxide, zinc niobate, or combinations thereof. Furthermore, a portion of the gate dielectric layer may include a layer of native oxide formed from several upper layers of the substrate 802. In embodiments, the gate dielectric layer consists of an upper high-k portion and a lower portion made of an oxide of a semiconductor material. In one embodiment, the gate dielectric layer consists of an upper portion of hafnium oxide and a lower portion of silicon dioxide or silicon oxynitride. In embodiments, the upper high-k portion consists of a "U"-shaped structure including a lower portion substantially parallel to the surface of the substrate and two sidewall portions substantially perpendicular to the upper surface of the substrate. In embodiments, the gate dielectric of region 870A includes a layer of non-native silicon oxide in addition to a layer of high-k material. The non-native silicon oxide layer may be formed using a CVD process and may be formed below or above the high-k material layer. In an exemplary embodiment, the non-native silicon oxide layer (e.g., layer 852A) is formed below the high-k material layer (e.g., layer 852B).

[0088] In one embodiment, the gate electrode consists of a metal layer, without limitation, such as a metal nitride, metal carbide, metal silide, metal aluminide, hafnium, zirconium, titanium, tantalum, aluminum, ruthenium, palladium, platinum, cobalt, nickel, or a conductive metal oxide. In a specific embodiment, the gate electrode consists of a non-work-function-setting filler material formed above a metal work-function-setting layer. In some implementations, the gate electrode may consist of a "U"-shaped structure including a lower portion substantially parallel to the surface of the substrate and two sidewall portions substantially perpendicular to the upper surface of the substrate. In another implementation, at least one of the metal layers forming the gate electrode may be a simply flat layer substantially parallel to the upper surface of the substrate and not including any sidewall portions substantially perpendicular to the upper surface of the substrate. In further implementations of the present disclosure, the gate electrode may consist of a combination of a U-shaped structure and a planar, non-U-shaped structure. For example, the gate electrode may consist of one or more U-shaped metal layers formed on one or more planar, non-U-shaped layers.

[0089] Spacers associated with the gate electrode stack may ultimately consist of a suitable material that electrically isolates the permanent gate structure from adjacent conductive contacts, such as self-aligned contacts, or contributes to such isolation. For example, in one embodiment, the spacer may consist of a dielectric material such as silicon dioxide, silicon oxynitride, silicon nitride, or carbon-doped silicon nitride, but is not limited to these materials.

[0090] The local interconnect 854, gate contact 814, the gate contact via 816 located above it, and the metal interconnect 860 located above it may be made of a conductive material. In embodiments, one or more of the contacts or vias are made of a metallic species. The metallic species may be a pure metal such as tungsten, nickel, or cobalt, or an alloy such as an intermetallic alloy or a metal-semiconductor alloy (e.g., silicide material). A common example is the use of a copper structure which may or may not include a barrier layer (such as a Ta or TaN layer) between the copper and the surrounding ILD material. As used herein, the term metal includes alloys, stacks, and other combinations of multiple metals. For example, a metal interconnect wire may include a barrier layer, a stack of different metals or alloys, etc.

[0091] In embodiments (though not shown), providing structure 800 involves forming a contact pattern that substantially perfectly matches an existing gate pattern, but eliminates the use of a lithography process with very tight alignment margins. In one such embodiment, this approach makes it possible to use inherently more selective wet etching (for example, compared to conventionally implemented dry or plasma etching) to generate contact openings. In embodiments, the contact pattern is formed by utilizing the existing gate pattern in combination with a lithography process for the contact plug. In one such embodiment, this approach eliminates the need for another critical lithography process to generate the contact pattern, as used in conventional approaches. In embodiments, the trench contact grid is formed between poly(gate) lines rather than being patterned separately. For example, in one such embodiment, the trench contact grid is formed after gate grid patterning and prior to gate grid cutting.

[0092] Furthermore, the gate structure 808 may be manufactured by a replacement gate process. In such a scheme, dummy gate material, such as polysilicon or silicon nitride pillar material, may be removed and replaced with a permanent gate electrode material. In one such embodiment, the permanent gate dielectric layer is formed in this process as well, rather than being carried over from the previous process. In embodiments, the dummy gate is removed by a dry or wet etching process. In one embodiment, the dummy gate is made of polycrystalline silicon or amorphous silicon and is removed by a dry etching process including the use of SF6. In another embodiment, the dummy gate is made of polycrystalline silicon or amorphous silicon and is removed by a wet etching process including the use of an aqueous NH4OH solution or tetramethylammonium hydroxide. In one embodiment, the dummy gate is made of silicon nitride and is removed by wet etching including an aqueous phosphoric acid solution.

[0093] In embodiments, one or more approaches described herein are substantially intended to be dummy and replacement gate processes in combination with dummy and replacement contact processes to reach structure 800. In such an embodiment, the replacement contact process is performed after the replacement gate process and allows for high-temperature annealing of at least a portion of the permanent gate stack. For example, in such specific embodiments, the annealing of at least a portion of the permanent gate structure is performed at a temperature higher than about 600 degrees Celsius, for example, after the gate dielectric layer has been formed. The annealing is performed prior to the formation of the permanent contacts.

[0094] Referring again to Figure 8A, in embodiments, the semiconductor device has a contact structure that contacts a portion of the gate electrode formed above the active region. Generally, prior to (for example, in addition to) forming a gate contact structure (such as a via) above the active portion of the gate and in the same layer as the trench contact via, one or more embodiments of the present disclosure include first using a gate-matched trench contact process. Such a process may be implemented to form trench contact structures for the manufacture of a semiconductor structure, e.g., the manufacture of an integrated circuit. In embodiments, the trench contact pattern is formed to match an existing gate pattern. Conventional approaches, on the other hand, typically involve an additional lithography process with tight alignment of the lithographic contact pattern to an existing gate pattern, often combined with selective contact etching. For example, a conventional process may include patterning of a poly(gate) grid along with separate patterning of contact features.

[0095] It should be understood that SAGE walls of varying width may be manufactured, as illustrated in Figures 8A and 8B. It should also be understood that the manufacturing of the gate end cap isolation structure may lead to seam formation within the gate end cap isolation structure. It should also be understood that a stack of dielectric layers may be used to form the SAGE wall. It should also be understood that the gate end cap isolation structure may have different compositions depending on the spacing between adjacent fins. As an example encompassing all such embodiments, Figures 9A-9C show cross-sectional views of key process steps in another self-aligned gate end cap process manufacturing scheme for a FinFET or tri-gate device according to an embodiment of the present disclosure.

[0096] Referring to Figure 9A, the group of fins 900 has a spacing of 906. The group of fins 900 is adjacent to the fins 902 with a larger spacing of 904. Sacrificial spacers 916 are formed adjacent to the upper sidewalls of each of the multiple semiconductor fins 900 and 902.

[0097] Referring to Figure 9B, a plurality of gate end cap isolation structures 926 and 950 are formed between sacrificial spacers 916. For the purposes of this description, at least some of the illustrated SAGE walls are manufactured after the fin cutting process. In embodiments, each of the plurality of gate end cap isolation structures 926 formed between the gaps 906, as shown, includes a lower dielectric portion 928 and a dielectric cap 930 on the lower dielectric portion 928. In embodiments, the plurality of gate end cap isolation structures 926 are formed by depositing and then forming a recess in a first dielectric material such as a silicon nitride layer to provide the lower dielectric portion 928. In one embodiment, the deposition process may be a conformal process that provides a seam 932 within the lower dielectric portion 928. Thus, in embodiments, each of the plurality of gate end cap isolation structures 926 includes a vertical seam 932 in the center within the gate end cap isolation structure 926. A dielectric cap material such as a metal oxide material (e.g., hafnium oxide) is then formed in the recessed region above the lower dielectric portion 928. The dielectric cap material may be planarized to form the dielectric cap 930, or it may be grown upward to directly provide the dielectric cap 930.

[0098] Referring again to Figure 9B, in an embodiment, the gate end cap isolation structure 926 is located between semiconductor fins having a spacing 906, and the gate end cap isolation structure 950 is located between semiconductor fins having a spacing 904. The gate end cap isolation structure 926 has a width narrower than the corresponding width of the gate end cap isolation structure 950. In one embodiment, the gate end cap isolation structure 926 has an overall composition different from the overall composition of the gate end cap isolation structure 950. In such an embodiment, the gate end cap isolation structure 950 further includes a third dielectric layer 956, such as a silicon oxide layer, below and within the sidewall of the lower dielectric portion 952. Furthermore, a dielectric cap 954 is located on the third dielectric layer 956. In an embodiment, as shown in Figure 9B, the sidewall of the lower dielectric portion 952 has an upper surface that is substantially coplanar with the uppermost surface of the third dielectric layer 956, and the dielectric cap 954 has a substantially planar lower surface. In another embodiment, the sidewall of the lower dielectric portion 952 has its uppermost surface below the uppermost surface of the third dielectric layer 956, and the dielectric cap 954 extends further downward above the position of the sidewall. In yet another embodiment, the sidewall of the lower dielectric portion 952 has its uppermost surface above the uppermost surface of the third dielectric layer 956, and the dielectric cap 954 extends further downward above the third dielectric layer 956.

[0099] In some embodiments, the deposition process for the third dielectric layer 956 is a conformal process that provides a vertical seam 958 within the third dielectric layer 956. However, in other embodiments, the seam 958 is formed in a narrower structure but not in a wider structure (e.g., the seam 932 described above). It should be understood that the lower dielectric portions 928 and 952 may be made of the same material, such as silicon nitride, and may be formed simultaneously with each other. It should also be understood that the dielectric caps 930 and 954 may be made of the same material, such as hafnium oxide, and may be formed simultaneously with each other. The third dielectric layer 956 of structure 950 may be formed by conformal deposition throughout the entire structure, although the lower dielectric portion 928 is excluded from structure 926 because it substantially fills the gap 906 in the first deposition process, which does not completely fill the gap 904.

[0100] Referring to Figure 9C, the sacrificial spacer 916 has been removed. In embodiments, the sacrificial spacer 916 is removed by a wet etching or dry etching process. In embodiments, the patterning of the stack layer above the fins is also removed to provide the fins 900' and 902'.

[0101] Referring again to Figure 9C, in embodiments, the gate end cap isolation structure 926 or 950 is located in a corresponding recess below the uppermost surface of the trench isolation layer. In embodiments, the gate end cap isolation structure 926 or 950 includes a lower dielectric portion and a dielectric cap on the lower dielectric portion. In embodiments, the gate end cap isolation structure 926 or 950 includes a vertical seam in the center within the second gate end cap isolation structure. In embodiments, the first gate end cap isolation structure 926 has a different overall composition from the second gate end cap isolation structure 950, for example, by including additional filler dielectric material.

[0102] In embodiments in which the gate end cap isolation structure 926 or 950 includes a lower dielectric portion and a dielectric cap on the lower dielectric portion, the gate end cap isolation structure 926 or 950 may be formed by first depositing a film and then forming a recess in a first dielectric material such as a SiN layer, SiCN layer, SiOCN layer, SiOC layer, or SiC layer, thereby providing the lower dielectric portion. In one embodiment, the first dielectric material is a silicon nitride layer. A dielectric cap material, such as a metal oxide material (e.g., hafnium oxide, hafnium-aluminum oxide, or aluminum oxide), is then formed in the recessed region above the lower dielectric portion. In one embodiment, the metal oxide material is hafnium oxide. In another embodiment, the dielectric cap material is a low-k dielectric material. The dielectric cap material may be planarized to form a dielectric cap, or it may be grown upward to directly provide the dielectric cap.

[0103] One or more embodiments described above relate to cap reduction or removal for the SAGE wall of a FinFET device. It should be understood that other embodiments may include applying such an approach to a fin consisting of alternating layers of two dissimilar semiconductor materials (e.g., Si and SiGe, or SiGe and Ge). One of the pair of dissimilar semiconductor materials is then removable in the gate region, thereby providing a nanowire / nano-ribbon channel to the gate-all-around device. In embodiments, the approach to the gate-all-around device is similar to the above-described approach to the FinFET by adding a nanowire / ribbon release step in the gate region.

[0104] In embodiments, as used throughout this specification, interlayer dielectric (ILD) materials consist of or include layers of dielectric or insulating material. Examples of preferred dielectric materials include, but are not limited to, silicon oxides (e.g., silicon dioxide (SiO2)), doped silicon oxides, silicon fluoride oxides, carbon-doped silicon oxides, various low-k dielectric materials known in the art, and combinations thereof. ILD materials may be formed by prior art methods such as chemical vapor deposition (CVD), physical vapor deposition (PVD), or by other film deposition methods.

[0105] In embodiments, as also used throughout this specification, the metal wire or interconnect wire material (and via material) consists of one or more metals or other conductive structures. A common example is the use of copper wires and structures which may or may not include a barrier layer between the copper and the surrounding ILD material. As used herein, the term metal includes alloys, stacks, and other combinations of multiple metals. For example, a metal interconnect wire may include a barrier layer (e.g., a layer containing one or more of Ta, TaN, Ti, or TiN), a stack of different metals or alloys, etc. Thus, an interconnect wire may be a single material layer or may be formed from multiple layers including a conductive liner layer and a filler layer. Any suitable deposition process, such as electroplating, chemical vapor deposition, or physical vapor deposition, may be used to form the interconnect wire. In embodiments, the interconnect wire is made of a conductive material such as Cu, Al, Ti, Zr, Hf, V, Ru, Co, Ni, Pd, Pt, W, Mo, Ag, Au, or alloys thereof, but is not limited to these. The interconnect wire may also be referred to in the art as a trace, wire, line, metal, or simply interconnect.

[0106] In embodiments, as also used throughout this specification, the hard mask material, cap layer, or plug consists of a dielectric material different from the interlayer dielectric material. In one embodiment, different hard mask, cap, or plug materials may be used in different regions to provide different growth or etching selectivity to each other and to the underlying dielectric and metal layers. In some embodiments, the hard mask layer, cap, or plug layer includes a layer of silicon nitride (e.g., silicon nitride) or a layer of silicon oxide, or both, or a combination thereof. Other suitable materials may include carbon-based materials. Depending on the specific implementation, other hard mask, cap, or plug layers known in the art may be used. The hard mask, cap, or plug layer may be formed by CVD, PVD, or other deposition methods.

[0107] In embodiments, as will also be used throughout this specification, the lithography process is performed using 193 nm immersion lithography (i193), EUV and / or EBDW lithography, etc. Positive or negative resists may be used. In one embodiment, the lithography mask is a three-layer mask consisting of a topography masking portion, an anti-reflective coating (ARC) layer, and a photoresist layer. In certain such embodiments, the topography masking portion is a carbon hard mask (CHM) layer, and the anti-reflective coating layer is a silicon ARC layer.

[0108] The embodiments disclosed herein may be used to manufacture a wide variety of different types of integrated circuits and / or microelectronic devices. Examples of such integrated circuits include, but are not limited to, processors, chipset components, graphics processors, digital signal processors, microcontrollers, and the like. In other embodiments, semiconductor memory may be manufactured. Furthermore, integrated circuits or other microelectronic devices may be used in a wide variety of electronic devices known in the art. For example, they may be used in computer systems (e.g., desktops, laptops, servers), mobile phones, personal electronic devices, and the like. Integrated circuits may be coupled with buses and other components in the system. For example, a processor may be coupled with memory, a chipset, and the like by one or more buses. Each of the processor, memory, and chipset may potentially be manufactured using the approaches disclosed herein.

[0109] Figure 10 shows a computing device 1000 according to one implementation of an embodiment of the present disclosure. The computing device 1000 houses a board 1002, which may include, but is not limited to, a number of components including a processor 1004 and at least one communication chip 1006. The processor 1004 is physically and electrically coupled to the board 1002. In some implementations, at least one communication chip 1006 is also physically and electrically coupled to the board 1002. In further implementations, the communication chip 1006 is part of the processor 1004.

[0110] Depending on the application, the computing device 1000 may include other components that are or may not be physically and electrically coupled to the board 1002. These other components include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, graphics processor, digital signal processor, cryptographic processor, chipset, antenna, display, touchscreen display, touchscreen controller, battery, audio codec, video codec, power amplifier, Global Positioning System (GPS) device, compass, accelerometer, gyroscope, speaker, camera, and mass storage devices (e.g., hard disk drive, compact disc (CD), digital versatile disc (DVD), etc.).

[0111] The communication chip 1006 enables wireless communication for data transfer to and from the computing device 1000. The term “wireless” and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communication channels, etc., that can communicate data via the use of modulated electromagnetic radiation over a non-solid medium. This term does not imply that the associated devices are entirely wireless, although in some embodiments they may be wireless. The communication chip 1006 may implement any of a number of wireless standards or protocols, including but not limited to Wi-Fi® (IEEE 802.11 family), WiMAX® (IEEE 802.16 family), IEEE 802.20, Long-Term Evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM®, GPRS, CDMA, TDMA, DECT, Bluetooth®, their derivatives, and any other wireless protocols designated as 3G, 4G, 5G and later. The computing device 1000 may include multiple communication chips 1006. For example, the first communication chip 1006 may be dedicated to short-range wireless communication such as Wi-Fi and Bluetooth®, and the second communication chip 1006 may be dedicated to long-range wireless communication such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, and Ev-DO.

[0112] The processor 1004 of the computing device 1000 includes an integrated circuit die packaged within the processor 1004. The integrated circuit die of the processor 1004 may include one or more structures, such as a self-aligned gate end cap (SAGE) structure, constructed according to an implementation of an embodiment of the present disclosure. The term “processor” may refer to any device or part of a device that processes electronic data from registers and / or memory and converts such electronic data into other electronic data that can be stored in registers and / or memory.

[0113] The communication chip 1006 also includes an integrated circuit die packaged within the communication chip 1006. The integrated circuit die of the communication chip 1006 may include one or more structures, such as a self-aligned gate end cap (SAGE) structure, constructed according to the implementation of the embodiments of this disclosure.

[0114] In further implementations, other components housed within the computing device 1000 may include an integrated circuit die comprising one or more structures, such as a self-aligned gate end cap (SAGE) structure, constructed according to an implementation of an embodiment of the present disclosure.

[0115] In various implementations, the computing device 1000 may be a laptop, netbook, notebook, ultrabook, smartphone, tablet, personal digital assistant (PDA), ultramobile PC, mobile phone, desktop computer, server, printer, scanner, monitor, set-top box, entertainment control unit, digital camera, portable music player, or digital video recorder. In further implementations, the computing device 1000 may be any other electronic device that processes data.

[0116] Figure 11 shows an interposer 1100 including one or more embodiments of the present disclosure. The interposer 1100 is an intervening substrate used to bridge a first substrate 1102 and a second substrate 1104. The first substrate 1102 may be, for example, an integrated circuit die. The second substrate 1104 may be, for example, a memory module, a computer motherboard, or another integrated circuit die. Generally, the purpose of the interposer 1100 is to spread connections to a wider pitch or to reroute connections to different connections. For example, the interposer 1100 may couple integrated circuit dies to a ball grid array (BGA) 1106 which may later be coupled to the second substrate 1104. In some embodiments, the first and second substrates 1102 / 1104 are mounted on opposite sides of the interposer 1100. In other embodiments, the first and second substrates 1102 / 1104 are mounted on the same side of the interposer 1100. In further embodiments, three or more substrates are interconnected by the interposer 1100.

[0117] The interposer 1100 may be formed from an epoxy resin, a glass fiber reinforced epoxy resin, a ceramic material, or a polymer material such as polyimide. In further implementation, the interposer 1100 may be formed from alternatingly stacked rigid or flexible materials, which may include the same materials as those used for semiconductor substrates, such as silicon, germanium, and other Group III-V and Group IV materials.

[0118] The interposer 1100 may include a metal interconnect 1108 and vias 1110, including, but not limited to, through-silicon vias (TSVs) 1112. The interposer 1100 may further include embedded devices 1114, which include both passive and active devices. Such devices include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, and electrostatic discharge (ESD) devices. More complex devices such as radio frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and MEMS devices may also be formed on the interposer 1100. According to embodiments of this disclosure, the apparatus or processes disclosed herein may be used in the manufacture of the interposer 1100 or the manufacture of components included in the interposer 1100.

[0119] Accordingly, embodiments of the present disclosure include a self-aligned gate end cap (SAGE) architecture with reduced or removed caps, and a method for manufacturing the self-aligned gate end cap (SAGE) architecture with reduced or removed caps.

[0120] The above description of the exemplary implementations of the embodiments of the Disclosure, including those described in the abstract, is not intended to be exhaustive or to limit the disclosure to the exact form disclosed. Specific implementations and examples of the Disclosure are described herein for illustrative purposes, but various equivalent variations are possible within the scope of the Disclosure, as those skilled in the art will understand.

[0121] These modifications may be added to the disclosure in light of the detailed description above. The terms used in the following claims should not be construed as limiting the disclosure to the specific implementations disclosed herein and in the claims. Rather, the scope of the disclosure should be determined solely by the following claims, which should be interpreted in accordance with established principles of claim interpretation.

[0122] Exemplary Embodiment 1: The integrated circuit structure includes a first gate electrode above a first semiconductor fin. A second gate electrode is located above a second semiconductor fin. A gate end cap isolation structure is located between the first and second gate electrodes, and the gate end cap isolation structure has a high-k dielectric cap layer on a low-k dielectric wall. A local interconnect is located on the first gate electrode, on the high-k dielectric cap layer, and on the second gate electrode, and the local interconnect has its bottom surface above the top surface of the high-k dielectric cap layer.

[0123] Exemplary Embodiment 2: The integrated circuit structure according to Exemplary Embodiment 1, wherein the first gate electrode and the second gate electrode each have an upper surface that is coplanar with the upper surface of the high-k dielectric cap layer of the gate end cap isolation structure.

[0124] Exemplary Embodiment 3: The local interconnect is an integrated circuit structure according to Exemplary Embodiment 1 or 2, electrically connecting the first gate electrode and the second gate electrode.

[0125] Exemplary Embodiment 4: The gate end cap isolation structure includes a vertical seam in the center within the low-k dielectric wall, as described in Exemplary Embodiments 1, 2, or 3.

[0126] Exemplary Embodiment 5: The integrated circuit structure includes a first trench contact above a first epitaxial structure above a first semiconductor fin. A second trench contact is located above a second epitaxial structure above a second semiconductor fin. A gate end cap isolation structure is located between the first and second trench contacts, and the gate end cap isolation structure has a high-k dielectric cap layer on a low-k dielectric wall. A local interconnect is located on the first trench contact, on the high-k dielectric cap layer, and on the second trench contact, and the local interconnect has its lowest surface above the uppermost surface of the high-k dielectric cap layer.

[0127] Exemplary Embodiment 6: The integrated circuit structure according to Exemplary Embodiment 5, wherein the first trench contact and the second trench contact each have an upper surface that is coplanar with the upper surface of the high-k dielectric cap layer of the gate end cap isolation structure.

[0128] Exemplary Embodiment 7: The local interconnect electrically connects the first trench contact and the second trench contact in the integrated circuit structure according to Exemplary Embodiment 5 or 6.

[0129] Exemplary Embodiment 8: The gate end cap isolation structure includes a vertical seam in the center within the low-k dielectric wall, as described in Exemplary Embodiments 5, 6, or 7.

[0130] Exemplary Embodiment 9: The computing device includes a board and components coupled to the board. The components include an integrated circuit structure. The integrated circuit structure includes a first gate electrode above a first semiconductor fin. A second gate electrode is above a second semiconductor fin. A gate end cap isolation structure is located between the first and second gate electrodes, and the gate end cap isolation structure has a high-k dielectric cap layer on a low-k dielectric wall. A local interconnect is located on the first gate electrode, on the high-k dielectric cap layer, and on the second gate electrode, and the local interconnect has its bottom surface above the top surface of the high-k dielectric cap layer.

[0131] Exemplary Embodiment 10: The computing device according to Exemplary Embodiment 9, further comprising memory coupled to a board.

[0132] Exemplary Embodiment 11: The computing device according to Exemplary Embodiment 9 or 10, further comprising a communication chip coupled to a board.

[0133] Exemplary Embodiment 12: The computing device according to Exemplary Embodiment 9, 10, or 11, further comprising a camera coupled to a board.

[0134] Exemplary Embodiment 13: A computing device according to Exemplary Embodiments 9, 10, 11, or 12, wherein the component is a packaged integrated circuit die.

[0135] Exemplary Embodiment 14: The computing device is selected from the group consisting of mobile phones, laptops, desktop computers, servers, and set-top boxes, as described in Exemplary Embodiments 9, 10, 11, 12, or 13.

[0136] Exemplary Embodiment 15: The computing device includes a board and components coupled to the board. The components include an integrated circuit structure. The integrated circuit structure includes a first trench contact above a first epitaxial structure above a first semiconductor fin. A second trench contact is located above a second epitaxial structure above a second semiconductor fin. A gate end cap isolation structure is located between the first and second trench contacts, and the gate end cap isolation structure has a high-k dielectric cap layer on a low-k dielectric wall. A local interconnect is located on the first trench contact, on the high-k dielectric cap layer, and on the second trench contact, and the local interconnect has its bottom surface above the top surface of the high-k dielectric cap layer.

[0137] Exemplary Embodiment 16: The computing device according to Exemplary Embodiment 15, further comprising memory coupled to a board.

[0138] Exemplary Embodiment 17: The computing device according to Exemplary Embodiment 15 or 16, further comprising a communication chip coupled to a board.

[0139] Exemplary Embodiment 18: The computing device according to Exemplary Embodiment 15, 16, or 17, further comprising a camera coupled to a board.

[0140] Exemplary Embodiment 19: A computing device according to Exemplary Embodiment 15, 16, 17, or 18, wherein the component is a packaged integrated circuit die.

[0141] Exemplary Embodiment 20: The computing device is selected from the group consisting of mobile phones, laptops, desktop computers, servers, and set-top boxes, as described in Exemplary Embodiments 15, 16, 17, 18, or 19. Other possible embodiments [Item 1] The first gate electrode above the first semiconductor fin, The second gate electrode above the second semiconductor fin, A gate end cap isolation structure between the first gate electrode and the second gate electrode, comprising a gate end cap isolation structure having a high-k dielectric cap layer on a low-k dielectric wall, A local interconnect on the first gate electrode, the high-k dielectric cap layer, and the second gate electrode, wherein the local interconnect has its lowest surface above the uppermost surface of the high-k dielectric cap layer. An integrated circuit structure comprising the features described above. [Item 2] The integrated circuit structure according to item 1, wherein the first gate electrode and the second gate electrode each have an upper surface that is coplanar with the uppermost surface of the high-k dielectric cap layer of the gate end cap isolation structure. [Item 3] The local interconnect electrically connects the first gate electrode and the second gate electrode, as described in item 1. [Item 4] The gate end cap separation structure is an integrated circuit structure according to item 1, having a vertical seam in the center within the low-k dielectric wall. [Item 5] A first trench contact above the first epitaxial structure above the first semiconductor fin, The second trench contact above the second epitaxial structure above the second semiconductor fin, A gate end cap isolation structure between the first trench contact and the second trench contact, comprising a gate end cap isolation structure having a high-k dielectric cap layer on a low-k dielectric wall, A local interconnect on the first trench contact, on the high-k dielectric cap layer, and on the second trench contact, wherein the local interconnect has its lowest surface above the uppermost surface of the high-k dielectric cap layer. An integrated circuit structure comprising the features described above. [Item 6] The integrated circuit structure according to item 5, wherein the first trench contact and the second trench contact each have a coplanar upper surface with the uppermost surface of the high-k dielectric cap layer of the gate end cap separation structure. [Item 7] The local interconnect is an integrated circuit structure according to item 5, electrically connecting the first trench contact and the second trench contact. [Item 8] The gate end cap separation structure is an integrated circuit structure according to item 5, having a vertical seam in the center within the low-k dielectric wall. [Item 9] Board and, A component coupled to the board, the component including an integrated circuit structure A computing device equipped with, The aforementioned integrated circuit structure is The first gate electrode above the first semiconductor fin, The second gate electrode above the second semiconductor fin, A gate end cap isolation structure between the first gate electrode and the second gate electrode, comprising a gate end cap isolation structure having a high-k dielectric cap layer on a low-k dielectric wall, A local interconnect on the first gate electrode, the high-k dielectric cap layer, and the second gate electrode, wherein the local interconnect has its lowest surface above the uppermost surface of the high-k dielectric cap layer. A computing device having the following features. [Item 10] The computing device according to item 9, further comprising memory coupled to the aforementioned board. [Item 11] The computing device according to item 9, further comprising a communication chip coupled to the aforementioned board. [Item 12] The computing device according to item 9, further comprising a camera coupled to the aforementioned board. [Item 13] The aforementioned component is a packaged integrated circuit die, as described in item 9 of the computing device. [Item 14] The computing device is selected from the group consisting of mobile phones, laptops, desktop computers, servers, and set-top boxes, as described in item 9. [Item 15] Board and, A component coupled to the board, the component including an integrated circuit structure A computing device equipped with, The aforementioned integrated circuit structure is A first trench contact above the first epitaxial structure above the first semiconductor fin, The second trench contact above the second epitaxial structure above the second semiconductor fin, A gate end cap isolation structure between the first trench contact and the second trench contact, comprising a gate end cap isolation structure having a high-k dielectric cap layer on a low-k dielectric wall, A local interconnect on the first trench contact, on the high-k dielectric cap layer, and on the second trench contact, wherein the local interconnect has its lowest surface above the uppermost surface of the high-k dielectric cap layer. A computing device having the following features. [Item 16] The computing device according to item 15, further comprising memory coupled to the aforementioned board. [Item 17] The computing device according to item 15, further comprising a communication chip coupled to the aforementioned board. [Item 18] The computing device according to item 15, further comprising a camera coupled to the aforementioned board. [Item 19] The aforementioned component is a packaged integrated circuit die, as described in item 15 of the computing device. [Item 20] The computing device is selected from the group consisting of mobile phones, laptops, desktop computers, servers, and set-top boxes, as described in item 15.

Claims

1. The first fin and, A first epitaxial source or drain structure located above the first fin, A first conductive contact located above the first epitaxial source or drain structure, A second fin that is laterally separated from the first fin, A second epitaxial source or drain structure located above the second fin, A second conductive contact located above the second epitaxial source or drain structure, A first gate end cap wall that is laterally separated from the side of the first fin opposite to the second fin, A second gate end cap wall that is laterally separated from the side of the second fin opposite to the first fin, The third gate end cap wall between the first fin and the second fin, A trench separation structure adjacent to the sides of the lower part of the first fin, the lower part of the second fin, the lower part of the first gate end cap wall, the lower part of the second gate end cap wall, and the lower part of the third gate end cap wall, A local conductive interconnect is located vertically above the third gate end cap wall and connects the first conductive contact and the second conductive contact, Equipped with, The first conductive contact and the second conductive contact are an integrated circuit structure spaced laterally apart from the third gate end cap wall.

2. The integrated circuit structure according to claim 1, wherein the local conductive interconnect is separated from and distinct from the first conductive contact and the second conductive contact.

3. The integrated circuit structure according to claim 1 or 2, wherein the first conductive contact is separate from and distinct from the second conductive contact.

4. The integrated circuit structure according to any one of claims 1 to 3, wherein the local conductive interconnect is separated vertically from the third gate end cap wall.

5. The integrated circuit structure according to any one of claims 1 to 4, wherein the third gate end cap wall has an uppermost surface above the uppermost surface of the first epitaxial source or drain structure and the second epitaxial source or drain structure.

6. The integrated circuit structure according to any one of claims 1 to 5, wherein the local conductive interconnect has a bottom surface above the top surface of the first conductive contact and the top surface of the second conductive contact.

7. The integrated circuit structure according to any one of claims 1 to 6, wherein the local conductive interconnect does not extend vertically upward from the first gate end cap wall and does not extend vertically upward from the second gate end cap wall.

8. The third gate end cap wall has a dielectric cap layer, The integrated circuit structure according to any one of claims 1 to 7, wherein the dielectric cap layer is provided below the local conductive interconnect.

9. A first fin having the longest dimension along the first direction, A first source or drain structure located above the first fin and extending laterally beyond the top of the first fin along a second direction perpendicular to the first direction, A first conductive material region located above the first source or drain structure, A second fin having the longest dimension along the first direction and moving laterally away from the first fin along the second direction, A second source or drain structure located above the second fin and extending laterally along the second direction, beyond the top of the second fin, A second conductive material region located above the second source or drain structure, A first dielectric wall having the longest dimension along the first direction and laterally separating from the side surface of the first fin opposite to the second fin along the second direction, A second dielectric wall having the longest dimension along the first direction and laterally separating from the side surface of the second fin opposite to the first fin along the second direction, Having the longest dimension along the first direction, and along the second direction, a third dielectric wall between the first fin and the second fin, A trench separation structure adjacent laterally to the lower part of the first fin, the lower part of the second fin, the lower part of the first dielectric wall, the lower part of the second dielectric wall, and the lower part of the third dielectric wall, A conductive interconnect located vertically above the third dielectric wall and coupled to the first conductive material region and the second conductive material region, A first dielectric is provided between the first dielectric wall and the third dielectric wall, A second dielectric is provided between the second dielectric wall and the third dielectric wall, Equipped with, The first conductive material region connects the first source or drain structure and the conductive interconnect through an opening formed in the first dielectric. The second conductive material region connects the second source or drain structure and the conductive interconnect through an opening formed in the second dielectric. The first conductive material region and the second conductive material region are spaced laterally apart from the third dielectric wall in an integrated circuit structure.

10. A first fin having the longest dimension along the first direction, A first source or drain structure located above the first fin and extending laterally beyond the top of the first fin along a second direction perpendicular to the first direction, A first conductive material region located above the first source or drain structure, A second fin having the longest dimension along the first direction and moving laterally away from the first fin along the second direction, A second source or drain structure located above the second fin and extending laterally along the second direction, beyond the top of the second fin, A second conductive material region located above the second source or drain structure, A first dielectric wall having the longest dimension along the first direction and laterally separating from the side surface of the first fin opposite to the second fin along the second direction, A second dielectric wall having the longest dimension along the first direction and laterally separating from the side surface of the second fin opposite to the first fin along the second direction, Having the longest dimension along the first direction, and along the second direction, a third dielectric wall between the first fin and the second fin, A trench separation structure adjacent laterally to the lower part of the first fin, the lower part of the second fin, the lower part of the first dielectric wall, the lower part of the second dielectric wall, and the lower part of the third dielectric wall, A conductive interconnect located vertically above the third dielectric wall and coupled to the first conductive material region and the second conductive material region, Equipped with, The conductive interconnect has a lower surface above the uppermost surface of the first conductive material region and the uppermost surface of the second conductive material region. The first conductive material region and the second conductive material region are spaced laterally apart from the third dielectric wall in an integrated circuit structure.

11. A first fin having the longest dimension along the first direction, A first source or drain structure located above the first fin and extending laterally beyond the top of the first fin along a second direction perpendicular to the first direction, A first conductive material region located above the first source or drain structure, A second fin having the longest dimension along the first direction and moving laterally away from the first fin along the second direction, A second source or drain structure located above the second fin and extending laterally along the second direction, beyond the top of the second fin, A second conductive material region located above the second source or drain structure, A first dielectric wall having the longest dimension along the first direction and laterally separating from the side surface of the first fin opposite to the second fin along the second direction, A second dielectric wall having the longest dimension along the first direction and laterally separating from the side surface of the second fin opposite to the first fin along the second direction, Having the longest dimension along the first direction, and along the second direction, a third dielectric wall between the first fin and the second fin, A trench separation structure adjacent laterally to the lower part of the first fin, the lower part of the second fin, the lower part of the first dielectric wall, the lower part of the second dielectric wall, and the lower part of the third dielectric wall, A conductive interconnect located vertically above the third dielectric wall and coupled to the first conductive material region and the second conductive material region, Equipped with, The conductive interconnect does not extend vertically upward of the first dielectric wall, nor does it extend vertically upward of the second dielectric wall. The first conductive material region and the second conductive material region are spaced laterally apart from the third dielectric wall in an integrated circuit structure.

12. The integrated circuit structure according to any one of claims 9 to 11, wherein the first conductive material region is separate from and distinct from the second conductive material region.

13. The integrated circuit structure according to any one of claims 9 to 12, wherein the conductive interconnect is separated vertically from the third dielectric wall.

14. The integrated circuit structure according to any one of claims 9 to 13, wherein the third dielectric wall has an uppermost surface above the uppermost surface of the first source or drain structure and the second source or drain structure.

15. The third dielectric wall has a dielectric cap layer, The integrated circuit structure according to any one of claims 9 to 14, wherein the dielectric cap layer is provided below the conductive interconnect.

16. The first nanowire and, A first epitaxial source or drain structure located above the first nanowire, A first conductive contact located above the first epitaxial source or drain structure, A second nanowire separated laterally from the first nanowire, A second epitaxial source or drain structure located above the second nanowire, A second conductive contact located above the second epitaxial source or drain structure, A first gate end cap wall that is laterally separated from the side of the first nanowire opposite to the second nanowire, A second gate end cap wall that is laterally separated from the side of the second nanowire opposite to the first nanowire, A third gate end cap wall between the first nanowire and the second nanowire, A trench separation structure adjacent to the lower part of the first gate end cap wall, the lower part of the second gate end cap wall, and the lower part of the third gate end cap wall, A local conductive interconnect is located vertically above the third gate end cap wall and connects the first conductive contact and the second conductive contact, Equipped with, The first conductive contact and the second conductive contact are an integrated circuit structure spaced laterally apart from the third gate end cap wall.

17. The integrated circuit structure according to claim 16, wherein the local conductive interconnect is separated from and distinct from the first conductive contact and the second conductive contact.

18. The integrated circuit structure according to claim 16 or 17, wherein the first conductive contact is separate from and distinct from the second conductive contact.

19. The integrated circuit structure according to any one of claims 16 to 18, wherein the local conductive interconnect is separated vertically from the third gate end cap wall.

20. The integrated circuit structure according to any one of claims 16 to 19, wherein the third gate end cap wall has an uppermost surface above the uppermost surface of the first epitaxial source or drain structure and the second epitaxial source or drain structure.

21. The integrated circuit structure according to any one of claims 16 to 20, wherein the local conductive interconnect has a bottom surface above the top surface of the first conductive contact and the top surface of the second conductive contact.

22. The integrated circuit structure according to any one of claims 16 to 21, wherein the local conductive interconnect does not extend vertically upward from the first gate end cap wall and does not extend vertically upward from the second gate end cap wall.

23. The third gate end cap wall has a dielectric cap layer, The integrated circuit structure according to any one of claims 16 to 22, wherein the dielectric cap layer is provided below the local conductive interconnect.

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