Degradation detection device, power conversion device, and degradation detection method

Abstract

To detect deterioration of a bonding material under a semiconductor chip with accuracy.SOLUTION: A deterioration detection device comprises: a conductor layer; a semiconductor chip whose rear face is bonded with a front face of the conductor layer with a bonding material; a wire bonded with a front face of the semiconductor chip; a first terminal electrically connected with the rear face of the semiconductor chip via the bonding material and the conductor layer; a second terminal electrically connected with the front face of the semiconductor chip via the wire; a third terminal electrically connected with the bonding material in the vicinity of the semiconductor chip; and a monitoring part that monitors an electric resistance between the first and third terminals, and when the electric resistance becomes larger than a predetermined value, outputs a predetermined signal.SELECTED DRAWING: Figure 5

Description

Technical Field

[0001] The present disclosure relates to a deterioration detection device, a power conversion device, and a deterioration detection method.

Background Art

[0002] Conventionally, a technique is known in which the voltage Vce between the collector and emitter is measured when a constant collector current flows through a semiconductor element, and when the difference between the measured value of the voltage Vce and the initial value exceeds a determination value, it is determined that the life of the semiconductor element is approaching (see, for example, Patent Document 1).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] However, the measured value of the voltage Vce described above not only increases due to deterioration of the bonding material (for example, solder, etc.) under the semiconductor chip, but also increases due to deterioration of the joint between the semiconductor chip and the bonding wire. Therefore, in the above method of monitoring the measured value of the voltage Vce, it may not be possible to accurately detect the deterioration of the bonding material under the semiconductor chip.

[0005] The present disclosure provides a deterioration detection device, a power conversion device, and a deterioration detection method capable of accurately detecting the deterioration of the bonding material under a semiconductor chip.

Means for Solving the Problems

[0006] In one aspect of the present disclosure, a conductor layer, a semiconductor chip having its back surface joined to the surface of the conductor layer by a bonding material, a wire joined to the surface of the semiconductor chip, A first terminal electrically connected to the back surface of the semiconductor chip via the bonding material and the conductor layer, A second terminal electrically connected to the surface of the semiconductor chip via the wire, A third terminal electrically connected to the bonding material near the semiconductor chip, A degradation detection device is provided, comprising: a monitoring unit that monitors the electrical resistance between the first terminal and the third terminal and outputs a predetermined signal when the electrical resistance exceeds a predetermined value.

[0007] In another aspect of this disclosure, Multiple semiconductor devices for power conversion, The system comprises a control unit that controls the switching of the plurality of semiconductor devices, Each of the aforementioned plurality of semiconductor devices is: Conductor layer, A semiconductor chip whose back surface is bonded to the surface of the conductor layer by a bonding material, A wire bonded to the surface of the semiconductor chip, A first terminal electrically connected to the back surface of the semiconductor chip via the bonding material and the conductor layer, A second terminal electrically connected to the surface of the semiconductor chip via the wire, It has a third terminal electrically connected to the bonding material near the semiconductor chip, The power conversion device is provided, which includes a control unit that monitors the electrical resistance between the first terminal and the third terminal, and outputs a predetermined signal when the electrical resistance exceeds a predetermined value.

[0008] In another aspect of this disclosure, A method for determining the degradation of a semiconductor device comprising: a conductor layer; a semiconductor chip whose back surface is bonded to the surface of the conductor layer by a bonding material; a wire bonded to the surface of the semiconductor chip; a first terminal electrically connected to the back surface of the semiconductor chip via the bonding material and the conductor layer; a second terminal electrically connected to the surface of the semiconductor chip via the wire; and a third terminal electrically connected to the bonding material near the semiconductor chip, wherein A deterioration detection method is provided that monitors the electrical resistance between the first terminal and the third terminal and outputs a predetermined signal when the electrical resistance exceeds a predetermined value.

Advantages of the Invention

[0009] According to the present disclosure, deterioration of the bonding material under the semiconductor chip can be accurately detected.

Brief Description of the Drawings

[0010] [Figure 1] It is a cross-sectional view of a part of a power semiconductor module at the time of deterioration of the wire bonding part. [Figure 2] It is a cross-sectional view of a part of a power semiconductor module at the time of deterioration of the bonding material under the semiconductor chip. [Figure 3] It is a diagram showing examples of semiconductor chips (IGBT chip and diode chip). [Figure 4] It is a diagram illustrating the relationship between the voltage Vce_on between the main terminals when the power semiconductor module is in the conducting state and the operating time of the power semiconductor module. [Figure 5] It is a configuration diagram showing an example of the deterioration detection device according to the present embodiment. [Figure 6] It is a cross-sectional view of a part of the power semiconductor module according to the present embodiment. [Figure 7] It is an equivalent circuit diagram of the power semiconductor module according to the present embodiment. [Figure 8] It is a configuration diagram showing an example of the monitoring unit. [Figure 9] It is a diagram showing the overall configuration of the power conversion device according to the present embodiment. [Figure 10] It is a diagram illustrating waveforms of each part accompanying the detection operation of the voltage Vcc_1 in the on state. [Figure 11] It is a timing chart for explaining a method of detecting deterioration of the bonding material by the electrical resistance R1.

Embodiments for Carrying Out the Invention

[0011] Hereinafter, embodiments will be described.

[0012] In recent years, power conversion devices have been extended to applications that require high reliability (such as power systems or moving bodies such as trains or automobiles), and accordingly, the requirement for high reliability of power conversion devices has been increasing. In response to this requirement, expectations for realizing predictive maintenance that predicts failures and takes preventive measures in advance have been increasing.

[0013] One of the main failure factors of a power semiconductor module is a power semiconductor module. The main failure of the power semiconductor module is caused by the thermal stress stress repeatedly generated by current conduction or switching operation deteriorating the bonding wire and solder. As the deterioration of the bonding wire and solder progresses, the conduction resistance between the main terminals when the power semiconductor module is in the on state (conducting state) increases, so the voltage Von between the main terminals when the power semiconductor module is in the conducting state rises. Therefore, by detecting the increase in the voltage Von, the deterioration of the power semiconductor module can be detected.

[0014] FIG. 1 is a cross-sectional view of a part of a power semiconductor module when the wire joint is deteriorated. FIG. 2 is a cross-sectional view of a part of a power semiconductor module when the bonding material under the semiconductor chip is deteriorated. In FIGS. 1 and 2, the power semiconductor module is a semiconductor device including a semiconductor chip 11, a wire 16 for connecting the semiconductor chip 11 to the outside, and a bonding material 8 for bonding the semiconductor chip 11 to a substrate (not shown).

[0015] The wire 16 is a conductor whose one end is joined to the surface 12 of the semiconductor chip 11. The wire 16 is, for example, a bonding wire such as an aluminum wire. The bonding material 8 is a conductor that contacts the back surface 13 of the semiconductor chip 11. The bonding material 8 is typically solder, but may be other bonding materials such as an adhesive. The thermal stress generated by the repeated conduction / blocking operation of the semiconductor chip 11 deteriorates the joint portion of the wire 16 with the semiconductor chip 11 and the bonding material 8 such as solder.

[0016] As the wire 16 deteriorates, for example, cracks 9 may form at the joint between the wire 16 and the surface 12, increasing the resistance of the joint. On the other hand, as the bonding material 8 deteriorates, for example, cracks 9 may form in the bonding material 8, increasing the resistance of the bonding material 8. Therefore, as the wire 16 and bonding material 8 deteriorate, the voltage Von between the main terminals in the conduction state of the power semiconductor module (see Figure 3; if the power semiconductor module is an IGBT, the voltage Vce_on between the collector and emitter in the conduction state) gradually increases (see Figure 4). By monitoring this increase in voltage Von (Vce_on), it is possible to detect signs of failure in the power semiconductor module.

[0017] However, as mentioned above, the increase in voltage Von(Vce_on) between the main terminals when the power semiconductor module is conductive includes both the increase due to deterioration of the wire 16 junction and the increase due to deterioration of the bonding material 8. Therefore, even if the increase in voltage Von(Vce_on) is monitored, it may not be possible to accurately detect the deterioration of the bonding material 8 under the semiconductor chip 11.

[0018] The degradation detection device and power converter according to this embodiment have a configuration that accurately detects the degradation of the bonding material under the semiconductor chip. The configuration of the degradation detection device and power converter according to this embodiment, and the degradation detection method performed by the degradation detection device or power converter according to this embodiment will be described below.

[0019] Figure 5 is a configuration diagram showing an example of a degradation detection device according to this embodiment. The degradation detection device 200 shown in Figure 5 is a device for detecting the degradation of a power semiconductor module 100. The degradation detection device 200 includes a power semiconductor module 100 and a monitoring unit 40.

[0020] The power semiconductor module 100 is an example of a semiconductor device. Figure 5 shows the power semiconductor module 100 in a plan view. The power semiconductor module 100 comprises an insulating substrate 1, a semiconductor chip 11, a collector terminal C, an emitter terminal E, a gate terminal G, an auxiliary emitter terminal EA, an auxiliary collector terminal CA, and wires 16, 17, 18, and 19.

[0021] The insulating substrate 1 is a substrate on which the semiconductor chip 11 is mounted, and can be, for example, a DCB (Direct Copper Bonding) substrate or an AMB (Active Metal Blazing) substrate. The insulating substrate 1 is fixed to a base substrate (not shown) formed on the bottom surface of the housing of the power semiconductor module 100, for example, via a bonding material (not shown) such as solder.

[0022] The insulating substrate 1 includes conductive layers 2 to 6 formed on its surface. The conductive layers 2 to 6 are made of conductive metals such as copper and aluminum and are provided on the upper surface of the insulating layer of the insulating substrate 1. The conductive layers 2 to 6 may be conductive plates or conductive foils.

[0023] Conductor layer 2 is a rectangular planar conductor located in the area on the back side of the semiconductor chip 11 in a plan view of the semiconductor chip 11. Conductor layer 3 is a rectangular planar conductor located in the area in the first direction (downward in the drawing) relative to the semiconductor chip 11 in a plan view of the semiconductor chip 11, and is located away from conductor layer 2 in the first direction. Conductor layers 4 and 5 are rectangular planar conductors located in the area in the second direction (opposite to the first direction; upward in the drawing) relative to the semiconductor chip 11 in a plan view of the semiconductor chip 11, and are located away from conductor layer 2 in the second direction. Conductor layer 6 is a rectangular planar conductor located in the area in the third direction (perpendicular to the first and second directions; leftward in the drawing) relative to the semiconductor chip 11 in a plan view of the semiconductor chip 11, and is located away from conductor layer 2 in the third direction. Note that the size, shape, and arrangement of conductor layers 2 to 6 are not limited to the illustrated form.

[0024] The semiconductor chip 11 is a semiconductor element incorporated into the power semiconductor module 100, and is, for example, a semiconductor switching element having electrodes on both its front and back surfaces. The semiconductor chip 11 may be either a Si semiconductor element or a SiC semiconductor element. Figure 5 illustrates the case where the semiconductor chip 11 is an insulated gate bipolar transistor (IGBT) chip.

[0025] Figure 6 is a cross-sectional view of a part of the power semiconductor module according to this embodiment. The semiconductor chip 11 has a surface surface 12 on which an emitter electrode 11e and a gate electrode 11g (see Figure 5) are arranged, and a back surface surface 13 on which a collector electrode 11c is arranged. The collector electrode 11c is an example of a first main electrode of the semiconductor chip 11, and in this example, it is formed on the back surface surface 13. The emitter electrode 11e is an example of a second main electrode of the semiconductor chip 11, and is formed on the surface surface 12. The gate electrode 11g is an example of a control electrode of the semiconductor chip 11, and is formed on the surface surface 12. The semiconductor chip 11 is fixed on the insulating substrate 1 (see Figure 5) on the back surface surface 13 by joining the collector electrode 11c to the conductor layer 2 with a bonding material 8 such as solder.

[0026] In Figure 5, the collector terminal C, emitter terminal E, gate terminal G, auxiliary emitter terminal EA, and auxiliary collector terminal CA are external terminals for connecting the power semiconductor module 100 to the outside. Each of these external terminals is formed into a cylindrical or flat shape using a conductive metal such as copper or aluminum.

[0027] The collector terminal C is a main terminal electrically connected to the collector electrode 11c (see Figure 6) of the semiconductor chip 11 via the conductor layer 2 and the bonding material 8. The emitter terminal E is a main terminal electrically connected to the emitter electrode 11e of the semiconductor chip 11 via the conductor layer 3 and the wire 16. The gate terminal G is a control terminal electrically connected to the gate electrode 11g of the semiconductor chip 11 via the conductor layer 4 and the wire 17. The auxiliary emitter terminal EA is an auxiliary terminal electrically connected to the emitter electrode 11e of the semiconductor chip 11 via the conductor layer 5 and the wire 18. The auxiliary collector terminal CA is an auxiliary terminal electrically connected to the bonding material 8 near the semiconductor chip 11 via the conductor layer 6 and the wire 19.

[0028] Wires 16-19 are linear members formed with a diameter of 300-500 μm using conductive metals such as copper and aluminum, or conductive alloys such as iron-aluminum alloys. Wire 16 is one or more (four in this example) wires that connect the emitter electrode 11e, which is the surface electrode of the semiconductor chip 11, to the conductor layer 3. Wire 17 is one or more (one in this example) wires that connect the gate electrode 11g, which is the surface electrode of the semiconductor chip 11, to the conductor layer 4. Wire 18 is one or more (one in this example) wires that connect the emitter electrode 11e, which is the surface electrode of the semiconductor chip 11, to the conductor layer 5. Wire 19 is one or more (one in this example) wires that connect the bonding material 8 to the conductor layer 6. Wire 19 has one end connected to the bonding material 8 near the semiconductor chip 11 and the other end connected to the conductor layer 6.

[0029] In this example, one end of the wire 19 is electrically connected to a conductor plate 7 that is electrically connected to the upper surface of the bonding material 8. The conductor plate 7 is located near the semiconductor chip 11 (in this example, near the corner of the semiconductor chip 11). The conductor plate 7 may also be located near the edge of the semiconductor chip 11. The conductor plate 7 functions as an electrode to which one end of the wire 19 is connected. The conductor plate 7 is a plate-shaped or foil-shaped conductor formed from a conductive metal such as copper or aluminum. The conductor plate 7 is connected to the auxiliary collector terminal CA via at least one wire 19. The location where the conductor plate 7 is installed is not limited to one; there may be multiple locations.

[0030] In Figure 6, the semiconductor chip 11 has its back surface 13 bonded to the surface of the conductor layer 2 by a bonding material 8. One end of the wire 16 is bonded to the emitter electrode 11e on the surface 12 of the semiconductor chip 11. The collector terminal C is an example of a first terminal electrically connected to the back surface 13 of the semiconductor chip 11 via the bonding material 8 and the conductor layer 2. The emitter terminal E is an example of a second terminal electrically connected to the surface 12 of the semiconductor chip 11 via the wire 16. The auxiliary collector terminal CA is an example of a third terminal electrically connected to the bonding material 8 near the semiconductor chip 11.

[0031] When the semiconductor chip 11 becomes conductive between the collector electrode 11c and the emitter electrode 11e, a current Ic flows in the following order: collector terminal C, conductor layer 2, bonding material 8, semiconductor chip 11, wire 16, and emitter terminal E. Repeated switching of the current Ic on and off accelerates the deterioration of the bonding material 8.

[0032] As the bonding material 8 deteriorates, cracks 9 (particularly cracks 9 approximately parallel to the back surface 13 of the semiconductor chip 11) may form in the bonding material 8. This makes it difficult for the current Ic flowing through the bonding material 8 to flow in the longitudinal direction where the conductor layer 2 and the collector electrode 11c face each other. As a result, the electrical resistance R1 (see Figure 7) between the collector terminal C and the auxiliary collector terminal CA increases. In Figure 6, the conductor layer 2 and the collector terminal C are less prone to deterioration than the bonding material 8, so the increase in the electrical resistance of the conductor layer 2 and the collector terminal C due to deterioration is extremely small. Therefore, the increase in electrical resistance R1 is almost entirely due to the deterioration of the bonding material 8.

[0033] Focusing on this point, the monitoring unit 40 (see Figure 5) monitors the electrical resistance R1 between the collector terminal C and the auxiliary collector terminal CA, and outputs a predetermined signal when the electrical resistance R1 between both the collector terminal C and the emitter terminal E in the ON state exceeds a predetermined value. The output of the predetermined signal indicates the detection of deterioration of the bonding material 8. In this way, the deterioration detection device 200 is equipped with a monitoring unit 40 that outputs a predetermined signal when the electrical resistance R1 of the monitored object exceeds a predetermined value, so that deterioration of the bonding material 8 under the semiconductor chip 11 can be detected with high accuracy.

[0034] The monitoring unit 40 monitors, for example, the voltage Vcc between the collector terminal C and the auxiliary collector terminal CA, detects the on-voltage Vcc_on which is the voltage Vcc between the two terminals in the on state, and measures the on-current Ic_on which is the current Ic that flows between the two terminals in the on state. The monitoring unit 40 may also monitor the value obtained by dividing the detected on-voltage Vcc_on by the measured value of the on-current Ic_on as the electrical resistance R1. The monitoring unit 40 can easily derive the electrical resistance R1 by performing such a division.

[0035] Figure 8 is a configuration diagram showing an example of a monitoring unit. The monitoring unit 40 shown in Figure 8 has the function of outputting a predetermined signal representing the detection of deterioration of the bonding material 8 using the electrical resistance R1 obtained by dividing the detected on-voltage Vcc_on value by the measured on-current Ic_on value. The function shown in Figure 8 may be realized solely by hardware resources such as circuits, or it may be realized through the cooperation of hardware resources and software.

[0036] The monitoring unit 40 may be, for example, a control device or a part thereof that includes a processor such as a CPU (Central Processing Unit) and memory. The functions of the monitoring unit 40 are realized by the processor operating according to a program stored in memory. The functions of the monitoring unit 40 may also be realized by an FPGA (Field Programmable Gate Array) or an ASIC (Application Specific Integrated Circuit).

[0037] The sample timing generation unit 41 generates timings for sampling the detected voltage Vcc and the measured current i, according to the timing at which the command value of the current i flowing between the collector terminal C and the emitter terminal E passes through a predetermined non-zero current value Ith.

[0038] The detected voltage Vcc is sampled and held by the sample-and-hold unit 42 at a timing generated by the sample timing generation unit 41. The sample-and-hold value obtained by the sample-and-hold unit 42 corresponds to the detected on-voltage Vcc_on. The measured current i is sampled and held by the sample-and-hold unit 43 at a timing generated by the sample timing generation unit 41. The sample-and-hold value obtained by the sample-and-hold unit 43 corresponds to the measured on-current Ic_on. The reciprocal of the measured on-current Ic_on is calculated by the arithmetic unit 45. The detected on-voltage Vcc_on and the reciprocal of the measured on-current Ic_on are multiplied by the multiplier 44 to calculate the electrical resistance R1.

[0039] The electrical resistance R1 may be corrected by an estimated value of the temperature Tj of the semiconductor chip 11 in the ON state. The temperature correction unit 46 estimates the temperature Tj of the semiconductor chip 11 in the ON state and corrects the output timing of a predetermined signal representing the detection of degradation of the bonding material 8 according to the estimated value of the temperature Tj. This suppresses a decrease in the accuracy of degradation detection due to changes in the temperature Tj of the semiconductor chip 11.

[0040] The temperature correction unit 46 acquires, for example, the temperature detection value Th of the heat sink of the semiconductor chip 11 at a timing generated by the sample timing generation unit 41, and estimates the temperature Tj of the semiconductor chip 11 from the acquired temperature detection value Th. The temperature correction unit 46 derives a correction value ΔR corresponding to the estimated temperature Tj based on a relationship rule (e.g., a map or calculation formula) between the estimated temperature Tj and the correction value ΔR. The correction value ΔR is a value used to remove the fluctuation in electrical resistance R1 due to the change in the temperature Tj of the semiconductor chip 11. The electrical resistance R1_0 (electrical resistance R1 before temperature correction) calculated by the multiplier 44 and the correction value ΔR derived by the temperature correction unit 46 are added by the adder 47 to derive the electrical resistance R1 after temperature correction.

[0041] The fault prediction unit 48 compares the electrical resistance R1 with a determination threshold and outputs a degradation detection signal according to the relationship between the electrical resistance R1 and the determination threshold. The determination threshold is set to a predetermined value (for example, a predetermined multiple of the initial value R1_s of the electrical resistance R1 (for example, 1.05 times)). The degradation detection signal is input to the latch circuit 49. Triggered by the input of the degradation detection signal, the latch circuit 49 outputs a determination value (an example of a predetermined signal) indicating that there is a fault indication in the power semiconductor module 100 due to degradation of the bonding material 8.

[0042] When the designated notification device receives a judgment value from the latch circuit 49 indicating the presence of a fault precursor, it notifies designated external devices or users that there is a fault precursor due to deterioration of the bonding material 8 of the power semiconductor module 100. By notifying them of the fault precursor, maintenance measures can be taken before a failure of the power semiconductor module 100 occurs.

[0043] Figure 9 is a diagram showing an example of the overall configuration of a power converter according to this embodiment. The power converter 101 shown in Figure 9 comprises a main circuit unit 10 that converts DC power supplied from a DC power source 33 into AC power supplied to a load 14, and a control unit 20 that controls the power conversion operation of the main circuit unit 10. Figure 9 illustrates a configuration in which the main circuit unit 10 converts DC power into three-phase AC power.

[0044] The main circuit section 10 comprises a plurality of power semiconductor modules 111 to 116, a plurality of gate drive units 121 to 126, and a current detection unit 30. The power semiconductor modules 111 to 116 are examples of semiconductor devices for power conversion.

[0045] Figure 9 illustrates an IGBT module in a 1-in-1 package, which incorporates an IGBT chip for one arm of an inverter and a diode chip (FWD chip) connected in antiparallel to it, as an example of a power semiconductor module. IGBT is an abbreviation for Insulated Gate Bipolar Transistor, an IGBT chip is an example of a power semiconductor element, and an FWD chip is an example of a rectifier element. However, the package configuration of the power semiconductor module may be other types of package configurations such as 6-in-1, and the power semiconductor elements configured in the power semiconductor module may be other types of power semiconductor elements such as MOSFETs. MOSFET is an abbreviation for Metal Oxide Semiconductor Field Effect Transistor. Furthermore, the multiple power semiconductor modules 111 to 116 each have the same configuration, and the multiple gate drive units 121 to 126 each have the same configuration. Therefore, for convenience, the upper arm of the u-phase will be used as an example in the following explanation.

[0046] In the example shown in Figure 9, the u-phase upper arm power semiconductor module 111 has an IGBT chip Q1 and an FWD chip D1. The power semiconductor module 111 also has a collector terminal C, an emitter terminal E, a gate terminal G, an auxiliary emitter terminal EA, and an auxiliary collector terminal CA. The collector terminal C is an example of a first terminal, the emitter terminal E is an example of a second terminal, the auxiliary collector terminal CA is an example of a third terminal, and the gate terminal G is an example of a control terminal.

[0047] The IGBT chip Q1 is an example of a switching element (semiconductor element) having a collector electrode 11c, an emitter electrode 11e, and a gate electrode 11g. The collector electrode 11c is an example of a first main electrode, the emitter electrode 11e is an example of a second main electrode, and the gate electrode 11g is an example of a control electrode.

[0048] The FWD chip D1 is an example of a rectifier element (semiconductor element) having an anode electrode 11a and a cathode electrode 11k.

[0049] The collector terminal C is electrically connected to the collector electrode 11c and the cathode electrode 11k. The emitter terminal E is electrically connected to the emitter electrode 11e and the anode electrode 11a. The gate terminal G is electrically connected to the gate electrode 11g. The auxiliary emitter terminal EA is electrically connected to the emitter electrode 11e and the anode electrode 11a. The auxiliary collector terminal CA is electrically connected to the collector electrode 11c and the cathode electrode 11k.

[0050] The gate drive unit 121 is a drive circuit that includes a pre-driver PD1 and a voltage detection circuit Vcc1.

[0051] The pre-driver PD1 is a circuit that drives the gate electrode 11g of the IGBT chip Q1 in response to an on or off switching command S_1 supplied from the control unit 20.

[0052] The voltage detection circuit Vcc1 detects the voltage Vcc_1 between the collector terminal C and the auxiliary collector terminal CA of the IGBT chip Q1 of the power semiconductor module 111, and transmits the detected value of Vcc_1 to the control unit 20.

[0053] The current detection unit 30 is a current sensor that detects the three-phase alternating currents iu, iv, and iw flowing between the power semiconductor modules 111 to 116 and the load 14 and transmits them to the control unit 20.

[0054] The control unit 20 is a control device that includes, for example, a processor such as a CPU (Central Processing Unit) and memory. The functions of the control unit 20 are realized by the processor operating according to a program stored in memory. The functions of the control unit 20 may also be realized by an FPGA (Field Programmable Gate Array) or an ASIC (Application Specific Integrated Circuit).

[0055] The main circuit unit 10 may also include a heat sink temperature detection unit 80. The heat sink temperature detection unit 80 is a temperature sensor that detects the temperature of a heat sink (e.g., fins, etc.) for cooling the power semiconductor modules 111 to 116 and transmits the detected heat sink temperature Th to the control unit 20.

[0056] Next, we will describe an example of how to detect the voltage Vcc_1 when the IGBT chip is ON.

[0057] Figure 10 illustrates the waveforms of each part during the detection operation of the voltage Vcc_1 in the ON state. In this example, iu is a sinusoidal current, and the U-phase voltage command is a sinusoidal voltage. The ON and OFF states of the upper and lower arms of the U-phase are determined by the relative magnitudes of the U-phase voltage command and the carrier wave. In this example, the control unit 20 outputs a switching command S_1 that turns Q1 ON and Q2 OFF during periods when the U-phase voltage command is greater than the carrier wave. On the other hand, the control unit 20 outputs a switching command S_1 that turns Q1 OFF and turns Q2 ON during periods when the U-phase voltage command is less than the carrier wave.

[0058] When Q1 is on and iu is positive, the same current Ic1 as iu flows through Q1. When Q2 is off and iu is negative, the same current as iu flows through D1. The voltage Vcc1_on when Q1 or D1 is conducting is determined depending on these currents and the respective chip temperatures of Q1 or D1. The voltage Vcc1_on is transmitted as a discrete value at the carrier wave frequency from the voltage detection circuit Vcc1 to the control unit 20. In the example shown in the figure, the sampling timing for Vcc1_on is at each bottom of the carrier wave. The control unit 20 samples the detected value of the current iu detected by the current detection unit 30 at each bottom of the carrier wave and obtains it from the current detection unit 30.

[0059] Note that the method for detecting the voltage Vcc_on1 between the main terminals when the device is ON is not limited to this.

[0060] The control unit 20 has the same functions as the monitoring unit 40 described above. The control unit 20 acquires the detected voltage Vcc_on1 and the measured current Ic1 at the same time, and calculates the electrical resistance R1_1 of the bonding material 8 of Q1 by dividing the detected voltage Vcc_on1 by the measured current Ic1.

[0061] When the control unit 20 receives a determination value from the latch circuit 49 indicating that there is a failure indicator, it notifies external devices and users of the power converter 101 that there is a failure indicator due to deterioration of the bonding material 8 of the power semiconductor module 111. The control unit 20 may notify either that there is a failure indicator in the main circuit section 10 on which the power semiconductor module 111 is mounted, or that there is a failure indicator in the power converter 101 on which the main circuit section 10 is mounted. Notifying of the failure indicator makes it possible to take maintenance measures before a failure of the power semiconductor module 111 occurs.

[0062] Thus, the power converter 101 includes a control unit 20 that has the function of a monitoring unit 40. Therefore, the control unit 20 can detect (determine) the deterioration of the bonding material 8 by executing the deterioration determination method described above.

[0063] Figure 11 is a timing chart illustrating a method for detecting deterioration of the bonding material using electrical resistance R1. Initially, the electrical resistance R1 between the collector terminal C and the auxiliary collector terminal CA is approximately constant, regardless of the applied voltage and current. As the bonding material 8 deteriorates due to repeated thermal stress, the electrical resistance R1 gradually increases. This increase in electrical resistance R1 is due to the deterioration of the bonding material 8 (increase in thermal resistance). The monitoring unit 40 determines that the bonding material 8 has deteriorated when the electrical resistance R1, which is observed online, exceeds the determination threshold Rt. The determination threshold Rt is set, for example, to 1.05 times the initial value R1_s of the electrical resistance R1.

[0064] Although embodiments have been described above, the present invention is not limited to the embodiments described above. Various modifications and improvements are possible, such as combinations or substitutions with some or all of the other embodiments.

[0065] For example, semiconductor chips are not limited to power transistors such as IGBTs, but can also include diodes, thyristors, gate turn-off thyristors, triacs, etc.

[0066] The semiconductor chip may also be a vertical power metal oxide semiconductor field-effect transistor (power MOSFET). In the above embodiment, if the semiconductor chip is a MOSFET chip, the collector is replaced by the drain and the emitter by the source, thereby enabling accurate detection of degradation of the bonding material beneath the MOSFET chip.

[0067] The semiconductor chip may also be a diode. The diode may be a diode connected in antiparallel to a switching element such as an IGBT. In the above embodiment, if the semiconductor chip is a diode chip, the collector is replaced with the cathode and the emitter with the anode, thereby enabling accurate detection of the degradation of the bonding material beneath the diode chip.

[0068] Furthermore, the temperature detection unit may estimate the semiconductor chip temperature by directly observing it, rather than indirectly estimating it from the heat sink temperature. [Explanation of Symbols]

[0069] 1. Insulating substrate 2-6 Conductor layers 7 Conductor plate 8 Bonding material 9. Cracks 10 Main circuit section 11 Semiconductor chips 11a Anode electrode 11c collector electrode 11e Emitter electrode 11g gate 11k cathode electrode 12 Surface 13 Back side 14 load 16, 17, 18, 19 wires 20 Control Unit 30 Current detection unit 33 Power supply 40 Monitoring Department 80 Heat sink temperature detection unit 100 Power Semiconductor Modules 101 Power converter 111-116 Power semiconductor modules 121-126 Gate drive unit 200 Deterioration detection device C Collector terminal CA Auxiliary Collector Terminal E emitter terminal EA Auxiliary Emitter Terminal G gate terminal

Claims

1. Conductor layer, A semiconductor chip whose back surface is bonded to the surface of the conductor layer by a bonding material, A wire bonded to the surface of the semiconductor chip, A first terminal electrically connected to the back surface of the semiconductor chip via the bonding material and the conductor layer, A second terminal electrically connected to the surface of the semiconductor chip via the wire, A third terminal electrically connected to the bonding material near the semiconductor chip, The system includes a monitoring unit that monitors the electrical resistance between the first terminal and the third terminal and outputs a predetermined signal when the electrical resistance exceeds a predetermined value, The first terminal is a collector terminal, and the third terminal is an auxiliary collector terminal. The third terminal is electrically connected to the bonding material near the semiconductor chip via a conductive plate that is electrically in contact with the upper surface of the bonding material. Deterioration detection device.

2. Multiple semiconductor devices for power conversion, The system comprises a control unit that controls the switching of the plurality of semiconductor devices, Each of the aforementioned plurality of semiconductor devices is: Conductor layer, A semiconductor chip whose back surface is bonded to the surface of the conductor layer by a bonding material, A wire bonded to the surface of the semiconductor chip, A first terminal electrically connected to the back surface of the semiconductor chip via the bonding material and the conductor layer, A second terminal electrically connected to the surface of the semiconductor chip via the wire, It has a third terminal electrically connected to the bonding material near the semiconductor chip, The first terminal is a collector terminal, and the third terminal is an auxiliary collector terminal. The third terminal is electrically connected to the bonding material near the semiconductor chip via a conductive plate that is electrically in contact with the upper surface of the bonding material. The control unit is a power conversion device that monitors the electrical resistance between the first terminal and the third terminal, and outputs a predetermined signal when the electrical resistance exceeds a predetermined value.

3. A method for detecting degradation of a semiconductor device comprising: a conductor layer; a semiconductor chip whose back surface is bonded to the surface of the conductor layer by a bonding material; a wire bonded to the surface of the semiconductor chip; a first terminal electrically connected to the back surface of the semiconductor chip via the bonding material and the conductor layer; a second terminal electrically connected to the surface of the semiconductor chip via the wire; and a third terminal electrically connected to the bonding material near the semiconductor chip, wherein The first terminal is a collector terminal, and the third terminal is an auxiliary collector terminal. The third terminal is electrically connected to the bonding material near the semiconductor chip via a conductive plate that is electrically in contact with the upper surface of the bonding material. A degradation detection method that monitors the electrical resistance between the first terminal and the third terminal, and outputs a predetermined signal when the electrical resistance exceeds a predetermined value.

4. Conductor layer, A semiconductor chip whose back surface is bonded to the surface of the conductor layer by a bonding material, A wire bonded to the surface of the semiconductor chip, A first terminal electrically connected to the back surface of the semiconductor chip via the bonding material and the conductor layer, A second terminal electrically connected to the surface of the semiconductor chip via the wire, A third terminal electrically connected to the bonding material near the semiconductor chip, The system includes a monitoring unit that monitors the electrical resistance between the first terminal and the third terminal and outputs a predetermined signal when the electrical resistance exceeds a predetermined value, The first terminal is a collector terminal, and the third terminal is an auxiliary collector terminal. The third terminal is an external terminal connected to the bonding material via a second conductor layer different from the conductor layer and a second wire different from the wire. Deterioration detection device.

5. Multiple semiconductor devices for power conversion, The system comprises a control unit that controls the switching of the plurality of semiconductor devices, Each of the aforementioned plurality of semiconductor devices is: Conductor layer, A semiconductor chip whose back surface is bonded to the surface of the conductor layer by a bonding material, A wire bonded to the surface of the semiconductor chip, A first terminal electrically connected to the back surface of the semiconductor chip via the bonding material and the conductor layer, A second terminal electrically connected to the surface of the semiconductor chip via the wire, It has a third terminal electrically connected to the bonding material near the semiconductor chip, The first terminal is a collector terminal, and the third terminal is an auxiliary collector terminal. The third terminal is an external terminal connected to the bonding material via a second conductor layer different from the conductor layer and a second wire different from the wire, The control unit is a power conversion device that monitors the electrical resistance between the first terminal and the third terminal, and outputs a predetermined signal when the electrical resistance exceeds a predetermined value.

6. A method for detecting degradation of a semiconductor device comprising: a conductor layer; a semiconductor chip whose back surface is bonded to the surface of the conductor layer by a bonding material; a wire bonded to the surface of the semiconductor chip; a first terminal electrically connected to the back surface of the semiconductor chip via the bonding material and the conductor layer; a second terminal electrically connected to the surface of the semiconductor chip via the wire; and a third terminal electrically connected to the bonding material near the semiconductor chip, wherein The first terminal is a collector terminal, and the third terminal is an auxiliary collector terminal. The third terminal is an external terminal connected to the bonding material via a second conductor layer different from the conductor layer and a second wire different from the wire, A degradation detection method that monitors the electrical resistance between the first terminal and the third terminal, and outputs a predetermined signal when the electrical resistance exceeds a predetermined value.

7. The electrical resistance is the resistance between the first terminal and the second terminal in the ON state, When the monitoring unit detects that the on-current, which is the current flowing between the two terminals in the on state, exceeds a threshold, it samples and holds the on-voltage, which is the voltage between the two terminals in the on state, and the on-current, and calculates the electrical resistance by dividing the on-voltage by the on-current. A deterioration detection device according to claim 1 or 4.

8. The power conversion device according to claim 2 or 5, wherein when the on-current, which is the current flowing between the first terminal and the second terminal in an on state, exceeds a threshold, the control unit samples and holds the on-voltage, which is the voltage between the terminals in the on state, and the on-current, and calculates the electrical resistance by dividing the on-voltage by the on-current.

9. The degradation detection method according to claim 3 or 6, wherein when the on-current, which is the current flowing between the two terminals in the on state between the first terminal and the second terminal, exceeds a threshold, the on-voltage, which is the voltage between the two terminals in the on state, and the on-current are sampled and held, and the electrical resistance is calculated by dividing the on-voltage by the on-current.

10. The monitoring unit temperature-corrects the electrical resistance based on the temperature of the semiconductor chip, and outputs the predetermined signal when the electrical resistance exceeds a predetermined multiple of the initial value. A deterioration detection device according to claim 1 or 4.

11. The power conversion device according to claim 2 or 5, wherein the control unit temperature-corrects the electrical resistance based on the temperature of the semiconductor chip, and outputs the predetermined signal when the electrical resistance exceeds a predetermined multiple of the initial value.

12. The degradation detection method according to claim 3 or 6, wherein the electrical resistance is temperature-compensated based on the temperature of the semiconductor chip, and when the electrical resistance exceeds a predetermined multiple of the initial value, the predetermined signal is output.

13. The power conversion device according to claim 2 or 5, wherein the control unit samples the on-voltage, which is the voltage between the first terminal and the second terminal in the on state, and the on-current, which is the current flowing between the two terminals in the on state, in accordance with the carrier wave, and calculates the electrical resistance.

14. The deterioration detection device according to any one of claims 1, 4, or 10, wherein the electrical resistance is the resistance between the first terminal and the second terminal in the ON state.

15. The deterioration detection device according to claim 14, wherein the monitoring unit detects an on-voltage, which is the voltage between the two terminals in the on state, and an on-current, which is the current flowing between the two terminals in the on state, and monitors the value obtained by dividing the on-voltage by the on-current as the electrical resistance.

16. The degradation detection device according to any one of claims 1, 4, 7, 10, 14, or 15, wherein the monitoring unit estimates the temperature of the semiconductor chip in the ON state between both the first terminal and the second terminal, and corrects the electrical resistance according to the estimated temperature.

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