Semiconductor equipment

Abstract

To suppress increasing of contact resistance while suppressing increasing of on-resistance.SOLUTION: In a second impurity region 17, parts extending from boundary parts 171a and 171b of a first abutting region 171 toward other trench 13 are defined as linear parts 173a and 173b, parts extending from boundary parts 172a and 172b of a second abutting region 172 toward one trench 13 are defined as linear parts 174a and 174b, one angle of two angles θ1 and θ2 between the one trench 13 and two linear parts 173a and 173b connected to the first abutting region is less than 90°. The other angle is less than or equal to 90°. One angle of two angles θ3 and θ4 between the other trench 13 and two linear parts 174a and 174b connected to the second abutting region 172 is less than 90° and the other angle is less than or equal to 90°.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device having a trench gate structure. [Background technology]

[0002] Conventionally, semiconductor devices having a trench gate structure have been proposed (see, for example, Patent Document 1). Specifically, this semiconductor device has n - The device has a semiconductor substrate that constitutes a drift layer of a certain type, with a base layer formed on the drift layer. Multiple trenches are formed in the semiconductor substrate, penetrating the base layer and with one direction in the planar direction of the semiconductor substrate as the longitudinal direction. A gate insulating film is formed in each trench so as to cover the wall surface, and a gate electrode is formed on the gate insulating film.

[0003] On the surface of the base layer, in contact with the trench, n + Source area of ​​type and p + A contact region of a certain type is formed. That is, the source region and the contact region are formed alternately along the longitudinal direction of the trench. In addition, the source region and the contact region have a rectangular planar shape.

[0004] A first electrode, connected to the source region and contact region, is positioned on one side of the semiconductor substrate, while a second electrode, connected to the drain layer, is positioned on the other side of the semiconductor substrate.

[0005] In such a semiconductor device, when a voltage exceeding a predetermined threshold voltage is applied to the gate electrode, an inversion layer is formed in the portion of the base layer that is in contact with the trench. The semiconductor device then turns on when current flows from the first electrode through the source region and the inversion layer to the drain layer. [Prior art documents] [Patent Documents]

[0006] [Patent Document 1] Japanese Patent Publication No. 2003-303967 [Overview of the project] [Problems that the invention aims to solve]

[0007] In the semiconductor device described above, the contact region in contact with the trench does not become a current path, so the on-resistance tends to increase. For this reason, in the semiconductor device described above, it is conceivable to shorten the length of the trench along the longitudinal direction in the contact region. However, shortening the length of the trench along the longitudinal direction in the contact region reduces the contact area between the contact region and the first electrode. Therefore, in this configuration, the contact resistance increases. In particular, when the semiconductor substrate is made of silicon carbide, the resistance of the contact region increases, so the effect of the increase in contact resistance tends to be greater.

[0008] In view of the above, the present invention aims to provide a semiconductor device that can suppress an increase in on-resistance while suppressing an increase in contact resistance between the contact region and the first electrode. [Means for solving the problem]

[0009] Claim 1, for achieving the above objective, provides a semiconductor device having a trench gate structure, comprising: a plurality of trench gate structures having: a drift layer (11) of a first conductivity type; a base layer (12) of a second conductivity type disposed on the drift layer; an impurity layer (20) of a first or second conductivity type formed on the opposite side of the base layer, sandwiching the drift layer; a gate insulating film (14) formed on the wall surface of a trench (13) that penetrates the base layer and extends with its longitudinal direction intersecting the stacking direction of the drift layer and the base layer; and a gate electrode (15) formed on the gate insulating film; a first impurity region (16) of a first conductivity type formed on the surface of the base layer and having a higher impurity concentration than the drift layer; a second impurity region (17) of a second conductivity type formed on the surface of the base layer and having a higher impurity concentration than the base layer; a first electrode (19) electrically connected to the first impurity region and the second impurity region; and a second electrode (21) electrically connected to the impurity layer. Furthermore, the semiconductor device has first impurity regions and second impurity regions formed alternately along the longitudinal direction of the trench, and the second impurity region has a first contact region (171) which abuts one trench of adjacent trenches in a direction intersecting the longitudinal direction in the stacking direction of the drift layer and the base layer, and has two boundary portions (171a, 171b) of a predetermined length that are away from the trench, and a second contact region (172) which abuts the other trench of adjacent trenches, and has two boundary portions (172a, 172b) of a predetermined length that are away from the trench, and the portions from each boundary portion of the first contact region toward the other trench are linear portions (173a, 173b), and the portions from each boundary portion of the second contact region toward one trench are linear portions (174a, 174b), and between one trench and the two linear portions connecting the first contact region First impurity region side One of the two angles (θ1, θ2) is less than 90°, and the other angle is 90° or less, and between the other trench and the two straight sections connecting to the second contact region First impurity region side One of the two angles (θ3, θ4) is less than 90°, and the other angle is 90° or less. Furthermore, the spacing between adjacent trenches is kept constant along the longitudinal direction of the trench. .

[0010] According to this, compared to the case where each angle in the second impurity region is 90° (i.e., the second impurity region is planar and rectangular), the area of ​​the second impurity region in the stacking direction between the drain layer and the base layer can be increased without increasing the length of the contact region. In other words, compared to the case where each angle in the second impurity region is 90°, shortening the length of the contact region makes it easier to secure the area of ​​the second impurity region in the stacking direction between the drain layer and the base layer while reducing on-resistance. Therefore, in this semiconductor device, it is possible to suppress an increase in on-resistance while suppressing an increase in contact resistance.

[0011] The reference numerals in parentheses attached to each component indicate an example of the correspondence between that component and the specific components described in the embodiments described later. [Brief explanation of the drawing]

[0012] [Figure 1] This is a cross-sectional view of the semiconductor device in the first embodiment. [Figure 2] This is a plan view showing the positional relationship between the source region and the contact region. [Figure 3] This is a plan view illustrating the shape of the contact area. [Figure 4] This diagram illustrates the situation when the trench is shifted in a second direction. [Figure 5] This is a plan view illustrating the shape of the contact area in a modified example of the first embodiment. [Figure 6] This is a plan view illustrating the shape of the contact area in a modified example of the first embodiment. [Figure 7] This is a plan view illustrating the shape of the contact area in a modified example of the first embodiment. [Figure 8] This is a plan view illustrating the shape of the contact area in a modified example of the second embodiment. [Figure 9A]It is an enlarged schematic view when the trench in the IXA region in FIG. 8 is displaced. [Figure 9B] It is an enlarged schematic view when the trench in the IXB region in FIG. 8 is displaced. [Figure 10] It is a plan view for explaining the shape of the contact region in the modification of the second embodiment.

Embodiments for Carrying Out the Invention

[0013] Hereinafter, embodiments of the present invention will be described based on the drawings. In each of the following embodiments, parts that are the same or equivalent to each other will be described with the same reference numerals.

[0014] (First Embodiment) The first embodiment will be described while referring to the drawings. Note that the semiconductor device of this embodiment is preferably used as a power switching element used in, for example, an inverter or the like.

[0015] As shown in FIG. 1, the semiconductor device is configured using a semiconductor substrate 10. The semiconductor substrate 10 is configured using a silicon substrate, a silicon carbide substrate, a gallium nitride substrate, or the like. The semiconductor substrate 10 has an n-type drift layer 11, and a p-type base layer 12 having a relatively low impurity concentration is disposed on the drift layer 11. Hereinafter, the surface of the semiconductor substrate 10 on the base layer 12 side will be described as one surface 10a of the semiconductor substrate 10, and the surface of the semiconductor substrate 10 on the drift layer 11 side will be described as the other surface 10b.

[0016] A plurality of trenches 13 are formed in the semiconductor substrate 10 so as to penetrate the base layer 12 from the one surface 10a side and reach the drift layer 11, and the base layer 12 is separated into a plurality of parts by these trenches 13. The plurality of trenches 13 have one direction in the plane direction of the one surface of the semiconductor substrate 10 (that is, the depth direction in the drawing in FIG. 1) as the longitudinal direction, and each trench 13 is extended so as to be in a stripe shape at equal intervals.

[0017] Each trench 13 is filled with a gate insulating film 14 formed to cover the walls of each trench 13, and a gate electrode 15 made of polysilicon or the like formed on top of the gate insulating film 14. This constitutes a trench gate structure.

[0018] As shown in Figures 1 and 2, the surface layer of the base layer 12 has n + Source region 16 and p of type + A contact region 17 of a certain type is formed. Specifically, the source region 16 is composed of a higher impurity concentration than the drift layer 11, and the contact region 17 is composed of a higher impurity concentration than the base layer 12. In this embodiment, the source region 16 and the contact region 17 are formed alternately along the longitudinal direction of the trench 13. The specific shape of the contact region 17 will be described later. In this embodiment, the source region 16 corresponds to the first impurity region, and the contact region 17 corresponds to the second impurity region.

[0019] As shown in Figure 1, an interlayer insulating film 18 made of BPSG (i.e., Boron Phosphorus Silicon Glass) or the like is formed on one surface 10a of the semiconductor substrate 10. Contact holes 18a are formed in the interlayer insulating film 18, exposing the source region 16 and the contact region 17. An upper electrode 19 is formed on the interlayer insulating film 18, electrically connected to the source region 16 and the contact region 17 through the contact holes 18a. In this embodiment, the upper electrode 19 corresponds to the first electrode. Figure 1 corresponds to a cross-section along line II in Figure 2. Figure 2 is a plan view of the semiconductor substrate 10 on the side of one surface 10a, and is not a cross-sectional view, but hatching has been applied to the gate insulating film 14 and gate electrode 15, which will be described later, for ease of understanding.

[0020] A drain layer 20 is formed on the drift layer 11 opposite to the base layer 12 (i.e., on the other side 10b of the semiconductor substrate 10). A lower electrode 21 is formed on the opposite side of the drift layer 11, across the drain layer 20, and electrically connected to the drain layer 20. In other words, a lower electrode 21 electrically connected to the drain layer 20 is formed on the other side 10b of the semiconductor substrate 10. In this embodiment, the drain layer corresponds to the impurity layer, and the lower electrode 21 corresponds to the second electrode.

[0021] The above describes the basic configuration of the semiconductor device in this embodiment. In this embodiment, n-type, n + The type corresponds to the first conductivity type, p type, p + The type corresponds to the second conductivity type. In such a semiconductor device, the semiconductor substrate 10 is composed of a drain layer 20, a drift layer 11, a base layer 12, a source region 16, a contact region 17, etc., as described above.

[0022] In such a semiconductor device, when a voltage above a predetermined threshold voltage is applied to the gate electrode 15, an inversion layer is formed in the portion of the base layer 12 that is in contact with the trench 13. The semiconductor device then turns on when current flows from the upper electrode 19 through the source region 16 and the inversion layer to the drain layer 20. The contact region 17 in contact with the trench 13 does not become a current path. Therefore, the larger the contact region 17 in contact with the trench 13, the more likely the on-resistance is to increase.

[0023] Next, the shape of the contact region 17 in this embodiment will be described in detail with reference to Figures 2 and 3. Figure 3 is an enlarged view of the vicinity of the contact region 17 shown in Figure 2. In the following description, as shown in Figures 2 and 3, the direction along the longitudinal direction of the trench 13 will be referred to as the first direction, and the direction perpendicular to the first direction and along the plane direction of the semiconductor substrate 10 will be referred to as the second direction. In Figures 2 and 3, the left-right direction of the paper is the first direction, and the up-down direction of the paper is the second direction.

[0024] The contact region 17 is formed between adjacent trenches 13 in the direction normal to one surface 10a of the semiconductor substrate 10 (hereinafter also simply referred to as "in the normal direction"). In other words, "in the normal direction" can also be said to mean in the stacking direction of the drift layer 11 and the base layer 12. In other words, "in the normal direction" can also be said to mean when viewed from the normal direction.

[0025] The contact region 17 is formed to have contact regions 171 and 172 that abut against adjacent trenches 13 in the normal direction. Hereinafter, the region of the contact region 17 that abuts against one of the adjacent trenches 13 in the normal direction will also be called the first contact region 171. Similarly, the region of the contact region 17 that abuts against the other of the adjacent trenches 13 will also be called the second contact region 172. In Figure 3, of the two trenches 13 arranged in the second direction, the trench 13 on the upper side of the paper becomes one trench 13, and the trench 13 on the lower side of the paper becomes the other trench 13.

[0026] The first contact region 171 is formed to contact the trench 13 with a first contact length a greater than 0. Similarly, the second contact region 172 is formed to contact the trench 13 with a second contact length b greater than 0. Therefore, the contact region 17 has a shape that includes two first boundary portions 171a and 171b at both ends of the first contact region 171 that move away from the trench 13, and two second boundary portions 172a and 172b at both ends of the second contact region 172 that move away from the trench 13. In other words, the contact region 17 has a shape that, in the normal direction, has a portion that contacts the trench 13 in a linear rather than point-like manner.

[0027] Furthermore, in the normal direction, the contact region 17 has straight sections 173a and 173b as its outline, extending from the two first boundary sections 171a and 171b towards the other trench 13. In the normal direction, the contact region 17 has straight sections 174a and 174b as its outline, extending from the two second boundary sections 172a and 172b towards the one trench 13. In this embodiment, the contact region 17 has acute angles θ1 to θ4 between each of the straight sections 173a, 173b, 174a, and 174b and each trench 13, with each angle being less than 90°. Moreover, the contact region 17 in this embodiment has a hexagonal shape with the first to fourth angles θ1 to θ4 being equal. Note that the outline refers to the lines that form the planar shape of the contact region 17, and in the normal direction, it can also be called the boundary line with the source region 16.

[0028] In this embodiment described above, the first to fourth angles θ1 to θ4 are less than 90°. Therefore, compared to the case where the first to fourth angles θ1 to θ4 are 90° (i.e., the contact area 17 is rectangular in shape), the area of ​​the contact area 17 in the normal direction can be increased without increasing the first contact length a and the second contact length b. In other words, compared to the case where the first to fourth angles θ1 to θ4 are 90°, shortening the first contact length a and the second contact length b makes it easier to secure the area of ​​the contact area 17 in the normal direction while reducing the on-resistance. Therefore, in the semiconductor device of this embodiment, it is possible to suppress an increase in on-resistance while suppressing an increase in contact resistance.

[0029] (1) In this embodiment, the first to fourth angles θ1 to θ4 are the same angle. Therefore, as shown in Figure 4, if the trench 13 is shifted in the second direction on one side of the trench 13 due to manufacturing errors, etc., and the change in contact length due to the shift of the trench 13 is d, then the first contact length becomes ad and the second contact length becomes b+d. However, the sum of the first contact length and the second contact length remains a+b even if the trench 13 is shifted in the second direction. Therefore, according to the semiconductor device of this embodiment, even if the trench 13 is shifted in the second direction due to manufacturing errors, etc., it is possible to suppress changes in on-resistance and suppress changes in characteristics.

[0030] (2) In this embodiment, the first to fourth angles θ1 to θ4 are the same angle. Therefore, compared to the case where the first to fourth angles θ1 to θ4 are different values, visual inspection in the contact area 17 can be made easier.

[0031] (Modified version of the first embodiment) In the first embodiment described above, the contact region 17 may have a shape having linear portions 173a, 173b, 174a, 174b and linear portions 175a, 175b that are not parallel to each other. For example, as shown in Figure 5, the planar shape may be octagonal. That is, the linear portion 173a connected to the first contact region 171 and the linear portion 174a connected to the second contact region 172 may be connected by a linear portion 175a, and the linear portion 173b connected to the first contact region 171 and the linear portion 174b connected to the second contact region 172 may be connected by a linear portion 175b. In this case, compared to the first embodiment described above, the angle of the corners of the contact region 17 becomes larger in the normal direction. Here, the contact region 17 is formed, for example, by placing a mask on one surface 10a of the semiconductor substrate 10 and ion implanting p-type impurities. In this case, compared to the first embodiment described above, the angle of the corners of the contact region 17 becomes larger, making it less likely for the planar shape of the contact region 17 to be distorted when the contact region 17 is formed. Therefore, it is easier to suppress changes in contact resistance.

[0032] In this example, the contact area 17 has an octagonal planar shape, but the contact area 17 may also have a decagonal planar shape or a dodecagonal shape.

[0033] Furthermore, in the first embodiment described above, as shown in Figure 6, the linear portion 173a connected to the first contact region 171 and the linear portion 174a connected to the second contact region 172 may be connected by an arc-shaped portion 176a. Alternatively, the linear portion 173b connected to the first contact region 171 and the linear portion 174b connected to the second contact region 172 may be connected by an arc-shaped portion 176b. In addition, although not specifically shown, for example, the linear portion 173a connected to the first contact region 171 and the linear portion 174a connected to the second contact region 172 may be connected by a linear portion 175a, and the linear portion 173b connected to the first contact region 171 and the linear portion 174b connected to the second contact region 172 may be connected by an arc-shaped portion 176b. In other words, the shape between the linear portion 173a connected to the first contact region 171 and the linear portion 174a connected to the second contact region 172, and the shape between the linear portion 173b connected to the first contact region 171 and the linear portion 174b connected to the second contact region 172 can be changed as appropriate.

[0034] Furthermore, in the first embodiment described above, one of the first angle θ1 and the second angle θ2 may be 90° or less. Similarly, one of the third angle θ3 and the fourth angle θ4 may be 90° or less. For example, as shown in Figure 7, the second angle θ2 and the fourth angle θ4 may be 90°, and the linear portion 173b connected to the first contact region 171 and the linear portion 174b connected to the second contact region 172 may be a common linear portion. Even with such a contact region 17, compared to the case where the first to fourth angles θ1 to θ4 are all 90°, the area of ​​the contact region 17 in the normal direction can be increased, and the same effects as in the first embodiment can be obtained.

[0035] (Second Embodiment) A second embodiment will now be described. This embodiment is a modification of the first embodiment in which the planar shape of the contact region 17 is changed. Other aspects are the same as in the first embodiment, so a detailed explanation will be omitted here.

[0036] In this embodiment, as shown in Figure 8, the first to fourth angles θ1 to θ4 of the contact region 17 are not all the same angle. However, the first to fourth angles θ1 to θ4 are formed such that the sum of the first contact length and the second contact length does not change even if the trench 13 is shifted in the second direction, as shown in the following equation 1.

[0037] (Equation 1) 1 / tanθ1 + 1 / tanθ2 = 1 / tanθ3 + 1 / tanθ4 ... (Equation 1) Here, the reason for the above equation 1 will be explained with reference to Figures 9A and 9B. When trench 13 is shifted to one side of trench 13 (i.e., the upper side of the paper), on the first contact region 171 side, if the amount of shift of trench 13 is ΔL and the changes in the first contact length due to the shift of trench 13 are d1 and d2, then the following equations 2 and 3 hold true.

[0038] (Equation 2) ΔL / d1 = tanθ1 ... (Equation 2)

[0039] (Mathematics 3) ΔL / d² = tanθ² ... (Equation 3) Therefore, the total change in the first contact length is given by the following equation 4.

[0040] (Formula 4) d1+d2=ΔL / tanθ1+ΔL / tanθ2…(Formula 4) Similarly, on the second contact region 172 side, if d3 and d4 are the changes in the second contact length due to the displacement of the trench 13, then the following equations 5 and 6 hold true.

[0041] (Math. 5) ΔL / d3=tanθ3…(Math. 5)

[0042] (Equation 6) ΔL / d4 = tanθ4 ... (Equation 6) Therefore, the total change in the second contact length is given by the following equation 7.

[0043] (Math 7)d3+d4=ΔL / tanθ3+ΔL / tanθ4…(Math 7) Furthermore, in order to ensure that the sum of the first contact length and the second contact length does not change even if trench 13 is shifted in the second direction, it is sufficient that equations 4 and 7 are equal, so that the following equation 8 holds true.

[0044] (Formula 8) ΔL / tanθ1+ΔL / tanθ2=ΔL / tanθ3+ΔL / tanθ4…(Formula 8) Then, by rearranging equation 8 above, we obtain equation 1 above. Therefore, in this embodiment, the first to fourth angles θ1 to θ4 are adjusted to satisfy equation 1 above.

[0045] Furthermore, in this embodiment, the contact region 17 is configured such that a linear portion 173a connected to the first contact region 171 and a linear portion 174a connected to the second contact region 172 are connected by a linear portion 175a, similar to the modified example of the first embodiment. The contact region 17 is configured such that a linear portion 173b connected to the first contact region 171 and a linear portion 174b connected to the second contact region 172 are connected by a linear portion 175b.

[0046] Even with this configuration, the sum of the first contact length and the second contact length does not change when the trench 13 is shifted along the second direction. In this embodiment, the contact region 17 is configured such that the first angle θ1 and the third angle θ3 are equal, and the second angle θ2 and the fourth angle θ4 are equal, thereby satisfying the above equation 1. Furthermore, in the above first embodiment, the first to fourth angles θ1 to θ4 are all equal, so the above equation 1 is satisfied.

[0047] According to the embodiment described above, since the first angle θ1 and the second angle θ2 are less than 90°, and the third angle θ3 and the fourth angle θ4 are also less than 90°, the same effects as in the first embodiment can be obtained.

[0048] (1) By forming the contact region 17 so as to satisfy the above formula (1) as in this embodiment, the same effects as those of the first embodiment can be obtained. Further, since it is only necessary that the contact region 17 be formed so as to satisfy the above formula (1), the degree of freedom in the shape of the contact region 17 can be improved as compared with the first embodiment in which all of the first to fourth angles θ1 to θ4 are made equal.

[0049] (Modification of the second embodiment) A modification of the above second embodiment will be described. In the above second embodiment, if the above formula (1) is satisfied, the shape of the contact region 17 can be appropriately changed. For example, as shown in FIG. 10, the contact region 17 may be configured such that the first angle θ1 and the third angle θ3 are equal and the second angle θ2 and the fourth angle θ4 are equal.

[0050] (Other embodiments) Although the present disclosure has been described based on the embodiments, it should be understood that the present disclosure is not limited to such embodiments and structures. The present disclosure includes various modifications and modifications within an equivalent range. In addition, various combinations and forms, and further other combinations and forms including only one element, more than one element, or less than one element thereof, are within the scope and spirit of the present disclosure.

[0051] For example, in the above first embodiment, a semiconductor device in which an n-channel type trench gate structure MOSFET having a first conductivity type of n-type and a second conductivity type of p-type is formed has been described. However, this is only an example, and for example, a semiconductor device in which a p-channel type trench gate structure MOSFET in which the conductivity types of each component are inverted with respect to the n-channel type may be formed. Further, the semiconductor device may be configured such that an IGBT having the same structure is formed in addition to the MOSFET. In the case of an IGBT, it is the same as the MOSFET described in each of the above embodiments except that the n-type drain layer in each of the above embodiments is changed to a p-type collector layer. + type drain layer to p + type collector layer, it is the same as the MOSFET described in each of the above embodiments.

Description of reference numerals

[0052] 11 Drift Layer 12 Base Layer 16. Source region (first impurity region) 17. Contact area (second impurity area) 19 Upper electrode (1st electrode) 20 Drain layer (impurity layer) 21 Lower electrode (second electrode) 171 1st contact area 171a, 171b border 172 Second contact area 172a, 172b border 173a, 173b Straight section 174a, 174b Straight section θ1~θ4 1st~4th angle

Claims

1. A semiconductor device having a trench gate structure, A first conductive drift layer (11), A second conductive base layer (12) is disposed on the drift layer, A first conductivity type or second conductivity type impurity layer (20) is formed on the opposite side of the base layer, sandwiching the drift layer, A plurality of trench gate structures having a gate insulating film (14) formed on the wall surface of a trench (13) that penetrates the base layer and extends with its longitudinal direction intersecting the stacking direction of the drift layer and the base layer, and a gate electrode (15) formed on the gate insulating film, A first impurity region (16) of a first conductivity type is formed on the surface of the base layer and has a higher impurity concentration than the drift layer, A second impurity region (17) of a second conductivity type is formed on the surface of the base layer and has a higher impurity concentration than the base layer, A first electrode (19) electrically connected to the first impurity region and the second impurity region, The device comprises a second electrode (21) electrically connected to the impurity layer, The first impurity region and the second impurity region are formed alternately along the longitudinal direction of the trench, The aforementioned second impurity region is located in the stacking direction between the drift layer and the base layer. The first contact region (171) abuts against one of the adjacent trenches in a direction intersecting the longitudinal direction and has two boundary portions (171a, 171b) having a predetermined length and moving away from the trench, and the second contact region (172) abuts against the other of the adjacent trenches and has two boundary portions (172a, 172b) having a predetermined length and moving away from the trench, The portions extending from each boundary of the first contact region toward the other trench are straight sections (173a, 173b), and the portions extending from each boundary of the second contact region toward the one trench are straight sections (174a, 174b). Between the one trench and the two linear portions connected to the first contact region, one of the two angles (θ1, θ2) on the first impurity region side is less than 90°, and the other angle is 90° or less. Between the other trench and the two linear portions connected to the second contact region, one of the two angles (θ3, θ4) on the first impurity region side is less than 90°, and the other angle is 90° or less. A semiconductor device in which adjacent trenches are spaced at a constant distance along the longitudinal direction of the trench.

2. The semiconductor device according to claim 1, wherein two angles between one trench and two linear portions connected to the first contact region are θ1 and θ2, and two angles between the other trench and the linear portion connected to the second contact region are θ3 and θ4, such that 1 / tanθ1 + 1 / tanθ2 = 1 / tanθ3 + 1 / tanθ4.

3. The semiconductor device according to claim 2, wherein one of the two angles between the one trench and the two linear portions connected to the first contact region is equal to one of the two angles between the other trench and the two linear portions connected to the second contact region.

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