Semiconductor equipment

Abstract

To provide a semiconductor device that reduces variations in on-resistance between semiconductor devices.SOLUTION: A semiconductor device 1 comprises: a substrate 10; a drift layer 12 of a first conductivity type; gate electrodes 26; a repeating area 40 of a second conductivity type and the like. When a center line passing through the center of the gate electrode 26 in the arrangement direction of the gate electrodes 26 and extending in the thickness direction of the substrate 10 is defined as a cell center line Oc, the distance between the adjacent cell center lines Oc in the arrangement direction of the gate electrodes 26 as a cell pitch Pc, a center line passing through the center of the repeating area 40 in the arrangement direction of the gate electrodes 26 and extending in the thickness direction of the substrate 10 as a repeating center line Or, and the distance between the adjacent repeating center lines Or in the arrangement direction of the gate electrodes 26 as a repeating pitch Pr, the cell pitch Pc is different from the repeating pitch Pr.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] This disclosure relates to semiconductor devices. [Background technology]

[0002] Conventionally, as described in Patent Document 1, a semiconductor device is known that comprises gate electrodes and p-type base regions arranged at equal intervals in the planar direction of the substrate, and p-type column regions and n-type column regions arranged alternately and repeatedly. Furthermore, the p-type column regions are arranged between adjacent gate electrodes in the arrangement direction of the gate electrodes. In addition, the arrangement spacing of the gate electrodes and the arrangement spacing of the p-type column regions are the same. [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2019-102761 [Overview of the project] [Problems that the invention aims to solve]

[0004] When semiconductor devices are manufactured, mask misalignment can cause the relative position of the p-type column regions to shift relative to the gate electrodes. As a result, in the semiconductor device described in Patent Document 1, since the spacing between the gate electrodes and the p-type column regions are the same, the spacing between the gate electrodes and the p-type column regions changes, for example, each p-type column may be directly opposite the gate electrode in the thickness direction of the substrate. Therefore, when a channel region is formed in the p-type base region when the semiconductor device is turned on, the movement of electrons flowing through the n-type columns is hindered by each p-type column region, increasing the on-resistance of the semiconductor device. Consequently, in the semiconductor device described in Patent Document 1, the variation in the relative position of the p-type column regions to the gate electrodes due to manufacturing variations results in large variations in on-resistance between semiconductor devices.

[0005] This disclosure aims to provide a semiconductor device that reduces variations in on-resistance between semiconductor devices. [Means for solving the problem]

[0006] The invention described in claim 1 is a semiconductor device comprising: a substrate (10) having a cell region (RC) on which a semiconductor element is formed; a first conductivity type drift layer (12) formed on the surface side of the substrate and having a lower impurity concentration than the substrate; a first electrode (32) formed on the surface side of the drift layer; a second electrode (34) formed on the back side of the substrate; a plurality of gate electrodes (26) arranged at intervals in one direction, which turn on the semiconductor element based on an applied voltage and cause a current to flow between the first electrode and the second electrode; and a plurality of second conductive electrodes arranged at intervals in the direction of the arrangement of the gate electrodes within the drift layer. The electrode comprises repeating regions (40, 41) and a cell center line (Oc) that passes through the center of each gate electrode in the gate electrode arrangement direction and extends in the thickness direction of the substrate, the distance between adjacent cell center lines in the gate electrode arrangement direction is the cell pitch (Pc), the center lines that pass through the center of each repeating region in the gate electrode arrangement direction and extend in the thickness direction of the substrate are the repeating center lines (Or, Or1), and the distance between adjacent repeating center lines in the gate electrode arrangement direction is the repeating pitch (Pr, Pr1). The cell pitch is different from the repeating pitch. Furthermore, if we denote the cell pitch as Pc, the repeating pitch as Pr, i as a natural number greater than or equal to 2, and j as a natural number different from i, then the gate electrode and repeating region are formed such that i × Pc = j × Pr holds, where j is greater than or equal to 2, and j ≠ 2 × i. It is a semiconductor device. Furthermore, the invention described in claim 2 is a semiconductor device comprising: a substrate (10) having cell regions (RC) on which semiconductor elements are formed; a first conductivity type drift layer (12) formed on the surface side of the substrate and having a lower impurity concentration than the substrate; a first electrode (32) formed on the surface side of the drift layer; a second electrode (34) formed on the back side of the substrate; gate electrodes (26) arranged in a plurality at intervals in one direction, which turn on the semiconductor elements based on the applied voltage and cause current to flow between the first electrode and the second electrode; and a plurality of second conductivity type repeating regions (40, 41) arranged in the drift layer at intervals in the direction of the arrangement of the gate electrodes, passing through the center of each gate electrode in the direction of the arrangement of the gate electrodes and in the thickness direction of the substrate. If we define a center line extending in a certain direction as the cell center line (Oc), the distance between adjacent cell center lines in the gate electrode arrangement direction as the cell pitch (Pc), the center lines passing through the center of each repeating region in the gate electrode arrangement direction and extending in the thickness direction of the substrate as the repeating center lines (Or, Or1), and the distance between adjacent repeating center lines in the gate electrode arrangement direction as the repeating pitch (Pr, Pr1), then the cell pitch is different from the repeating pitch. If we define the cell pitch as Pc, the repeating pitch as Pr, i as a natural number greater than or equal to 2, and j as a natural number different from i, then the gate electrodes and repeating regions are formed such that i × Pc = j × Pr, and the cell pitch is smaller than the repeating pitch. Furthermore, the invention described in claim 5 is a semiconductor device comprising: a substrate (10) having cell regions (RC) on which semiconductor elements are formed; a first conductivity type drift layer (12) formed on the surface side of the substrate and having a lower impurity concentration than the substrate; a first electrode (32) formed on the surface side of the drift layer; a second electrode (34) formed on the back side of the substrate; gate electrodes (26) arranged in a plurality at intervals in one direction, which turn on the semiconductor elements based on the applied voltage and cause current to flow between the first electrode and the second electrode; and a plurality of second conductivity type repeating regions (40, 41) arranged in the drift layer at intervals in the direction of the arrangement of gate electrodes, wherein the center line passing through the center of each gate electrode in the direction of the arrangement of gate electrodes and extending in the thickness direction of the substrate is defined as the cell center line (Oc), the distance between adjacent cell center lines in the direction of the arrangement of gate electrodes is defined as the cell pitch (Pc), and the center line passing through the center of each repeating region in the direction of the arrangement of gate electrodes and extending in the thickness direction of the substrate is repeated Let the center line be (Or, Or1), and the distance between adjacent repeating center lines in the gate electrode arrangement direction be the repeating pitch (Pr, Pr1). The cell pitch is different from the repeating pitch, and the repeating region has a plurality of wavy sections (400) that are connected to each other and arranged in an intersecting direction which is the direction that intersects the gate electrode arrangement direction. The wavy section has a straight section (410) that extends in the intersecting direction and a first inclined section (410) that is connected to the straight section and extends inclined with respect to the intersecting direction from the boundary with the straight section. 21) A semiconductor device comprising: an intermediate portion (430) connected to the first inclined portion and extending in the direction in which the straight portion extends from the boundary with the first inclined portion; and a second inclined portion (422) connected to the intermediate portion and extending inclined with respect to the intersecting direction from the boundary with the intermediate portion, wherein the end (4220) of the second inclined portion opposite to the intermediate portion is connected to the end (4100) of the straight portion of the adjacent wavy portion opposite to the first inclined portion, so that adjacent wavy portions are connected and aligned in the intersecting direction. Furthermore, the invention described in claim 6 is a semiconductor device comprising: a substrate (10) having cell regions (RC) on which semiconductor elements are formed; a first conductivity type drift layer (12) formed on the surface side of the substrate and having a lower impurity concentration than the substrate; a first electrode (32) formed on the surface side of the drift layer; a second electrode (34) formed on the back side of the substrate; gate electrodes (26) arranged in a plurality at intervals in one direction, which turn on the semiconductor elements based on the applied voltage and cause current to flow between the first electrode and the second electrode; and a plurality of repeating regions (40, 41) of a second conductivity type arranged in a plurality at intervals in the direction of the arrangement of gate electrodes, wherein the center line passing through the center of each gate electrode in the direction of the arrangement of gate electrodes and extending in the thickness direction of the substrate is defined as the cell center line (Oc), and the distance between adjacent cell center lines in the direction of the arrangement of gate electrodes is defined as the cell pitch (Pc), and the repeating region in the direction of the arrangement of gate electrodes In this semiconductor device, a repeating center line (Or, Or1) is defined as a center line passing through the center of each region and extending in the thickness direction of the substrate, and the repeating pitch (Pr, Pr1) is defined as the distance between adjacent repeating center lines in the gate electrode arrangement direction. The cell pitch is different from the repeating pitch, and the repeating region has a plurality of wavy sections (400) that are connected to each other and arranged in an intersecting direction which intersects the gate electrode arrangement direction. Each wavy section includes a first curved section (441) that curves and extends so that the tangent is inclined with respect to the intersecting direction, and a second curved section (442) that is connected to the first curved section and curves and extends from the boundary with the first curved section so that the tangent is inclined with respect to the intersecting direction. The end of the second curved section opposite to the first curved section (4420) is connected to the end of the first curved section in the adjacent wavy section (4410) so that adjacent wavy sections are connected and arranged in an intersecting direction. Furthermore, the invention described in claim 7 is a semiconductor device comprising: a substrate (10) having cell regions (RC) on which semiconductor elements are formed; a first conductivity type drift layer (12) formed on the surface side of the substrate and having a lower impurity concentration than the substrate; a first electrode (32) formed on the surface side of the drift layer; a second electrode (34) formed on the back side of the substrate; a plurality of gate electrodes (26) arranged at intervals in one direction, which turn on the semiconductor elements based on the applied voltage and cause current to flow between the first electrode and the second electrode; and a plurality of repeating regions (40, 41) of a second conductivity type arranged at intervals in the direction of the arrangement of gate electrodes within the drift layer, wherein the center line passing through the center of each gate electrode in the direction of the arrangement of gate electrodes and extending in the thickness direction of the substrate is defined as the cell center line (Oc), and the distance between adjacent cell center lines in the direction of the arrangement of gate electrodes is defined as the cell pitch (Pc), and the gate electrodes In this semiconductor device, the repeating centerlines (Or, Or1) are defined as the centerlines that pass through the center of each repeating region in the array direction and extend in the thickness direction of the substrate, and the distance between adjacent repeating centerlines in the array direction of the gate electrodes is defined as the repeating pitch (Pr, Pr1). The cell pitch is different from the repeating pitch, and the repeating region has a plurality of corrugated portions (400) that are connected to each other and arranged in an intersecting direction which is the direction that intersects the array direction of the gate electrodes. Each corrugated portion includes a first inclined portion (421) that extends inclined with respect to the intersecting direction, and a second inclined portion (422) that is connected to the first inclined portion and extends inclined with respect to the intersecting direction from the boundary with the first inclined portion. The end of the second inclined portion opposite to the first inclined portion (4220) is connected to the end of the first inclined portion in the adjacent corrugated portion (4210) so that adjacent corrugated portions are connected and arranged in an intersecting direction. Furthermore, the invention described in claim 8 is a semiconductor device comprising: a substrate (10) having cell regions (RC) on which semiconductor elements are formed; a first conductivity type drift layer (12) formed on the surface side of the substrate and having a lower impurity concentration than the substrate; a first electrode (32) formed on the surface side of the drift layer; a second electrode (34) formed on the back side of the substrate; gate electrodes (26) arranged in a plurality at intervals in one direction, which turn on the semiconductor elements based on the applied voltage and cause current to flow between the first electrode and the second electrode; and a plurality of second conductivity type repeating regions (40, 41) arranged in the drift layer at intervals in the direction of the arrangement of the gate electrodes, wherein the center line passing through the center of each gate electrode in the direction of the arrangement of the gate electrodes and extending in the thickness direction of the substrate is defined as the cell center line (Oc), the distance between adjacent cell center lines in the direction of the arrangement of the gate electrodes is defined as the cell pitch (Pc), and the center line passing through the center of each repeating region in the direction of the arrangement of the gate electrodes and extending in the thickness direction of the substrate is defined as the repeating center line (Or Let , Or1) be the repeat pitch (Pr, Pr1) in the direction of the gate electrode arrangement, and the distance between adjacent repeat centerlines is the repeat pitch, then the cell pitch is different from the repeat pitch, and the repeat region has a plurality of first wavy parts (401) that are connected to each other and arranged in an intersecting direction which is the direction that intersects the direction of the gate electrode arrangement, and a plurality of second wavy parts (402) that are connected to each other and arranged in an intersecting direction, and the first wavy parts and second wavy parts are arranged alternately with a gap in the direction of the gate electrode arrangement, and adjacent to each other A center line passing through the center between the meeting first and second wave-shaped sections and extending in the intersecting direction is defined as the inter-wave-shaped section center line (Ow). The second wave-shaped section is formed symmetrically with respect to the first wave-shaped section with respect to the inter-wave-shaped section center line and is located between adjacent inter-wave-shaped section center lines. Between the first and second wave-shaped sections, a first region (R1) and a second region (R2) are formed, the length of which in the gate electrode arrangement direction is smaller than the length of which in the gate electrode arrangement direction is smaller than the length of the first region.

[0007] As a result, even if the relative position of the repeating region with respect to the gate electrode in the gate electrode arrangement direction shifts, the range of change in the on-resistance of the semiconductor device is smaller compared to when the cell pitch is the same as the repeating pitch. Therefore, the variation in on-resistance in semiconductor devices is smaller compared to when the cell pitch is the same as the repeating pitch. Consequently, the variation in on-resistance between semiconductor devices is reduced.

[0008] The reference numerals in parentheses attached to each component indicate an example of the correspondence between that component and the specific components described in the embodiments described later. [Brief explanation of the drawing]

[0009] [Figure 1] A top view layout diagram of the semiconductor device of the first embodiment. [Figure 2] Cross-sectional view along line II-II in Figure 1. [Figure 3] Cross-sectional view of a comparative example semiconductor device. [Figure 4] Cross-sectional view of a comparative example semiconductor device. [Figure 5] Diagram showing the relationship between the amount of misalignment and the on-resistance. [Figure 6] Cross-sectional view of a semiconductor device when the displacement is one-quarter of the cell pitch. [Figure 7] Cross-sectional view of a semiconductor device when the displacement is half the cell pitch. [Figure 8] Cross-sectional view of the semiconductor device according to the second embodiment. [Figure 9] Cross-sectional view of the semiconductor device according to the third embodiment. [Figure 10] Cross-sectional view of line XX in Figure 9. [Figure 11] Cross-sectional view of the semiconductor device according to the fourth embodiment. [Figure 12] A top view of a portion of the semiconductor device in the fifth embodiment. [Figure 13] Figure 12 shows a cross-sectional view along line XIII-XIII. [Figure 14] Figure 12 shows a cross-sectional view along line XIV-XIV. [Figure 15] A schematic diagram showing electrons and electric currents flowing within a semiconductor device. [Figure 16] A schematic diagram showing electrons and electric currents flowing within a semiconductor device. [Figure 17] A top view of a portion of the semiconductor device in a modified example of the fifth embodiment. [Figure 18] A top view of a portion of the semiconductor device in a modified example of the fifth embodiment. [Figure 19] A top view of a portion of the semiconductor device in the sixth embodiment. [Figure 20] Figure 19 shows a cross-sectional view along the line XX-XX. [Figure 21] A schematic diagram showing electrons flowing within a semiconductor device. [Figure 22] A schematic diagram showing electrons flowing within a semiconductor device. [Figure 23] A top view of a portion of the semiconductor device in a modified example of the sixth embodiment. [Figure 24] A top view of a portion of the semiconductor device in a modified example of the sixth embodiment. [Modes for carrying out the invention]

[0010] The embodiments will be described below with reference to the drawings. In the following embodiments, parts that are the same or equivalent to each other will be denoted by the same reference numeral, and their descriptions will be omitted.

[0011] (First Embodiment) The semiconductor device 1 of this embodiment is used, for example, to drive electronic devices for vehicles. Here, as an example of the semiconductor device 1, a SiC semiconductor device on which a trench gate inverting type MOSFET is formed will be described.

[0012] As shown in Figures 1 and 2, the semiconductor device 1 is n + Type substrate 10, drift layer 12, p-type base region 14, n +It includes an n-type source region 16 and a p-type contact region 18. Further, the semiconductor device 1 includes a gate trench 22, a gate insulating film 24, a gate electrode 26, an interlayer insulating film 30, a source electrode 32, a drain electrode 34, a p-type guard ring 36, and a repetitive region 40.

[0013] n + The n-type substrate 10 is formed of SiC in a square shape. Also, + the n-type impurity concentration of the n-type substrate 10 is, for example, 1.0×10 19 / cm 3 . Further, + the surface of the n-type substrate 10 is, for example, a (0001) Si plane. Also, + the off direction of the n-type substrate 10 is, for example, in the <11-20> direction. Note that the n-type impurity is, for example, nitrogen, phosphorus, or the like.

[0014] Here, the region where the MOSFET is formed in the semiconductor device 1 is defined as the cell region RC. Also, the region surrounding this cell region RC is defined as the outer peripheral region RG.

[0015] The drift layer 12 has an n-type layer 120. - The n-type layer 120 is formed of SiC on the surface of the n-type substrate 10 in the cell region RC and the outer peripheral region RG. Also, - the n-type impurity concentration of the n-type layer 120 is lower than the n-type impurity concentration of the n-type substrate 10, and is, for example, 5.0×10 + ~2.0×10 - / cm + . Further, 15 the n-type layer 120 forms n-type columns 125 that are alternately repeated with p-type columns formed of the repetitive region 40, as will be described later. 16 / cm 3 . Further, - the n-type layer 120 forms n-type columns 125 that are alternately repeated with p-type columns formed of the repetitive region 40, as will be described later.

[0016] The p-type base region 14 is formed of SiC in the surface layer portion of the n-type layer 120 in the cell region RC. Also, the p-type impurity concentration of the p-type base region 14 is, for example, 2.0×10 - / cm 17 / cm3 Furthermore, the thickness of the p-type base region 14 is, for example, 300 nm. The p-type impurities are, for example, aluminum and boron.

[0017] n + The p-type source region 16 is formed on the surface of the p-type base region 14. + The n-type impurity concentration in the type source region 16 is n + The n-type impurity concentration is higher than that of the substrate 10, for example, 2.5 × 10 18 ~1.0×10 19 / cm 3 That is the case. Also, n + The thickness of the mold source region 16 is, for example, 500 nm.

[0018] The p-type contact region 18 is formed on the surface of the p-type base region 14. The p-type contact region 18 is formed of two n + It is sandwiched in the p-type source region 16. Furthermore, the p-type impurity concentration in the p-type contact region 18 is higher than the p-type impurity concentration in the p-type base region 14.

[0019] The gate trench 22 extends in one direction, for example, with the vertical direction of the paper in Figure 1 as its longitudinal direction. The gate trench 22 also extends through the p-type base region 14 and n + It penetrates the type source region 16, n - The mold layer reaches 120. Furthermore, the width of the gate trench 22 is, for example, 800 nm. Also, the depth of the gate trench 22 is 1000 nm. Furthermore, the sides of the gate trench 22 are the p-type base region 14 and n + It is in contact with the p-type source region 16. The portion of the p-type base region 14 that is in contact with the side surface of this gate trench 22 is n during MOSFET operation. + Type source area 16 and n - This is a channel region connecting to layer 120.

[0020] The gate insulating film 24 has electrical insulating properties. Furthermore, the gate insulating film 24 is formed on the inner wall surface of the gate trench 22, which includes the channel region. The gate insulating film 24 is formed, for example, by thermal oxidation of the inner wall surface of the gate trench 22, or by the use of a CVD (Chemical Vapor Deposition) method. The thickness of the gate insulating film 24 is, for example, 100 nm.

[0021] Multiple gate electrodes 26 are arranged at intervals in one direction. Furthermore, the gate electrodes 26 are formed on the surface of the gate insulating film 24 using doped poly-Si. This creates a trench gate structure with one direction as the longitudinal direction.

[0022] The interlayer insulating film 30 has electrical insulating properties. Furthermore, the interlayer insulating film 30 is n - Part of mold layer 120, n + It is formed on a portion of the mold source region 16 and on the surface of the gate insulating film 24.

[0023] The source electrode 32 corresponds to the first electrode and is made of multiple metals, such as Ni / Al. The source electrode 32 is also connected to n through a contact hole formed in the interlayer insulating film 30. + It is electrically connected to the p-type source region 16 and the p-type contact region 18. Furthermore, of the source electrodes 32, n + The portion of the source electrode 32 that contacts the n-type source region 16 is made of a metal that can make ohmic contact with n-type SiC. Furthermore, the portion of the source electrode 32 that contacts the p-type contact region 18 is made of a metal that can make ohmic contact with p-type SiC.

[0024] The drain electrode 34 corresponds to the second electrode, and in the cell region RC and the outer peripheral region RG, n + It is formed on the back side of the mold substrate 10.

[0025] The p-type guard ring 36 has n in the outer peripheral region RG. +It is formed on the surface layer of the mold substrate 10. Furthermore, the upper surface layout of the p-type guard ring 36 is a square shape with rounded corners. In addition, n is formed along the radial direction centered on the cell region RC. + The cross-section of the p-type guard ring 36 in the thickness direction of the mold substrate 10 is square-shaped. Furthermore, the p-type impurity concentration of the p-type guard ring 36 is, for example, the same as the p-type impurity concentration of the p-type base region 14, which is 2.0 × 10⁻⁶. 17 / cm 3 Furthermore, the thickness of the p-type guard ring 36 is, for example, 800 nm.

[0026] The repeating region 40 is, here, n in the arrangement direction of the gate electrodes 26. - The p-type column forms a superjunction structure that is alternately repeated with an n-type column 125 consisting of a type layer 120. Specifically, the repeating region 40 is n + In the thickness direction of the mold substrate 10, n is greater than the gate trench 22. + It is formed on the back side of the substrate 10 and is arranged in multiples with spacing in the direction of the arrangement of the gate electrodes 26. In addition, the repeating region 40 is formed in the cell region RC, n - It is formed of SiC within the mold layer 120. Furthermore, n + The distance from the bottom of the gate trench 22 to the top of the repeating region 40 in the thickness direction of the mold substrate 10 is, for example, 0.2 to 3.0 μm. The p-type impurity concentration in the repeating region 40 is, for example, 2.0 × 10⁻⁶. 16 ~5.0×10 17 / cm 3 Furthermore, in a cross-section different from that shown in Figure 2, the repeating region 40 is connected to the source electrode 32 via a connecting layer (not shown). This connects the p-type column consisting of the repeating region 40 to the n-type column. - A superjunction structure is formed in which n-type columns 125 consisting of type layers 120 are alternately repeated.

[0027] Here, the gate electrode 26 passes through the center of the gate electrode 26 in the direction of arrangement, and n +The center line extending in the thickness direction of the substrate 10 is defined as the cell center line Oc. Furthermore, in the arrangement direction of the gate electrodes 26, the distance between adjacent cell center lines Oc is defined as the cell pitch Pc. In addition, the repeating region 40 in the arrangement direction of the gate electrodes 26 passes through the center and n + Let the center line extending in the thickness direction of the substrate 10 be called the repeating center line Or. Also, in the arrangement direction of the gate electrodes 26, the distance between adjacent repeating center lines Or is called the repeating pitch Pr. Furthermore, let the width of the repeating region 40 be the region width Wr. Also, let the thickness of the repeating region 40 be the region thickness Tr. Furthermore, let i be a natural number of 2 or greater. Also, let j be a natural number of 2 or greater other than i. Note that the arrangement direction of the gate electrodes 26 is the length in the left-right direction of the paper in Figure 2. Furthermore, the region width Wr is the length of the repeating region 40 in the arrangement direction, which is the length in the left-right direction of the paper in Figure 2. Furthermore, the region thickness Tr is n + This is the length of the repeating region 40 in the thickness direction of the mold substrate 10, and is the length in the vertical direction of the paper in Figure 2.

[0028] The cell pitch Pc is, for example, 1.0 to 2.0 μm. The repeat pitch Pr is, for example, 1.2 to 3.0 μm. Furthermore, the cell pitch Pc is different from the repeat pitch Pr. Therefore, the relationship Pc ≠ Pr holds. Also, the region width Wr is about half of the repeat pitch Pr. Furthermore, the region thickness Tr is larger than the region width Wr, for example, 1.5 times or more the region width Wr. Also, the relationship i × Pc = j × Pr holds. For this reason, the cell center line Oc coincides with the repeat center line Or at intervals of the value i × Pc = j × Pr, and it is preferable that the value of i × Pc = j × Pr is 3 μm or more.

[0029] As described above, the semiconductor device 1 of the first embodiment is configured as described. Next, a method for manufacturing the semiconductor device 1 will be described.

[0030] Due to epitaxial growth, etc., n + n -The lower part of the mold layer 120 is formed. Next, by ion implantation of p-type impurities, n - A repeating region 40 is formed in the surface layer of the lower part of the mold layer 120. This results in a p-type column consisting of the repeating region 40 and n - A superjunction structure is formed in which n-type columns 125 consisting of type layers 120 are alternately repeated.

[0031] And, through epitaxial growth, n - On the lower part of the mold layer 120 and on the surface of the repeating region 40, n - The upper layer of the mold layer 120 is formed. In addition, by ion implantation of p-type impurities, n - A p-type base region 14 is formed in the upper surface layer of the mold layer 120. Furthermore, n-type impurities are ion-implanted. + After the p-type source region 16 is formed, the p-type contact region 18 is formed by ion implantation of p-type impurities. Furthermore, by ion implantation of p-type impurities, n - A p-type guard ring 36 is formed on the surface of the upper layer of the mold layer 120. In this embodiment, n - The concentration of n-type impurities in the lower part of mold layer 120 is n - The n-type impurity concentration is the same as that of the upper layer of the mold layer 120, - The concentration of n-type impurities in the upper layer of the mold layer 120 may differ from that of the upper layer.

[0032] Furthermore, the gate trench 22 is formed by RIE using a mask, i.e., anisotropic etching such as Reactive Ion Etching. In addition, a gate insulating film 24 is formed by thermal oxidation or CVD, and the inner wall surface of the gate trench 22 and n +The type source region 16 is covered. Then, Poly-Si doped with p-type or n-type impurities is formed by CVD or the like. Subsequently, this is etched back, leaving at least Poly-Si in the gate trench 22, thereby forming a gate electrode 26 with a cell pitch Pc different from the repeating pitch Pr. Furthermore, an interlayer insulating film 30 is formed by CVD or the like, and the gate insulating film 24 and gate electrode 26 are covered by the interlayer insulating film 30. After a mask (not shown) is formed on the surface of the interlayer insulating film 30, the portion of the mask located between each gate electrode 26, i.e., the portion corresponding to the p-type contact region 18 and its vicinity, is opened. Subsequently, the interlayer insulating film 30 is patterned using the mask, so that n + Contact holes are formed that expose the p-type source region 16 and the p-type contact region 18. Then, the source electrode 32 is formed by patterning the electrode material. Finally, n + Processes such as forming a drain electrode 34 on the back side of the mold substrate 10 are carried out.

[0033] As described above, the semiconductor device 1 is manufactured. In the semiconductor device 1 manufactured in this way, when the MOSFET is turned on, the voltage applied to the gate electrode 26 is controlled. At this time, a channel region is formed on the surface of the p-type base region 14 located on the side of the gate trench 22. As a result, n + Type source region 16, channel region, n - A drift layer 12 and n including a type layer 120 and an n-type column 125 + Current flows between the source electrode 32 and the drain electrode 34 via the substrate 10.

[0034] Here, when semiconductor device 1 is turned off, the equipotential lines extend from the cell region RC toward the outer peripheral region RG, and in the outer peripheral region RG, n + It extends from the back side to the front side of the substrate 10. Then, in the outer peripheral region RG, the equipotential lines are gradually terminated by the p-type guard ring 36 from the cell region RC toward the outer peripheral region RG. This improves the breakdown voltage of the semiconductor device 1.

[0035] Furthermore, when the MOSFET is turned off, the p-type column consisting of repeating regions 40 and n - A depletion layer is formed around the repeating region 40 by a superjunction structure in which n-type columns 125 consisting of mold layers 120 are alternately repeated. This improves the breakdown voltage of the semiconductor device 1. Here, the area around the repeating region 40 where the depletion layer is formed refers to the area between the bottom of the gate trench 22 and the repeating region 40, between the repeating regions 40 themselves, and between the repeating region 40 and n + This is between the mold substrates 10.

[0036] Furthermore, in semiconductor device 1, the variation in on-resistance between semiconductor devices 1 is reduced. This reduction in variation will be explained below.

[0037] To explain this reduction in variability, a comparative semiconductor device 900, such as those described in Patent Document 1, International Publication No. 2017-212773, and Japanese Patent Publication No. 2020-502792, will be described as a comparative example.

[0038] The comparison semiconductor device 900 is as shown in Figure 3, comparison n + Type board 910, n for comparison - Type layer 912, comparison p-type base region 914, comparison n + It includes a type source region 916 and a comparison p-type contact region 918. The comparison semiconductor device 900 also includes a comparison gate trench 922, a comparison gate insulating film 924, a comparison gate electrode 926, a comparison interlayer insulating film 930, a comparison source electrode 932, a comparison drain electrode 934, and a comparison p-type column region 940. + The substrate 910 is n + Corresponds to the substrate type 10. Comparison n - The mold layer 912 is n - Corresponds to type layer 120. The comparison p-type base region 914 corresponds to the p-type base region 14. Comparison n + The type source region 916 is n +The p-type source region 16 corresponds to the comparison p-type contact region 918. The comparison gate trench 922 corresponds to the gate trench 22. The comparison gate insulating film 924 corresponds to the gate insulating film 24. The comparison gate electrode 926 corresponds to the gate electrode 26. The comparison interlayer insulating film 930 corresponds to the interlayer insulating film 30. The comparison source electrode 932 corresponds to the source electrode 32. The comparison drain electrode 934 corresponds to the drain electrode 34. The comparison p-type column region 940 corresponds to the repeating region 40. Therefore, a detailed explanation of these components of the comparison semiconductor device 900 is omitted.

[0039] Furthermore, here, the comparison gate electrode 926 passes through the center of the comparison gate electrode 926 in the arrangement direction of the comparison n + The center line extending in the thickness direction of the substrate 910 is defined as the comparison cell center line Oc_ref. Furthermore, in the arrangement direction of the comparison gate electrodes 926, the distance between adjacent comparison cell center lines Oc_ref is defined as the comparison cell pitch Pc_ref. Additionally, the comparison n-type column region 940 passes through the center of the comparison p-type column region 940 in the arrangement direction of the comparison gate electrodes 926. + The center line extending in the thickness direction of the substrate 910 is defined as the comparison column center line Or_ref. Furthermore, in the arrangement direction of the comparison gate electrodes 926, the distance between adjacent comparison column center lines Or_ref is defined as the comparison column pitch Pr_ref. Note that the length of the comparison gate electrodes 926 in the arrangement direction is the length in the left-right direction of the paper in Figure 3.

[0040] Furthermore, in the comparison semiconductor device 900, the comparison cell pitch Pc_ref is the same as the comparison column pitch Pr_ref. Therefore, the relationship Pc_ref = Pr_ref holds true. Also, the comparison cell pitch Pc_ref is the same as the cell pitch Pc. Therefore, in the comparison semiconductor device 900, the relationship Pc_ref = Pr_ref = Pc holds true. In addition, the comparison column center line Or_ref passes through the center between adjacent comparison cell center lines Oc_ref.

[0041] Furthermore, when the comparison semiconductor device 900 is manufactured, let's assume that the relative position of the comparison p-type column region 940 with respect to the comparison gate electrode 926 is shifted by half the comparison cell pitch Pc_ref and the comparison column pitch Pr_ref, as shown in Figure 4. In this case, the comparison column centerline Or_ref coincides with the comparison cell centerline Oc_ref. Also, since the comparison cell pitch Pc_ref is the same as the comparison column pitch Pr_ref, the distance between the comparison gate electrode 926 and the comparison p-type column region 940 changes. As a result, each comparison p-type column region 940 is positioned relative to the comparison gate electrode 926 and the comparison n + It faces the thickness direction of the substrate 910. Therefore, when the comparison semiconductor device 900 is turned on, a channel region is formed in the comparison p-type base region 914, and the comparison n - The movement of electrons flowing through the mold layer 912 is hindered by each of the comparison p-type column regions 940. As a result, as shown in Figure 5, the on-resistance increases when the comparison column center line Or_ref passes through the center between adjacent comparison cell center lines Oc_ref. Therefore, among the comparison semiconductor devices 900, the variation in on-resistance among the comparison semiconductor devices 900 increases due to variations in the relative position of the comparison p-type column region 940 with respect to the comparison gate electrode 926 caused by manufacturing. In Figure 5, the amount of deviation is the amount of deviation in the relative position of the comparison p-type column region 940 with respect to the comparison gate electrode 926 in the alignment direction of the comparison gate electrode 926. The amount of deviation is shown as 0 when the comparison column center line Or_ref passes through the center between adjacent comparison cell center lines Oc_ref. Also, the amount of deviation when the comparison column center line Or_ref coincides with the comparison cell center line Oc_ref is shown as Pc_ref / 2. Furthermore, the relationship between the amount of displacement and the on-resistance in the comparative semiconductor device 900 is shown by a dashed line. Also, in Figures 3 and 4, the rightward direction on the page is considered the positive direction of the displacement, and the leftward direction on the page is considered the negative direction of the displacement.

[0042] In contrast, in the semiconductor device 1 of the present embodiment, the cell pitch Pc is different from the repetition pitch Pr. The meaning of the configuration in which this cell pitch Pc is different from the repetition pitch Pr will be described.

[0043] Here, for example, as shown in FIG. 6, it is assumed that the relative position of the repetition region 40 with respect to the gate electrode 26 in the arrangement direction of the gate electrode 26 is shifted by one-fourth of the cell pitch Pc from the arrangement shown in FIG. 2. In the arrangement shown in FIG. 2, a part of the repetition region 40 is opposite to the gate electrode 26 in the thickness direction of the n + type substrate 10. In the arrangement shown in FIG. 6, each repetition region 40 does not face the gate electrode 26 in the thickness direction of the n + type substrate 10. Therefore, when the MOSFET of the semiconductor device 1 is turned on and a channel region is formed in the p-type base region 14, the movement of electrons flowing through the n - type layer 120 is less hindered in the repetition region 40 compared to the arrangement shown in FIG. 2, and thus it becomes easier to flow. From this, at this time, as shown in FIG. 5, the on-resistance decreases compared to the arrangement shown in FIG. 2. In FIG. 5, the displacement amount is shown as 0 when in the arrangement shown in FIG. 2. Further, since the comparison cell pitch Pc_ref is the same as the cell pitch Pc, the displacement amount when it is one-fourth of the cell pitch Pc is shown as Pc_ref / 4 = Pc / 4. Furthermore, the right direction on the paper surface in FIG. 2 is defined as the positive direction of the displacement amount. Also, the left direction on the paper surface in FIG. 2 is defined as the negative direction of the displacement amount.

[0044] Also, as shown in FIG. 7, it is assumed that the relative position of the repetition region 40 with respect to the gate electrode 26 in the arrangement direction of the gate electrode 26 is shifted by one-half of the cell pitch Pc from the arrangement shown in FIG. 2. At this time, a part of the repetition region 40 faces the gate electrode 26 and the n + type substrate 10 in the thickness direction. Therefore, when the MOSFET of the semiconductor device 1 is turned on and a channel region is formed in the p-type base region 14, the n -The movement of electrons flowing through the mold layer 120 is hindered by the repeating region 40, making it more difficult for electrons to flow compared to the configuration shown in Figure 6. As a result, the on-resistance increases in this configuration compared to the configuration shown in Figure 6, as shown in Figure 5. Also, in this configuration, the distance relationship between the gate electrode 26 and the repeating region 40 corresponding to the gate electrode 26 is the same in the configuration shown in Figure 7 and the configuration shown in Figure 2. Consequently, the on-resistance in the configuration shown in Figure 7 is the same as the on-resistance in the configuration shown in Figure 2. Note that in Figure 5, the amount of deviation when the cell pitch Pc is half is shown as Pc_ref / 2 = Pc / 2.

[0045] Therefore, in the semiconductor device 1 of this embodiment, when the amount of misalignment is within the range of half the cell pitch Pc, the on-resistance decreases and increases with increasing misalignment. In contrast, in the comparative semiconductor device 900, when the amount of misalignment is within the range of half the cell pitch Pc, i.e., half the comparative cell pitch Pc_ref, the on-resistance only increases with increasing misalignment. Thus, as shown in Figure 5, the range of change in on-resistance due to the misalignment of the relative position of the repeating region 40 with respect to the gate electrode 26 in the arrangement direction of the gate electrode 26 is smaller compared to the comparative semiconductor device 900. As a result, the variation in on-resistance among the semiconductor devices 1 of this embodiment is smaller compared to the variation in on-resistance among the comparative semiconductor devices 900. For this reason, in the semiconductor device 1 of this embodiment, the variation in on-resistance among the semiconductor devices 1 is reduced because the cell pitch Pc is different from the repeating pitch Pr.

[0046] Furthermore, the semiconductor device 1 of the first embodiment also provides the following effects.

[0047] [1-1] The repeating region 40 is n in the direction of the arrangement of the gate electrodes 26 - This is a p-type column that forms a superjunction structure by alternating with an n-type column 125 consisting of a mold layer 120. As a result, when the MOSFET is turned off, a depletion layer is formed around the repeating region 40. Therefore, the breakdown voltage of the semiconductor device 1 is improved.

[0048] [1-2] As shown in FIG. 2, the region thickness Tr is larger than the region width Wr. As a result, compared with the case where the region thickness Tr is less than or equal to the region width Wr, n + In the thickness direction of the p-type substrate 10, the range in which the depletion layer spreads becomes larger, so that the breakdown voltage of the semiconductor device 1 is improved and the on-resistance becomes smaller.

[0049] [1-3] The gate electrode 26 and the repeating region 40 are formed such that i×Pc = j×Pr holds. As a result, in a part of the gate electrode 26 and the repeating region 40, the cell center line Oc and the repeating center line Or coincide. Therefore, the position of the gate electrode 26 and the repeating region 40 where they coincide is more likely to be a reference compared with the case where the cell center line Oc and the repeating center line Or do not coincide. From this, since the positional relationship between the gate electrode 26 and the repeating region 40 is easily determined, the manufacture of the gate electrode 26 and the repeating region 40 becomes easy. Therefore, the manufacture of the semiconductor device 1 becomes easy.

[0050] (Second Embodiment) In the second embodiment, the form of the repeating region 40 is different from that of the first embodiment. Other than this, it is the same as the first embodiment.

[0051] Specifically, in the semiconductor device 1 of the second embodiment, the repeating region 40 is a deep layer sandwiching an n - type layer 120 in the arrangement direction of the gate electrode 26 instead of the p-type column. The p-type impurity concentration of the repeating region 40 is, for example, the same as the p-type impurity concentration of the p-type base region 14, and is 2.0×10 17 / cm 3 . Further, as shown in FIG. 8, the region width Wr is larger than the region thickness Tr, and is, for example, 1.5 times or more the region thickness Tr. The deep layer is sometimes called an electric field relaxation layer.

[0052] As described above, the semiconductor device 1 of the second embodiment is configured as described. The second embodiment also provides the same effects as the first embodiment. Furthermore, the second embodiment also provides the effects described below.

[0053] [2-1] The repeating region 40 is a deep layer. This suppresses the penetration of the electric field into the bottom of the gate trench 22, even when a high voltage is applied. As a result, electric field concentration at the bottom of the gate trench 22 is mitigated. Consequently, the breakdown of the gate insulating film 24 is suppressed.

[0054] [2-2] The region width Wr is greater than the region thickness Tr. As a result, compared to the case where the region width Wr is less than or equal to the region thickness Tr, n - Because the movement of electrons flowing through the mold layer 120 is less hindered by the repeating region 40, the on-resistance is reduced.

[0055] (Third embodiment) In the third embodiment, the drift layer 12 is as shown in Figures 9 and 10, n - Instead of the mold layer 120, the semiconductor device has a first n-type layer 121, a second n-type layer 122, a third n-type layer 123, and an n-type current diffusion layer 124. Also, instead of the repeating region 40, the semiconductor device 1 has a first repeating region 41 and a second repeating region 42. Other than these, it is the same as the first embodiment.

[0056] The first n-type layer 121 has n in the cell region RC and the outer region RG. + It is formed of SiC on the surface of the substrate 10. Furthermore, the n-type impurity concentration of the first n-type layer 121 is n + The n-type impurity concentration is lower than that of the substrate 10, for example, 5.0 × 10 15 ~2.0×10 16 / cm 3 That is the case.

[0057] The second n-type layer 122 is formed of SiC on the surface of the first n-type layer 121. Furthermore, the n-type impurity concentration of the second n-type layer 122 is higher than that of the first n-type layer 121. + The concentration of n-type impurities is lower than that of the substrate 10.

[0058] The third n-type layer 123 is formed of SiC on the surface of the second n-type layer 122 and the first repeating region 41 described later. Furthermore, the n-type impurity concentration of the third n-type layer 123 is the same as that of the second n-type layer 122. For this reason, the n-type impurity concentration of the third n-type layer 123 is higher than that of the first n-type layer 121, and n + The concentration of n-type impurities is lower than that of the substrate 10.

[0059] The n-type current diffusion layer 124 expands the range over which current flows when the MOSFET is turned on. Specifically, the n-type current diffusion layer 124 is formed of SiC on the surface of the third n-type layer 123 and the second repeating region 42 described later. Furthermore, the n-type current diffusion layer 124 is n + In the thickness direction of the substrate 10, it is located between the third n-type layer 123 and the second repeating region 42 (described later) and the p-type base region 14. Furthermore, the n-type impurity concentration of the n-type current diffusion layer 124 is higher than that of the second n-type layer 122 and the third n-type layer 123. + The n-type impurity concentration is lower than that of the substrate 10, for example, 5.0 × 10 16 ~1.5×10 17 / cm 3 Furthermore, the thickness of the n-type current diffusion layer 124 is, for example, 300 nm to 700 nm. In addition, the gate trench 22 is located between the p-type base region 14 and n + It penetrates the type source region 16, n - Instead of reaching the mold layer 120, it reaches the n-type current diffusion layer 124.

[0060] The first repeating region 41 is formed of SiC in the cell region RC. Furthermore, the first repeating region 41 is formed within the second n-type layer 122 by ion implantation of p-type impurities. Additionally, the p-type impurity concentration in the first repeating region 41 is, for example, the same as the p-type impurity concentration in the repeating region 40, which is 2.0 × 10⁻⁶. 15 ~5.0×10 15 / cm 3 Furthermore, the first repeating region 41 is connected to the source electrode 32 via a connecting layer (not shown) and a second repeating region 42 (described later). This forms a first superjunction structure in which a first p-type column consisting of the first repeating region 41 and a first n-type column consisting of the second n-type layer 122 are alternately repeated.

[0061] The second repeating region 42 is formed of SiC in the cell region RC. Furthermore, the second repeating region 42 is formed within the third n-type layer 123 by ion implantation of p-type impurities. The second repeating region 42 is arranged in a direction perpendicular to the arrangement direction of the first repeating region 41. The second repeating region 42 also extends in the arrangement direction of the first repeating region 41. Moreover, the p-type impurity concentration in the second repeating region 42 is, for example, the same as that of the first repeating region 41. The second repeating region 42 is connected to the source electrode 32 via a connecting layer (not shown). This forms a second superjunction structure in which a second p-type column consisting of the second repeating region 42 and a second n-type column consisting of the third n-type layer 123 are alternately repeated. Note that the p-type impurity concentration in the second repeating region 42 may differ from that of the first repeating region 41.

[0062] Here, the first repeating region 41 passes through the center in the arrangement direction of the gate electrode 26, and n +The center line extending in the thickness direction of the substrate 10 is defined as the first repeating center line Or1. In addition, in the arrangement direction of the gate electrodes 26, the distance between adjacent first repeating center lines Or1 is defined as the first repeating pitch Pr1. Furthermore, the second repeating region 42 in the arrangement direction of the gate electrodes 26 passes through the center and n + The center line extending in the thickness direction of the substrate 10 is defined as the second repeating center line Or2. Furthermore, in the arrangement direction of the gate electrodes 26, the distance between adjacent second repeating center lines Or2 is defined as the second repeating pitch Pr2. Additionally, the width of the first repeating region 41 is defined as the first region width Wr1. The thickness of the first repeating region 41 is defined as the first region thickness Tr1. Furthermore, the width of the second repeating region 42 is defined as the second region width Wr2. The thickness of the second repeating region 42 is defined as the second region thickness Tr2. Note that the first region width Wr1 is the length of the first repeating region 41 in the arrangement direction, and in Figure 9, it is the length in the left-right direction of the paper. Furthermore, the first region thickness Tr1 is n + The length of the first repeating region 41 in the thickness direction of the mold substrate 10 is the length in the vertical direction of the paper in Figure 9. The second region width Wr2 is the length in the arrangement direction of the second repeating region 42, that is, the length in the direction perpendicular to the arrangement direction of the first repeating region 41, and is the length in the horizontal direction of the paper in Figure 10. Furthermore, the second region thickness Tr2 is n + This is the length of the second repeating region 42 in the thickness direction of the mold substrate 10, and is the length in the vertical direction of the paper in Figure 10.

[0063] The first repeat pitch Pr1 and the second repeat pitch Pr2 are, like the repeat pitch Pr, for example, 1.2 to 3.0 μm. Also, the first repeat pitch Pr1 is, for example, the same as the second repeat pitch Pr2. However, the first repeat pitch Pr1 may be different from the second repeat pitch Pr2.

[0064] Furthermore, the cell pitch Pc is different from the first repeat pitch Pr1 and the second repeat pitch Pr2. Therefore, the relationships Pc≠Pr1 and Pc≠Pr2 hold true. Also, the first region width Wr1 is about half the first repeat pitch Pr1. Furthermore, the first region thickness Tr1 is larger than the first region width Wr1, for example, it is 1.5 times or more the first region width Wr1. Also, the relationship i×Pc=j×Pr1 holds true. For this reason, the cell centerline Oc coincides with the first repeat centerline Or1 at intervals of the value i×Pc=j×Pr1. Furthermore, the value of i×Pc=j×Pr1 is preferably 3μm or more. Also, the second region width Wr2 is about half the second repeat pitch Pr2. Furthermore, the second region thickness Tr2 is larger than the second region width Wr2, for example, it is 1.5 times or more the second region width Wr2.

[0065] As described above, the semiconductor device 1 of the third embodiment is configured as described. The third embodiment also provides the same effects as the first embodiment. Furthermore, the third embodiment also provides the effects described below.

[0066] [3-1] In addition to the formation of the first superjunction structure, a second superjunction structure is formed in which a second p-type column consisting of a second repeating region 42 and a second n-type column consisting of a third n-type layer 123 are alternately repeated. As a result, when the MOSFET is turned off, a depletion layer is formed not only around the first repeating region 41 but also around the second repeating region 42. Therefore, the breakdown voltage of the semiconductor device 1 is improved compared to when the second repeating region 42 is not formed.

[0067] [3-2] The drift layer 12 is n +The substrate 10 has an n-type current diffusion layer 124 positioned between the third n-type layer 123 and the p-type base region 14 in the thickness direction. As a result, when the MOSFET of the semiconductor device 1 is turned on and a channel region is formed in the p-type base region 14, electrons injected from the source electrode 32 pass through that channel region and then reach the n-type current diffusion layer 124. Therefore, the range over which current flows in the n-type current diffusion layer 124 is widened, allowing current to flow to a position far from the trench gate structure, thereby reducing the on-resistance of the semiconductor device 1.

[0068] (Fourth Embodiment) In the fourth embodiment, the configuration of the second repeating region 42 differs from that of the third embodiment. Otherwise, it is the same as the third embodiment.

[0069] Specifically, the second repeating region 42 is a deep layer instead of a second p-type column. Therefore, the third n-type layer 123, which is alternately arranged with the second repeating region 42, functions as a JFET section. JFET stands for Junction Field Effect Transistor.

[0070] Furthermore, the p-type impurity concentration in the second repeating region 42 is, for example, the same as the p-type impurity concentration in the p-type base region 14, which is 2.0 × 10⁻⁶. 17 / cm 3 Furthermore, as shown in Figure 11, the width of the second region Wr2 is larger than the thickness of the second region Tr2, and is more than 1.5 times the thickness of the second region Tr2.

[0071] As described above, the semiconductor device 1 of the fourth embodiment is configured as described. The fourth embodiment also provides the same effects as the third embodiment. Furthermore, the fourth embodiment also provides the effects described below.

[0072] [4]n +The second repeating region 42, positioned between the gate trench 22 and the first repeating region 41 in the thickness direction of the mold substrate 10, is a deep layer. This suppresses the intrusion of an electric field from the second n-type layer 122 between the first repeating regions 41 to the bottom of the gate trench 22, even when a high voltage is applied. As a result, electric field concentration at the bottom of the gate trench 22 is mitigated. Consequently, the breakdown of the gate insulating film 24 is suppressed.

[0073] (Fifth embodiment) In the fifth embodiment, the configuration of the repeating region 40 differs from that of the first embodiment. Otherwise, it is the same as in the first embodiment.

[0074] Specifically, the repeating region 40 has a plurality of wavy portions 400, as shown in Figures 12 to 14. The wavy portions 400 are connected to each other and arranged in a direction perpendicular to the arrangement direction of the gate electrodes 26. Note that the direction perpendicular to the arrangement direction of the gate electrodes 26 corresponds to the direction intersecting the arrangement direction of the gate electrodes 26.

[0075] The wavy section 400 also includes a straight section 410, a first inclined section 421, an intermediate section 430, and a second inclined section 422. The straight section 410 extends in a direction perpendicular to the arrangement direction of the gate electrodes 26. The first inclined section 421 is connected to the straight section 410. Furthermore, the first inclined section 421 extends from its boundary with the straight section 410 in a direction perpendicular to the arrangement direction of the gate electrodes 26. The intermediate section 430 is connected to the first inclined section 421. Furthermore, the intermediate section 430 extends from its boundary with the first inclined section 421 in the direction in which the straight section 410 extends, in this case in a direction perpendicular to the arrangement direction of the gate electrodes 26. The second inclined section 422 is connected to the intermediate section 430. Furthermore, the second inclined section 422 extends from its boundary with the intermediate section 430 in a direction perpendicular to the arrangement direction of the gate electrodes 26. Furthermore, the second inclined portion 422 has a shape symmetrical to the first inclined portion 421 in a direction perpendicular to the arrangement direction of the gate electrodes 26, with respect to the intermediate portion 430. Therefore, the inclination angle of the second inclined portion 422 is the same as the inclination angle of the first inclined portion 421. In addition, the end 4220 of the second inclined portion 422 opposite to the intermediate portion 430 is connected to the end 4100 of the straight portion 410 of the adjacent wavy portion 400, opposite to the first inclined portion 421. As a result, adjacent wavy portions 400 are connected and aligned in a direction perpendicular to the arrangement direction of the gate electrodes 26.

[0076] Furthermore, let Nr be the p-type impurity concentration in the repeating region 40. -Let Nd be the n-type impurity concentration in the mold layer 120 and the n-type column 125. Let the first center line O1 be the center line that passes through the center between adjacent repeating regions 40 in the alignment direction of the gate electrodes 26 and extends along the wavy portion 400. Let the second center line O2 be the center line adjacent to the first center line O1 in the alignment direction of the gate electrodes 26. Let the first distance Wd1 be the distance from the first center line O1 to the repeating region 40 located between the first center line O1 and the second center line O2 in the alignment direction of the gate electrodes 26. Let the second distance Wd2 be the distance from the second center line O2 to the repeating region 40 located between the first center line O1 and the second center line O2 in the alignment direction of the gate electrodes 26. Let Wd be the sum of the first distance Wd1 and the second distance Wd2, i.e., Wd1 + Wd2.

[0077] And, n - The type layer 120, the n-type column 125, and the repeating region 40 are formed such that a × Nr × Wr = Nd × Wd holds true. Here, a is a coefficient between 0.5 and 1.5. Wr is the region width Wr, as described above, and corresponds to the length of the repeating region 40 in the direction of the gate electrode 26 arrangement.

[0078] As described above, the semiconductor device 1 of the fifth embodiment is configured as described. The fifth embodiment also provides the same effects as the first embodiment. Furthermore, the fifth embodiment also provides the effects described below.

[0079] [5-1] If the size of the region between the gate electrode 26 and the repeating region 40 is smaller than the size of the region between adjacent repeating regions 40, an increase and narrowing of the current path is likely to occur in the region between the gate electrode 26 and the repeating region 40. As a result, the resistance increases in the region between the gate electrode 26 and the repeating region 40, which makes it likely that the current flowing between the source electrode 32 and the drain electrode 34 will be uneven. Therefore, the on-resistance of the semiconductor device 1 increases.

[0080] In contrast, in the semiconductor device 1 of the fifth embodiment, the repeating region 40 has a wavy portion 400, and the wavy portion 400 includes a straight portion 410, a first inclined portion 421, an intermediate portion 430, and a second inclined portion 422.

[0081] As a result, the relative position of the repeating region 40 with respect to the gate electrode 26 changes depending on its position in a direction perpendicular to the arrangement direction of the gate electrode 26. Therefore, the areas where resistance increases in the region between the gate electrode 26 and the repeating region 40 are more easily dispersed compared to when the repeating region 40 is formed in a straight line extending in a direction perpendicular to the arrangement direction of the gate electrode 26. Consequently, as shown in Figures 15 and 16, the electrons and current flowing between the source electrode 32 and the drain electrode 34 tend to become more uniform overall. Thus, the increase in the on-resistance of the semiconductor device 1 is suppressed. Note that in Figures 15 and 16, the flow of electrons is e - The diagram is schematically shown by arrows. The flow of current is also schematically shown by Ie and arrows.

[0082] [5-2] The wavy portion 400 includes an intermediate portion 430. The intermediate portion 430 is connected to the first inclined portion 421 and the second inclined portion 422 and extends in the direction in which the straight portion 410 extends, in this case in a direction perpendicular to the arrangement direction of the gate electrodes 26.

[0083] As a result, the corners of the first inclined section 421 and the second inclined section 422 become gentler compared to the case where the first inclined section 421 and the second inclined section 422 are connected to each other. Therefore, the concentration of electric fields at the corners of the first inclined section 421 and the second inclined section 422 is mitigated.

[0084] [5-3] The n-type column 125 and the repeating region 40 are formed such that a × Nr × Wr = Nd × Wd holds true.

[0085] This makes it easier to ensure a balance of charge amounts between the n-type column 125 and the repeating region 40. As a result, the breakdown voltage of the semiconductor device 1 is suppressed.

[0086] (Modified version of the fifth embodiment) In the fifth embodiment, the wavy portion 400 may include a first curved portion 441 and a second curved portion 442 instead of the straight portion 410, the first inclined portion 421, the intermediate portion 430, and the second inclined portion 422, as shown in Figure 17.

[0087] The first curved section 441 extends in a curved manner such that the tangent to the first curved section 441 is inclined in a direction perpendicular to the arrangement direction of the gate electrodes 26. The second curved section 442 is connected to the first curved section 441. Furthermore, the second curved section 442 extends in a curved manner from the boundary with the first curved section 441 such that the tangent to the second curved section 442 is inclined in a direction perpendicular to the arrangement direction of the gate electrodes 26. In addition, the second curved section 442 has a shape symmetrical to the first curved section 441 in a direction perpendicular to the arrangement direction of the gate electrodes 26, with respect to the boundary with the first curved section 441. Furthermore, the end 4420 of the second curved section 442 opposite to the first curved section 441 is connected to the end 4410 of the first curved section 441 in the adjacent wavy section 400, opposite to the second curved section 442. As a result, adjacent corrugated portions 400 are connected and aligned in a direction perpendicular to the arrangement direction of the gate electrodes 26. Even in this configuration, the same effects as in the fifth embodiment are achieved. Here, symmetry includes the manufacturing tolerance range.

[0088] Furthermore, in the fifth embodiment, the wavy portion 400 may not include the straight portion 410 and the intermediate portion 430, but may include only the first inclined portion 421 and the second inclined portion 422, as shown in Figure 18. In this case, the first inclined portion 421 extends inclined with respect to a direction perpendicular to the arrangement direction of the gate electrodes 26. The second inclined portion 422 is connected to the first inclined portion 421. Moreover, the second inclined portion 422 extends inclined from the boundary with the first inclined portion 421 with respect to a direction perpendicular to the arrangement direction of the gate electrodes 26. In this case, the second inclined portion 422 has a shape symmetrical to the first inclined portion 421 in a direction perpendicular to the arrangement direction of the gate electrodes 26, with respect to the boundary with the first inclined portion 421. Furthermore, the end 4220 of the second inclined portion 422 opposite to the first inclined portion 421 is connected to the end 4210 of the adjacent corrugated portion 400 opposite to the second inclined portion 422 of the first inclined portion 421. As a result, adjacent corrugated portions 400 are connected and aligned in a direction perpendicular to the arrangement direction of the gate electrodes 26. Even with this configuration, the same effects as in the fifth embodiment are achieved.

[0089] (Sixth Embodiment) In the sixth embodiment, the configuration of the repeating region 40 differs from that of the fifth embodiment. Otherwise, it is the same as the fifth embodiment.

[0090] Specifically, the repeating region 40 has a plurality of first wavy sections 401 and a plurality of second wavy sections 402, as shown in Figures 19 and 20. The first wavy sections 401 correspond to the wavy section 400 described above and are connected to each other and arranged in a direction perpendicular to the arrangement direction of the gate electrodes 26. The second wavy sections 402 are connected to each other and arranged in a direction perpendicular to the arrangement direction of the gate electrodes 26. Furthermore, the second wavy sections 402 are arranged alternately with the first wavy sections 401 with gaps in the arrangement direction of the gate electrodes 26. Here, in the arrangement direction of the gate electrodes 26, the distance between adjacent first wavy sections 401 corresponds to the repeating pitch Pr. Also, in the arrangement direction of the gate electrodes 26, the distance between adjacent second wavy sections 402 corresponds to the repeating pitch Pr.

[0091] Here, the center line Ow between the corrugated portions is defined as the center line passing through the center between the adjacent first corrugated portion 401 and second corrugated portion 402 and extending in a direction perpendicular to the arrangement direction of the gate electrodes 26.

[0092] Furthermore, the second wavy portion 402 is formed symmetrically with respect to the first wavy portion 401 with respect to the center line Ow between the wavy portions. In addition, the second wavy portion 402 is located between adjacent center lines Ow between the wavy portions.

[0093] Furthermore, the first wavy section 401 includes a first straight section 411, a first inclined section 421, a first intermediate section 431, and a second inclined section 422. The first straight section 411 corresponds to the straight section 410 described above. In addition, the first intermediate section 431 corresponds to the intermediate section 430 described above. For this reason, a detailed explanation of the first straight section 411 and the first intermediate section 431 will be omitted.

[0094] The second wavy section 402 also includes a second straight section 412, a third inclined section 423, a second intermediate section 432, and a fourth inclined section 424. The second straight section 412 extends in the direction in which the first straight section 411 extends. The third inclined section 423 is connected to the second straight section 412. Furthermore, the third inclined section 423 extends from its boundary with the second straight section 412 in a direction symmetrical to the first inclined section 421 with respect to the center line Ow between the wavy sections. The second intermediate section 432 is connected to the third inclined section 423. Furthermore, the second intermediate section 432 extends from its boundary with the third inclined section 423 in a direction symmetrical to the first intermediate section 431 with respect to the center line Ow between the wavy sections. The fourth inclined section 424 is connected to the second intermediate section 432. Furthermore, the fourth inclined portion 424 extends from the boundary with the second intermediate portion 432 in a direction symmetrical to the second inclined portion 422, with respect to the center line Ow between the wavy portions.

[0095] Furthermore, the end 4240 of the fourth inclined portion 424 opposite to the second intermediate portion 432 is connected to the end 4120 of the second straight portion 412 of the adjacent second wavy portion 402 opposite to the third inclined portion 423. As a result, adjacent second wavy portions 402 are connected and aligned in a direction perpendicular to the arrangement direction of the gate electrodes 26.

[0096] Furthermore, a first region R1 and a second region R2 are formed between the first wavy portion 401 and the second wavy portion 402. The length of the second region R2 in the direction of arrangement of the gate electrodes 26 is smaller than the length of the first region R1 in the direction of arrangement of the gate electrodes 26.

[0097] Specifically, the region between the first inclined portion 421, the first intermediate portion 431, and the second inclined portion 422, and the region between the third inclined portion 423, the second intermediate portion 432, and the fourth inclined portion 424 corresponds to the first region R1. Also, the region between the first straight portion 411 and the second straight portion 412 corresponds to the second region R2. Furthermore, the length between the first straight portion 411 and the second straight portion 412 in the arrangement direction of the gate electrode 26 is smaller than the length between the first inclined portion 421 and the third inclined portion 423 in the arrangement direction of the gate electrode 26. Also, the length between the first straight portion 411 and the second straight portion 412 in the arrangement direction of the gate electrode 26 is smaller than the length between the first intermediate portion 431 and the second intermediate portion 432 in the arrangement direction of the gate electrode 26. Furthermore, the length between the first linear portion 411 and the second linear portion 412 in the arrangement direction of the gate electrodes 26 is smaller than the length between the second inclined portion 422 and the fourth inclined portion 424 in the arrangement direction of the gate electrodes 26.

[0098] As described above, the semiconductor device 1 of the sixth embodiment is configured as described. The sixth embodiment also provides the same effects as the fifth embodiment. Furthermore, the sixth embodiment also provides the effects described below.

[0099] [6] The repeating region 40 has a first wavy portion 401 and a second wavy portion 402. The second wavy portion 402 is formed symmetrically with respect to the first wavy portion 401 with respect to the center line Ow between the wavy portions, and is located between adjacent center lines Ow between the wavy portions. A first region R1 and a second region R2 are formed between the first wavy portion 401 and the second wavy portion 402. Furthermore, the length of the second region R2 in the direction of arrangement of the gate electrodes 26 is smaller than the length of the first region R1 in the direction of arrangement of the gate electrodes 26.

[0100] As a result, because the size of the second region R2 is relatively small, when the voltage applied to the drain electrode 34 is relatively high, as shown in Figure 21, the flow of electrons to the second region R2 is interrupted by the progression of the depletion layer. Therefore, the current to the second region R2 is interrupted. This suppresses the increase in the saturation current flowing between the source electrode 32 and the drain electrode 34. Also, when the voltage applied to the drain electrode 34 is relatively low, as shown in Figure 22, electrons flow through the second region R2, and therefore current flows through the second region R2. Therefore, the increase in the on-resistance of the semiconductor device 1 is suppressed. Thus, the short-circuit withstand capability of the semiconductor device 1 is improved while the increase in the on-resistance of the semiconductor device 1 is suppressed. Note that in Figures 21 and 22, the flow of electrons is e - And this is schematically represented by arrows.

[0101] (Modified version of the sixth embodiment) In the sixth embodiment, the first wavy portion 401 may include the first curved portion 441 and the second curved portion 442 as shown in Figure 23, instead of the first straight portion 411, the first inclined portion 421, the first intermediate portion 431, and the second inclined portion 422. Also, the second wavy portion 402 may include the third curved portion 443 and the fourth curved portion 444 instead of the second straight portion 412, the third inclined portion 423, the second intermediate portion 432, and the fourth inclined portion 424.

[0102] The third curved section 443 extends symmetrically with respect to the first curved section 441, with respect to the center line Ow between the wavy sections. The fourth curved section 444 extends symmetrically with respect to the second curved section 442, with respect to the center line Ow between the wavy sections. Furthermore, the end 4440 of the fourth curved section 444 opposite to the third curved section 443 is connected to the end 4430 of the third curved section 443 of the adjacent second wavy section 402, opposite to the fourth curved section 444. As a result, adjacent second wavy sections 402 are connected and aligned in a direction perpendicular to the arrangement direction of the gate electrodes 26. Even with this configuration, the same effects as in the sixth embodiment are achieved.

[0103] Furthermore, in the sixth embodiment, the first wavy portion 401 may not include the first straight portion 411 and the first intermediate portion 431, but instead include only the first inclined portion 421 and the second inclined portion 422, as shown in Figure 24. Moreover, the second wavy portion 402 may not include the second straight portion 412 and the second intermediate portion 432, but instead include only the third inclined portion 423 and the fourth inclined portion 424. In this case, the end 4240 of the fourth inclined portion 424 opposite to the third inclined portion 423 is connected to the end 4230 of the third inclined portion 423 of the adjacent second wavy portion 402 opposite to the fourth inclined portion 424. As a result, adjacent second wavy portions 402 are connected and aligned in a direction perpendicular to the arrangement direction of the gate electrodes 26. Even in this configuration, the same effects as in the sixth embodiment are achieved.

[0104] (Other embodiments) This disclosure is not limited to the embodiments described above, and modifications can be made to these embodiments as appropriate. Furthermore, it goes without saying that, in each of the embodiments described above, the elements constituting the embodiment are not necessarily essential, except in cases where they are explicitly stated to be particularly essential or where they are clearly considered essential in principle.

[0105] In the embodiments described above, SiC is used as the semiconductor material. However, the semiconductor material is not limited to SiC; it may also be Si or other materials.

[0106] In each of the above embodiments, the MOSFET has a trench gate structure. However, the MOSFET is not limited to having a trench gate structure and may have a planar gate structure. Also, in each of the above embodiments, the MOSFET is an n-channel MOSFET with the first conductivity type being n-type and the second conductivity type being p-type. However, the MOSFET is not limited to being an n-channel MOSFET and may be a p-channel MOSFET in which the conductivity types of each component are reversed.

[0107] In the embodiments described above, a MOSFET is given as an example of a semiconductor element. However, the semiconductor element is not limited to a MOSFET and may be other elements such as an IGBT.

[0108] In each of the above embodiments, n is aligned along the radial direction centered on the cell region RC. + The cross-section of the repeating region 40 in the thickness direction of the mold substrate 10 is rectangular, but is not limited to this, and may be other shapes, such as a rectangular shape with rounded corners.

[0109] In the first embodiment described above, the repeating region 40 is a p-type column forming a superjunction structure and is connected to the source electrode 32 via a connecting layer (not shown). In contrast, the repeating region 40 may be floating and not connected to the source electrode 32. In the third and fourth embodiments described above, the first repeating region 41 is a p-type column forming a first superjunction structure and is connected to the source electrode 32 via a connecting layer (not shown) and a second repeating region 42 described later. In contrast, the first repeating region 41 may be floating and not connected to the source electrode 32 via a connecting layer (not shown) and a second repeating region 42 described later.

[0110] In each of the above embodiments, n + The p-type source region 16 and the p-type contact region 18 extend in the longitudinal direction of the gate trench 22. In contrast, the p-type base region 14, n +The p-type source region 16 and the p-type contact region 18 are not limited to extending in the longitudinal direction of the gate trench 22. + The type source region 16 and the p-type contact region 18 may extend, for example, in a direction perpendicular to the longitudinal direction of the gate trench 22.

[0111] In the fourth embodiment described above, the first repeating region 41 is a first p-type column that is repeated alternately with the first n-type column to form a first superjunction structure, and the second repeating region 42 is a deep layer. In contrast, the first repeating region 41 is not limited to being a first p-type column, and may be, for example, a deep layer.

[0112] The above embodiments may be combined as appropriate.

[0113] (Perspective of this disclosure) [Perspective 1] A semiconductor device, A substrate (10) having a cell region (RC) on which a semiconductor element is formed, A first-conductivity type drift layer (12) is formed on the surface side of the substrate and has a lower impurity concentration than the substrate, The first electrode (32) formed on the surface side of the drift layer, A second electrode (34) formed on the back side of the substrate, Multiple gate electrodes (26) are arranged at intervals in one direction, and based on the applied voltage, they turn on the semiconductor element and cause a current to flow between the first electrode and the second electrode. Within the drift layer, there are multiple repeating regions (40, 41) of the second conductivity type that are spaced apart in the direction of the gate electrode arrangement, Equipped with, The cell center line (Oc) is defined as the center line passing through the center of each gate electrode in the arrangement direction of the gate electrodes and extending in the thickness direction of the substrate. In the arrangement direction of the gate electrodes, the distance between adjacent cell centerlines is defined as the cell pitch (Pc). The repeating centerlines (Or, Or1) are defined as the centerlines that pass through the center of each of the repeating regions in the arrangement direction of the gate electrodes and extend in the thickness direction of the substrate. In the arrangement direction of the gate electrodes, if the distance between adjacent repeating centerlines is defined as the repeating pitch (Pr, Pr1), A semiconductor device in which the cell pitch is different from the repeating pitch. [Perspective 2] The drift layer has a first conductivity type column, The semiconductor device according to viewpoint 1, wherein the repeating region is a column of a second conductivity type that forms a superjunction structure by being alternately repeated with the column of a first conductivity type in the direction of the arrangement of the gate electrodes. [Perspective 3] The semiconductor device according to viewpoint 2, wherein the length of the repeating region (Tr, Tr1) in the thickness direction of the substrate is greater than the length of the repeating region (Wr, Wr1) in the arrangement direction of the gate electrodes. [Perspective 4] The semiconductor device according to viewpoint 1, wherein the repeating region is a deep layer sandwiching the drift layer in the direction of the arrangement of the gate electrodes. [Perspective 5] The semiconductor device according to viewpoint 4, wherein the length of the repeating region (Wr, Wr1) in the direction of the gate electrode arrangement is greater than the length of the repeating region (Tr, Tr1) in the thickness direction of the substrate. [Perspective 6] Let the cell pitch be Pc, Let the repeating pitch be Pr. Let i be a natural number greater than or equal to 2. Let j be a natural number different from i mentioned above. The semiconductor device according to any one of views 1 to 5, wherein the gate electrode and the repeating region are formed such that i × Pc = j × Pr holds true. [perspective 7] The repeating region has a plurality of wavy portions (400) that are connected to each other and arranged in an intersecting direction which is the direction that intersects the arrangement direction of the gate electrodes. The aforementioned wavy portion is The straight section (410) extending in the aforementioned intersecting direction, A first inclined portion (421) is connected to the straight portion and extends inclined with respect to the intersecting direction from the boundary portion with the straight portion, An intermediate portion (430) is connected to the first inclined portion and extends in the direction in which the straight portion extends from the boundary with the first inclined portion, A second inclined portion (422) is connected to the aforementioned intermediate portion and extends inclined with respect to the intersecting direction from the boundary portion with the aforementioned intermediate portion, Includes, A semiconductor device according to any one of viewpoints 1 to 6, wherein the end (4220) of the second inclined portion opposite to the intermediate portion is connected to the end (4100) of the straight portion of the adjacent wavy portion opposite to the first inclined portion, so that adjacent wavy portions are connected and aligned in the intersecting direction. [Perspective 8] The repeating region has a plurality of wavy portions (400) that are connected to each other and arranged in an intersecting direction which is the direction that intersects the arrangement direction of the gate electrodes. The aforementioned wavy portion is A first curved section (441) in which the tangent line is curved and extends so as to be inclined with respect to the aforementioned intersection direction, A second curved section (442) is connected to the first curved section and extends curved from the boundary with the first curved section such that the tangent line is inclined with respect to the direction of intersection, Includes, A semiconductor device according to any one of viewpoints 1 to 6, wherein the end (4420) of the second curved portion opposite to the first curved portion is connected to the end (4410) of the adjacent wavy portion opposite to the second curved portion of the first curved portion, so that adjacent wavy portions are connected and aligned in the intersecting direction. [Perspective 9] The repeating region has a plurality of wavy portions (400) that are connected to each other and arranged in an intersecting direction which is the direction that intersects the arrangement direction of the gate electrodes. The aforementioned wavy portion is A first inclined portion (421) extending inclined with respect to the aforementioned intersecting direction, A second inclined portion (422) is connected to the first inclined portion and extends inclined with respect to the intersecting direction from the boundary portion with the first inclined portion, Includes, A semiconductor device according to any one of viewpoints 1 to 6, wherein the end (4220) of the second inclined portion opposite to the first inclined portion is connected to the end (4210) of the adjacent wavy portion of the first inclined portion, so that adjacent wavy portions are connected and aligned in the intersecting direction. [Perspective 10] Let the coefficient be a. The impurity concentration of the second conductivity type in the repeating region is Nr. Let Wr be the length of the repeating region in the direction of the array of the gate electrodes. The impurity concentration of the first conductivity type in the drift layer is Nd. The first center line (O1) is defined as a center line that passes through the center between adjacent repeating regions in the direction of the arrangement of the gate electrodes and extends in a direction along the wavy portion. The first center line and the center line adjacent to the gate electrode in the alignment direction are defined as the second center line (O2). The distance from the first center line to the repeating region located between the first center line and the second center line in the arrangement direction of the gate electrodes is defined as the first distance (Wd1). The distance from the second center line to the repeating region located between the first center line and the second center line in the arrangement direction of the gate electrodes is defined as the second distance (Wd2). If the sum of the first distance and the second distance is Wd, The above a is 0.5 or more and 1.5 or less, The semiconductor device according to any one of views 7 to 9, wherein the drift layer and the repeating region are formed such that a × Nr × Wr = Nd × Wd holds true. [Perspective 11] The aforementioned repeating region is A plurality of first wavy portions (401) are connected to each other and arranged in an intersecting direction which is a direction intersecting the arrangement direction of the gate electrodes, The aforementioned multiple second wavy portions (402) are connected to each other and arranged in the intersecting direction, It has, The first wavy portion and the second wavy portion are arranged alternately with spacing in the direction of the gate electrode arrangement, The center line passing through the center between the adjacent first and second wavy sections and extending in the intersecting direction is defined as the inter-wavy section center line (Ow). The second wavy portion is formed symmetrically with respect to the first wavy portion with respect to the center line between the wavy portions, and is located between adjacent center lines between the wavy portions. A semiconductor device according to any one of views 1 to 6, wherein a first region (R1) and a second region (R2) are formed between the first and second wavy portions, the length of which in the direction of the gate electrode arrangement is smaller than the length of the first region in the direction of the gate electrode arrangement.

[0114] In addition, when indicating the orientation of a crystal, a bar (-) should ideally be placed above the desired number. However, due to the limitations on expression imposed by electronic filing, a bar is placed before the desired number in this specification. [Explanation of Symbols]

[0115] 10 n + substrate type 12 Drift Layers 14 p-type base region 16 n + Type source area 18 p-type contact area 22 Gate Trench 26 gate 32 Source electrodes 34 Drain electrode 40 Repeating Regions

Claims

1. A semiconductor device, A substrate (10) having a cell region (RC) on which a semiconductor element is formed, A first-conductivity type drift layer (12) is formed on the surface side of the substrate and has a lower impurity concentration than the substrate, The first electrode (32) formed on the surface side of the drift layer, A second electrode (34) formed on the back side of the substrate, Multiple gate electrodes (26) are arranged at intervals in one direction, and based on the applied voltage, they turn on the semiconductor element and cause a current to flow between the first electrode and the second electrode. Within the drift layer, there are multiple repeating regions (40, 41) of the second conductivity type that are spaced apart in the direction of the arrangement of the gate electrodes, Equipped with, The cell center line (Oc) is defined as the center line passing through the center of each gate electrode in the arrangement direction of the gate electrodes and extending in the thickness direction of the substrate. In the arrangement direction of the gate electrodes, the distance between adjacent cell centerlines is defined as the cell pitch (Pc). The repeating centerlines (Or, Or1) are defined as the centerlines that pass through the center of each of the repeating regions in the arrangement direction of the gate electrodes and extend in the thickness direction of the substrate. In the arrangement direction of the gate electrodes, if the distance between adjacent repeating centerlines is defined as the repeating pitch (Pr, Pr1), The cell pitch is different from the repeating pitch. Let the cell pitch be Pc. Let the repeating pitch be Pr. Let i be a natural number greater than or equal to 2. Let j be a natural number different from i mentioned above. The gate electrode and the repeating region are formed such that i × Pc = j × Pr holds true. A semiconductor device where j ≠ 2 × i.

2. A semiconductor device, A substrate (10) having a cell region (RC) on which a semiconductor element is formed, A first-conductivity type drift layer (12) is formed on the surface side of the substrate and has a lower impurity concentration than the substrate, The first electrode (32) formed on the surface side of the drift layer, A second electrode (34) formed on the back side of the substrate, Multiple gate electrodes (26) are arranged at intervals in one direction, and based on the applied voltage, they turn on the semiconductor element and cause a current to flow between the first electrode and the second electrode. Within the drift layer, there are multiple repeating regions (40, 41) of the second conductivity type that are spaced apart in the direction of the arrangement of the gate electrodes, Equipped with, The cell center line (Oc) is defined as the center line passing through the center of each gate electrode in the arrangement direction of the gate electrodes and extending in the thickness direction of the substrate. In the arrangement direction of the gate electrodes, the distance between adjacent cell centerlines is defined as the cell pitch (Pc). The repeating centerlines (Or, Or1) are defined as the centerlines that pass through the center of each of the repeating regions in the arrangement direction of the gate electrodes and extend in the thickness direction of the substrate. In the arrangement direction of the gate electrodes, if the distance between adjacent repeating centerlines is defined as the repeating pitch (Pr, Pr1), The cell pitch is different from the repeating pitch. Let the cell pitch be Pc. Let the repeating pitch be Pr. Let i be a natural number greater than or equal to 2. Let j be a natural number different from i mentioned above. The gate electrode and the repeating region are formed such that i × Pc = j × Pr holds true. A semiconductor device in which the cell pitch is smaller than the repeating pitch.

3. The semiconductor device comprises a gate trench (22) and a gate insulating film (24), The gate electrode is provided in the gate trench via the gate insulating film, The semiconductor device according to claim 1 or 2, wherein the repeating region is formed on the back side of the substrate in the thickness direction of the substrate, relative to the gate trench.

4. The semiconductor device comprises a gate trench (22) and a gate insulating film (24), The gate electrode is provided in the gate trench via the gate insulating film, The semiconductor device according to claim 1 or 2, wherein the distance from the bottom of the gate trench to the top of the repeating region in the thickness direction of the substrate is 0.2 to 3.0 μm.

5. A semiconductor device, A substrate (10) having a cell region (RC) on which a semiconductor element is formed, A first-conductivity type drift layer (12) is formed on the surface side of the substrate and has a lower impurity concentration than the substrate, The first electrode (32) formed on the surface side of the drift layer, A second electrode (34) formed on the back side of the substrate, Multiple gate electrodes (26) are arranged at intervals in one direction, and based on the applied voltage, they turn on the semiconductor element and cause a current to flow between the first electrode and the second electrode. Within the drift layer, there are multiple repeating regions (40, 41) of the second conductivity type that are spaced apart in the direction of the arrangement of the gate electrodes, Equipped with, The cell center line (Oc) is defined as the center line passing through the center of each gate electrode in the arrangement direction of the gate electrodes and extending in the thickness direction of the substrate. In the arrangement direction of the gate electrodes, the distance between adjacent cell centerlines is defined as the cell pitch (Pc). The repeating centerlines (Or, Or1) are defined as the centerlines that pass through the center of each of the repeating regions in the arrangement direction of the gate electrodes and extend in the thickness direction of the substrate. In the arrangement direction of the gate electrodes, if the distance between adjacent repeating centerlines is defined as the repeating pitch (Pr, Pr1), The cell pitch is different from the repeating pitch. The repeating region has a plurality of wavy portions (400) that are connected to each other and arranged in an intersecting direction which is the direction that intersects the arrangement direction of the gate electrodes. The aforementioned wavy portion is The straight section (410) extending in the aforementioned intersecting direction, A first inclined portion (421) is connected to the straight portion and extends inclined with respect to the intersecting direction from the boundary portion with the straight portion, An intermediate portion (430) is connected to the first inclined portion and extends in the direction in which the straight portion extends from the boundary with the first inclined portion, A second inclined portion (422) is connected to the aforementioned intermediate portion and extends inclined with respect to the intersecting direction from the boundary portion with the aforementioned intermediate portion, Includes, A semiconductor device in which adjacent wavy portions are connected and aligned in the intersecting direction, such that the end (4220) of the second inclined portion opposite to the intermediate portion is connected to the end (4100) of the straight portion of the adjacent wavy portion opposite to the first inclined portion.

6. A semiconductor device, A substrate (10) having a cell region (RC) on which a semiconductor element is formed, A first-conductivity type drift layer (12) is formed on the surface side of the substrate and has a lower impurity concentration than the substrate, The first electrode (32) formed on the surface side of the drift layer, A second electrode (34) formed on the back side of the substrate, Multiple gate electrodes (26) are arranged at intervals in one direction, and based on the applied voltage, they turn on the semiconductor element and cause a current to flow between the first electrode and the second electrode. Within the drift layer, there are multiple repeating regions (40, 41) of the second conductivity type that are spaced apart in the direction of the arrangement of the gate electrodes, Equipped with, The cell center line (Oc) is defined as the center line passing through the center of each gate electrode in the arrangement direction of the gate electrodes and extending in the thickness direction of the substrate. In the arrangement direction of the gate electrodes, the distance between adjacent cell centerlines is defined as the cell pitch (Pc). The repeating centerlines (Or, Or1) are defined as the centerlines that pass through the center of each of the repeating regions in the arrangement direction of the gate electrodes and extend in the thickness direction of the substrate. In the arrangement direction of the gate electrodes, if the distance between adjacent repeating centerlines is defined as the repeating pitch (Pr, Pr1), The cell pitch is different from the repeating pitch. The repeating region has a plurality of wavy portions (400) that are connected to each other and arranged in an intersecting direction which is the direction that intersects the arrangement direction of the gate electrodes. The aforementioned wavy portion is A first curved section (441) in which the tangent line is curved and extends so as to be inclined with respect to the aforementioned intersection direction, A second curved section (442) is connected to the first curved section and extends curved from the boundary with the first curved section such that the tangent line is inclined with respect to the direction of intersection, Includes, A semiconductor device in which adjacent wavy portions are connected and aligned in the intersecting direction, such that the end (4420) of the second curved portion opposite to the first curved portion is connected to the end (4410) of the adjacent wavy portion opposite to the second curved portion of the first curved portion.

7. A semiconductor device, A substrate (10) having a cell region (RC) on which a semiconductor element is formed, A first-conductivity type drift layer (12) is formed on the surface side of the substrate and has a lower impurity concentration than the substrate, The first electrode (32) formed on the surface side of the drift layer, A second electrode (34) formed on the back side of the substrate, Multiple gate electrodes (26) are arranged at intervals in one direction, and based on the applied voltage, they turn on the semiconductor element and cause a current to flow between the first electrode and the second electrode. Within the drift layer, there are multiple repeating regions (40, 41) of the second conductivity type that are spaced apart in the direction of the arrangement of the gate electrodes, Equipped with, The cell center line (Oc) is defined as the center line passing through the center of each gate electrode in the arrangement direction of the gate electrodes and extending in the thickness direction of the substrate. In the arrangement direction of the gate electrodes, the distance between adjacent cell centerlines is defined as the cell pitch (Pc). The repeating centerlines (Or, Or1) are defined as the centerlines that pass through the center of each of the repeating regions in the arrangement direction of the gate electrodes and extend in the thickness direction of the substrate. In the arrangement direction of the gate electrodes, if the distance between adjacent repeating centerlines is defined as the repeating pitch (Pr, Pr1), The cell pitch is different from the repeating pitch. The repeating region has a plurality of wavy portions (400) that are connected to each other and arranged in an intersecting direction which is the direction that intersects the arrangement direction of the gate electrodes. The aforementioned wavy portion is A first inclined portion (421) extending inclined with respect to the aforementioned intersecting direction, A second inclined portion (422) is connected to the first inclined portion and extends inclined with respect to the intersecting direction from the boundary portion with the first inclined portion, Includes, A semiconductor device in which adjacent wavy portions are connected and aligned in the intersecting direction, such that the end (4220) of the second inclined portion opposite to the first inclined portion is connected to the end (4210) of the adjacent wavy portion opposite to the second inclined portion of the first inclined portion.

8. A semiconductor device, A substrate (10) having a cell region (RC) on which a semiconductor element is formed, A first-conductivity type drift layer (12) is formed on the surface side of the substrate and has a lower impurity concentration than the substrate, The first electrode (32) formed on the surface side of the drift layer, A second electrode (34) formed on the back side of the substrate, Multiple gate electrodes (26) are arranged at intervals in one direction, and based on the applied voltage, they turn on the semiconductor element and cause a current to flow between the first electrode and the second electrode. Within the drift layer, there are multiple repeating regions (40, 41) of the second conductivity type that are spaced apart in the direction of the arrangement of the gate electrodes, Equipped with, The cell center line (Oc) is defined as the center line passing through the center of each gate electrode in the arrangement direction of the gate electrodes and extending in the thickness direction of the substrate. In the arrangement direction of the gate electrodes, the distance between adjacent cell centerlines is defined as the cell pitch (Pc). The repeating centerlines (Or, Or1) are defined as the centerlines that pass through the center of each of the repeating regions in the arrangement direction of the gate electrodes and extend in the thickness direction of the substrate. In the arrangement direction of the gate electrodes, if the distance between adjacent repeating centerlines is defined as the repeating pitch (Pr, Pr1), The cell pitch is different from the repeating pitch. The aforementioned repeating region is A plurality of first wavy portions (401) are connected to each other and arranged in an intersecting direction which is a direction intersecting the arrangement direction of the gate electrodes, The aforementioned multiple second wavy portions (402) are connected to each other and arranged in the intersecting direction, It has, The first wavy portion and the second wavy portion are arranged alternately with spacing in the direction of the gate electrode arrangement, The center line passing through the center between the adjacent first and second wavy sections and extending in the intersecting direction is defined as the inter-wavy section center line (Ow). The second wavy portion is formed symmetrically with respect to the first wavy portion with respect to the center line between the wavy portions, and is located between the center lines of adjacent wavy portions. A semiconductor device having a first region (R1) and a second region (R2) formed between the first and second wavy portions, wherein the length in the direction of the gate electrode arrangement is smaller than the length of the first region in the direction of the gate electrode arrangement.

9. The drift layer has a column of the first conductivity type, The semiconductor device according to any one of claims 1, 2, 5, 6, 7, or 8, wherein the repeating region is a column of second conductivity that forms a superjunction structure by being alternately repeated with the column of first conductivity in the arrangement direction of the gate electrodes.

10. The semiconductor device according to claim 9, wherein the length of the repeating region (Tr, Tr1) in the thickness direction of the substrate is greater than the length of the repeating region (Wr, Wr1) in the arrangement direction of the gate electrodes.

11. The semiconductor device according to any one of claims 1, 2, 5, 6, 7, or 8, wherein the repeating region is a deep layer sandwiching the drift layer in the direction of the gate electrode arrangement.

12. The semiconductor device according to claim 11, wherein the length of the repeating region (Wr, Wr1) in the arrangement direction of the gate electrodes is greater than the length of the repeating region (Tr, Tr1) in the thickness direction of the substrate.

13. Let the coefficient be a. The impurity concentration of the second conductivity type in the repeating region is Nr. Let Wr be the length of the repeating region in the direction of the gate electrode arrangement. The impurity concentration of the first conductivity type in the drift layer is Nd. The first center line (O1) is defined as a center line that passes through the center between adjacent repeating regions in the direction of the arrangement of the gate electrodes and extends in a direction along the wavy portion. The first center line and the center line adjacent to the gate electrode in the alignment direction are defined as the second center line (O2). The distance from the first center line to the repeating region located between the first center line and the second center line in the arrangement direction of the gate electrodes is defined as the first distance (Wd1). The second distance (Wd2) is defined as the distance from the second center line to the repeating region located between the first center line and the second center line in the arrangement direction of the gate electrodes. If the sum of the first distance and the second distance is Wd, The above a is 0.5 or more and 1.5 or less, The semiconductor device according to any one of claims 5 to 7, wherein the drift layer and the repeating region are formed such that a × Nr × Wr = Nd × Wd holds true.

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