SOI wafer and method for manufacturing the same

Abstract

To provide an SOI wafer for a high-frequency integrated circuit board, which has an ability to reduce harmonics, the ability being superior to that of an SOI wafer comprising a conventional polysilicon layer as a trap-rich layer, and which can be processed easily, and a method for manufacturing the same.SOLUTION: An SOI wafer 1 includes, in this order on a silicon single crystal substrate 2 having a resistivity of 10 Ω cm or more to 5,000 Ω cm or less: a silicon epitaxial film 3 having a carbon concentration of 2×1019 atoms / cm3 or more and less than 3×1020 atoms / cm3 and including carbon defects; a dielectric layer 4; and a silicon single crystal substrate 5. The thickness of the silicon epitaxial film 3 satisfies the relationship: 6.6×1020×exp{-1.6×[thickness of epitaxial film (μm)]}>[carbon concentration of epitaxial film (atoms / cm3)].SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to SOI wafers and methods for manufacturing the same. [Background technology]

[0002] In recent years, the demand for high-capacity communication has been extremely high, and the development of equipment applicable to fifth and sixth generation mobile communication systems (commonly known as 5G and 6G) ​​is accelerating. These communication devices incorporate integrated circuits, and the active elements (such as transistors) and passive elements (such as inductors) that make up these integrated circuits require a high degree of operational stability in 5G and 6G environments. In particular, since these high-capacity communication systems are planned to use high frequency bands (millimeter wave to subterahertz band), there is a societal demand for device design and material development that combines excellent high-frequency characteristics with low power consumption.

[0003] When considering the materials required for semiconductor integrated circuits, silicon wafers fabricated by the Czochralski (CZ) method are sometimes used as substrates for high-frequency integrated circuits. In this case, the silicon wafers used need to have high substrate resistivity in order to achieve low resistance loss and good high-frequency characteristics.

[0004] Furthermore, in applications requiring superior high-frequency characteristics, wafers with trap-rich layers, as described in Patent Documents 1 and 2, are frequently used. This is because it is known that when a high-frequency signal is input to a device formed on a high-resistivity substrate, an inversion layer is formed within the substrate, causing a change in resistivity. By trapping carriers generated in the inversion layer at deep levels within the trap-rich layer, a high substrate resistivity can be maintained. In particular, passive devices use wafers in which a polysilicon layer is formed as a trap-rich layer on a high-resistivity substrate. In contrast, SOI wafers with trap-rich layers are widely used for active devices. In the structure of such an SOI wafer, a polysilicon layer as a trap-rich layer, an oxide film as a dielectric layer, and a single-crystal silicon layer are stacked in this order on a high-resistivity substrate.

[0005] However, the manufacturing of high-resistivity substrates, which are widely used as substrates for high-frequency integrated circuits, is technically difficult due to the need for resistivity control, resulting in low yields. In addition, polysilicon, which is used as a trap-rich layer, is difficult to process, leading to reduced productivity, and SOI structures that utilize polysilicon as a trap-rich layer have complicated manufacturing processes and significant cost issues. Therefore, there has been a need to develop technology to create SOI wafers that exhibit excellent high-frequency characteristics, particularly in reducing harmonics, by using wafers with a silicon epitaxial film formed on a silicon single-crystal substrate (hereinafter simply referred to as "silicon substrate") instead of using high-resistivity substrates.

[0006] Furthermore, wafers with a carbon-doped epitaxial film formed on a silicon substrate are described in Patent Documents 3 and 4. However, the wafers in Patent Documents 3 and 4 are basically epitaxial wafers consisting of a silicon substrate, a carbon-doped epitaxial film, and a silicon epitaxial film, and are mainly intended for use in image sensors. The use of the epitaxial layer as a trap-rich layer to form an SOI wafer has not been considered. Moreover, Patent Documents 3 and 4 do not describe heat treatment after epitaxial film formation, so no trap-rich layer is formed in the epitaxial film.

[0007] Furthermore, epitaxial wafers in which a carbon-doped epitaxial film is formed on a silicon substrate and then subjected to heat treatment are described in Patent Document 5. However, their use in wafers for high-frequency devices and SOI wafers with a trap-rich layer are not mentioned.

[0008] Patent Document 5 describes a development project that utilizes a silicon epitaxial film containing a high concentration of carbon as a gettering layer, and the heat treatment is intended to drive the gettering. Therefore, the heat treatment conditions are described as being in the range of 450 to 750°C for about 30 minutes. Although heat treatment at 800 to 1000°C is also mentioned to drive the gettering in a shorter time, it is presumed that the heat treatment time in that case is 30 minutes or less. However, it is difficult to obtain stable high-frequency characteristics under such conditions.

[0009] For the reasons stated above, the wafers described in Patent Documents 3, 4, and 5 are not suitable for use as wafers for high-frequency devices. [Prior art documents] [Patent Documents]

[0010] [Patent Document 1] Special Publication No. 2015-503853 [Patent Document 2] Japanese Patent Publication No. 2019-129195 [Patent Document 3] Japanese Patent Publication No. 2009-164590 [Patent Document 4] Japanese Patent Publication No. 2009-200231 [Patent Document 5] Japanese Patent Publication No. 2006-216934 [Overview of the project] [Problems that the invention aims to solve]

[0011] As described above, there has been a demand for SOI wafers that can reduce harmonics without using high-resistivity substrates and that can replace polysilicon layers as trap-rich layers for high-frequency integrated circuits. The inventors of this invention have diligently studied materials to meet these demands and have found that SOI wafers using epitaxial wafers in which a silicon epitaxial film containing a high concentration of carbon is formed on a substrate with normal resistivity are promising. This makes it possible to provide substrates for high-frequency integrated circuits that can be manufactured with fewer steps and have an easy processing process.

[0012] However, even with these substrates, the ability to reduce harmonics did not reach the level of conventional SOI wafers that used a polysilicon layer as a trap-rich layer, making the development of SOI wafers exhibiting superior high-frequency characteristics an urgent need.

[0013] The present invention has been made in view of the above problems, and aims to provide an SOI wafer for high-frequency integrated circuit substrates and a method for manufacturing the same, which uses an epitaxial wafer in which a silicon epitaxial film containing a high concentration of carbon is formed on a substrate with normal resistivity, and which has a superior ability to reduce harmonics compared to conventional SOI wafers that use a polysilicon layer as a trap-rich layer, and which is easy to process. [Means for solving the problem]

[0014] This invention was made to achieve the above objective, and involves a silicon single crystal substrate with a resistivity of 10 Ω·cm to 5000 Ω·cm, wherein the carbon concentration is 2 × 10 19 atoms / cm 3 The above 3 x 10 20 atoms / cm 3 The silicon epitaxial film, dielectric layer, and silicon single crystal film are provided in this order, and the silicon epitaxial film has a thickness of 6.6 × 10⁻¹⁰. 20 ×exp{-1.6×[epitaxial film thickness (μm)]}>[carbon concentration of epitaxial film (atoms / cm³)] 3 The present invention provides an SOI wafer characterized by satisfying the following conditions.

[0015] With such an SOI wafer, the silicon epitaxial film containing minute carbon defects acts as a trap-rich layer, resulting in superior high-frequency characteristics compared to conventional SOI wafers that use a polysilicon layer as the trap-rich layer.

[0016] In this case, the SOI wafer can be used as a wafer for high-frequency devices.

[0017] The SOI wafer according to the present invention has superior high-frequency characteristics compared to conventional SOI wafers that use a polysilicon layer as the trap-rich layer, because the silicon epitaxial film containing minute carbon defects acts as a trap-rich layer. Therefore, it is suitable for use as a wafer for high-frequency devices.

[0018] In this case, the carbon defects have a size of 10 nm or less and a density of 1 × 10 in the silicon epitaxial film. 10 cm -2 The above may be the case.

[0019] If such carbon defects are present, the resulting wafer will be more stable and possess superior high-frequency characteristics compared to conventional SOI wafers that use a polysilicon layer as a trap-rich layer.

[0020] The present invention also includes a step of preparing a first substrate which is a single crystal silicon substrate with a resistivity of 10 Ω·cm or more and 5000 Ω·cm or less, and on the first substrate, under reduced pressure, a carbon concentration of 2×10 19 atoms / cm 3 or more and 3×10 20 atoms / cm 3 less than that, a step of vapor-phase growing a silicon epitaxial film, and heat-treating the first substrate on which the silicon epitaxial film is formed at a heat treatment temperature of 900°C or more and 1100°C or less for a heat treatment time of 3 hours or more and 36 hours or less to form carbon defects in the silicon epitaxial film, a step of preparing a second substrate which is a single crystal silicon substrate, a step of forming a dielectric layer on the surface of the second substrate, and a step of bonding the epitaxial film formed on the first substrate and the dielectric layer of the second substrate, and in the step of vapor-phase growing the silicon epitaxial film, the thickness of the silicon epitaxial film satisfies 6.6×10 20 ×exp{-1.6×[thickness of the epitaxial film (μm)]}>[carbon concentration of the epitaxial film (atoms / cm 3 )], and a method for manufacturing an SOI wafer is provided, characterized in that a silicon epitaxial film satisfying this condition is formed.

[0021] According to such a method for manufacturing an SOI wafer, by vapor-phase growing the first substrate and then heat-treating it, minute carbon defects can be formed at a high density inside the silicon epitaxial film of the first substrate. Using the first substrate as a base wafer and manufacturing an SOI wafer by a bonding method, the silicon epitaxial film acts as a trap-rich layer, and an SOI wafer having higher frequency characteristics than an SOI wafer using a conventional polysilicon layer as a trap-rich layer can be easily manufactured.

[0022] The present invention also includes a step of preparing a first substrate which is a single crystal silicon substrate with a resistivity of 10 Ω·cm or more and 5000 Ω·cm or less, and on the first substrate, under reduced pressure, a carbon concentration of 2×1019 atoms / cm 3 The above 3 x 10 20 atoms / cm 3 The process includes the steps of vapor-phase growth of a silicon epitaxial film less than 6.6 × 10¹⁶, heat treatment of a first substrate on which the silicon epitaxial film is formed in an oxidizing atmosphere at a heat treatment temperature of 900°C to 1100°C and a heat treatment time of 3 hours to 36 hours to form carbon defects in the silicon epitaxial film and form an oxide film on the silicon epitaxial film, preparing a second substrate which is a silicon single crystal substrate, and bonding the oxide film formed on the epitaxial film formed on the first substrate to the second substrate, wherein in the step of vapor-phase growth of the silicon epitaxial film, the thickness of the silicon epitaxial film is 6.6 × 10¹⁶. 20 ×exp{-1.6×[epitaxial film thickness (μm)]}>[carbon concentration of epitaxial film (atoms / cm³)] 3 The present invention provides a method for manufacturing an SOI wafer, characterized by forming a silicon epitaxial film that satisfies the following conditions:

[0023] This method of manufacturing SOI wafers also allows for the formation of high-density microcarbon defects within the silicon epitaxial film of the first substrate. By using this as the base wafer and manufacturing an SOI wafer by a bonding method, the silicon epitaxial film acts as a trap-rich layer, making it possible to easily manufacture an SOI wafer with superior high-frequency characteristics compared to conventional SOI wafers that use a polysilicon layer as the trap-rich layer.

[0024] In this case, the second substrate, which does not have the oxide film formed on its surface, can be a substrate that has been cut into multiple substrates from a single silicon single crystal substrate and thinned before being bonded to the first substrate.

[0025] This makes it possible to cut out multiple silicon substrates, which serve as the second substrate required for the SOI wafer of the present invention, from a single silicon single crystal substrate, thus providing a significant advantage in terms of manufacturing cost.

[0026] In this case, the SOI wafer manufactured using the SOI wafer manufacturing method described above can be used as a wafer for high-frequency devices.

[0027] SOI wafers manufactured using the above-described SOI wafer manufacturing method have superior high-frequency characteristics compared to conventional SOI wafers that use a polysilicon layer as the trap-rich layer, because the silicon epitaxial film with densely formed minute carbon defects acts as a trap-rich layer. Therefore, they are particularly suitable for high-frequency device wafers.

[0028] In this case, the carbon defects have a size of 10 nm or less and a density of 1 × 10 in the silicon epitaxial film. 10 cm -2 The above may be the case.

[0029] By incorporating such carbon defects, it is possible to obtain an SOI wafer that is more stable and achieves better high-frequency characteristics than conventional SOI wafers that use a polysilicon layer as a trap-rich layer. [Effects of the Invention]

[0030] As described above, the SOI wafer of the present invention does not require a high resistivity substrate, and because the silicon epitaxial film containing minute carbon defects acts as a trap-rich layer, it has superior harmonic reduction capabilities compared to conventional SOI wafers that use a polysilicon layer as the trap-rich layer, making it suitable as a wafer for high-frequency devices. Furthermore, the manufacturing method of the SOI wafer of the present invention makes it possible to easily manufacture an SOI wafer with the aforementioned superior harmonic reduction capabilities. [Brief explanation of the drawing]

[0031] [Figure 1] This is a schematic diagram showing the SOI wafer according to the present invention. [Figure 2] This is a flowchart showing an example of a method for manufacturing an SOI wafer according to the first embodiment of the present invention. [Figure 3] This is a flowchart showing an example of a method for manufacturing an SOI wafer according to the second embodiment of the present invention. [Figure 4] This is a flowchart showing an example of a method for manufacturing an SOI wafer according to the third embodiment of the present invention. [Figure 5] This graph shows the conditions for carbon concentration and film thickness of the silicon epitaxial film in the SOI wafer of the present invention, where a void defect region is formed near the interface between the silicon epitaxial film and the silicon substrate. [Figure 6] This plot shows the changes in the second and third harmonic characteristics of an epitaxial wafer when heat treatment is performed on the epitaxial wafer with varying heat treatment times in Experimental Example 2. [Figure 7] This graph shows the relationship between the second harmonic characteristics and third harmonic characteristics of epitaxial wafers in Example 1 and Comparative Examples 1-2, and the carbon concentration. [Modes for carrying out the invention]

[0032] The present invention will be described in detail below, but the present invention is not limited to these descriptions.

[0033] As mentioned above, the demands for miniaturization, power saving, and cost reduction of communication equipment have created a need for inexpensive SOI wafers that can further improve high-frequency characteristics, particularly by reducing harmonics.

[0034] As a result of diligent research into the above problem, the inventors have found a silicon single crystal substrate with a resistivity of 10 Ω·cm to 5000 Ω·cm, and a carbon concentration of 2 × 10 19 atoms / cm 3 The above 3 x 10 20atoms / cm 3 The silicon epitaxial film, dielectric layer, and silicon single crystal film are provided in this order, and the silicon epitaxial film has a thickness of 6.6 × 10⁻¹⁰. 20 ×exp{-1.6×[epitaxial film thickness (μm)]}>[carbon concentration of epitaxial film (atoms / cm³)] 3 We have completed the present invention by discovering that an SOI wafer characterized by satisfying the following conditions has superior harmonic reduction capability compared to conventional SOI wafers using a polysilicon layer as a trap-rich layer, due to the action of a silicon epitaxial film containing minute carbon defects.

[0035] The present inventors also provide a first substrate which is a silicon single crystal substrate with resistivity of 10 Ω·cm or more and 5000 Ω·cm or less, and a first substrate which has a carbon concentration of 2 × 10 under reduced pressure. 19 atoms / cm 3 The above 3 x 10 20 atoms / cm 3 The process includes the steps of vapor-depositing a silicon epitaxial film less than 6.6 × 10¹⁶, heat-treating a first substrate on which the silicon epitaxial film is formed at a heat treatment temperature of 900°C to 1100°C and a heat treatment time of 3 hours to 36 hours to form carbon defects in the silicon epitaxial film, preparing a second substrate which is a silicon single crystal substrate, forming a dielectric layer on the surface of the second substrate, and bonding the epitaxial film formed on the first substrate and the dielectric layer of the second substrate, wherein in the step of vapor-depositing the silicon epitaxial film, the thickness of the silicon epitaxial film is 6.6 × 10¹⁶. 20 ×exp{-1.6×[epitaxial film thickness (μm)]}>[carbon concentration of epitaxial film (atoms / cm³)] 3 We have discovered that by a method for manufacturing SOI wafers characterized by forming a silicon epitaxial film that satisfies the following conditions, it is possible to easily manufacture SOI wafers having the aforementioned excellent harmonic reduction capability, and thus completed the present invention.

[0036] The present inventors also provide a first substrate which is a silicon single crystal substrate with resistivity of 10 Ω·cm or more and 5000 Ω·cm or less, and a first substrate which has a carbon concentration of 2 × 10 under reduced pressure. 19 atoms / cm 3 The above 3 x 10 20 atoms / cm 3 The process includes the steps of vapor-phase growth of a silicon epitaxial film less than 6.6 × 10¹⁶, heat treatment of a first substrate on which the silicon epitaxial film is formed in an oxidizing atmosphere at a heat treatment temperature of 900°C to 1100°C and a heat treatment time of 3 hours to 36 hours to form carbon defects in the silicon epitaxial film and form an oxide film on the silicon epitaxial film, preparing a second substrate which is a silicon single crystal substrate, and bonding the oxide film formed on the epitaxial film formed on the first substrate to the second substrate, wherein in the step of vapor-phase growth of the silicon epitaxial film, the thickness of the silicon epitaxial film is 6.6 × 10¹⁶. 20 ×exp{-1.6×[epitaxial film thickness (μm)]}>[carbon concentration of epitaxial film (atoms / cm³)] 3 We have discovered that by a method for manufacturing SOI wafers characterized by forming a silicon epitaxial film that satisfies the following conditions, it is possible to easily manufacture SOI wafers having the aforementioned excellent harmonic reduction capability, and thus completed the present invention.

[0037] [SOI wafer of the present invention] The SOI wafer of the present invention will be described below with reference to Figure 1. As shown in Figure 1, the SOI wafer 1 of the present invention comprises, in this order, a silicon epitaxial film 3 containing carbon defects, a dielectric layer 4, and a silicon single crystal substrate 5 on a silicon single crystal substrate 2.

[0038] The silicon single crystal substrate 2 has a resistivity of 10 Ω·cm to 5000 Ω·cm. Silicon single crystal substrates 2 with resistivity in this range can be used for high-frequency devices. The above resistivity is particularly preferably in the range of 1000 to 5000 Ω·cm, as this allows for good high-frequency characteristics and enables resistivity control during single-crystal manufacturing.

[0039] Silicon epitaxial film 3 has a typical carbon solid solubility of 3 × 10⁻¹⁰. 17 atoms / cm 3 (The maximum solid solubility of carbon at the melting point of silicon) is 2 × 10⁻¹⁰, which is significantly higher. 19 atoms / cm 3 The above 3 x 10 20 atoms / cm 3 It contains carbon at a concentration below a certain level and includes carbon defects. It also does not contain void defects.

[0040] The minute carbon defects contained in the silicon epitaxial film 3 are approximately 10 nm or less in size and have a density of approximately 1 × 10⁻¹⁶ in the silicon epitaxial film 3. 10 cm -2 It is preferable that the above conditions are met (if the carbon concentration of the silicon epitaxial film 3 is lower than that of the present invention, carbon defects of approximately 25 nm or larger are included at a low density). The size of the carbon defects is measured by measuring the longest portion of the defects detected by cross-sectional TEM. This is also the case in the SOI wafer manufacturing method described later.

[0041] Furthermore, to ensure that the silicon epitaxial film 3 does not contain void defects, the thickness and carbon concentration of the silicon epitaxial film 3 are set to 6.6 × 10⁻¹⁰. 20 ×exp{-1.6×[epitaxial film thickness (μm)]}>[carbon concentration of epitaxial film (atoms / cm³)] 3 The relationship ) is satisfied.

[0042] The densely packed, minute carbon defects within the silicon epitaxial film 3 create new deep energy levels within the film, resulting in a trap-rich SOI wafer. Such SOI wafers possess the advantages of minute carbon defects while eliminating the disadvantages of void defects, resulting in superior harmonic characteristics. This is thought to be because the silicon epitaxial film, with its densely packed minute carbon defects, acts as a trap-rich layer, inhibiting the formation of an inversion layer. Therefore, it is a suitable substrate for high-frequency device wafers and active elements.

[0043] The upper and lower limits of the carbon concentration in silicon epitaxial film 3 are 2.0 × 10⁻⁶ 19 atoms / cm 3 The above is 3 x 10 20 atoms / cm 3 It should be less than 2.0 × 10⁻⁶. At such concentrations, the carbon concentration is significantly higher than the typical carbon solid solubility, making it possible to form dense, minute carbon defects through heat treatment, thus achieving sufficient high-frequency characteristics. If the carbon concentration falls below the lower limit, the degree of carbon supersaturation is small, resulting in the formation of coarse carbon defects and a low density, which prevents the achievement of sufficient high-frequency characteristics. On the other hand, if the carbon concentration is 2.0 × 10⁻⁶ 19 atoms / cm 3 In the above case, if the film thickness exceeds a predetermined value, void defects are formed, and when they coexist with minute carbon defects inside the film, although the high-frequency characteristics improve with heat treatment, the degree of improvement becomes small. This is thought to be because the volume of void defects is much larger than that of carbon defects, so the influence of void defects becomes dominant. Therefore, in order for an SOI wafer to have significantly superior high-frequency characteristics, it is important that the film thickness of the silicon epitaxial film 3 is thin enough so that void defects do not form. Also, the carbon concentration is 3 × 10⁻⁶. 20 atoms / cm 3 Beyond this point, the film quality of the silicon epitaxial film 3 deteriorates, and productivity also decreases. The upper limit of the carbon concentration depends on the silicon epitaxial film thickness, and the upper limit of the carbon concentration is 6.6 × 10⁻⁶. 20×exp{-1.6×[epitaxial film thickness (μm)]}>[carbon concentration of epitaxial film (atoms / cm³)] 3 This can be determined from the relationship between ( ). With such a concentration, stable and excellent high-frequency characteristics are obtained. This is also true in the manufacturing method of SOI wafers described later.

[0044] The upper and lower limits of the thickness of the silicon epitaxial film 3 can be set to, for example, 0.1 μm or more and 2.5 μm or less, taking productivity and cost into consideration. Within this range, a lower cost can be achieved while maintaining sufficient high-frequency characteristics. However, if the carbon concentration of the silicon epitaxial film is 2.0 × 10⁻⁶ 19 atoms / cm 3 In the above case, heat treatment of the silicon epitaxial film makes it easier for void defect regions to form at the interface between the silicon epitaxial film and the silicon substrate. Since void defects are aggregates of vacancies, reducing the thickness of the silicon epitaxial film 3 reduces the amount of vacancies generated inside the film, thereby suppressing the formation of void defects. Therefore, it is necessary to adjust the film thickness according to the carbon concentration. From the above, the relationship between the thickness of the silicon epitaxial film 3 and the carbon concentration is 6.6 × 10⁻⁶. 20 ×exp{-1.6×[epitaxial film thickness (μm)]}>[carbon concentration of epitaxial film (atoms / cm³)] 3 The following conditions must be met.

[0045] (Experimental Example 1) The following describes the results of an experimental evaluation of the relationship between carbon concentration and film thickness in carbon-doped silicon epitaxial films formed on a silicon substrate, focusing on preventing the formation of void defects in the epitaxial film.

[0046] The inventors used a vacuum CVD apparatus to produce 2.0 × 10⁻⁶ 19 atoms / cm 3 A silicon epitaxial film containing the above amount of carbon and varying in thickness (carbon concentration: 2.0 × 10⁻⁶) 19 atoms / cm 3The samples had film thicknesses of 1 μm, 1.5 μm, 2 μm, 3 μm, and 5.5 μm, and a carbon concentration of 1.0 × 10⁻⁶. 20 atoms / cm 3 In the sample, the film thickness was 1 μm, 2 μm, and 3 μm, and the carbon concentration was 3.0 × 10⁻⁶. 20 atoms / cm 3 and 1.0 × 10 21 In the sample, a film thickness of 1 μm was formed on a silicon substrate. The carbon concentration and thickness of the silicon epitaxial film were adjusted by changing the amount of source gas introduced and the processing time in the reduced-pressure CVD furnace.

[0047] To evaluate the presence or absence of void defect regions in these epitaxial wafers, the obtained epitaxial wafers were subjected to a heat treatment at 1000°C for 36 hours in an oxygen atmosphere. After the heat treatment, planar TEM observation was performed on thin section samples (approximately 500 nm thick) containing the interface between the silicon epitaxial film and the silicon substrate of each epitaxial wafer.

[0048] The results of Experiment Example 1 showed a carbon concentration of 2.0 × 10⁻⁶. 19 atoms / cm 3 In the sample, the film thickness was 3 μm or more, and the carbon concentration was 1.0 × 10⁻⁶ 20 atoms / cm 3 In the sample, the film thickness was 2 μm or more, and the carbon concentration was 3.0 × 10⁻⁶ 20 atoms / cm 3 In the above samples, the film thickness was 1 μm, and it was found that a void defect region was formed near the interface between the silicon epitaxial film and the silicon substrate.

[0049] Based on the above results, the inventors concluded that the conditions under which void defects are formed in a silicon epitaxial film by heat treatment vary depending on both the carbon concentration contained in the silicon epitaxial film and the thickness of the silicon epitaxial film.

[0050] Figure 5 shows the results of organizing the presence or absence of void defect regions, as shown in Experimental Example 1, based on the carbon concentration in the silicon epitaxial film and the thickness of the silicon epitaxial film. Figure 5 is a graph showing the conditions for carbon concentration and film thickness of a silicon epitaxial film in which a void defect region is formed near the interface between the silicon epitaxial film and the silicon substrate in the epitaxial wafer of the present invention. In this case, the region in the figure where a void defect region is formed at the interface between the silicon epitaxial film and the silicon substrate after heat treatment is indicated by a dashed line and shaded area. That is, the white area in the figure is the region in which a void defect region is not formed in the silicon epitaxial film. This is because the relationship between the carbon concentration contained in the silicon epitaxial film and the film thickness is 6.6 × 10⁻⁶. 20 ×exp{-1.6×[epitaxial film thickness (μm)]}>[carbon concentration of epitaxial film (atoms / cm³)] 3 The range can satisfy the following conditions:

[0051] According to the SOI wafer of the present invention, there is no need for a high-resistivity substrate, and because the silicon epitaxial film containing minute carbon defects at high density acts as a trap-rich layer, it has superior harmonic reduction capabilities compared to conventional SOI wafers that use a polysilicon layer as the trap-rich layer, making it suitable as a wafer for high-frequency devices.

[0052] Next, a method for manufacturing an SOI wafer according to the present invention will be described.

[0053] [First Embodiment] Figure 2 shows an example of a method for manufacturing an SOI wafer according to the first embodiment of the present invention. This method utilizes a silicon epitaxial film in which minute carbon defects are formed at high density as a trap-rich layer to manufacture an SOI wafer.

[0054] First, we will explain the manufacturing method for the epitaxial wafer of the first substrate, which will serve as the base wafer.

[0055] (Step to prepare the first circuit board) As the first substrate, a silicon substrate with a resistivity of 10 to 5000 Ω·cm is prepared.

[0056] (Step of vapor-phase growing a silicon epitaxial film) Next, on a first substrate, a silicon epitaxial film having a carbon concentration of 2×10 19 atoms / cm 3 or more and less than 3×10 20 atoms / cm 3 is vapor-phase grown under reduced pressure. Specifically, by supplying a gas containing silicon atoms and carbon atoms onto a silicon substrate under reduced pressure, 2×10 19 atoms / cm 3 or more and less than 3×10 20 atoms / cm 3 is obtained on the surface of the first substrate, and the relationship between the thickness and carbon concentration of the silicon epitaxial film satisfies 6.6×10 20 ×exp{-1.6×[thickness of epitaxial film (μm)]}>[carbon concentration of epitaxial film (atoms / cm 3 ). A silicon epitaxial film (hereinafter, also simply referred to as "epitaxial film") is vapor-phase grown.

[0057] By performing the vapor-phase growth of the epitaxial film under reduced pressure, the concentration of impurities other than carbon doped in the epitaxial film can be reduced. The pressure for forming the epitaxial film may be reduced pressure, and there is no particular limitation, but it is preferably performed at about 10 Torr (about 1.3 kPa), for example, 5 Torr (about 0.67 kPa) or more and 20 Torr (about 2.7 kPa) or less.

[0058] For carbon doping in the vapor-phase growth of the epitaxial film, as described above, a gas (source gas) containing silicon atoms and carbon atoms is used. As the source gas, it is preferable to include at least one of monomethylsilane gas and trimethylsilane gas. By using these gases, good carbon doping can be easily performed on the silicon epitaxial film. Also, as the carrier gas during source gas supply, the atmosphere of the vapor-phase growth may contain hydrogen, argon, or the like.

[0059] Epitaxial films under reduced pressure can be formed more effectively by vapor phase growth at, for example, 600-1000°C.

[0060] Furthermore, it is preferable to appropriately set the pressure, temperature, time, and raw material gas concentration of the vapor phase growth so that the thickness of the epitaxial film to be formed reaches the desired thickness. The thickness of the epitaxial film can be, for example, 0.1 μm or more and 2.5 μm or less, but 6.6 × 10 20 ×exp{-1.6×[epitaxial film thickness (μm)]}>[carbon concentration of epitaxial film (atoms / cm³)] 3 This is not limited to the above, as long as the following conditions are met. With such a relationship between the carbon concentration and film thickness of the epitaxial film, no void defects will be formed in the epitaxial film.

[0061] (Step to form carbon defects) Subsequently, by heat-treating the epitaxial wafer having the epitaxial film, minute carbon defects can be formed at high density within the epitaxial film.

[0062] The method of heat treatment after deposition of the epitaxial film is not particularly limited; for example, a general heat treatment furnace for silicon wafers or a chamber used for vapor phase growth of the epitaxial film can be used.

[0063] The lower limit of the heat treatment temperature is set at 900°C or higher, and the upper limit is set at 1100°C or lower. By doing so, it is possible to form minute carbon defects at high density using a general heat treatment furnace, while suppressing the effects of heavy metal diffusion, thereby improving manufacturing efficiency.

[0064] Furthermore, the heat treatment time should be between 3 and 36 hours. This process creates sufficiently minute carbon defects, resulting in improved quality and an epitaxial wafer with superior manufacturing efficiency.

[0065] Here, the results of our investigation into the heat treatment time in heat treatment are explained in Experimental Example 2 below.

[0066] (Experimental Example 2) The heat treatment time required to form high-density minute carbon defects was determined by the following experiment. To conduct a basic investigation into the heat treatment time required for manufacturing epitaxial wafers exhibiting excellent harmonic characteristics, the carbon concentration during film deposition was set to 1.0 × 10⁻⁶. 20 atoms / cm 3 An epitaxial wafer was subjected to heat treatment in an oxygen atmosphere at 1000°C, with the heat treatment time varying from 15 minutes to 12 hours. To investigate the high-frequency characteristics of this epitaxial wafer, the second and third harmonic characteristics were measured.

[0067] The high-frequency characteristics of an SOI wafer are measured as follows. To measure harmonic characteristics [second harmonic characteristics (2HD) and third harmonic characteristics (3HD)], first, the top layer of silicon single crystal film is removed, and then a co-planar waveguide (CPW) is formed on a dielectric layer (e.g., oxide film) using a metal (e.g., aluminum). Probes are then grounded to both ends of this metal electrode. Subsequently, a high-frequency signal is input from one of the electrodes, and the second and third harmonics output from the other side are measured (e.g., input signal frequency: 1 GHz, input power: 15 dBm).

[0068] For the epitaxial wafers used in this experiment, aluminum electrodes with a line length of 2200 μm were formed on silicon epitaxial films heat-treated for the heat treatment time within the range described above, and the second and third harmonic characteristics were measured. The measurement results are shown in Figure 6. As shown in Figure 6, for samples with a heat treatment time of 3 hours or more, when the input signal frequency was 1 GHz, the second harmonic characteristics were all around -50 dBm, and the third harmonic characteristics were all below -60 dBm.

[0069] These results indicate that in order to manufacture epitaxial wafers exhibiting excellent harmonic characteristics by forming a high density of minute carbon defects, heat treatment at 1000°C for at least 3 hours is necessary. Therefore, the heat treatment time should be between 3 and 36 hours. The upper limit was set at 36 hours or less, considering productivity, as excessively long treatment times do not change the effect of forming carbon defects. By doing so, sufficiently minute carbon defects are formed, resulting in high quality and an epitaxial wafer that is superior from the standpoint of manufacturing efficiency.

[0070] Based on the above, by directly placing an epitaxial wafer into a heat treatment furnace heated to around 1000°C and heat-treating it for approximately 3 to 36 hours, minute carbon defects are formed at high density within the epitaxial film created by vapor phase growth under reduced pressure. In this case, the type of gas used during heat treatment is not particularly limited and can be, for example, oxygen gas or inert gases such as argon or nitrogen.

[0071] After the above heat treatment, the formation of a dielectric layer on the epitaxial film is not essential, and it is acceptable even if no dielectric layer is formed on the epitaxial film.

[0072] In this way, an epitaxial wafer (base wafer) used as the trap-rich layer in the SOI wafer of the first embodiment of the present invention can be manufactured. The epitaxial film, in which minute carbon defects are formed at high density, functions as the trap-rich layer.

[0073] Next, a method for manufacturing a second substrate in the SOI wafer manufacturing method of the first embodiment will be described.

[0074] (Step to prepare the second circuit board) A silicon single crystal substrate is prepared as the second substrate. The resistivity of the second substrate can be, for example, a silicon single crystal substrate with a resistivity of about 10 Ω·cm, but is not limited to this. It can be appropriately determined in the range of 10 to 1000 Ω·cm depending on the device being fabricated.

[0075] (Step of forming a dielectric layer) Next, a dielectric layer is formed on the surface of the second substrate. The material of the dielectric layer is not particularly limited. For example, a silicon oxide film can be formed by thermal oxidation, pyrogenic oxidation, etc. When forming an oxide film as the dielectric layer, the oxide film can be formed on the entire surface of the substrate by thermal oxidation (oxidizing atmosphere, 1000 °C, 1 to 12 hours). This second substrate becomes a bonding wafer.

[0076] The order of fabricating the first substrate and the second substrate in FIG. 2 is not limited. Either can be done first, or they can be done in parallel.

[0077] (Step of bonding the epitaxial film formed on the first substrate and the dielectric layer of the second substrate) After preparing the first substrate, which is an epitaxial wafer fabricated by vapor phase growth and subsequent heat treatment as described above, and the second substrate, as shown in FIG. 2, the epitaxial film of the first substrate and the dielectric layer of the second substrate are bonded (joined).

[0078] After bonding, the silicon substrate of the second substrate can be thinned. This thinning can be achieved by methods such as polishing, etching the silicon substrate of the second substrate, or the ion implantation lift-off method to a desired thickness according to the application. The ion implantation lift-off method can be implemented, for example, by implanting hydrogen ions or the like from the dielectric layer side of the silicon substrate before bonding in FIG. 2 to form an ion implantation layer in the silicon substrate, and then peeling along the ion implantation layer by heat treatment or the like after bonding.

[0079] By such a method for manufacturing an SOI wafer according to the first embodiment of the present invention, an SOI wafer can be manufactured. The SOI wafer manufactured in this way has, on a silicon substrate with a resistivity of 10 to 5000 Ω·cm, 2×10 19 atoms / cm 3 or more, 3×10 20 atoms / cm 3The structure consists of an epitaxial film with minute carbon defects, obtained by heat-treating an epitaxial film containing carbon at a concentration of less than 100%, a dielectric layer, and a silicon single crystal film, stacked in this order.

[0080] The carbon concentration of the epitaxial film is 2 × 10 19 atoms / cm 3 If the above conditions are met, a sufficient number of minute carbon defects will be formed by heat treatment, and the second and third harmonics can be significantly reduced compared to before heat treatment. On the other hand, if the carbon concentration in the epitaxial film is 3 × 10⁻⁶ 20 atoms / cm 3 In the above cases, the quality of the epitaxial film deteriorates, and productivity also decreases.

[0081] The tiny carbon defects contained in the epitaxial film are approximately 10 nm or less in size and have a density of approximately 1 × 10⁻¹⁶ in the epitaxial film. 10 cm -2 Preferably, the above conditions apply (if the carbon concentration of the epitaxial film is lower than that of the present invention, carbon defects of approximately 25 nm or larger are included at a low density).

[0082] According to the manufacturing method for SOI wafers of this first embodiment of the present invention, it is possible to easily manufacture SOI wafers in which minute carbon defects are densely formed in the epitaxial film without using a high-resistivity substrate. The manufactured SOI wafer has superior harmonic reduction capability compared to conventional SOI wafers that use a polysilicon layer as the trap-rich layer, because the epitaxial film functions as a trap-rich layer and reliably reduces harmonics. As a result, it becomes an SOI wafer suitable for high-frequency devices.

[0083] [Second Embodiment] Figure 3 shows an example of a method for manufacturing an SOI wafer according to a second embodiment of the present invention. This method is a method for manufacturing an SOI wafer that utilizes a silicon epitaxial film in which minute carbon defects are formed at high density as a trap-rich layer as described above.

[0084] (Step of preparing the first substrate) ~ (Step of vapor-phase growth of the silicon epitaxial film) First, we will describe the manufacturing method for the epitaxial wafer of the first substrate, which will serve as the base wafer. The steps from preparing the first substrate to growing the silicon epitaxial film in the vapor phase are the same as those for the manufacturing method of the epitaxial wafer in the first embodiment shown in Figure 2.

[0085] (Step of forming carbon defects and oxide film) In the manufacturing method of the SOI wafer according to the second embodiment, as shown in Figure 3, a first substrate on which a silicon epitaxial film is formed is heat-treated in an oxidizing atmosphere at a heat treatment temperature of 900°C to 1100°C and a heat treatment time of 3 hours to 36 hours, thereby forming carbon defects in the silicon epitaxial film and forming an oxide film on the silicon epitaxial film. The heat treatment conditions in this case are as described in the first embodiment above, and by performing the heat treatment for carbon defect formation in an oxidizing atmosphere, carbon defects are formed in the silicon epitaxial film and an oxide film is formed on the silicon epitaxial film simultaneously.

[0086] The thickness of the oxide film is not particularly limited and can be adjusted according to the application, but for productivity reasons, it can be between 100 nm and 1 μm.

[0087] The SOI wafer manufacturing method of the second embodiment described above can also be used to manufacture an epitaxial wafer (base wafer) that functions as a trap-rich layer of the SOI wafer.

[0088] In the second embodiment, an oxide film is formed on the epitaxial film surface on the first substrate. The formation of the oxide film and the heat treatment necessary to form high-density minute carbon defects in the epitaxial film can be carried out simultaneously in the same chamber, making it possible to reduce the number of steps required for manufacturing SOI wafers.

[0089] (Step to prepare the second circuit board) Similar to the first embodiment described above, a second substrate, which is a silicon single crystal substrate, is prepared. The second substrate, which will become the bond wafer shown in Figure 3, can be, for example, a silicon substrate with a resistivity of about 10 Ω·cm, but is not limited to this. It can be appropriately determined in the range of 10 to 1000 Ω·cm depending on the device to be fabricated.

[0090] (A step of bonding the oxide film formed on the epitaxial film formed on the first substrate to the second substrate.) In the second embodiment, since an oxide film is formed on the epitaxial film, the step of forming a dielectric layer on the surface of the second substrate as in the first embodiment is not performed, but this does not mean that the presence of a dielectric layer is to be eliminated. As shown in Figure 3, the oxide film formed on the epitaxial film formed on the first substrate and the second substrate are bonded together.

[0091] In this case, it is preferable that the second substrate be a substrate that has been cut into multiple substrates from a single silicon single crystal substrate and thinned before being bonded to the first substrate which will serve as the base wafer. The method of thinning is not particularly limited, but thinning by polishing, ion implantation technology such as the Smart Cut method (registered trademark), and laser cutting technology can be used. However, from the viewpoint of manufacturing cost, it is more cost-effective to produce multiple thinned second substrates from a single silicon substrate before bonding to the first substrate compared to thinning to the same thickness after bonding.

[0092] The thickness of the thinned second substrate is not particularly limited and can be adjusted according to the application and thinning method. For example, if a silicon substrate approximately 60 μm thick is cut from a single silicon substrate (775 μm thick) using laser cutting technology before bonding, at least 10 or more second substrates necessary for manufacturing SOI wafers can be produced, which is highly advantageous from a manufacturing cost perspective and therefore preferable. In this case, the second substrate becomes the bond wafer.

[0093] After bonding, the second substrate can be further thinned. In this case, the desired thickness can be achieved according to the application by methods such as polishing, etching, or ion implantation delamination. Ion implantation delamination can be performed, for example, by implanting hydrogen ions into the silicon substrate from the side of the thinned silicon substrate that is in contact with the oxide film (dielectric layer) of the first substrate before bonding to form an ion implantation layer within the silicon substrate, and then delaminating along the ion implantation layer by heat treatment or other methods after bonding.

[0094] In the manufacturing process of the SOI wafer according to the second embodiment, the order in which the first and second substrates shown in Figure 3 are manufactured does not matter. Either can be done first, or they can be done in parallel. Furthermore, the order in which the second substrate is thinned and bonded does not matter. It can be thinned and then bonded, or bonded and then thinned.

[0095] SOI wafers can be manufactured by the SOI wafer manufacturing method of the second embodiment of the present invention. The SOI wafer manufactured in this way is placed on a silicon substrate with a resistivity of 10 to 5000 Ω·cm, with a layer of 2 × 10¹⁶ layers. 19 atoms / cm 3 The above is 3 x 10 20 atoms / cm 3 The structure consists of an epitaxial film with minute carbon defects, obtained by heat-treating an epitaxial film containing carbon at a concentration of less than 100%, a dielectric layer, and a silicon single crystal film, stacked in this order.

[0096] The tiny carbon defects contained in the epitaxial film are approximately 10 nm or less in size and have a density of approximately 1 × 10⁻¹⁶ in the epitaxial film. 10 cm -2 Preferably, the above conditions apply (if the carbon concentration of the epitaxial film is lower than that of the present invention, carbon defects of approximately 25 nm or larger are included at a low density).

[0097] According to the SOI wafer manufacturing method of this second embodiment of the present invention, an SOI wafer in which minute carbon defects are densely formed in the epitaxial film can be easily manufactured without using a high-resistivity substrate. The manufactured SOI wafer has superior harmonic reduction capability compared to conventional SOI wafers that use a polysilicon layer as the trap-rich layer, because the epitaxial film functions as a trap-rich layer and reliably reduces harmonics. As a result, it becomes an SOI wafer suitable for high-frequency devices.

[0098] [Third Embodiment] The SOI wafer according to the present invention can also be manufactured by the method described below.

[0099] First, we will describe the manufacturing method for the epitaxial wafer of the first substrate, which will serve as the base wafer. The method for fabricating the carbon-doped silicon epitaxial film (hereinafter also simply referred to as the "epitaxial film") on the first substrate shown in Figure 4 is the same as the manufacturing method for the epitaxial wafer in the manufacturing method of the first embodiment shown in Figure 2.

[0100] In the manufacturing method of the SOI wafer according to the third embodiment, as shown in Figure 4, a dielectric layer is formed on a first substrate on which an epitaxial film has been formed. In this case, an oxide film is formed as the dielectric layer.

[0101] As a method for forming the oxide film (dielectric layer), oxidation methods covering the entire substrate surface, such as thermal oxidation or pyrogenic oxidation, can be used (oxidizing atmosphere, 1000°C, 1-12 hours), but the method is not particularly limited as long as it is performed under an oxidizing atmosphere. The thickness of the oxide film (dielectric layer) is also not particularly limited and can be adjusted according to the application, but considering productivity, it can be set to 100 nm or more and 1 μm or less.

[0102] A first substrate on which an oxide film (dielectric layer) is formed is heat-treated at a heat treatment temperature of 900°C to 1100°C and a heat treatment time of 3 hours to 36 hours to form carbon defects in the silicon epitaxial film. The heat treatment conditions in this case are as described in the first embodiment above.

[0103] However, if a sufficient number of minute carbon defects are formed in the silicon epitaxial film by the oxidation treatment for the formation of the oxide film (dielectric layer), this can be used as the first substrate (base wafer). If the formation of carbon defects is insufficient, minute carbon defects can be formed in the epitaxial film by additional heat treatment in an oxidizing atmosphere. Alternatively, if there is no need to further increase the thickness of the oxide film (dielectric layer), an inert gas can be used as the additional heat treatment atmosphere. The implementation of additional heat treatment and the additional heat treatment conditions can be adjusted according to the situation and are not particularly limited.

[0104] The SOI wafer manufacturing method of the third embodiment described above can also be used to manufacture an epitaxial wafer (base wafer) that functions as a trap-rich layer of an SOI wafer.

[0105] In the third embodiment, an oxide film (dielectric layer) is formed on the epitaxial film surface on the first substrate. This allows the formation of the oxide film (dielectric layer) and the heat treatment necessary to form high-density minute carbon defects in the epitaxial film to be carried out in steps within the same chamber, thereby reducing the number of steps required for manufacturing the SOI wafer.

[0106] Next, the method for manufacturing the second substrate in the SOI wafer manufacturing method of the third embodiment will be described.

[0107] The second substrate, which will become the bond wafer shown in Figure 4, can be, for example, a silicon substrate with a resistivity of about 10 Ω·cm, but is not limited to this. It can be appropriately determined within the range of 10 to 1000 Ω·cm depending on the device being fabricated.

[0108] In the third embodiment, a dielectric layer is not formed on the second substrate, but this does not mean that the presence of a dielectric layer is to be excluded.

[0109] As described above, a first substrate, which is an epitaxial wafer fabricated by vapor phase growth and oxide film (dielectric layer) formation followed by heat treatment, and a second substrate are prepared. Then, as shown in Figure 4, the oxide film (dielectric layer) formed on the first substrate and the second substrate are bonded together. In this way, an SOI wafer can be manufactured.

[0110] In this case, the second substrate can be thinned using the same method as the thinning method in the second embodiment, both before and after bonding.

[0111] In the manufacturing process of the SOI wafer according to the third embodiment, the order in which the first and second substrates shown in Figure 4 are manufactured does not matter. They can be made in any order, or they can be made in parallel. Furthermore, the order in which the second substrate is thinned and bonded does not matter. It can be thinned and then bonded, or bonded and then thinned.

[0112] The SOI wafer according to the present invention can be manufactured by the SOI wafer manufacturing method of the third embodiment of the present invention. The SOI wafer manufactured in this manner is placed on a silicon substrate with a resistivity of 10 to 5000 Ω·cm, with a layer of 2 × 10¹⁶ layers. 19 atoms / cm 3 The above is 3 x 10 20 atoms / cm 3 The structure consists of an epitaxial film with a high density of minute carbon defects, obtained by heat-treating an epitaxial film containing carbon at a concentration of less than 100%, an oxide film (dielectric layer), and a silicon single crystal film, stacked in this order.

[0113] The tiny carbon defects contained in the epitaxial film are approximately 10 nm or less in size and have a density of approximately 1 × 10⁻¹⁶ in the epitaxial film. 10 cm -2Preferably, the above conditions apply (if the carbon concentration of the epitaxial film is lower than that of the present invention, carbon defects of approximately 25 nm or larger are included at a low density).

[0114] According to the SOI wafer manufacturing method of this third embodiment of the present invention, an SOI wafer in which minute carbon defects are densely formed in the epitaxial film can be easily manufactured without using a high-resistivity substrate. The manufactured SOI wafer has superior harmonic reduction capability compared to conventional SOI wafers that use a polysilicon layer as the trap-rich layer, because the epitaxial film functions as a trap-rich layer and reliably reduces harmonics. As a result, it becomes an SOI wafer suitable for high-frequency devices.

[0115] [High-frequency characteristics] This section describes the high-frequency characteristics of SOI wafers.

[0116] In the SOI wafer of the present invention, minute carbon defects are formed at high density in the carbon-doped silicon epitaxial film on the silicon substrate by heat treatment. As a result, the trap density of the trap-rich layer is higher than before heat treatment, and the carrier trapping ability is improved. Therefore, even when the silicon substrate is not high resistivity, harmonics can be significantly reduced compared to conventional SOI wafers in which a polysilicon layer is formed as a trap-rich layer on a high resistivity substrate, and excellent harmonic characteristics can be obtained.

[0117] Thus, the SOI wafer of the present invention can improve the second harmonic characteristics and third harmonic characteristics, and is suitable as a wafer for high-frequency devices. [Examples]

[0118] The present invention will be described in detail below with reference to examples, but this is not intended to limit the present invention.

[0119] (Example 1) As shown in Figure 2, an epitaxial wafer that serves as the first substrate (base wafer) functioning as a trap-rich layer in the SOI wafer manufacturing method of the first embodiment of the present invention was manufactured.

[0120] Specifically, a carbon-doped silicon epitaxial film (carbon concentration: 2.0 × 10¹⁶) is formed on a 300 mm diameter silicon substrate (P-type, resistivity 10 Ω·cm) obtained by slicing a single crystal ingot produced by the Czochralski method using a reduced-pressure CVD apparatus, using monomethylsilane as the carbon source gas. 19 ~1.0×10 20 atoms / cm 3 A film thickness of 1 μm was formed. Within this carbon concentration range, void defects are not formed if the film thickness is between 0.1 and 1.1 μm. After film formation, the obtained epitaxial wafer was subjected to heat treatment in a non-oxidizing atmosphere at 1000°C for 12 hours to form a high density of minute carbon defects in the silicon epitaxial film. At this time, no oxide film was formed on the silicon epitaxial film.

[0121] The concentration of the carbon-doped silicon epitaxial film is (1) 2.0 × 10 19 atoms / cm 3 (2) 3.0 × 10 19 atoms / cm 3 (3) 6.0 × 10 19 atoms / cm 3 (4) 1.0 × 10 20 atoms / cm 3 These were the four types.

[0122] Next, SOI wafers were fabricated using heat-treated epitaxial wafers. As a second substrate to serve as the bond wafer, a silicon wafer was prepared by forming a 400 nm thick oxide film as a dielectric layer on the surface of a 300 mm diameter silicon substrate (P-type, resistivity 10 Ω·cm).

[0123] A silicon epitaxial film with minute carbon defects formed on a first substrate was bonded to the oxide film surface (surface of the dielectric layer) of a second substrate. By polishing the silicon substrate of the second substrate, an SOI wafer with a 1 μm layer of silicon single crystal film remaining was manufactured. This was designated as the SOI wafer of Example 1.

[0124] To investigate the high-frequency characteristics of the SOI wafer of Example 1, the second and third harmonic characteristics of the SOI wafer of Example 1 were measured. After removing the silicon single crystal film on the second substrate side of the manufactured SOI wafer, an aluminum electrode with a line length of 2200 μm was formed on the dielectric layer exposed on the surface of a silicon epitaxial film [carbon concentration: (1)~(4), film thickness: 1 μm] in which minute carbon defects were formed at high density, and the high-frequency characteristics were measured.

[0125] The measurement results are shown in Figure 7. As shown in Figure 7, when the input signal frequency is 1 GHz, the second harmonic characteristics of the wafer were (1) -55.0 dBm, (2) -47.3 dBm, (3) -52.4 dBm, and (4) -59.5 dBm for the carbon concentrations of the silicon epitaxial film, respectively, from (1) to (4). Furthermore, the third harmonic characteristics were (1)-85.2 dBm, (2)-87.1 dBm, (3)-91.2 dBm, and (4)-84.1 dBm for the cases where the carbon concentration of the silicon epitaxial film was (1) to (4), respectively. These results demonstrate that the epitaxial wafer of Example 1 can significantly reduce harmonics, and it was found to be excellent as a trap-rich layer when applied to the first substrate (base wafer) of an SOI wafer.

[0126] (Comparative Example 1) An SOI wafer was manufactured using the same method as the SOI wafer manufacturing method of Example 1, differing only in that heat treatment was not performed after the deposition of the silicon epitaxial layer on the first substrate. This was used as the SOI wafer for Comparative Example 1.

[0127] Figure 7 shows the results of measuring the second and third harmonic characteristics of the SOI wafer of Comparative Example 1 using the same method as in Example 1. figure 7 As shown, the second harmonic characteristics of the wafer were (1)-18.3 dBm, (2)-18.8 dBm, (3)-20.4 dBm, and (4)-19.9 dBm for the carbon concentrations of the silicon epitaxial film, respectively. Furthermore, the third harmonic characteristics were (1) -43.4 dBm, (2) -41.2 dBm, (3) -41.4 dBm, and (4) -47.0 dBm. These results show that the second and third harmonic characteristics of Comparative Example 1 were both inferior to those of Example 1.

[0128] Based on the above results, the carbon concentration of the carbon-doped silicon epitaxial film is 2 × 10⁻⁶. 19 atoms / cm 3 The above 3 x 10 20 atoms / cm 3 The ratio shall be less than 6.6 × 10⁻¹⁰, and the relationship between the thickness of the silicon epitaxial film and the carbon concentration shall be less than 6.6 × 10⁻¹⁰. 20 ×exp{-1.6×[epitaxial film thickness (μm)]}>[carbon concentration of epitaxial film (atoms / cm³)] 3 When an epitaxial layer formed by heat-treating the silicon epitaxial film satisfying the condition ) to create a high density of minute carbon defects was applied to the first substrate (base wafer) of an SOI wafer, it was found to be superior as a trap-rich layer compared to when an epitaxial layer without carbon defects was applied to the first substrate (base wafer) of an SOI wafer.

[0129] (Comparative Example 2) Epitaxial wafers were manufactured using the same method as for the manufacturing methods of the epitaxial wafers in Example 1 and Comparative Example 1, but differing only in the carbon concentration contained in the silicon epitaxial film. First, a carbon-doped silicon epitaxial film (carbon concentration: 3.0 × 10¹⁶) is made on a 300 mm diameter silicon substrate (P-type, resistivity 10 Ω·cm) obtained by slicing a single crystal ingot produced by the Czochralski method using a reduced-pressure CVD apparatus, using monomethylsilane as the carbon source gas. 20 ~1.0×10 21 atoms / cm 3 The first substrate (base wafer) of the SOI wafer in Comparative Example 2 was prepared by forming a film thickness of 1 μm. It has been found that void defects are formed at film thicknesses of 1 μm or more within this carbon concentration range. For all of the above base wafers, samples were prepared that were heat-treated at 1000°C for 12 hours in an oxygen atmosphere, and samples that were not heat-treated.

[0130] The concentration of the carbon-doped silicon epitaxial film is (1) 3.0 × 10⁻⁶ 20 atoms / cm 3 (2) 1.0 × 10 21 atoms / cm 3 There were two types: and .

[0131] Next, as a second substrate (bond wafer), a silicon wafer was prepared by forming a 400 nm thick oxide film as a dielectric layer on the surface of a 300 mm diameter silicon substrate (P-type, resistivity 10 Ω·cm). The silicon epitaxial film surface of the base wafer and the oxide film surface (surface of the dielectric layer) of the bond wafer were bonded, and the silicon substrate on the bond wafer side was polished to obtain an SOI wafer with a 1 μm silicon single crystal film remaining. This was designated as the SOI wafer of Comparative Example 2.

[0132] Figure 7 shows the results of measuring the second and third harmonic characteristics of the SOI wafer of Comparative Example 2 using the same method as in Example 1. As shown in Figure 7, when the input signal frequency is 1 GHz, the second harmonic characteristics of the wafer (without heat treatment) were (1) -26.0 dBm and (2) -26.3 dBm for the cases where the carbon concentration of the silicon epitaxial film is (1) to (2), respectively, and the second harmonic characteristics (with heat treatment) were (1) -29.5 dBm and (2) -28.5 dBm. Furthermore, the third harmonic characteristics (without heat treatment) were (1) -64.0 dBm and (2) -65.7 dBm, while the third harmonic characteristics (with heat treatment) were (1) -49.7 dBm and (2) -64.2 dBm. The results showed that the second and third harmonic characteristics of Comparative Example 2 were both inferior to those of Example 1.

[0133] (Example 2) As shown in Figure 3, an epitaxial wafer, which will serve as a first substrate (base wafer) functioning as a trap-rich layer, was manufactured using the SOI wafer manufacturing method of the second embodiment of the present invention.

[0134] Specifically, a carbon-doped silicon epitaxial film (carbon concentration: 2.0 × 10¹⁶) is formed on a 300 mm diameter silicon substrate (P-type, resistivity 10 Ω·cm) obtained by slicing an ingot manufactured by the Czochralski method using a reduced-pressure CVD apparatus, using monomethylsilane as the carbon source gas. 19 ~1.0×10 20 atoms / cm 3 A film thickness of 1 μm was formed. Within this carbon concentration range, void defects are not formed if the film thickness is between 0.1 and 1.1 μm. After film formation, the obtained epitaxial wafer was subjected to heat treatment in an oxidizing atmosphere at 1000°C for 12 hours to form a high density of minute carbon defects in the silicon epitaxial film. At this time, an oxide film is formed on the silicon epitaxial film.

[0135] A silicon epitaxial film, formed on a first substrate and having an oxide film on its surface with minute carbon defects, was bonded to a silicon substrate (P-type, resistivity 10 Ω·cm) of a second substrate with a diameter of 300 mm. By polishing the silicon substrate of the second substrate, an SOI wafer with a 1 μm layer of silicon single crystal film remaining was manufactured. This was designated as the SOI wafer of Example 2.

[0136] The second and third harmonic characteristics of the SOI wafer of Example 2 were measured using the same method as in Example 1. As a result, it was confirmed that it exhibited high-frequency characteristics almost equivalent to those of Example 1. From the above, it was shown that SOI wafers exhibiting equivalent high-frequency characteristics can be manufactured regardless of whether they are in the first or second form.

[0137] (Example 3) As shown in Figure 4, an epitaxial wafer that serves as the first substrate (base wafer) functioning as a trap-rich layer was manufactured using the SOI wafer manufacturing method of the third embodiment of the present invention. A carbon-doped silicon epitaxial film (carbon concentration: 2.0 × 10¹⁶) was applied to a 300 mm diameter silicon substrate (P-type, resistivity 10 Ω·cm) obtained by slicing an ingot manufactured by the Czochralski method using a reduced-pressure CVD apparatus, using monomethylsilane as the carbon source gas. 19 ~1.0×10 20 atoms / cm 3 A film thickness of 1 μm was formed. In this carbon concentration range, void defects are not formed if the film thickness is 0.1 to 1.1 μm. After deposition, a 400 nm dielectric oxide film was formed on the surface of the carbon-doped silicon epitaxial film by pyrogenic oxidation (1000°C / 4 hours). The obtained epitaxial wafer was subjected to heat treatment in a non-oxidizing atmosphere at 1000°C for 8 hours to form minute carbon defects in the silicon epitaxial film. This was used as the base wafer in Example 3. In the third embodiment, it is necessary that an oxide film is formed on this silicon epitaxial film.

[0138] Next, an SOI wafer was fabricated using the base wafer. As a second substrate (bond wafer), a silicon substrate with a diameter of 300 mm (thickness 775 μm, P-type, resistivity 10 Ω·cm) was thinned by laser cutting to obtain a bond wafer with a thickness of approximately 100 μm. Then, the dielectric layer on the surface of a silicon epitaxial film, in which minute carbon defects were formed on the first substrate, was bonded to the bond wafer to produce an SOI wafer. This was designated as the SOI wafer of Example 3.

[0139] The second and third harmonic characteristics of the SOI wafer of Example 3 were measured using the same method as in Example 1. As a result, it was confirmed that it exhibited high-frequency characteristics almost equivalent to those of Example 1. From the above, it was shown that SOI wafers exhibiting equivalent high-frequency characteristics can be manufactured regardless of whether it is the first, second, or third embodiment.

[0140] Furthermore, in Example 3, it is possible to produce a second substrate necessary for manufacturing five SOI wafers from a single silicon substrate, which offers a significant advantage in terms of manufacturing costs.

[0141] As described above, according to the embodiments of the present invention, by not using a high-resistivity substrate and by having a silicon epitaxial film containing minute carbon defects at high density act as a trap-rich layer, it was possible to easily manufacture an SOI wafer having superior high-frequency characteristics compared to conventional SOI wafers that use a polysilicon layer as a trap-rich layer.

[0142] The present invention is not limited to the embodiments described above. The embodiments described above are illustrative, and any configuration that has the same technical idea as described in the claims of the present invention and achieves similar effects is included within the technical scope of the present invention. [Explanation of Symbols]

[0143] 1…SOI wafer, 2…Silicon single crystal substrate, 3…Silicon epitaxial film containing carbon defects, 4…Dielectric layer, 5…Silicon single crystal substrate.

Claims

1. On a silicon single crystal substrate with resistivity of 10 Ω·cm to 5000 Ω·cm, a carbon concentration of 2 × 10 １９ atoms / cm ３ The above 3 x 10 ２０ atoms / cm ３ The silicon epitaxial film, dielectric layer, and silicon single crystal film are less than and contain carbon defects, in this order. The thickness of the silicon epitaxial film is 6.6 × 10 ２０ ×exp{-1.6 × [epitaxial film thickness (μm)]} > [carbon concentration of epitaxial film (atoms / cm³)] ３ An SOI wafer characterized by satisfying the following conditions.

2. The SOI wafer according to claim 1, characterized in that it is a wafer for high-frequency devices.

3. The carbon defects have a size of 10 nm or less and a density of 1 × 10 in the silicon epitaxial film. １０ cm －２ The SOI wafer according to claim 1 or 2, characterized by being as described above.

4. The first step is to prepare a silicon single crystal substrate having a resistivity of 10 Ω·cm or more and 5000 Ω·cm or less, On the first substrate, a silicon epitaxial film having a carbon concentration of 2×10 １９ atoms / cm ３ or more and less than 3×10 ２０ atoms / cm ３ is vapor-grown under reduced pressure; The first substrate on which the silicon epitaxial film is formed is heat-treated at a heat treatment temperature of 900°C to 1100°C and a heat treatment time of 3 hours to 36 hours to form carbon defects in the silicon epitaxial film, The steps include preparing a second substrate, which is a silicon single crystal substrate, The steps include forming a dielectric layer on the surface of the second substrate, The process includes the step of bonding an epitaxial film formed on the first substrate to a dielectric layer on the second substrate, In the step of vapor-phase growth of the silicon epitaxial film, the thickness of the silicon epitaxial film is 6.6 × 10 ２０ ×exp{-1.6 × [epitaxial film thickness (μm)]} > [carbon concentration of epitaxial film (atoms / cm³)] ３ A method for manufacturing an SOI wafer, characterized by forming a silicon epitaxial film that satisfies the following conditions.

5. The first step is to prepare a silicon single crystal substrate having a resistivity of 10 Ω·cm or more and 5000 Ω·cm or less, On the first substrate, under reduced pressure, the carbon concentration is 2 × 10 １９ atoms / cm ３ The above 3 x 10 ２０ atoms / cm ３ The steps include: growing a silicon epitaxial film of less than 100% in vapor phase, The first substrate on which the silicon epitaxial film is formed is heat-treated in an oxidizing atmosphere at a heat treatment temperature of 900°C to 1100°C and a heat treatment time of 3 hours to 36 hours, thereby forming carbon defects in the silicon epitaxial film and forming an oxide film on the silicon epitaxial film. The steps include preparing a second substrate, which is a silicon single crystal substrate, The process includes the step of bonding an oxide film formed on an epitaxial film formed on the first substrate to the second substrate, In the step of vapor-phase growth of the silicon epitaxial film, the thickness of the silicon epitaxial film is 6.6 × 10 ２０ ×exp{-1.6 × [epitaxial film thickness (μm)]} > [carbon concentration of epitaxial film (atoms / cm³)] ３ A method for manufacturing an SOI wafer, characterized by forming a silicon epitaxial film that satisfies the following conditions.

6. The method for manufacturing an SOI wafer according to claim 5, characterized in that the second substrate is a substrate that has been cut into multiple substrates from a single silicon single crystal substrate and thinned before being bonded to the first substrate.

7. A method for manufacturing an SOI wafer, characterized in that the SOI wafer manufactured using the SOI wafer manufacturing method described in claim 4 or 5 is used as a wafer for high-frequency devices.

8. The carbon defects have a size of 10 nm or less and a density of 1 × 10 in the epitaxial film. １０ cm －２ The method for manufacturing an SOI wafer according to claim 4 or 5, characterized in that it is as described above.

Images