Phase adjustment circuit

Abstract

This phase adjusting circuit comprises: a clock generation circuit (1) that generates a clock signal of a sinusoidal shape; an amplification circuit (2) that amplifies the clock signal; a transfer line (4) the input end of which is connected to the output terminal of the amplification circuit (2); a load circuit (5) which is connected to the terminal end of the transfer line (4) and the impedance of which can be externally adjusted; and an amplification circuit (3) that receives, as an input thereof, a signal obtained by adding, at the output terminal of the amplification circuit (2), the output signal of the amplification circuit (2) and a return signal from the transfer line (4).

Description

[Technical Field]

[0001] This invention relates to a sinusoidal phase adjustment circuit. [Background technology]

[0002] In modern times, sine waves play a crucial role. In communications, sine waves are sometimes used to generate carrier waves, and sometimes they are used as clocks. In communications, clocks are used not only as carrier waves, but also as timing standards for determining data.

[0003] When using a clock as the timing reference for data determination, it is necessary to adjust the clock phase and perform data determination at the appropriate timing. One method for performing data determination at the appropriate timing is clock-data recovery. A known configuration for implementing clock-data recovery uses a phase comparator and a phase adjustment circuit. In this configuration, the phases are compared by some means, and the desired phase is generated based on the comparison result.

[0004] Conventionally, the configuration disclosed in Non-Patent Document 1 was known as a phase adjustment circuit. The configuration of the conventional phase adjustment circuit is shown in Figure 28. In the configuration of Figure 28, a reference sine wave sinωt and a sine wave cosωt having a fixed phase difference of π / 2 with respect to the sine wave sinωt are added by an adder 203 to generate a waveform with an arbitrary intermediate phase. The sine waves sinωt and cosωt are multiplied by constants A and B, respectively, by multipliers 201 and 202. From the trigonometric function synthesis formula, the following equation holds.

[0005]

number

[0006] In equation (1), α is given by the following:

[0007]

number

[0008] In the configuration shown in Figure 28, a Quadrature-VCO (Voltage Controlled Oscillator) 200 is used to generate sine waves sinωt and cosωt. However, due to its structure, the Quadrature-VCO 200 has a low oscillation frequency, making it difficult to use in the device's limit region. Furthermore, while a 90-degree hybrid method is known for creating sine waves with a fixed phase difference of π / 2 from a sine wave, this method has the drawback of only operating at specific frequencies. [Prior art documents] [Non-patent literature]

[0009] [Non-Patent Document 1] Arun Goyal,et al.,“AHigh-Resolution Digital Phase Interpolator Based CDR with a Half-Rate HybridPhase Detector”,2019 IEEE International Symposium onCircuits and Systems (ISCAS),May 2019 [Overview of the project] [Problems that the invention aims to solve]

[0010] This invention was made to solve the above problems and aims to provide a phase adjustment circuit that can be used over a wide range of frequencies. [Means for solving the problem]

[0011] The phase adjustment circuit of the present invention includes a clock generation circuit configured to generate a sine-wave clock signal, an amplification circuit configured to amplify the clock signal output from the clock generation circuit, a transmission line having an input end connected to an output terminal of the amplification circuit, a load circuit connected to the end of the transmission line and capable of adjusting impedance from the outside, and an output circuit that takes as an input a signal obtained by adding the output signal of the amplification circuit and the return signal from the transmission line at the output terminal of the amplification circuit.

Effect of the Invention

[0012] According to the present invention, by providing a clock generation circuit, an amplification circuit, a transmission line, a load circuit, and an output circuit, it is not necessary to use a conventional Quadrature-VCO as a clock generation circuit that forms the basis of a sine-wave signal, and an LC-VCO composed of a general LC oscillator can be used as the clock generation circuit. Therefore, a clock with an intermediate phase can be generated, and operation at a higher frequency can be realized. Further, in the present invention, it can be used over a wider range of frequencies compared to a configuration using a 90-degree hybrid as the clock generation circuit.

Brief Description of the Drawings

[0013] [Figure 1] FIG. 1 is a block diagram showing the configuration of a phase adjustment circuit according to a first embodiment of the present invention. [Figure 2] FIG. 2 is a diagram showing the simulation result of the phase adjustment circuit according to the first embodiment of the present invention. [Figure 3] FIG. 3 is a block diagram showing the configuration of a phase adjustment circuit according to a second embodiment of the present invention. [Figure 4] FIG. 4 is a circuit diagram showing the configuration of an amplification circuit according to the second embodiment of the present invention. [Figure 5] FIG. 5 is a block diagram showing the configuration of a phase adjustment circuit according to a third embodiment of the present invention. [Figure 6] FIG. 6 is a circuit diagram showing the configuration of a mixer according to the third embodiment of the present invention. [Figure 7] Figure 7 is a block diagram showing the configuration of a phase adjustment circuit according to a fourth embodiment of the present invention. [Figure 8] Figure 8 is a block diagram showing the configuration of a phase adjustment circuit according to the fifth embodiment of the present invention. [Figure 9] Figure 9 is a block diagram showing the configuration of a phase adjustment circuit according to the sixth embodiment of the present invention. [Figure 10] Figure 10 is a circuit diagram showing the configuration of a signal quality evaluation circuit according to the sixth embodiment of the present invention. [Figure 11] Figure 11 is a circuit diagram showing the configuration of a load circuit according to the seventh embodiment of the present invention. [Figure 12] Figure 12 is a circuit diagram showing another configuration of the load circuit according to the seventh embodiment of the present invention. [Figure 13] Figure 13 is a circuit diagram showing another configuration of the load circuit according to the seventh embodiment of the present invention. [Figure 14] Figure 14 is a circuit diagram showing another configuration of the load circuit according to the seventh embodiment of the present invention. [Figure 15] Figure 15 is a circuit diagram showing another configuration of the load circuit according to the seventh embodiment of the present invention. [Figure 16] Figure 16 is a circuit diagram showing another configuration of the load circuit according to the seventh embodiment of the present invention. [Figure 17] Figure 17 is a circuit diagram showing another configuration of the load circuit according to the seventh embodiment of the present invention. [Figure 18] Figure 18 is a circuit diagram showing another configuration of the load circuit according to the seventh embodiment of the present invention. [Figure 19] Figure 19 is a circuit diagram showing another configuration of the load circuit according to the seventh embodiment of the present invention. [Figure 20] Figure 20 is a circuit diagram showing another configuration of the load circuit according to the seventh embodiment of the present invention. [Figure 21] Figure 21 is a circuit diagram showing another configuration of the load circuit according to the seventh embodiment of the present invention. [Figure 22] Figure 22 is a circuit diagram showing another configuration of the load circuit according to the seventh embodiment of the present invention. [Figure 23] Figure 23 is a circuit diagram showing another configuration of the load circuit according to the seventh embodiment of the present invention. [Figure 24] Figure 24 is a circuit diagram showing another configuration of the load circuit according to the seventh embodiment of the present invention. [Figure 25] Figure 25 is a cross-sectional view showing the configuration of a transmission line according to the eighth embodiment of the present invention. [Figure 26] Figure 26 is a cross-sectional view showing another configuration of a transmission line according to the eighth embodiment of the present invention. [Figure 27] Figure 27 is a cross-sectional view showing another configuration of a transmission line according to the eighth embodiment of the present invention. [Figure 28] Figure 28 is a block diagram showing the configuration of a conventional phase adjustment circuit. [Modes for carrying out the invention]

[0014] [Principle of the invention] In this invention, a circuit configuration is provided in which a transmission line with a variable impedance load is attached to the clock buffer, thereby realizing the function of adjusting a sine wave to an arbitrary phase.

[0015] [First Embodiment] Hereinafter, embodiments of the present invention will be described with reference to the drawings. Figure 1 is a block diagram showing the configuration of a phase adjustment circuit according to a first embodiment of the present invention. The phase adjustment circuit comprises a clock generation circuit 1 that generates a sinusoidal clock signal, an amplification circuit 2 that amplifies the clock signal output from the clock generation circuit 1, an amplification circuit 3 whose input terminal is connected to the output terminal of the amplification circuit 2, a transmission line 4 whose input terminal is connected to the output terminal of the amplification circuit 2, and a load circuit 5 connected to the end of the transmission line 4, whose impedance can be adjusted from the outside.

[0016] In the configuration of FIG. 1, the sine-wave clock signal output from the clock generation circuit 1 passes through the amplifier circuit 2 and is input to the amplifier circuit 3 and the transmission line 4. Since the impedance of the transmission line 4 is different from the impedance of the load circuit 5, the signal input to the transmission line 4 is reflected at the end of the transmission line 4 and returns to the output of the amplifier circuit 2. Therefore, the signal output from the amplifier circuit 2 and the signal delayed by traveling back and forth through the transmission line 4 are added at the output terminal of the amplifier circuit 2.

[0017] As the amplifier circuits 2 and 3, a buffer circuit with a gain of 1 may be used, an amplifier circuit with a gain higher than 1 may be used, or an amplifier circuit with a gain higher than 0 and lower than 1 may be used. In this embodiment, the amplifier circuit 3 is used as the output circuit that takes as input the signal obtained by adding the output signal of the amplifier circuit 2 and the return signal from the transmission line 4 at the output terminal of the amplifier circuit 2. However, as will be described later, the output circuit does not have to be an amplifier circuit, and may be a circuit combining a mixer and a filter.

[0018] The operation of the phase adjustment circuit will be described using mathematical formulas. Assuming that the signal input from the amplifier circuit 2 to the transmission line 4 is Asinωt and the signal reflected and returned from the transmission line 4 is Bsin(ωt + φ), the output signal OUT of the amplifier circuit 3 finally becomes as follows.

[0019]

Equation

[0020] In Equation (3), the gain of the amplifier circuit 3 is set to 1. e jωt represents a reference sine wave. Since Bsin(ωt + φ) is the reflected wave returning from the transmission line 4, it is not amplified and B < A. The values of B and φ depend on the impedance of the load circuit 5 and the length of the transmission line 4.

[0021] From equation (3), it can be seen that by adding a sine wave of the reference frequency and a sine wave with an arbitrary phase difference of φ, a sine wave with a phase difference of ρ can be generated from the sine wave of the reference phase. The amount of change in output phase is re jρ Since we only need to calculate this, we can rearrange equation (3) to get equation (4).

[0022]

number

[0023] Therefore, the phase angle ρ is given by equation (5).

[0024]

number

[0025] Although the effects of multiple reflections were ignored here, the possibility of generating an intermediate-phase sine wave can be explained by a similar argument even when multiple reflections are present. While Figure 1 shows a single-phase configuration, it can also be implemented with a differential circuit.

[0026] Next, we will explain the actual operation of the phase adjustment circuit in more detail. The output impedance of amplifier circuit 2 is set to r o The characteristic impedance of transmission line 4 is Z0, and the impedance of load circuit 5 is Z T Let's assume the impedance Z of transmission line 4 and load circuit 5 as seen from the input of transmission line 4. in The equation is as shown in equation (6).

[0027]

number

[0028] B is the phase constant, and L is the length of transmission line 4. Since B × L is determined by the physical structure and the signal frequency, tanBL can be considered a constant when focusing on a specific frequency. Impedance Z at the output terminal of amplifier circuit 2.out is the combined resistance of Z in and r o and can be expressed as in Equation (7).

[0029]

Number

[0030] Generally, the output voltage of an amplifier circuit is expressed as the product of the transconductance and the impedance of the output terminal. Therefore, if the transconductance of amplifier circuit 2 is denoted as gma, the output voltage V out of amplifier circuit 2 can be expressed as in Equation (8). V out = gma × Z out ···(8)

[0031] From Equation (7), it can be seen that by changing the impedance Z T of load circuit 5, the phase angle of impedance Z out changes. That is, by changing the impedance Z T , the phase of the output of the phase adjustment circuit can be adjusted. However, it is necessary to exclude the combinations of signal frequency and the length of transmission line 4 for which tanBL = 0 holds.

[0032] The results of circuit simulation confirming that the phase of a sine wave changes by the phase adjustment circuit of this embodiment are shown in FIG. 2. 20 shows the sine wave output from clock generation circuit 1, and 21 shows the sine wave whose phase has been changed by the phase adjustment circuit of this embodiment. The frequency of the sine wave is 60 GHz. By changing the impedance Z T of load circuit 5, it can be confirmed that the phase of the sine wave changes by approximately 3 ps in terms of time.

[0033] As in the above numerical analysis, impedance Z TThe range is not limited to real numbers, but may also include complex numbers. Furthermore, in order to prevent multiple reflections in transmission line 4, the characteristic impedance Z0 of transmission line 4 and the output impedance r of amplifier circuit 2 are used. o You may make them the same.

[0034] [Second Example] Figure 3 is a block diagram showing the configuration of a phase adjustment circuit according to a second embodiment of the present invention. The phase adjustment circuit of this embodiment includes a differential output type clock generation circuit 1a that generates a sinusoidal differential clock signal, a differential input differential output type amplifier circuit 2a whose non-inverting input terminal is connected to the non-inverting output terminal of the clock generation circuit 1a and whose inverting input terminal is connected to the inverting output terminal of the clock generation circuit 1a, a differential input differential output type amplifier circuit 3a whose non-inverting input terminal is connected to the non-inverting output terminal of the amplifier circuit 2a and whose inverting input terminal is connected to the inverting output terminal of the amplifier circuit 2a, a transmission line 4p whose input terminal is connected to the non-inverting output terminal of the amplifier circuit 2a, a transmission line 4n whose input terminal is connected to the inverting output terminal of the amplifier circuit 2a, a load circuit 5p connected to the end of the transmission line 4p whose impedance can be adjusted from the outside, and a load circuit 5n connected to the end of the transmission line 4n whose impedance can be adjusted from the outside.

[0035] Transmission lines 4p and 4n have the same length L and the same characteristic impedance Z0. Load circuits 5p and 5n have the same impedance Z T These are the same circuit. However, as will be described later, the impedance Z of the load circuits 5p and 5n T You may adjust this to a different value. For the amplifier circuits 2a and 3a, the configuration shown in Figure 4, which is a typical differential amplifier circuit, can be used.

[0036] Amplifier circuit 2a consists of an NPN bipolar transistor Q1, which receives the inverted clock signal IN2n output from clock generation circuit 1a as input to its base (inverting input terminal of amplifier circuit 2a) and outputs the positive-phase output signal OUT2p from its collector (non-inverting output terminal of amplifier circuit 2a); an NPN bipolar transistor Q2, which receives the positive-phase clock signal IN2p output from clock generation circuit 1a as input to its base (non-inverting input terminal of amplifier circuit 2a) and outputs the inverted-phase output signal OUT2n from its collector (inverting output terminal of amplifier circuit 2a); and a bias voltage Vb applied to its base. It consists of an NPN bipolar transistor Q3, a resistor R1 with one end connected to the power supply voltage VCC and the other end connected to the collector of transistor Q1, a resistor R2 with one end connected to the power supply voltage VCC and the other end connected to the collector of transistor Q2, a resistor R3 with one end connected to the emitter of transistor Q1 and the other end connected to the collector of transistor Q3, a resistor R4 with one end connected to the emitter of transistor Q2 and the other end connected to the collector of transistor Q3, and a resistor R5 with one end connected to the emitter of transistor Q3 and the other end connected to ground.

[0037] The configuration of amplifier circuit 3a is the same as that of amplifier circuit 2a. As in the first embodiment, the amplification of amplifier circuits 2a and 3a may be 1, higher than 1, or higher than 0 and lower than 1.

[0038] [Third embodiment] In the first and second embodiments, any active circuit may be used instead of the second-stage amplification circuit. Figure 5 is a block diagram showing the configuration of a phase adjustment circuit according to the third embodiment of the present invention. The phase adjustment circuit of this embodiment includes a clock generation circuit 1a, an amplification circuit 2a, transmission lines 4p, 4n, load circuits 5p, 5n, a differential input differential output mixer 6 that mixes the sum of the output signal of the amplification circuit 2a and the return signals from the transmission lines 4p, 4n, and the carrier signals IN7p, IN7n input from an external source, and a differential input differential output filter 7 that filters the output signal of the mixer 6 and allows differential signals OUTp, OUTn of a desired frequency to pass through.

[0039] Let f1 be the frequency of the summing signals IN6p and IN6n, and f2 be the frequency of the carrier signals IN7p and IN7n. When the summing signals IN6p and IN6n and the carrier signals IN7p and IN7n are mixed by mixer 6, a signal with the sum and difference frequencies f1 ± f2 is output from mixer 6. Filter 7 filters the output signal of mixer 6, allowing a signal of, for example, frequency f1+f2 to pass through. In this way, the summation signals IN6p and IN6n input to mixer 6 can be converted into higher frequency signals OUTp and OUTn and output.

[0040] As the mixer 6 that functions as a multiplier, the Gilbert cell circuit shown in Figure 6 can be used. Mixer 6 consists of an NPN bipolar transistor Q4 to which the inverse-phase summation signal IN6n is input to the base and the positive-phase output signal OUT6p of mixer 6 is output from the collector, an NPN bipolar transistor Q5 to which the positive-phase summation signal IN6p is input to the base and the inverse-phase output signal OUT6n of mixer 6 is output from the collector, an NPN bipolar transistor Q6 to which the summation signal IN6n is input to the base and the output signal OUT6n is output from the collector, an NPN bipolar transistor Q7 to which the summation signal IN6p is input to the base and the output signal OUT6p is output from the collector, an NPN bipolar transistor Q8 to which the positive-phase carrier signal IN7p is input to the base and the collector is connected to the emitters of transistors Q4 and Q5, and an inverse-phase carrier signal I The circuit consists of an NPN bipolar transistor Q9 to which N7n is input and whose collector is connected to the emitters of transistors Q6 and Q7, an NPN bipolar transistor Q10 to which a bias voltage VB is applied to the base, a resistor R6 with one end connected to the power supply voltage VCC and the other end connected to the collectors of transistors Q4 and Q7, a resistor R7 with one end connected to the power supply voltage VCC and the other end connected to the collectors of transistors Q5 and Q6, a resistor R8 with one end connected to the emitter of transistor Q8 and the other end connected to the collector of transistor Q10, a resistor R9 with one end connected to the emitter of transistor Q9 and the other end connected to the collector of transistor Q10, and a resistor R10 with one end connected to the emitter of transistor Q10 and the other end connected to ground.

[0041] In the example shown in Figure 5, a differential configuration circuit is displayed. However, in a single-phase configuration as shown in Figure 1, a single-phase input, single-phase output mixer and a single-phase input, single-phase output filter may be provided instead of the amplifier circuit 3.

[0042] [Fourth embodiment] Figure 7 is a block diagram showing the configuration of a phase adjustment circuit according to a fourth embodiment of the present invention. The phase adjustment circuit of this embodiment comprises a clock generation circuit 1a, a differential input differential output type variable gain amplifier circuit 2b whose non-inverting input terminal is connected to the non-inverting output terminal of the clock generation circuit 1a and whose inverting input terminal is connected to the inverting output terminal of the clock generation circuit 1a, a differential input differential output type amplifier circuit 3a whose non-inverting input terminal is connected to the non-inverting output terminal of the variable gain amplifier circuit 2b and whose inverting input terminal is connected to the inverting output terminal of the variable gain amplifier circuit 2b, transmission lines 4p, 4n, and load circuits 5p, 5n.

[0043] In this embodiment, a variable gain amplifier circuit 2b is provided instead of the amplifier circuit 2a in the second embodiment in order to adjust the amplitude of the differential signals OUTp and OUTn output from the amplifier circuit 3a. The configuration of the variable gain amplifier circuit 2b is not limited, but for example, the Gilbert cell circuit shown in Figure 6 can be used.

[0044] When using a Gilbert cell circuit as the variable gain amplifier circuit 2b, the positive-sequence gain control signal should be input instead of IN6p in Figure 6, the negative-sequence gain control signal instead of IN6n, the positive-sequence clock signal output from the clock generation circuit 1a should be input instead of IN7p, and the negative-sequence clock signal output from the clock generation circuit 1a should be input instead of IN7n. The gain of the variable gain amplifier circuit 2b can be controlled by the voltage difference between the positive-sequence gain control signal and the negative-sequence gain control signal.

[0045] [Fifth Example] Figure 8 is a block diagram showing the configuration of a phase adjustment circuit according to a fifth embodiment of the present invention. The phase adjustment circuit of this embodiment includes a clock generation circuit 1a, a variable gain amplifier circuit 2b, an amplifier circuit 3a, transmission lines 4p, 4n, load circuits 5p, 5n, and an amplitude control circuit 8.

[0046] The amplitude control circuit 8 outputs a gain control signal to the variable gain amplifier circuit 2b so that the amplitudes of the output signals OUTp and OUTn of the amplifier circuit 3a remain constant. In this way, by detecting the amplitudes of the output signals OUTp and OUTn and performing feedback control to adjust the gain of the variable gain amplifier circuit 2b, the amplitudes of the output signals OUTp and OUTn can be kept constant.

[0047] [Sixth embodiment] Figure 9 is a block diagram showing the configuration of a phase adjustment circuit according to the sixth embodiment of the present invention. The phase adjustment circuit of this embodiment comprises a clock generation circuit 1a, amplification circuits 2a and 3a, transmission lines 4p and 4n, load circuits 5p and 5n, and an impedance control circuit 9.

[0048] In differential transmission lines 4p and 4n, the quality of the differential signal is a concern. In this embodiment, an impedance control circuit 9 is used to maintain the signal quality of the differential signal. The impedance control circuit 9 evaluates the signal quality of the differential signals OUTp and OUTn output from the amplifier circuit 3a and individually controls the impedance of the load circuits 5p and 5n based on the evaluation result.

[0049] Signal quality can be evaluated by focusing on the fact that the sum of the positive-sequence output signal OUTp and the negative-sequence output signal OUTn is 0. Figure 10 is a circuit diagram showing the configuration of the signal quality evaluation circuit 10 within the impedance control circuit 9. The signal quality evaluation circuit 10 consists of an NPN bipolar transistor Q11 to which the positive-sequence output signal OUTp output from the amplifier circuit 3a is input to the base and which outputs the negative-sequence output signal OUT10n from the collector, an NPN bipolar transistor Q12 to which the negative-sequence output signal OUTn output from the amplifier circuit 3a is input to the base and which outputs the positive-sequence output signal OUT10p from the collector, an NPN bipolar transistor Q13 to which a bias voltage Vb is applied to the base, and a transistor with one end connected to the power supply voltage VCC and the other end connected to a transistor It consists of resistor R11 connected to the collector of transistor Q11, resistor R12 with one end connected to the power supply voltage VCC and the other end connected to the collector of transistor Q12, resistor R13 with one end connected to the emitter of transistor Q11 and the other end connected to the collector of transistor Q13, resistor R14 with one end connected to the emitter of transistor Q12 and the other end connected to the collector of transistor Q13, and resistor R15 with one end connected to the emitter of transistor Q13 and the other end connected to ground.

[0050] When the sum of the differential signals OUTp and OUTn is 0, the difference between the output signals OUT10p and OUT10n of the signal quality evaluation circuit 10 becomes 0. By controlling the impedance of the load circuits 5p and 5n so that the sum of the differential signals OUTp and OUTn is 0 (so that the difference between the output signals OUT10p and OUT10n is 0), the quality of the differential signals OUTp and OUTn can be improved.

[0051] Since the sum of the differential signals OUTp and OUTn changes over time, a processor or the like that performs digital signal processing is provided in the impedance control circuit 9 after the signal quality evaluation circuit 10. Based on the output signals OUT10p and OUT10n of the signal quality evaluation circuit 10, the impedances of the load circuits 5p and 5n can be controlled so that the time average of the sum of the differential signals OUTp and OUTn becomes zero.

[0052] The signal quality evaluation circuit 10 is not limited to the configuration shown in Figure 10, and may be implemented using a passive multiplexing circuit. In addition, in the third and sixth embodiments, a variable gain amplifier circuit 2b may be provided instead of the amplifier circuit 2a. Also, in the fourth to sixth embodiments, the mixer 6 and filter 7 described in the third embodiment may be provided instead of the amplifier circuit 3a.

[0053] [Seventh Embodiment] In the first to sixth embodiments, the load circuits 5, 5p, and 5n can be the same as those shown in Figure 11, which consist of a capacitor and a variable resistor for blocking the DC component. One end of the capacitor C1 is connected to the termination of the transmission lines 4, 4p, and 4n, and the other end of the capacitor C1 is connected to one end of the variable resistor VR1. The other end of the variable resistor VR1 is connected to ground.

[0054] In actual circuits, the configuration shown in Figures 12 and 13 can also be used as the variable resistor VR1. In the configuration shown in Figure 12, the variable resistor VR1 consists of an NPN bipolar transistor Q14, to which a control voltage Vctrl is input at the base, the collector connected to the power supply voltage VCC, and the emitter connected to the other end of the capacitor C1, and a resistor R16, to which one end is connected to the emitter of transistor Q14 and the other end is connected to ground.

[0055] In the configuration shown in Figure 13, the variable resistor VR1 consists of an NPN bipolar transistor Q15, to which a control voltage Vctrl is input at the base, the collector connected to the power supply voltage VCC, and the emitter connected to the other end of the capacitor C1, and an NPN bipolar transistor Q16, to which a bias voltage Vb is applied at the base, the collector connected to the emitter of transistor Q15, and the emitter connected to ground.

[0056] In both configurations shown in Figures 12 and 13, the impedance of the load circuit 5 can be changed by changing the control voltage Vctrl. In the examples shown in Figures 12 and 13, increasing the control voltage Vctrl increases the impedance of the load circuit 5, and decreasing the control voltage Vctrl decreases the impedance of the load circuit 5.

[0057] Alternatively, the load circuit 5 may be realized by a feedback configuration using a variable gain amplifier circuit, as shown in Figure 14. In the configuration of Figure 14, the variable resistor VR1 consists of a variable gain amplifier circuit A1, to which a reference voltage VRef is input at the non-inverting input terminal and which has its inverting input terminal connected to the other end of the capacitor C1, and a resistor R17, to which one end is connected to the output terminal of the variable gain amplifier circuit A1 and the other end is connected to the inverting input terminal of the variable gain amplifier circuit A1. In the configuration of Figure 14, increasing the gain of the variable gain amplifier circuit A1 decreases the impedance of the load circuit 5, and decreasing the gain of the variable gain amplifier circuit A1 increases the impedance of the load circuit 5.

[0058] The impedance of the load circuit 5 can be changed by changing the gain of the variable gain amplifier circuit A1 using the control voltage Vctrl. As described above, a Gilbert cell circuit can be used as the variable gain amplifier circuit A1. In the examples shown in Figures 11 to 14, capacitance C1 is inserted due to the bias point considerations, but depending on the design, capacitance C1 may be omitted, and the terminations of transmission lines 4, 4p, and 4n may be directly connected to the variable resistor VR1.

[0059] In the first to sixth embodiments, a variable capacitor VC1 as shown in Figure 15 can also be used as the load circuits 5, 5p, and 5n. One end of the variable capacitor VC1 is connected to the termination of the transmission lines 4, 4p, and 4n, and the other end of the variable capacitor VC1 is connected to ground.

[0060] In actual circuits, the configuration shown in Figures 16 and 17 can also be used as the variable capacitor VC1. In the configuration of Figure 16, the variable capacitor VC1 consists of a capacitor C2 with one end connected to the termination of transmission lines 4, 4p, and 4n, a diode D1 with a control voltage Vctrl input to its anode and its cathode connected to the other end of capacitor C2, and a resistor R18 with one end connected to the cathode of diode D1 and the other end connected to ground.

[0061] In the configuration shown in Figure 17, the variable capacitance VC1 consists of a capacitance C3, one end of which is connected to the termination of transmission lines 4, 4p, and 4n; a diode D2, to which a control voltage Vctrl is input and whose cathode is connected to the other end of capacitance C3; and an NPN bipolar transistor Q17, to which a bias voltage Vb is applied at the base, whose collector is connected to the cathode of diode D2, and whose emitter is connected to ground.

[0062] In both configurations shown in Figures 16 and 17, the impedance of the load circuit 5 can be changed by changing the control voltage Vctrl. In the examples shown in Figures 16 and 17, increasing the control voltage Vctrl increases the impedance of the load circuit 5, and decreasing the control voltage Vctrl decreases the impedance of the load circuit 5.

[0063] Alternatively, as shown in Figure 18, the variable capacitance VC1 may be realized by a feedback configuration using a variable gain amplifier circuit. In the configuration of Figure 18, the variable capacitance VC1 consists of a capacitance C4, one end of which is connected to the termination of transmission lines 4, 4p, and 4n; a variable gain amplifier circuit A2, to which a reference voltage VRef is input at the non-inverting input terminal and to which the inverting input terminal is connected to the other end of capacitance C4; and a capacitance C5, one end of which is connected to the output terminal of the variable gain amplifier circuit A2 and the other end of which is connected to the inverting input terminal of the variable gain amplifier circuit A2. In the configuration of Figure 18, increasing the gain of the variable gain amplifier circuit A2 decreases the impedance of the load circuit 5, and decreasing the gain of the variable gain amplifier circuit A2 increases the impedance of the load circuit 5.

[0064] The impedance of the load circuit 5 can be changed by changing the gain of the variable gain amplifier circuit A2 using the control voltage Vctrl. As described above, a Gilbert cell circuit can be used as the variable gain amplifier circuit A2.

[0065] In the first to sixth embodiments, it is also possible to use a circuit combining a variable resistor VR1 and a variable capacitor VC1 as the load circuits 5, 5p, and 5n, as shown in Figure 19. In actual circuits, the configurations shown in Figures 20 to 22 can be adopted as the load circuits 5, 5p, and 5n.

[0066] In the configuration shown in Figure 20, the load circuit 5 consists of a capacitor C1 with one end connected to the termination of transmission lines 4, 4p, and 4n; an NPN bipolar transistor Q14 with a control voltage Vctrl input to its base, a collector connected to the power supply voltage VCC, and an emitter connected to the other end of capacitor C1; a resistor R16 with one end connected to the emitter of transistor Q14 and the other end connected to ground; and a diode D1 with a control voltage Vctrlc input to its anode and a cathode connected to the other end of capacitor C1.

[0067] In the configuration shown in Figure 21, the load circuit 5 consists of a capacitor C1 with one end connected to the termination of transmission lines 4, 4p, and 4n; an NPN bipolar transistor Q15 with a control voltage Vctrl input to its base, a collector connected to the power supply voltage VCC, and an emitter connected to the other end of capacitor C1; an NPN bipolar transistor Q16 with a bias voltage Vb applied to its base, a collector connected to the emitter of transistor Q15, and an emitter connected to ground; and a diode D2 with a control voltage Vctrlc input to its anode and a cathode connected to the other end of capacitor C1.

[0068] In the examples in Figures 20 and 21, increasing the control voltages Vctrl and Vctrlc increases the impedance of the load circuit 5, while decreasing the control voltages Vctrl and Vctrlc decreases the impedance of the load circuit 5.

[0069] In the configuration shown in Figure 22, the load circuit 5 consists of a capacitor C1 with one end connected to the termination of transmission lines 4, 4p, and 4n; a variable gain amplifier circuit A1 with a reference voltage VRef input to its non-inverting input terminal and an inverting input terminal connected to the other end of capacitor C1; a resistor R17 with one end connected to the output terminal of variable gain amplifier circuit A1 and the other end connected to the inverting input terminal of variable gain amplifier circuit A1; a variable gain amplifier circuit A2 with a reference voltage VRef input to its non-inverting input terminal and an inverting input terminal connected to the other end of capacitor C1; and a capacitor C5 with one end connected to the output terminal of variable gain amplifier circuit A2 and the other end connected to the inverting input terminal of variable gain amplifier circuit A2.

[0070] In the configuration shown in Figure 22, increasing the gain of the variable gain amplifier circuits A1 and A2 decreases the impedance of the load circuit 5, while decreasing the gain of the variable gain amplifier circuits A1 and A2 increases the impedance of the load circuit 5. By changing the gain of the variable gain amplifier circuits A1 and A2 using the control voltages Vctrl and Vctrlc, the impedance of the load circuit 5 can be changed.

[0071] In the first to sixth embodiments, a variable inductor VL1 as shown in Figure 23 can also be used as the load circuits 5, 5p, and 5n. One end of capacitor C1 is connected to the termination of transmission lines 4, 4p, and 4n, and the other end of capacitor C1 is connected to one end of variable inductor VL1. The other end of variable inductor VL1 is connected to ground.

[0072] As shown in Figure 24, it is also possible to use a circuit that combines a variable resistor VR1, a variable capacitor VC1, and a variable inductor VL1 as the load circuits 5, 5p, and 5n in the first to sixth embodiments. Alternatively, the variable resistor VR1 may be combined with the variable inductor VL1, or the variable capacitor VC1 may be combined with the variable inductor VL1.

[0073] Figures 11 to 24 illustrate the configuration of load circuit 5 as an example, but the configurations of load circuits 5p and 5n are the same as those of load circuit 5. As explained in the sixth embodiment, when the load circuits 5p and 5n are combined with the impedance control circuit 9, if the sum of the differential signals OUTp and OUTn is positive, the impedance of the load circuit 5n is increased and the impedance of the load circuit 5p is decreased. Also, if the sum of the differential signals OUTp and OUTn is negative, the impedance of the load circuit 5p is increased and the impedance of the load circuit 5n is decreased.

[0074] [Eighth embodiment] Next, an eighth embodiment of the present invention will be described. This embodiment shows specific examples of the transmission lines 4, 4p, and 4n of the first to seventh embodiments. Cross-sectional views of the transmission lines 4p and 4n are shown in Figures 25 to 27. The example in Figure 25 shows an example of a microstrip line. The transmission line 4p consists of a dielectric 400, a signal line 401 consisting of a conductor formed on the surface of the dielectric 400, and a ground plane 403 consisting of a conductor formed on the back surface of the dielectric 400. The transmission line 4n consists of a dielectric 400, a signal line 402 consisting of a conductor formed on the surface of the dielectric 400, and a ground plane 403.

[0075] The example in Figure 26 shows an example of a coplanar transmission line. Transmission line 4p consists of a dielectric 400, a signal line 401, and a ground plane 404 consisting of a conductor formed on the surface of the dielectric 400 opposite the signal line 402, with the signal line 401 in between. Transmission line 4n consists of a dielectric 400, a signal line 402, and a ground plane 405 consisting of a conductor formed on the surface of the dielectric 400 opposite the signal line 401, with the signal line 402 in between.

[0076] In this invention, in order to reduce the mounting area, a composite structure combining a coplanar line and a microstrip line may be adopted. Figure 27 shows an example of a composite coplanar line with back-surface grounding. Transmission line 4p consists of a dielectric 400, a signal line 401, and ground planes 403 and 404. Transmission line 4n consists of a dielectric 400, a signal line 402, and ground planes 403 and 405.

[0077] Figures 25 to 27 illustrate the configuration of transmission lines 4p and 4n as an example, but in the case of transmission line 4, it is sufficient to provide only one of the signal lines 401 or 402. The structure of transmission lines 4, 4p, and 4n is not limited to the cross-sectional structures shown in Figures 25 to 27; other structures are also acceptable as long as they allow for the definition of characteristic impedance.

[0078] Figures 4, 6, 10, 12, 13, 17, 20, and 21 show examples using bipolar transistors as transistors Q1 to Q17, but MOS transistors may also be used. When using MOS transistors, simply replace the base with the gate, the collector with the drain, and the emitter with the source in the above explanation.

[0079] Some or all of the above examples may also be described as follows, but are not limited to the following:

[0080] (Note 1) The phase adjustment circuit of the present invention comprises a clock generation circuit configured to generate a sinusoidal clock signal, an amplification circuit configured to amplify the clock signal output from the clock generation circuit, a transmission line whose input terminal is connected to the output terminal of the amplification circuit, a load circuit connected to the end of the transmission line whose impedance can be adjusted from the outside, and an output circuit whose input is a signal obtained by adding the output signal of the amplification circuit and the return signal from the transmission line at the output terminal of the amplification circuit.

[0081] (Note 2) In the phase adjustment circuit described in Note 1, the load circuit consists of a variable resistor whose impedance can be adjusted from the outside.

[0082] (Note 3) In the phase adjustment circuit described in Note 1, the load circuit consists of a variable capacitance whose impedance can be adjusted from the outside.

[0083] (Note 4) In the phase adjustment circuit described in Note 1, the load circuit consists of a variable inductor whose impedance can be adjusted from the outside.

[0084] (Note 5) In the phase adjustment circuit described in Note 1, the load circuit consists of at least two combinations of a variable resistor, a variable capacitor, and a variable inductor, whose impedance can be adjusted from the outside.

[0085] (Note 6) In the phase adjustment circuit described in Note 1, the clock generation circuit generates a sinusoidal differential clock signal, the amplification circuit is a differential input differential output type circuit that amplifies the differential clock signal, the transmission line consists of a first transmission line whose input terminal is connected to the non-inverting output terminal of the amplification circuit, and a second transmission line whose input terminal is connected to the inverting output terminal of the amplification circuit, the load circuit consists of a first load circuit connected to the end of the first transmission line whose impedance can be adjusted from the outside, and a second load circuit connected to the end of the second transmission line whose impedance can be adjusted from the outside The output circuit is a differential input differential output type circuit that takes as input a signal obtained by adding the positive-phase output signal of the amplification circuit and the return signal from the first transmission line at the non-inverting output terminal of the amplification circuit, and a signal obtained by adding the negative-phase output signal of the amplification circuit and the return signal from the second transmission line at the inverting output terminal of the amplification circuit, and further includes an impedance control circuit configured to control the impedances of the first and second load circuits so that the sum of the differential signals output from the output circuit is 0.

[0086] (Note 7) In the phase adjustment circuit described in Note 1, the output circuit is an amplifier circuit configured to amplify the signal added at the output terminal of the amplifier circuit.

[0087] (Note 8) In the phase adjustment circuit described in Note 1, the output circuit comprises a mixer configured to mix the signal added at the output terminal of the amplification circuit with a carrier signal input from an external source, and a filter configured to filter the output signal of the mixer and allow a signal of a desired frequency to pass through. [Industrial applicability]

[0088] This invention can be applied to techniques for adjusting the phase of a sine wave. [Explanation of Symbols]

[0089] 1,1a...Clock generation circuit, 2,2a,3,3a...Amplifier circuit, 2b,A1,A2...Variable gain amplifier circuit, 4,4p,4n...Transmission line, 5,5p,5n...Load circuit, 6...Mixer, 7...Filter, 8...Amplitude control circuit, 9...Impedance control circuit, 10...Signal quality evaluation circuit, 400...Dielectric, 401,402...Signal line, 403~405...Ground plane, Q1~Q17...NPN transistor, D1,D2...Diode, R1~R18...Resistor, C1~C5...Capacitance, VR1...Variable resistor, VC1...Variable capacitance, VL1...Variable inductor.

Claims

1. A phase adjustment for a clock signal used as a timing reference for data determination. A phase adjustment circuit, A clock generation circuit configured to generate a sinusoidal clock signal, A differential input configured to amplify the clock signal output from the clock generation circuit. A differential output type amplifier circuit, A first transmission line whose input terminal is connected to the non-inverting output terminal of the amplification circuit, A second transmission line whose input terminal is connected to the inverting output terminal of the amplification circuit, A first transmission line is connected to the end of the first transmission line, and its impedance can be adjusted from the outside. The load circuit and A second impedance adjustment is externally controlled and connected to the termination of the second transmission line. The load circuit and The output signal on the positive phase side of the amplification circuit and the return signal from the first transmission line are connected to the amplification circuit. The signal added at the non-inverting output terminal of the circuit, and the output signal on the reversed phase side of the amplification circuit and the preceding The return signal from the second transmission line is added to the signal at the inverting output terminal of the amplification circuit. A differential input differential output type output circuit that takes a number as input, A signal component that outputs the sum of the differential signals output from the non-inverting and inverting output terminals of the aforementioned output circuit. The quality evaluation circuit is included, and the first and second load circuits are configured such that the sum of the differential signals is zero. A control circuit is configured to adjust the impedance from an external source, comprising: A phase adjustment circuit characterized by the following.

2. In the phase adjustment circuit according to claim 1, Each of the first and second load circuits is capable of externally adjusting its impedance. A phase adjustment circuit characterized by consisting of variable resistors.

3. In the phase adjustment circuit according to claim 1, Each of the first and second load circuits is capable of externally adjusting its impedance. A phase adjustment circuit characterized by being composed of variable capacitance.

4. In the phase adjustment circuit according to claim 1, Each of the first and second load circuits is capable of externally adjusting its impedance. A phase adjustment circuit characterized by consisting of a variable inductor.

5. In the phase adjustment circuit according to claim 1, Each of the first and second load circuits is capable of externally adjusting its impedance. It is characterized by consisting of at least two combinations of variable resistors, variable capacitors, and variable inductors. A phase adjustment circuit that serves as a distinguishing feature.

6. In the phase adjustment circuit according to claim 1, The output circuit is summed at the non-inverting and inverting output terminals of the amplification circuit, respectively. Phase adjustment is characterized by a second amplification circuit configured to amplify the aforementioned signal. circuit.

7. In the phase adjustment circuit according to claim 1, The output circuit described above is The sum of the above signals at the non-inverting and inverting output terminals of the amplification circuit and the external A mixer configured to mix the input carrier signal with the following: The mixer is configured to filter the output signal and allow a signal of a desired frequency to pass through. A phase adjustment circuit characterized by being composed of a filter.

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