Optical connection structure, optical module
The optical connection structure enhances positional accuracy between silicon photonics chips and waveguides by using a cladding and core configuration, addressing alignment challenges and reducing optical loss.
Patent Information
- Authority / Receiving Office
- JP · JP
- Patent Type
- Patents
- Current Assignee / Owner
- SHINKO ELECTRIC IND CO LTD
- Filing Date
- 2022-10-20
- Publication Date
- 2026-07-07
AI Technical Summary
The existing optical connection structures face challenges in achieving sufficient positional accuracy between silicon photonics chips and optical waveguides, leading to alignment difficulties.
The optical connection structure integrates a first and second silicon photonics chip with an optical waveguide, utilizing a first cladding to fill the gap between the chips and a core to optically connect the waveguides, with a second cladding covering the core, enhancing alignment precision.
This configuration improves positional accuracy between the silicon photonics chips and optical waveguides to the submicron order, reducing optical loss and facilitating high-precision alignment.
Smart Images
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Figure 0007885980000003
Abstract
Description
Technical Field
[0001] The present invention relates to an optical connection structure and an optical module.
Background Art
[0002] In a data center or the like where various computers and devices for data communication are installed, optical signals are transmitted and received using an optical connection structure having a silicon photonics chip and an optical waveguide.
[0003] For example, a silicon photonics chip is flip-chip mounted on a wiring board having an optical waveguide, and an optical connection structure is known in which a silicon waveguide included in the silicon photonics chip and a core included in the optical waveguide are arranged to face each other with a gap therebetween.
Prior Art Documents
Patent Documents
[0004]
Patent Document 1
Summary of the Invention
Problems to be Solved by the Invention
[0005] However, in the above optical connection structure, it is difficult to align the silicon photonics chip and the optical waveguide, and thus the positional accuracy between the silicon photonics chip and the optical waveguide may not be sufficient.
[0006] The present invention has been made in view of the above points, and an object thereof is to improve the positional accuracy between a silicon photonics chip and an optical waveguide in an optical connection structure having a silicon photonics chip and an optical waveguide.
Means for Solving the Problems
[0007] The optical connection structure comprises a first silicon photonics chip having a first side surface, a second silicon photonics chip having a second side surface and arranged such that the second side surface faces the first side surface, and an optical waveguide arranged across the first silicon photonics chip and the second silicon photonics chip, wherein the first silicon photonics chip comprises a first silicon substrate and a first silicon waveguide provided on one side of the first silicon substrate, and the second silicon photonics chip comprises a second silicon substrate and a second silicon waveguide provided on one side of the second silicon substrate, and the optical waveguide is In contact with the first side and the second side Fill the gap between the first side and the second side , protruding from the other side of the first silicon substrate and the second silicon substrate or being flush with it. The device comprises a first cladding, a core disposed on the first cladding and covering one end of the first silicon waveguide and one end of the second silicon waveguide, thereby optically connecting the first silicon waveguide and the second silicon waveguide, and a second cladding covering the core. [Effects of the Invention]
[0008] According to the disclosed technology, in an optical connection structure having a silicon photonics chip and an optical waveguide, the positional accuracy between the silicon photonics chip and the optical waveguide can be improved. [Brief explanation of the drawing]
[0009] [Figure 1] This figure illustrates an optical connection structure according to the first embodiment. [Figure 2] This is a diagram (part 1) illustrating the manufacturing process of the optical connection structure according to the first embodiment. [Figure 3] This is a diagram (part 2) illustrating the manufacturing process of the optical connection structure according to the first embodiment. [Figure 4] This is a diagram (part 3) illustrating the manufacturing process of the optical connection structure according to the first embodiment. [Figure 5] This is a diagram (part 4) illustrating the manufacturing process of the optical connection structure according to the first embodiment. [Figure 6] This is a cross-sectional view illustrating an optical module according to the first embodiment. [Figure 7] This is a cross-sectional view illustrating an optical module related to a comparative example. [Figure 8] This is a cross-sectional view illustrating an optical connection structure according to a modified example 1 of the first embodiment. [Modes for carrying out the invention]
[0010] The embodiments for carrying out the invention will be described below with reference to the drawings. In each drawing, the same reference numerals are used for identical components, and redundant explanations may be omitted.
[0011] <First Embodiment> [Optical connection structure] Figure 1 illustrates an optical connection structure according to the first embodiment, where Figure 1(a) is a plan view and Figure 1(b) is a cross-sectional view along line AA in Figure 1(a). In Figure 1, mutually orthogonal X, Y, and Z directions are defined for reference. Similar directions may be defined in subsequent figures as needed.
[0012] As shown in Figure 1, the optical connection structure 1 according to the first embodiment includes a first silicon photonics chip 10, a second silicon photonics chip 20, and an optical waveguide 30. Here, as an example, the planar shape of the optical connection structure 1 is rectangular, with the longer side of the rectangle parallel to the X direction and the shorter side of the rectangle parallel to the Y direction. The Z direction is the stacking direction of each layer constituting the optical connection structure 1. Note that viewing an object from the Z direction is called a planar view, and the shape that is visible at that time is called the planar shape.
[0013] The first silicon photonics chip 10 comprises a first silicon substrate 11 and a first silicon waveguide 13 provided on one side of the first silicon substrate 11. The first silicon photonics chip 10 has a first side surface 10c. The first side surface 10c is, for example, parallel to the YZ plane. The thickness of the first silicon substrate 11 is, for example, about 100 μm to 800 μm.
[0014] The first silicon waveguide 13 is disposed between a first protective film 12 provided on the first silicon substrate 11 and a second protective film 14 provided on the first protective film 12. The first protective film 12 and the second protective film 14 can be formed of, for example, SiO2, SiOx, etc. The thicknesses of the first protective film 12 and the second protective film 14 are, for example, about 2 μm to 6 μm.
[0015] The number of the first silicon waveguides 13 can be determined as needed. In the example of FIG. 1, four elongated first silicon waveguides 13 whose longitudinal direction in plan view is the X direction are juxtaposed in the Y direction at a predetermined interval on the first protective film 12. The pitch of the juxtaposed first silicon waveguides 13 can be, for example, about 20 μm to 300 μm. A part of each of the first silicon waveguides 13 is covered with the second protective film 14. The first silicon waveguide 13 functions as a core, and the first protective film 12 and the second protective film 14 function as claddings.
[0016] One end of each of the first silicon waveguides 13 is exposed from the second protective film 14. In plan view, one end of each of the first silicon waveguides 13 has a tapered shape. That is, in plan view, one end of each of the first silicon waveguides 13 becomes narrower as it approaches the first cladding 31 (described later). With such a shape, the optical coupling efficiency between the first silicon waveguide 13 and the core 32 (described later) can be improved. The width of the first silicon waveguide 13 is, for example, about 200 nm to 500 nm except for the tapered portion. The width of the tip of the tapered portion is, for example, about half of the width of the portion with a constant width. The thickness of each of the first silicon waveguides 13 is constant. The thickness of each of the first silicon waveguides 13 is, for example, about 20 nm to 300 nm.
[0017] The first silicon photonics chip 10 further includes light-emitting elements 15 and 16 that emit light to the other end of the first silicon waveguide 13, and light-receiving elements 17 and 18 that receive light emitted from the other end of the first silicon waveguide 13. The light-emitting elements 15 and 16, and the light-receiving elements 17 and 18 are mounted, for example, on the first silicon substrate 11. A cavity for mounting the light-emitting elements 15 and 16 and the light-receiving elements 17 and 18 may be provided in the first silicon substrate 11. The light-emitting elements 15 and 16 are, for example, laser diodes. The light-receiving elements 17 and 18 are, for example, photodiodes.
[0018] The first silicon photonics chip 10 further includes electrode pads 19 for external connection. The electrode pads 19 are provided, for example, in plurality on the second protective film 14 and are electrically connected to the light-emitting elements 15 and 16 and the light-receiving elements 17 and 18. The electrode pads 19 can be formed, for example, from copper or aluminum.
[0019] The second silicon photonics chip 20 includes a second silicon substrate 21 and a second silicon waveguide 23 provided on one surface side of the second silicon substrate 21. The second silicon photonics chip 20 includes a second side surface 20c. The second side surface 20c is, for example, parallel to the YZ plane. The second silicon photonics chip 20 is arranged such that the second side surface 20c faces the first side surface 10c. The thickness of the second silicon substrate 21 is, for example, the same as the thickness of the first silicon substrate 11.
[0020] The second silicon waveguide 23 is arranged between a third protective film 22 provided on the second silicon substrate 21 and a fourth protective film 24 provided on the third protective film 22. The third protective film 22 and the fourth protective film 24 can be formed, for example, from SiO2, SiOx, etc. The thicknesses of the third protective film 22 and the fourth protective film 24 are, for example, the same as the thicknesses of the first protective film 12 and the second protective film 14.
[0021] The number of second silicon waveguides 23 can be determined as needed, but in the example shown in Figure 1, four elongated second silicon waveguides 23, with their longitudinal direction in the X direction in a plan view, are arranged side by side in the Y direction at predetermined intervals on the third protective film 22. The pitch of the side by side second silicon waveguides 23 is, for example, the same as the pitch of the side by side first silicon waveguides 13. A portion of each second silicon waveguide 23 is covered with a fourth protective film 24. The second silicon waveguides 23 function as a core, and the third protective film 22 and the fourth protective film 24 function as cladding.
[0022] One end of each second silicon waveguide 23 is exposed from the fourth protective film 24. In a plan view, one end of each second silicon waveguide 23 is tapered. That is, in a plan view, one end of each second silicon waveguide 23 narrows in width as it approaches the first cladding 31 (described later). This shape improves the optical coupling efficiency between the second silicon waveguide 23 and the core 32 (described later). The width of the second silicon waveguide 23 is the same as the width of the first silicon waveguide 13. The width of the tip of the tapered portion is the same as that of the first silicon waveguide 13. The thickness of each second silicon waveguide 23 is constant. For example, the thickness of each second silicon waveguide 23 is the same as that of each first silicon waveguide 13.
[0023] The second silicon photonics chip 20 further includes photodetectors 25 and 26 that receive light emitted from the other end of the second silicon waveguide 23, and light-emitting elements 27 and 28 that receive light incident on the other end of the second silicon waveguide 23. The photodetectors 25 and 26 and the light-emitting elements 27 and 28 are mounted, for example, on the second silicon substrate 21. Cavities for mounting the photodetectors 25 and 26 and the light-emitting elements 27 and 28 may be provided in the second silicon substrate 21. The photodetectors 25 and 26 are, for example, photodiodes. The light-emitting elements 27 and 28 are, for example, laser diodes.
[0024] The second silicon photonics chip 20 further includes electrode pads 29 for external connections. Multiple electrode pads 29 are provided, for example, on the fourth protective film 24 and are electrically connected to the photodetectors 25 and 26, and the light-emitting elements 27 and 28. The electrode pads 29 can be formed from, for example, copper or aluminum.
[0025] The optical waveguide 30 is positioned across the first silicon photonics chip 10 and the second silicon photonics chip 20. The optical waveguide 30 comprises a first cladding 31, a core 32, and a second cladding 33. The first cladding 31 fills the space between the first side surface 10c of the first silicon photonics chip 10 and the second side surface 20c of the second silicon photonics chip 20. The distance between the first side surface 10c and the second side surface 20c is, for example, about 0.3 mm to 20 mm.
[0026] The upper surface of the first protective film 12 on which the first silicon waveguide 13 is located, the upper surface of the third protective film 22 on which the second silicon waveguide 23 is located, and the upper surface of the first cladding 31 on which the core 32 is located are, for example, flush. The lower surface of the first cladding 31 may protrude from the lower surface of the first silicon substrate 11 and the lower surface of the second silicon substrate 21. Alternatively, the lower surface of the first cladding 31 may be flush with the lower surface of the first silicon substrate 11 and the lower surface of the second silicon substrate 21.
[0027] The first cladding 31 is formed from, for example, a photosensitive material. Specifically, the first cladding 31 can be formed from polymers such as polyimide resins, acrylic resins, epoxy resins, polyolefin resins, and polynorbornene resins. The thickness of the first cladding 31 is preferably, for example, 10 μm or more.
[0028] The cores 32 are selectively placed on the first cladding 31 and extend from the first cladding 31 onto the first protective film 12 and the third protective film 22. In the example shown in Figure 1, four elongated cores 32, with their longitudinal direction in the X direction in a plan view, are arranged side by side on the first cladding 31 at predetermined intervals in the Y direction. Each core 32 covers one end of each first silicon waveguide 13 and one end of each second silicon waveguide 23, optically connecting the first silicon waveguide 13 and the second silicon waveguide 23. Each core 32 covers at least the tapered portion of each first silicon waveguide 13 and each second silicon waveguide 23. The pitch of the side by side cores 32 can be, for example, about 100 μm to 300 μm. The cores 32 can be formed from the same material as the first cladding 31. The thickness of the cores 32 can be, for example, about 3 μm to 10 μm. The cross-sectional shape of the core 32 in the shorter direction can be, for example, a square.
[0029] The second cladding 33 is formed on the first cladding 31 and extends from the first cladding 31 onto the first protective film 12 and the third protective film 22. The second cladding 33 covers at least the top surface, both longitudinal sides, and both short sides of each core 32. Preferably, the second cladding 33 covers the first silicon waveguide 13 exposed from the second protective film 14 and the second silicon waveguide 23 exposed from the fourth protective film 24. The second cladding 33 may also cover the edges of the second protective film 14 and the fourth protective film 24. This reduces optical loss due to light leakage from the first silicon waveguide 13 and the second silicon waveguide 23. The second cladding 33 can be formed from the same material as the first cladding 31. The thickness of the second cladding 33 can be, for example, about 10 μm to 30 μm.
[0030] As described above, the first cladding 31, the core 32, and the second cladding 33 can be formed from the same material, but the refractive index of the core 32 is higher than that of the first cladding 31 and the second cladding 33. By including a refractive index controlling additive such as Ge in the core 32, the refractive index of the core 32 can be made higher than that of the first cladding 31 and the second cladding 33. For example, the refractive index of the first cladding 31 and the second cladding 33 can be 1.5, and the refractive index of the core 32 can be 1.6.
[0031] In Figure 1, for example, light emitted from the light-emitting element 15 enters the first silicon waveguide 13, propagates through the first silicon waveguide 13, and enters the core 32 of the optical waveguide 30. The light that propagates through the core 32 and exits the core 32 enters the second silicon waveguide 23, propagates through the second silicon waveguide 23, reaches the photodetector 25, and is converted into an electrical signal by the photodetector 25.
[0032] Furthermore, the light emitted from the light-emitting element 16 enters the first silicon waveguide 13, propagates within the first silicon waveguide 13, and enters the core 32 of the optical waveguide 30. The light that propagates within the core 32 and exits from the core 32 enters the second silicon waveguide 23, propagates within the second silicon waveguide 23, reaches the photodetector 26, and is converted into an electrical signal by the photodetector 26.
[0033] Furthermore, the light emitted from the light-emitting element 27 enters the second silicon waveguide 23, propagates within the second silicon waveguide 23, and enters the core 32 of the optical waveguide 30. The light that propagates within the core 32 and exits from the core 32 enters the first silicon waveguide 13, propagates within the first silicon waveguide 13, reaches the photodetector 17, and is converted into an electrical signal by the photodetector 17.
[0034] Furthermore, the light emitted from the light-emitting element 28 enters the second silicon waveguide 23, propagates within the second silicon waveguide 23, and enters the core 32 of the optical waveguide 30. The light that propagates within the core 32 and exits from the core 32 enters the first silicon waveguide 13, propagates within the first silicon waveguide 13, reaches the photodetector 18, and is converted into an electrical signal by the photodetector 18.
[0035] [Manufacturing method for optical connection structure] Next, the manufacturing method of the optical connection structure 1 will be described. Figures 2 to 5 illustrate the manufacturing process of the optical connection structure according to the first embodiment. In Figures 2 to 5, (a) is a plan view corresponding to Figure 1(a), and (b) is a cross-sectional view corresponding to Figure 1(b).
[0036] First, in the process shown in Figures 2(a) and 2(b), a first silicon photonics chip 10, a second silicon photonics chip 20, and a support substrate 100 having at least one flat surface are prepared. Then, the first silicon photonics chip 10 and the second silicon photonics chip 20 are bonded face up to one surface of the support substrate 100 using a first adhesive layer 120 and a second adhesive layer 130, such that the first side surface 10c and the second side surface 20c face each other. Examples of the first adhesive layer 120 and the second adhesive layer 130 include die attach film, photosensitive patterning adhesive, and liquid adhesive. Note that the support substrate 100 and the first silicon photonics chip 10 and the second silicon photonics chip 20 are only mechanically connected and not electrically connected.
[0037] The support substrate 100 can be made of silicon, glass, ceramic, metal, or the like. The thickness of the support substrate 100 can be, for example, about 500 μm. It is preferable that alignment marks are formed on one surface of the support substrate 100 for use in positioning the first silicon photonics chip 10 and the second silicon photonics chip 20 when bonding them together.
[0038] When bonding the first silicon photonics chip 10 and the second silicon photonics chip 20 to one side of the support substrate 100, pressure and heat may be applied during the process. The pressure and heat required at this time can be significantly lower than those generally required when mounting a device using a flip-chip method.
[0039] Furthermore, multiple regions for forming the optical connection structure 1 are defined on one surface of the support substrate 100. These multiple regions are arranged in a two-dimensional matrix, for example. The region enclosed by the dashed line C shown in Figure 2(a) is one of the regions for forming the optical connection structure 1. In this step, the first silicon photonics chip 10 and the second silicon photonics chip 20 are bonded to each region defined on one surface of the support substrate 100.
[0040] Next, in the steps shown in Figures 3(a) and 3(b), a first cladding 31 is formed on one surface of the support substrate 100 so as to fill the gap between the first side surface 10c of the first silicon photonics chip 10 and the second side surface 20c of the second silicon photonics chip 20. The first cladding 31 can be formed, for example, by laminating a film-like resin material. The first cladding 31 may also be formed by applying a liquid or paste-like resin material to one surface of the support substrate 100 and then curing it by ultraviolet irradiation or heating. The material of the first cladding 31 is as described above. In this step, it is preferable to make the upper surface of the first cladding 31 flush with the upper surface of the first protective film 12 and the upper surface of the third protective film 22 by pressing the upper surface of the first cladding 31 or the like. This facilitates the formation of the core 32.
[0041] Next, in the steps shown in Figures 4(a) and 4(b), a plurality of cores 32 are formed on the upper surface of the first cladding 31, the upper surface of the first protective film 12, and the upper surface of the third protective film 22. Each core 32 is formed to cover one end of each first silicon waveguide 13 and one end of each second silicon waveguide 23, thereby optically connecting the first silicon waveguide 13 and the second silicon waveguide 23. Each core 32 is formed to cover at least the tapered portion of each first silicon waveguide 13. Each core 32 can be formed, for example, by laminating a film-like resin material. Each core 32 may also be formed by applying a liquid or paste-like resin material and then curing it by ultraviolet irradiation or heating. The materials for each core 32 are as described above.
[0042] Next, in the steps shown in Figures 5(a) and 5(b), a second cladding 33 is formed on the upper surface of the first cladding 31, the upper surface of the first protective film 12, and the upper surface of the third protective film 22 so as to cover each core 32. The second cladding 33 is formed to cover at least the upper surface, both longitudinal sides, and both short sides of each core 32. Preferably, the second cladding 33 covers the first silicon waveguide 13 exposed from the second protective film 14 and the second silicon waveguide 23 exposed from the fourth protective film 24. The second cladding 33 may also cover the edges of the second protective film 14 and the fourth protective film 24. The second cladding 33 can be formed, for example, by the same method as the first cladding 31. The material of the second cladding 33 is as described above.
[0043] Next, after the steps shown in Figures 5(a) and 5(b), the support substrate 100 is removed and cut at the position of the dashed line C shown in Figures 5(a) and 5(b) to form individual pieces, thereby completing multiple optical connection structures 1. Cutting can be done using a dicer or the like. The first adhesive layer 120 and the second adhesive layer 130 may be removed at the same time as the support substrate 100, or some or all of them may remain on the optical connection structure 1 side.
[0044] In this way, the optical connection structure 1 integrates the first silicon photonics chip 10, the second silicon photonics chip 20, and the optical waveguide 30 on the support substrate 100. Since the adhesion of the first silicon photonics chip 10 and the second silicon photonics chip 20 to the support substrate 100 does not involve electrical connections, the amount of pressure and heat applied can be reduced compared to flip-chip mounting. As a result, high-precision alignment of the first silicon photonics chip 10 and the second silicon photonics chip 20 and the optical waveguide 30 becomes possible, achieving positional accuracy on the submicron order (for example, about ±0.5 μm).
[0045] Furthermore, in the optical connection structure 1, the first silicon waveguide 13 of the first silicon photonics chip 10 and the second silicon waveguide 23 of the second silicon photonics chip 20 are directly connected to the optical waveguide 30 without an air gap. Therefore, optical loss between the first silicon waveguide 13 and the second silicon waveguide 23 and the optical waveguide 30 can be reduced.
[0046] [Optical Module] Figure 6 is a cross-sectional view illustrating an optical module according to the first embodiment. As shown in Figure 6, the optical module 2 includes an optical connection structure 1 and a wiring substrate 3. The wiring substrate 3 is, for example, a build-up substrate in which insulating layers and wiring layers are alternately laminated, but is not limited to this, and may be any wiring substrate such as a silicon substrate or a ceramic substrate. Note that in Figure 6, the optical connection structure 1 is depicted inverted vertically compared to Figure 1, etc.
[0047] In the optical module 2, the first silicon photonics chip 10 and the second silicon photonics chip 20 of the optical connection structure 1 are flip-chip mounted on the wiring board 3. Specifically, a plurality of electrode pads 50 are formed on the upper surface of the wiring board 3. The electrode pads 50 of the wiring board 3 are electrically connected to the electrode pads 19 of the first silicon photonics chip 10 and the electrode pads 29 of the second silicon photonics chip 20 via bonding members 60. The bonding members 60 are, for example, solder balls or copper pillar bumps.
[0048] In the optical module 2, the light-emitting element 15 of the first silicon photonics chip 10 emits light in response to an electrical signal from the wiring board 3, which is then converted into an electrical signal by the light-receiving element 25 of the second silicon photonics chip 20 and sent to the wiring board 3. The reason why flip-chip mounting is used in the optical module 2 is to input and output high-speed electrical signals from the wiring board 3 to the first silicon photonics chip 10 and the second silicon photonics chip 20.
[0049] Figure 7 is a cross-sectional view illustrating an optical module according to a comparative example. As shown in Figure 7, in the optical module 2X according to the comparative example, a first silicon photonics chip 10X, a second silicon photonics chip 20X, and an optical waveguide 30X, which are independent of each other, are flip-chip mounted on the wiring board 3.
[0050] The first silicon photonics chip 10X, the second silicon photonics chip 20X, and the optical waveguide 30X are aligned when mounted on the wiring board 3. For example, the first silicon photonics chip 10X and the second silicon photonics chip 20X are flip-chip mounted on the wiring board 3 on which the optical waveguide 30X is formed, while optically aligning them with the optical waveguide 30X. Since the flip-chip mounting is performed while applying pressure and heat, the positional accuracy between the first silicon photonics chip 10X, the second silicon photonics chip 20X and the optical waveguide 30X is on the order of microns (for example, about ±2 to 3 μm).
[0051] On the other hand, the alignment of the first silicon photonics chip 10X and the second silicon photonics chip 20X with the optical waveguide 30X requires a positional accuracy on the submicron order (for example, about ±0.5 μm). In the structure of the optical module 2X, which requires flip-chip mounting while optically aligning with the optical waveguide 30X, achieving a positional accuracy on the submicron order (for example, about ±0.5 μm) is extremely difficult.
[0052] In contrast, the optical module 2 has an optical connection structure 1, which integrates the first silicon photonics chip 10, the second silicon photonics chip 20, and the optical waveguide 30, flip-chip mounted on the wiring board 3. The required positional accuracy for the first silicon photonics chip 10, the second silicon photonics chip 20, and the optical waveguide 30 is already achieved by the optical connection structure 1. Therefore, even if the positional accuracy when flip-chip mounting the optical connection structure 1 on the wiring board 3 is on the order of microns (for example, about ±2 to 3 μm), it does not affect optical communication.
[0053] Thus, in the optical module 2, even if the optical connection structure 1 is flip-chip mounted on the wiring board 3 with normal positional accuracy, the submicron-order positional accuracy required for the first silicon photonics chip 10, the second silicon photonics chip 20, and the optical waveguide 30 can be achieved. In other words, the positional accuracy of the first silicon photonics chip 10, the second silicon photonics chip 20, and the optical waveguide 30 can be improved compared to the optical module 2X of the comparative example.
[0054] <Variation 1 of the First Embodiment> Modification 1 of the first embodiment shows an example of an optical connection structure having a support substrate. In Modification 1 of the first embodiment, descriptions of components that are the same as those described in the previously described embodiments may be omitted.
[0055] Figure 8 is a cross-sectional view illustrating an optical connection structure according to Modification 1 of the First Embodiment. As shown in Figure 8, optical connection structure 1A differs from optical connection structure 1 in that it has a support substrate 100.
[0056] In the optical connection structure 1A, the other side of the first silicon substrate 11 is connected to one side of the support substrate 100 via the first adhesive layer 120. Similarly, the other side of the second silicon substrate 21 is connected to one side of the support substrate 100 via the second adhesive layer 130. The support substrate 100 and the first silicon photonics chip 10, and the support substrate 100 and the second silicon photonics chip 20 are only mechanically connected and not electrically connected. To manufacture the optical connection structure 1A, the support substrate 100 can be removed without separating the components using the process shown in Figures 5(a) and 5(b).
[0057] Thus, the optical connection structure 1A can be made more rigid than the optical connection structure 1 by including the support substrate 100. On the other hand, since the optical connection structure 1 does not have the support substrate 100, it offers greater design flexibility as any component such as a heat sink can be placed in the position where the support substrate 100 would have been.
[0058] In addition, in optical module 2, optical connection structure 1A may be used instead of optical connection structure 1.
[0059] Although preferred embodiments have been described in detail above, the invention is not limited to the embodiments described above, and various modifications and substitutions can be made to the embodiments described above without departing from the scope of the claims. [Explanation of symbols]
[0060] 1.1A Optical Connection Structure 2 Optical Modules 3 Wiring board 10. First Silicon Photonics Chip 10c 1st side 11. First silicon substrate 12 1st protective film 13. First Silicon Waveguide 14 Second protective film 15,16,27,28 Light-emitting element 17, 18, 25, 26 Photodetector 19,29 Electrode pads 20. Second Silicon Photonics Chip 20c 2nd side 21 Second silicon substrate 22 Third protective film 23. Second Silicon Waveguide 24 4th protective film 30 Optical waveguide 31 First Clad 32 cores 33 Second Clad 50 electrode pads 60 Joining members 100 Support substrate 120 1st adhesive layer 130 Second adhesive layer
Claims
1. A first silicon photonics chip having a first side surface, A second silicon photonics chip having a second side surface, wherein the second side surface is arranged to face the first side surface, The present invention comprises an optical waveguide arranged across the first silicon photonics chip and the second silicon photonics chip, The first silicon photonics chip is First silicon substrate and The first silicon waveguide is provided on one side of the first silicon substrate, The aforementioned second silicon photonics chip is The second silicon substrate and The second silicon waveguide is provided on one side of the second silicon substrate, The optical waveguide is, A first cladding that contacts the first and second surfaces and fills the space between the first and second surfaces, and that protrudes from or is flush with the other surface of the first and second silicon substrates, A core is disposed on the first cladding, covering one end of the first silicon waveguide and one end of the second silicon waveguide, and optically connecting the first silicon waveguide and the second silicon waveguide. An optical connection structure comprising a second cladding covering the core.
2. In a plan view, one end of the first silicon waveguide narrows in width as it approaches the first cladding. The optical connection structure according to claim 1, wherein, in a plan view, one end of the second silicon waveguide narrows in width as it approaches the first cladding.
3. Having a support substrate, The other side of the first silicon substrate is connected to one side of the support substrate via the first adhesive layer. The optical connection structure according to claim 1, wherein the other surface of the second silicon substrate is connected to one surface of the support substrate via a second adhesive layer.
4. The optical connection structure according to claim 3, wherein the support substrate and the first silicon photonics chip, and the support substrate and the second silicon photonics chip are not electrically connected.
5. The first silicon waveguide is disposed between a first protective film provided on the first silicon substrate and a second protective film provided on the first protective film. One end of the first silicon waveguide is exposed from the second protective film, The second silicon waveguide is positioned between a third protective film provided on the second silicon substrate and a fourth protective film provided on the third protective film. The optical connection structure according to claim 1, wherein one end of the second silicon waveguide is exposed from the fourth protective film.
6. The optical connection structure according to claim 5, further comprising electrode pads for external connection on the second protective film and the fourth protective film.
7. The optical connection structure according to claim 5, wherein the surface of the first protective film on which the first silicon waveguide is arranged, the surface of the third protective film on which the second silicon waveguide is arranged, and the surface of the first cladding on which the core is arranged are flush.
8. The first silicon photonics chip includes a light-emitting element that incidents light on the other end of the first silicon waveguide. The optical connection structure according to claim 1, wherein the second silicon photonics chip includes a photodetector that receives light emitted from the other end of the second silicon waveguide.
9. A plurality of first silicon waveguides are provided on one side of the first silicon substrate. A plurality of second silicon waveguides are provided on one side of the second silicon substrate. The optical waveguide is, The optical connection structure according to claim 1, comprising a plurality of cores that cover one end of each of the first silicon waveguides and one end of each of the second silicon waveguides, and optically connect each of the first silicon waveguides and each of the second silicon waveguides.
10. The optical connection structure is as described in any one of claims 1 to 9, and the wiring board is also included. An optical module in which the first silicon photonics chip and the second silicon photonics chip are flip-chip mounted on the wiring substrate.