Wrap-around projection liner for AI devices

Abstract

The semiconductor structure includes a plurality of conductive lines formed in a dielectric, each of the plurality of conductive lines in electrical communication with a respective contact, a metal layer disposed on each of the plurality of conductive lines, a phase change memory (PCM) element disposed on the metal layer of each of the plurality of conductive lines, and a projection liner encapsulating the PCM element, where a spacer is in direct contact with a sidewall of the projection liner, and the PCM element includes a GeSbTe (germanium antimony tellurium or GST) layer.

Description

Technical Field

[0001] The present invention generally relates to semiconductor devices, and more particularly to the formation of a wraparound projection liner for artificial intelligence (AI) devices.

Background Art

[0002] The use of phase change memory for analog computing requires memory cells having a resistance that changes linearly with a programming pulse and is predictable and repeatable. Amorphous phase change materials often suffer from "resistance drift" where the resistance of the cell changes over time, thereby making the resistance of the cell unpredictable.

Summary of the Invention

[0003] According to one embodiment, a semiconductor structure is provided. The semiconductor structure includes a phase change memory (PCM) element that horizontally and electrically connects a first contact and a second contact, and a projection liner that encapsulates the PCM element.

[0004] According to another embodiment, a semiconductor structure is provided. The semiconductor structure includes a plurality of conductive lines formed in a dielectric, each of the plurality of conductive lines being in electrical communication with a respective contact, a metal layer disposed on each of the plurality of conductive lines, a phase change memory (PCM) element disposed on the metal layer of each of the plurality of conductive lines, and a projection liner that encapsulates the PCM element.

[0005] According to yet another embodiment, a method is provided. The method includes forming a phase change memory (PCM) element, horizontally and electrically connecting the PCM element to a first contact and a second contact, and encapsulating the PCM element with a projection liner.

[0006] It should be noted that the exemplary embodiments are described with respect to a variety of subject matter. In particular, some embodiments are described with respect to method-type claims, while others are described with respect to apparatus-type claims. However, those skilled in the art will recognize from the above and below descriptions that, unless otherwise indicated, any combination of features belonging to one type of subject matter, as well as any combination of features relating to different subject matter, particularly between features of method-type claims and features of apparatus-type claims, will also be considered described in this document.

[0007] These and other features and advantages will become apparent from the following detailed description of the exemplary embodiment, which should be read in conjunction with the attached drawings.

[0008] The present invention will be described in detail in the following description of preferred embodiments with reference to the following drawings. [Brief explanation of the drawing]

[0009] [Figure 1] This is a cross-sectional view of a semiconductor structure according to one embodiment of the present invention, which includes a plurality of conductive lines formed in a dielectric layer, and on one or more of the plurality of conductive lines, a metal deposit is performed. [Figure 2] Figure 1 is a cross-sectional view of a semiconductor structure according to one embodiment of the present invention, in which a GeSbTe (germanium-antimony-tellurium or GST) layer, a projection liner, and a hard mask layer are deposited. [Figure 3] Figure 2 is a cross-sectional view of a semiconductor structure according to one embodiment of the present invention, in which a GST layer, a projection liner, and a hard mask layer are patterned to form a GST stack. [Figure 4] Figure 3 is a cross-sectional view of a semiconductor structure in which another projection liner is deposited on top of a GST stack, according to one embodiment of the present invention. [Figure 5] This is a cross-sectional view of the semiconductor structure shown in Figure 4, on which a spacer layer is deposited, according to one embodiment of the present invention. [Figure 6] Figure 5 is a cross-sectional view of a semiconductor structure according to one embodiment of the present invention, in which a spacer layer is etched to form a spacer adjacent to a projection liner. [Figure 7] This is a cross-sectional view of the semiconductor structure shown in Figure 6, in which a projection liner is etched, according to one embodiment of the present invention. [Figure 8] This is a cross-sectional view of the semiconductor structure shown in Figure 7, in which the uppermost layer is formed, according to one embodiment of the present invention. [Modes for carrying out the invention]

[0010] Throughout the drawing, the same or similar reference numbers represent the same or similar elements.

[0011] Embodiments of the present invention provide methods and devices for constructing wrap-around or all-around projection liners for phase-change material (PCM) devices. PCM devices having a resistive liner (e.g., projection segment) offer better repeatability and reduced resistive drift of the device due to the bypass of current through amorphous phase-change regions during readout operations. Self-healing of confined PCM devices by controlling the electromigration of the PCM at the nanoscale enables effective Joule heating for controlling the PCM, resulting in 2 × 10⁻⁶ 12 It offers superior reliability, enabling ultra-long programming cycles and noise reduction for low drift and multi-level cell operation, while eliminating etching damage (by constructing confined cells). However, confined cells present several challenges, including damage from chemi-mechanical planarization (CMP) and the need to fill small confined cells with GeSbTe (germanium antimony tellurium or GST).

[0012] Embodiments of the present invention provide methods and devices for mitigating such challenges by forming a projection liner that minimizes reactive ion etch (RIE) damage during PCM formation. Exemplary embodiments utilize a horizontal confinement cell structure of GST having a projection liner. Exemplary embodiments introduce self-aligned bridge cell contacts. In other words, a horizontal mushroom cell structure is introduced to improve durability, resistance drift, and program current. As a result, the exemplary method minimizes wet damage to the GST cell. The exemplary projection liner is a wrap-around or all-around liner that surrounds, encloses, or surrounds the PCM material containing the GST layer.

[0013] Phase-change materials can switch between a first structural state in which the material is generally amorphous solid and a second structural state in which the material is generally crystalline solid in the active region of the cell. The term "amorphous" is used to refer to a relatively unordered structure that is more disordered than a single crystal and has detectable properties such as higher electrical resistivity than the crystalline phase. The term "crystalline" is used to refer to a relatively ordered structure that is more regular than the amorphous structure and has detectable properties such as lower electrical resistivity than the amorphous phase. Other material properties affected by the transition between the amorphous and crystalline phases include atomic order, free electron density, and activation energy. This material can switch between different solid phases or mixtures of two or more solid phases, providing a gradient between a completely amorphous state and a completely crystalline state.

[0014] The transition from an amorphous to a crystalline state is generally a lower-current operation, requiring sufficient current to raise the phase-change material to a level between the phase transition temperature and the melting temperature. The transition from crystalline to amorphous, referred to as a "reset," is generally a higher-current operation involving a short pulse of high current density to melt or break down the crystalline structure, after which the phase-change material cools rapidly to halt the phase-change process, thereby allowing at least a portion of the phase-change structure to stabilize in the amorphous state.

[0015] While the present invention is described in relation to a given exemplary architecture, it should be understood that within the scope of the invention, a variety of other architectures, structures, substrate materials, process features, and steps / blocks are possible. Note that, for clarity, it is not possible to show all specific features in the figures. This is not intended to be construed as any particular embodiment, or illustration, or limitation of the claims.

[0016] Figure 1 is a cross-sectional view of a semiconductor structure according to one embodiment of the present invention, which includes a plurality of conductive lines formed in a dielectric layer, and on one or more of the plurality of conductive lines a metal deposit is performed.

[0017] The semiconductor structure 5 includes a plurality of conductive lines 18 formed within trenches in the interlayer insulating film (ILD) 12. The ILD 12 may be formed on a substrate 10. A conductive filler material or liner 20 may be formed or deposited around each of the trenches. In one example, the liner may be a tantalum nitride (TaN) liner 20, or in an alternative example, a tantalum (Ta) liner 20. In one exemplary embodiment, the conductive filler material 20 may be deposited, for example, by electroplating, electroless plating, chemical vapor deposition (CVD), atomic layer deposition (ALD), or physical vapor deposition (PVD), or a combination thereof.

[0018] In various exemplary embodiments, the dielectric 22 is deposited on a plurality of conductive lines 18. The dielectric 22 may have a thickness of, for example, 50 nm.

[0019] Thereafter, metal deposition may be performed. The metal deposition involves forming the metal layer 24 directly on and in direct contact with the conductive line 18. The width of the metal layer 24 may be substantially equal to the width of the conductive line 18. The metal layer 24 may be, for example, Ti, Ta, TiN, or TaN, or a combination thereof.

[0020] Furthermore, the first contact 14 and the second contact 16 may be formed directly under the conductive line 18. The first contact 14 and the second contact 16 extend through the substrate 10.

[0021] The substrate 10 may be crystalline, semi-crystalline, microcrystalline, or amorphous. The substrate 10 may be substantially (e.g., excluding contaminants) a single element (e.g., silicon), may consist mainly of (e.g., with doping) a single element, such as silicon (Si) or germanium (Ge), or the substrate 10 may include a compound, such as GaAs, SiC, or SiGe. The substrate 10 may also have a plurality of material layers. In some embodiments, the substrate 10 includes semiconductor materials including, but not necessarily limited to, silicon (Si), silicon-germanium (SiGe), silicon carbide (SiC), Si:C (carbon-doped silicon), silicon-germanium carbide (SiGeC), carbon-doped silicon-germanium (SiGe:C), group III-V (e.g., GaAs, AlGaAs, InAs, InP, etc.), group II-V compound semiconductors (e.g., ZnSe, ZnTe, ZnCdSe, etc.), or other similar semiconductors. Additionally, a plurality of layers of semiconductor materials may be used as the semiconductor material of the substrate 10. In some embodiments, the substrate 10 includes both a semiconductor material and a dielectric material. The semiconductor substrate 10 may include a stacked semiconductor such as, for example, Si / SiGe, silicon-on-insulator, or SiGe-on-insulator.

[0022] ILD12 may include any material known in the art, such as, for example, porous silicate, carbon-doped oxide, silicon dioxide, silicon nitride, silicon oxynitride, or other dielectric materials. ILD12 may be formed using any method known in the art, such as, for example, chemical vapor deposition, plasma-assisted chemical vapor deposition, atomic layer deposition, or physical vapor deposition. ILD12 may have a thickness in the range of about 25 nm to about 200 nm.

[0023] The dielectric material of layer 12 may include, but is not limited to, ultra-low-k (ULK) materials such as, for example, porous silicate, carbon-doped oxide, silicon dioxide, silicon nitride, silicon oxynitride, carbon-doped silicon oxide (SiCOH) and its porous form, silsesquioxane, siloxane, or other dielectric materials having a dielectric constant in the range of about 2 to about 4.

[0024] The conductive line 18 may be formed in an opening or trench formed in the ILD12. The conductive line 18 may be any conductive material known in the art, such as, for example, copper (Cu), aluminum (Al), or tungsten (W). The conductive line 18 may be fabricated using any technique known in the art, such as, for example, single or dual damascene techniques. In one embodiment not shown, the conductive line 18 may be copper (Cu) and may include a metal liner, and the metal liner may be a metal such as, for example, tantalum nitride and tantalum (TaN / Ta), titanium, titanium nitride, cobalt, ruthenium, and manganese or combinations thereof.

[0025] The dielectric layer 22 may be a nitride, such as, for example, silicon nitride (SiN), an oxynitride, such as, for example, silicon oxynitride (SiON), or a combination thereof. In a preferred embodiment, the dielectric layer 22 may be silicon nitride (SiN), such as, for example, Si3N4.

[0026] The conductive material of the metal layer 24 may be copper (Cu), cobalt (Co), aluminum (Al), platinum (Pt), gold (Au), tungsten (W), titanium (Ti), or any combination thereof. The metal layer 24 may be deposited by a suitable deposition process, such as chemical vapor deposition (CVD), plasma-assisted chemical vapor deposition (PECVD), physical vapor deposition (PVD), plating, thermal deposition or electron beam deposition, or sputtering.

[0027] Figure 2 is a cross-sectional view of the semiconductor structure shown in Figure 1, according to one embodiment of the present invention, in which a GeSbTe (germanium-antimony-tellurium or GST) layer, a projection liner, and a hard mask layer are deposited.

[0028] A first projection liner 30, a GST layer 32, a second projection liner 34, and a hard mask layer 36 are deposited on a plurality of metal lines 24 and a plurality of conductive lines 18. Thus, the GST layer 32 is enclosed or confined within the first projection liner 30 and the second projection liner 34. The first projection liner 30 may be referred to as the bottom projection liner, and the second projection liner 34 may be referred to as the top projection liner.

[0029] The GST layer 32 may have a thickness between approximately 20 nm and approximately 50 nm.

[0030] The GST layer 32 may be formed, for example, by physical vapor deposition (PVD) technology.

[0031] The first projection liner 30 and the second projection liner 34 may be referred to as phase-change material (PCM) liners. Liners 30 and 34 may be metallic liners. The metallic liners 30 and 34 may be constructed from metals such as tantalum nitride and tantalum (TaN / Ta), titanium, titanium nitride, cobalt, ruthenium, and manganese.

[0032] In various exemplary embodiments, the hard mask layer 36 may be a nitride, such as silicon nitride (SiN), an oxynitride, such as silicon oxynitride (SiON), or a combination thereof. In a preferred embodiment, the hard mask layer 36 may be silicon nitride (SiN), such as Si3N4.

[0033] In one or more embodiments, the hard mask layer 36 may have a thickness in the range of about 20 nm to about 100 nm, or in the range of about 35 nm to about 75 nm, or in the range of about 45 nm to about 55 nm, but other thicknesses are also possible.

[0034] Phase-change materials can be changed from one phase state to another by applying an electrical pulse. Shorter, higher-amplitude pulses tend to change the phase-change material generally to an amorphous state and are called reset pulses. Longer, lower-amplitude pulses tend to change the phase-change material generally to a crystalline state and are called program pulses. The energy of the shorter, higher-amplitude pulses is high enough to melt the material in the active region, and short enough to allow the material to solidify in the amorphous state.

[0035] Phase change materials may include chalcogenide materials and other materials. Chalcogens contain one of four elements that form part of Group VI of the periodic table: oxygen (O), sulfur (S), selenium (Se), and tellurium (Te). Chalcogenides include compounds of chalcogens with more electropositive elements or radicals. Chalcogenide alloys include combinations of chalcogenides with other materials such as transition metals. Chalcogenide alloys typically contain one or more elements from Column 6 of the periodic table, such as germanium (Ge) and tin (Sn). Often, chalcogenide alloys include combinations of one or more of antimony (Sb), gallium (Ga), indium (In), and silver (Ag). Phase-change-based memory materials may include alloys of Ga / Sb, In / Sb, In / Se, Sb / Te, Ge / Te, Ge / Sb / Te, In / Sb / Te, Ga / Se / Te, Sn / Sb / Te, In / Sb / Ge, Ag / In / Sb / Te, Ge / Sn / Sb / Te, Ge / Sb / Se / Te, and Te / Ge / Sb / S. Within the Ge / Sb / Te alloy system, a wide range of alloy compositions may be available.

[0036] In some embodiments, impurities are doped into chalcogenides and other phase-change materials to adjust the conductivity, transition temperature, melting temperature, and other properties of memory elements using the doped chalcogenides. Typical impurities used to dope chalcogenides include nitrogen, silicon, oxygen, silicon dioxide, silicon nitride, copper, silver, gold, aluminum, aluminum oxide, tantalum, tantalum oxide, tantalum nitride, titanium, and titanium oxide.

[0037] In this example, the phase change material stack preferably includes a Ge-Sb-Te (germanium-antimony-tellurium or "GST") alloy. Alternatively, other suitable materials for the phase change material stack may optionally include Si-Sb-Te alloys, Ga-Sb-Te alloys, As-Sb-Te alloys, Ag-In-Sb-Te alloys, Ge-In-Sb-Te alloys, Ge-Sb alloys, Sb-Te alloys, Si-Sb alloys, and combinations thereof.

[0038] Figure 3 is a cross-sectional view of the semiconductor structure shown in Figure 2, according to one embodiment of the present invention, in which a GST layer, a projection liner, and a hard mask layer are patterned to form a GST stack.

[0039] The GST stack 40 is formed by patterning a first projection liner 30, a GST layer 32, a second projection liner 34, and a hard mask layer 36.

[0040] Therefore, the top surface 23 of the dielectric 22 is exposed by patterning.

[0041] The top view 45 of the structure shows the H-shaped hard mask layer 36 in relation to the top surface 23 of the dielectric 22. In other words, the PCM element defines a fin-type GST cell.

[0042] Figure 4 is a cross-sectional view of the semiconductor structure of Figure 3, in which another projection liner is deposited on top of the GST stack, according to one embodiment of the present invention.

[0043] A third projection liner 50 is deposited on top of the GST stack. The third projection liner 50 is in direct contact with the top surface of the dielectric 22 and the top surface of the hard mask layer 36. In addition, the third projection liner 50 is in direct contact with the side walls of the GST layer 32 such that the GST layer 32 is completely surrounded or wrapped by the first projection liner 30, the second projection liner 34, and the third projection liner 50.

[0044] The third projection liner 50 may be constructed from the same material as the first projection liner 30 and the second projection liner 34.

[0045] The top view 55 shows a third projection liner 50 formed on the structure.

[0046] Figure 5 is a cross-sectional view of the semiconductor structure shown in Figure 4, on which a spacer layer is deposited, according to one embodiment of the present invention.

[0047] A spacer layer 60 is deposited on top of the third projection liner 50.

[0048] The top view 65 shows the spacer layer 60 on top of the entire structure.

[0049] Figure 6 is a cross-sectional view of the semiconductor structure of Figure 5, according to one embodiment of the present invention, in which the spacer layer is etched to form a spacer adjacent to the projection liner.

[0050] The spacer layer 60 is etched to form a spacer 70 adjacent to the GST stack 40. The formation of the spacer 70 exposes the surface of the third projection liner 50. The GST layer 32 is wrapped or surrounded by the first projection liner 30, the second projection liner 34, and the third projection liner 50. In other words, the GST layer 32 is surrounded or confined by the projection liners 30, 34, and 50. Specifically, the bottom of the GST layer 32 is in direct contact with the first projection liner 30, the top of the GST layer 32 is in direct contact with the second projection liner 34, and the sidewalls of the GST layer 32 are in direct contact with the third projection liner 50. As a result, the first projection liner 30, the second projection liner 34, and the third projection liner 50 collectively define a projection liner that completely encloses, surrounds, or surrounds the GST layer 32.

[0051] The PCM structure may be referred to as a horizontally confined PCM cell. Thus, the PCM structure includes a GST layer 32 having an all-around or wrap-around projection liner that completely and entirely encloses the GST layer 32.

[0052] The top view 75 shows the relationship between the spacer 70 and the third projection liner 50, and their relationship with the hard mask layer 36.

[0053] The spacer 70 may include any one or more thin films of SiN, SiBN, SiCN, or SiBCN, or combinations thereof.

[0054] Figure 7 is a cross-sectional view of the semiconductor structure shown in Figure 6, in which a projection liner is etched, according to one embodiment of the present invention.

[0055] The exposed surface of the third projection liner 50 is etched, for example, by a reactive ion etching (RIE) process 80. This exposes the top surface 23 of the dielectric 22 and the top surface 37 of the hard mask layer 36. This further causes the spacer 70 to recede, forming spacer 70'. The GST layer 32 remains encased by the collective first projection liner 30, the second projection liner 34, and the third projection liner 50. The third projection liner 50 extends perpendicularly above the GST layer 32 such that the sidewalls of the hard mask layer 36 are in direct contact with the third projection liner 50. Thus, the edges of the third projection liner 50 define L-shaped and inverted L-shaped configurations. The L-shaped and inverted L-shaped configurations accommodate spacer 70'.

[0056] The top view 85 shows the relationship between the spacer 70', the hard mask layer 36, and the dielectric 22. In addition, the fin-type GST cell highlights the fin-type configuration of the third projection liner 50.

[0057] As a result, the first projection liner 30, the second projection liner 34, and the third projection liner 50 work together to collectively define a single projection liner having segments 30, 34, and 50 that completely enclose the GST layer 32.

[0058] Figure 8 is a cross-sectional view of the semiconductor structure shown in Figure 7, in which the uppermost layer is formed, according to one embodiment of the present invention.

[0059] ILD90 may be deposited on the GST stack to form structure 100. ILD90 is in direct contact with the top surface of dielectric 22, spacer 70', and the top surface of hard mask layer 36.

[0060] Top view 97 shows the deposit of ILD90 and defines the fin-shaped GST cells. The X-axis extends horizontally through the fin-shaped GST cells, and the Y-axis extends vertically through the fin-shaped GST cells.

[0061] Figure Y95 shows a single liner collectively formed from a first liner 30, a second liner 34, and a third liner 50, defining a substantially H-shaped configuration. The GST layer 32 is confined within the single liner 30, 34, and 50.

[0062] Figure X 100 shows contacts 14 and 16 that are in horizontal and electrical communication with the PCM element having the GST layer 32.

[0063] In conclusion, exemplary embodiments of the present invention form a wrap-around or all-around projection liner that minimizes reactive ion etch (RIE) damage during PCM formation. The exemplary embodiments utilize a horizontal confinement cell structure of a GST having a projection liner. The exemplary embodiments introduce self-aligned bridge cell contacts. In other words, a horizontal mushroom cell structure is introduced to improve durability, resistance drift, and program current. As a result, the exemplary method minimizes wet damage to the GST cell.

[0064] In conclusion, a semiconductor structure is formed that includes a horizontally confined PCM cell, the PCM structure comprising a GST layer enclosed or surrounded by a projection liner (all-around or wrap-around projection liner). The confined cell PCM may be formed by physical vapor deposition (PVD). The method for forming the semiconductor structure minimizes reactive ion etch (RIE) damage to the GST layer, thereby forming a GST cell free from CMP, WET, or RIE damage. The method for forming the semiconductor structure further includes constructing a wrap-around projection liner that encloses the GST layer. As a result, exemplary embodiments introduce a horizontally confined cell structure of GST with a projection liner, suggesting a self-aligned bridge cell contact having a GST all-around projection liner.

[0065] Regarding Figures 1 to 8, deposition is any process of growing, coating, or otherwise transferring a material onto a wafer. Available techniques include, but are not limited to, thermal oxidation, physical vapor deposition (PVD), chemical vapor deposition (CVD), electrochemical deposition (ECD), molecular beam epitaxy (MBE), and, more recently, atomic layer deposition (ALD). As used herein, “deposition” may include any currently known or subsequently developed techniques suitable for depositing materials, including but not limited to chemical vapor deposition (CVD), reduced-pressure CVD (LPCVD), plasma-assisted CVD (PECVD), near-atmospheric pressure CVD (SACVD), and high-density plasma CVD (HDPCVD), rapid thermal CVD (RTCVD), ultra-high vacuum CVD (UHVCVD), limited-reaction treatment CVD (LRPCVD), metalloorganic CVD (MOCVD), sputter deposition, ion beam deposition, electron beam deposition, laser-assisted deposition, thermal oxidation, thermal nitriding, spin-on methods, physical vapor deposition (PVD), atomic layer deposition (ALD), chemical oxidation, molecular beam epitaxy (MBE), plating, and vapor deposition.

[0066] As used herein, the term “processing” includes the deposition, patterning, exposure, development, etching, washing, stripping, injection, doping, stress application, lamination, or removal of material or photoresist, or any combination thereof, of material or photoresist, necessary for the formation of the described structure.

[0067] While the present invention will be described in relation to a given exemplary architecture, it should be understood that within the scope of the invention, a variety of other architectures, structures, substrate materials, process features, and steps / blocks are possible.

[0068] When an element such as a layer, region, or substrate is described as being "on top of" another element, it should be understood that it may be directly on top of that other element, or there may be an intervening element. Conversely, when an element is described as being "directly on top of" another element, or "directly on top of" another element, there is no intervening element. When an element is described as being "connected to" or "joined" another element, it should be understood that it may be directly connected to or joined to that other element, or there may be an intervening element. Conversely, when an element is described as being "directly connected to" or "directly joined" another element, there is no intervening element.

[0069] This embodiment may include a design for an integrated circuit chip, created in a graphical computer programming language and stored on a computer storage medium (such as a disk, tape, physical hard drive, or virtual hard drive in a storage access network, etc.). If the designer does not manufacture the chip or the photolithography mask used to manufacture the chip, the designer may transmit the resulting design directly or indirectly to such an entity by a physical mechanism (e.g., by providing a copy of the storage medium on which the design is stored) or electronically (e.g., via the Internet). The stored design is then converted into a suitable format (e.g., GDSII) for manufacturing a photolithography mask, which includes multiple copies of the chip design to be formed on a wafer. The photolithography mask is used to define areas of the wafer to be etched or otherwise processed.

[0070] The methods described herein may be used to manufacture integrated circuit chips. The resulting integrated circuit chips may be distributed by the manufacturer in the form of raw wafers (as a single wafer having multiple unpackaged chips), as bare dies, or in packaged form. In the latter case, the chips are mounted in single-chip packages (such as plastic carriers with leads attached to a motherboard or other higher-level carrier) or in multi-chip packages (such as ceramic carriers with either or both surface-mounted or embedded-mounted wiring). In either case, the chips are then integrated with other chips, discrete circuit elements, or other signal processing devices or combinations thereof as part of either (a) an intermediate product such as a motherboard, or (b) a final product. The final product may be any product containing integrated circuit chips, ranging from toys and other low-end applications to displays, keyboards or other input devices, and advanced computer products with central processors.

[0071] It should be understood that material compounds can be described in terms of multiple elements listed, such as SiGe. These compounds contain various proportions of elements within the compound; for example, SiGe contains Si x Ge 1-x This includes, and x is 1 or less, etc. In addition, other elements may be included in the compound and may also function according to this embodiment. Compounds having additional elements are referred to herein as alloys. Any “one embodiment” or “one example” of the present invention herein, and any other variations thereof, means that certain features, structures, properties, etc. described in relation to that embodiment are included in at least one embodiment of the present invention. Thus, any appearance of the phrase “in one embodiment” or “in one example” in various places throughout this specification, and any other variations thereof, does not necessarily all refer to the same embodiment.

[0072] For example, in phrases such as "A / B," "A or B or both," and "at least one of A and B," the use of " / ," "or both," and "at least one of" is intended to encompass the selection of only the first option (A), only the second option (B), or both options (A and B). As further examples, in phrases such as "A, B, or C or a combination thereof" and "at least one of A, B, and C," such phrases are intended to encompass the selection of only the first option (A), only the second option (B), only the third option (C), only the first and second options (A and B), only the first and third options (A and C), only the second and third options (B and C), or all three options (A, B, and C). This may be extended to the number of items listed, as will be readily apparent to those skilled in the art in this and related fields.

[0073] The terms used herein are intended solely to describe specific embodiments and are not intended to limit the exemplary embodiments. Where used herein, the singular forms “a,” “an,” and “the” are intended to include the plural form unless explicitly indicated otherwise by the context. Furthermore, the terms “comprises,” “comprising,” “includes,” or “including,” as used herein, indicate the presence of a described feature, integer, step, operation, element, or component, or a combination thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or groups thereof or combinations thereof.

[0074] Spatially relative terms such as “down,” “below,” “underside,” “up,” and “top” may be used herein to facilitate descriptions of the relationship between one element or feature shown in the drawings and another element or feature. These spatially relative terms are intended to encompass various orientations of the device in use or operation, in addition to the orientation shown in the drawings. For example, if the device in the drawing is turned over, an element described as being “below” or “below” another element or feature will be “above” that other element or feature. Thus, the term “down” may encompass both upward and downward orientations. The device may also be in other orientations (rotated by 90 degrees or other directions), and the spatially relative descriptions used herein may be interpreted accordingly. In addition, when a layer is described as being “between” two layers, it should be understood that this may be the single layer between the two layers, or there may be one or more intervening layers.

[0075] In this specification, terms such as "First," "Second," etc., may be used to describe various elements, but it should be understood that these elements should not be limited by these terms. These terms are used solely to distinguish one element from another. Therefore, as long as it does not deviate from the scope of this concept, the first element discussed below may be referred to as the second element.

[0076] Preferred embodiments of methods and structures for forming projection liners for artificial intelligence (AI) devices (these are intended to be illustrative, not limiting) have been described, but it should be noted that modifications and variations may be made by those skilled in the art in light of the above teachings. Therefore, it should be understood that changes within the scope of the invention as defined by the appended claims may be made in the particular embodiments described. While aspects of the invention have been described with the details and specifics required by patent law, the claims and requirements protected by the patent are described in the appended claims.

Claims

1. A semiconductor structure, A phase-change memory (PCM) element that connects a first contact and a second contact horizontally and electrically, A projection liner enclosing the PCM element, wherein a portion of the projection liner is positioned between the PCM element and the first contact and the second contact, and directly contacts the bottom of the PCM element. A semiconductor structure comprising the following features.

2. The semiconductor structure according to claim 1, wherein the spacer is formed adjacent to the projection liner.

3. The semiconductor structure according to claim 1, wherein the spacer is in direct contact with the side wall of the projection liner.

4. The semiconductor structure according to claim 1, wherein the PCM element includes a GeSbTe (germanium antimony tellurium or GST) layer.

5. The semiconductor structure according to claim 4, wherein a hard mask layer is formed on the GST layer.

6. The semiconductor structure according to claim 5, wherein the sidewall of the hard mask layer is in direct contact with a portion of the projection liner.

7. The semiconductor structure according to claim 1, wherein a conductive line is formed between the PCM element and the first contact and the second contact.

8. A semiconductor structure, A plurality of conductive lines formed within a dielectric, wherein each of the plurality of conductive lines is electrically in communication with its respective contact, A metal layer is placed on each of the plurality of conductive lines, A phase-change memory (PCM) element is disposed on the metal layer of each of the plurality of conductive lines, The projection liner enclosing the aforementioned PCM element and A semiconductor structure comprising the following features.

9. The semiconductor structure according to claim 8, wherein the spacer is formed adjacent to the projection liner.

10. The semiconductor structure according to claim 8, wherein the spacer is in direct contact with the side wall of the projection liner.

11. The semiconductor structure according to claim 8, wherein the PCM element includes a GeSbTe (germanium antimony tellurium or GST) layer.

12. The semiconductor structure according to claim 11, wherein a hard mask layer is formed on the GST layer.

13. The semiconductor structure according to claim 12, wherein the sidewall of the hard mask layer is in direct contact with a portion of the projection liner.

14. It is a method, Forming a phase-change memory (PCM) element, The PCM element is connected horizontally and electrically to the first contact and the second contact, The method involves enclosing the PCM element with a projection liner, wherein a portion of the projection liner is positioned between the PCM element and the first contact and the second contact, and directly contacts the bottom of the PCM element. A method that includes this.

15. The method according to claim 14, further comprising forming a spacer adjacent to the projection liner.

16. The method according to claim 14, wherein the PCM element includes a GeSbTe (germanium antimony tellurium or GST) layer.

17. The method according to claim 16, further comprising forming a hard mask layer on the GST layer.

18. The method according to claim 17, wherein the side wall of the hard mask layer is in direct contact with a portion of the projection liner.

19. The method according to claim 14, wherein the PCM element defines a fin-type GST cell.

20. The method according to claim 14, wherein the PCM element is formed by physical vapor deposition (PVD).

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