Level conversion circuit
The level conversion circuit addresses high power consumption by using transistor control circuits and one-shot pulses to manage transistor states, achieving reduced power usage and efficient output level transitions.
Patent Information
- Authority / Receiving Office
- JP · JP
- Patent Type
- Patents
- Current Assignee / Owner
- NISSHINBO MICRO DEVICES INC
- Filing Date
- 2022-08-12
- Publication Date
- 2026-07-07
AI Technical Summary
Conventional level conversion circuits experience high power consumption due to continuous current flow through transistors when the input and output voltages are at the low level.
A level conversion circuit design that includes specific transistor configurations and control circuits to manage transistor states based on input voltage transitions, using one-shot pulse output circuits and current mirrors to minimize current flow during idle states.
Reduces power consumption by controlling transistor states with one-shot pulses and current mirrors, maintaining output levels efficiently while minimizing current flow during transitions.
Smart Images
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Abstract
Description
Technical Field
[0001] The present invention relates to a level conversion circuit.
Background Art
[0002] Fig. 4 shows a conventional level conversion circuit (see, for example, Fig. 1 of Patent Document 1). When an input voltage having an amplitude between H level (VDD1) and L level (GND) is input to the input terminal IN, the conventional level conversion circuit outputs an output voltage having an amplitude between H level (VDD2) and L level (VL2 = VDD2 - VDD3) from the output terminal OUT. In Fig. 4, MP21 to MP29 are P-channel field effect transistors, MN21 to MN28 are N-channel field effect transistors, R11 to R17 are resistors, AND1 and AND2 are AND circuits, and INV1 to INV7 are inverters.
[0003] The conventional level conversion circuit has a problem that when the input voltage and the output voltage are at the L level, the transistors MP24, MN21, MP29, MN27, and MN28 are turned on, and current continuously flows through the four resistors R11, R15, R16, and R17 as indicated by the arrows, resulting in high power consumption.
Prior Art Documents
Patent Documents
[0004]
Patent Document 1
Summary of the Invention
Problems to be Solved by the Invention
[0005] The present invention has been made in view of the above circumstances, and an object thereof is to provide a level conversion circuit with reduced power consumption.
Means for Solving the Problems
[0006] To achieve the aforementioned objectives, the level conversion circuit according to the present invention is characterized by the following [1] to [4]. [1] A level conversion circuit that converts an input voltage having amplitudes of a first high voltage and a first low voltage to an output voltage having amplitudes of a second high voltage and a second low voltage, The first node is connected to the gate or base, and the second high voltage is connected to the source or emitter. From the positive electrode The first transistor to which the positive terminal of the second power supply is connected, A second transistor having a second node connected to its gate or base and the positive terminal of the second power supply connected to its source or emitter, The second high voltage is output when the first transistor is on and the second transistor is off; the second low voltage is output when the first transistor is off and the second transistor is on; and the output is maintained when the first transistor is off and the second transistor is off. A latch circuit and The first node and the first high voltage The first low voltage is supplied from the positive electrode and from the negative electrode. A third transistor connected between the negative terminals of the first power supply, A fourth transistor connected between the second node and the negative terminal of the first power supply, A first transistor control circuit is provided between the positive terminal of the second power supply and the first and second nodes, which turns on the first transistor and turns off the second transistor when the third transistor is on and the fourth transistor is off, and turns off the first transistor and turns on the second transistor when the third transistor is off and the fourth transistor is on. A fifth transistor connected between the positive terminal of the second power supply and the first node, A sixth transistor connected between the positive terminal of the second power supply and the second node, A first one-shot pulse output circuit that outputs a first one-shot pulse in response to the rise of the input voltage from the first low voltage to the first high voltage, A second one-shot pulse output circuit that outputs a second one-shot pulse in accordance with the falling edge of the input voltage from the first high voltage to the first low voltage, The third transistor is turned on during the output of the first one-shot pulse. Turn off the fifth transistor, While the output of the first one-shot pulse is stopped Turn off the third transistor,The fifth transistor is turned on, and the fourth transistor is turned on during the output of the second one-shot pulse. Turn off the sixth transistor, During the output of the second one-shot pulse described above Turn off the fourth transistor, The system includes a second transistor control circuit that turns on the sixth transistor. It is a level conversion circuit. [2] In the level conversion circuit described in [1], The second transistor control circuit is, A seventh transistor connected between the positive terminal of the second power supply and the gate or base of the fifth transistor, The seventh transistor and the second low voltage From the negative electrode A first resistor connected between the negative terminal of the third power supply for supplying power, A second resistor connected between the positive terminal of the second power supply and the gate or base of the seventh transistor, The gate or base of the seventh transistor An eighth transistor is connected between the first power supply and the negative terminal, with the first one-shot pulse output circuit connected to its gate or base, A ninth transistor connected between the positive terminal of the second power supply and the gate or base of the sixth transistor, A third resistor connected between the ninth transistor and the negative terminal of the third power supply, A fourth resistor connected between the positive terminal of the second power supply and the gate or base of the ninth transistor, The gate or base of the ninth transistor It has a 10th transistor connected between the first power supply and the negative terminal, with the second one-shot pulse output circuit connected to its gate or base. It is a level conversion circuit. [3] In the level conversion circuit described in [2], The second transistor control circuit is, The circuit includes a current source that receives power from the first power supply and supplies current, and a current mirror circuit that folds back the current supplied from the current source or a current corresponding to the current supplied from the current source and supplies it to the eighth transistor and the tenth transistor. It is a level conversion circuit. [4] In the level conversion circuit according to any one of [1] to [3], The first transistor control circuit An eleventh transistor having a source or emitter connected to the positive electrode of the second power supply, and a drain or collector connected to the first node and a gate or base; A twelfth transistor having a source or emitter connected to the positive electrode of the second power supply, a gate or base connected to the gate or base of the eleventh transistor, and a drain or collector connected to the second node; A thirteenth transistor having a source or emitter connected to the positive electrode of the second power supply, and a drain or collector connected to the second node and a gate or base; And a fourteenth transistor having a source or emitter connected to the positive electrode of the second power supply, a gate or base connected to the gate or base of the thirteenth transistor, and a drain or collector connected to the first node. It is a level conversion circuit.
Advantages of the Invention
[0007] According to the present invention, a level conversion circuit with reduced power consumption can be provided.
[0008] The present invention has been briefly described above. Further, the details of the present invention will be further clarified by reading through the embodiments for carrying out the invention described below (hereinafter referred to as "embodiments") with reference to the attached drawings.
Brief Description of the Drawings
[0009] [Figure 1] FIG. 1 is a circuit diagram showing an embodiment of the level conversion circuit of the present invention. [Figure 2] FIG. 2 is a circuit diagram showing the details of the first and second one-shot pulse output circuits shown in FIG. 1. [Figure 3]Figure 3 is a time chart of each voltage and current in the level conversion circuit shown in Figure 1. [Figure 4] Figure 4 is a circuit diagram showing an example of a conventional level conversion circuit. [Modes for carrying out the invention]
[0010] Specific embodiments of the present invention will be described below with reference to the figures.
[0011] Figure 1 is a circuit diagram showing one embodiment of the level conversion circuit 1 of the present invention. The level conversion circuit 1 is a circuit that converts an input voltage VIN having amplitudes of H level (VDD1) and L level (GND) input to the input terminal IN into an output voltage VOUT having amplitudes of H level (VDD2) and L level (VL2 = VDD2 - VDD3) and outputs it from the output terminal OUT. VDD1 is the power supply voltage supplied from the first power supply 21. VDD2 is the power supply voltage supplied from the second power supply 22. VDD3 is the power supply voltage supplied from the third power supply 23 and is provided to supply VL2. For example, GND = 0V, VDD1 = 5V, VDD2 = 30V, VDD3 = 3V. In this embodiment, VDD1 corresponds to the first high voltage, GND corresponds to the first low voltage, VDD2 corresponds to the second high voltage, and VL2 corresponds to the second low voltage.
[0012] The level conversion circuit 1 includes transistors MP1 and MP2, a latch circuit 3, an inverter circuit 4, transistors MN3 and MN4, a first transistor control circuit 5, transistors MP5 and MP6, first and second one-shot pulse output circuits 71 and 72, and a second transistor control circuit 8.
[0013] The first and second transistors, MP1 and MP2, are composed of P-channel field-effect transistors. Transistor MP1 has node A, the first node, connected to its gate, the positive terminal of the second power supply 22, and is supplied with VDD2 to its source. Transistor MP2 has node B, the second node, connected to its gate, the positive terminal of the second power supply 22, and is supplied with VDD2 to its source.
[0014] Latch circuit 3 is a circuit to which the voltage between VDD2 and VL2 is applied. Latch circuit 3 latches the output based on the on / off state of transistors MP1 and MP2, and outputs voltages with amplitudes of H level (VDD2) and L level (VL2) (details will be described later). Latch circuit 3 has transistors MP15, MP16, MN15, and MN16. Transistors MP15 and MP16 are composed of P-channel field-effect transistors, and transistors MN15 and MN16 are composed of N-channel field-effect transistors.
[0015] Transistors MP15 and MP16 have the positive terminal of the second power supply 22 connected to their source, and are supplied with VDD2. Transistors MN15 and MN16 have the negative terminal of the third power supply 23 connected to their source, and are supplied with VL2. Also, the drains of transistors MP15 and MN15 are connected to each other, and the gates are connected to each other. Transistors MP16 and MN16 are connected to each other, and the drains of transistors MP15 and MN15 are connected to the gates of transistors MP16 and MN16. The drains of transistors MP16 and MN16 are connected to the gates of transistors MP15 and MN15.
[0016] The drain of transistor MP1 is connected to the gates of transistors MP15 and MN15, and the drains of transistors MP16 and MN16. The drain of transistor MP2 is connected to the drains of transistors MP15 and MN15, and the gates of transistors MP16 and MN16. The drains of transistors MP16 and MN16 become the outputs of latch circuit 3.
[0017] With the above configuration, as shown in Table 1 below, when transistor MP1 is ON and transistor MP2 is OFF, the latch circuit 3 turns transistors MP15 and MN16 OFF and then ON, outputting a high level (VDD2). When transistors MP1 and MP2 are switched OFF from this state, the OFF state of transistors MP15 and MN16 and the ON state of transistors MN15 and MP16 are maintained, and the high level (VDD2) output is maintained.
[0018] [Table 1]
[0019] Furthermore, when transistor MP1 is off and transistor MP2 is on, the latch circuit 3 turns transistors MP15 and MN16 on and transistors MN15 and MP16 off, outputting an L level (VL2). When transistors MP1 and MP2 are switched off from this state, the ON state of transistors MP15 and MN16 and the OFF state of transistors MN15 and MP16 are maintained, and the L level (VL2) output is maintained.
[0020] Inverter circuit 4 inverts the output of latch circuit 3 twice and outputs it as output voltage VOUT. Inverter circuit 4 has two inverters 41 and 42. Inverter 41 has its input connected to the output of latch circuit 3. Inverter 42 has its input connected to the output of inverter 41 and its output connected to the output terminal OUT.
[0021] The third and fourth transistors, MN3 and MN4, are composed of high-voltage N-channel field-effect transistors. Transistor MN3 is connected between node A and the negative terminal of the first power supply 21. Transistor MN4 is connected between node B and the negative terminal of the first power supply 21. More specifically, transistor MN3 has the negative terminal of the first power supply 21 as its source and node A as its drain. Transistor MN4 has the negative terminal of the first power supply 21 as its source and node B as its drain.
[0022] The first transistor control circuit 5 has transistors MP11 to MP14 as the 11th to 14th transistors, which are composed of P-channel field-effect transistors. Transistors MP11 and MP12 are current mirrored. Transistor MP11 has the positive terminal of the second power supply 22 connected as its source, and its gate and drain connected as well. The drain of transistor MP11 is connected to node A. Transistor MP12 has the positive terminal of the second power supply 22 connected as its source, and its gate is connected to the gate and drain of transistor MP11. The drain of transistor MP12 is connected to node B.
[0023] Transistors MP13 and MP14 are in current mirror connection. Transistor MP13 has the positive terminal of the second power supply 22 connected as its source, and its gate and drain connected as well. The drain of transistor MP13 is connected to node B. Transistor MP14 has the positive terminal of the second power supply 22 connected as its source, and the gate and drain of transistor MP13 connected as its gate. The drain of transistor MP14 is connected to node A.
[0024] When transistor MN3 is ON and transistor MN4 is OFF, the first transistor control circuit 5 turns on transistors MP11 and M12 and turns off transistors MP13 and MP14. As a result, the first transistor control circuit 5 outputs a low level (VDD2-VGSMP11) from node A and a high level (VDD2) from node B, controlling transistor MP1 to turn ON and transistor MP2 to turn OFF. VGSMP11 is the gate-source voltage of transistor MP11 and is a voltage greater than or equal to the threshold voltage of transistor MP1.
[0025] Furthermore, when transistor MN3 is off and transistor MN4 is on, the first transistor control circuit 5 turns off transistors MP11 and M12 and turns on transistors MP13 and MP14. As a result, the first transistor control circuit 5 outputs a high level (VDD2) from node A and a low level (VDD2-VGSMP13) from node B, controlling transistor MP1 to turn off and transistor MP2 to turn on. VGSMP13 is the gate-source voltage of transistor MP13 and is a voltage greater than or equal to the threshold voltage of transistor MP2.
[0026] Transistors MP5 and MP6, acting as the fifth and sixth transistors, are composed of P-channel field-effect transistors. Transistor MP5 has the positive terminal of the second power supply 22 connected to its source and node A connected to its drain. Transistor MP6 has the positive terminal of the second power supply 22 connected to its source and node B connected to its drain. When transistors MP5 and MP6 are turned on while transistors MN3 and MN4 are off, a high level (VDD2) is forcibly output from nodes A and B.
[0027] The first one-shot pulse output circuit 71 has the input terminal IN connected to its input, and the input voltage VIN is input to it. The first one-shot pulse output circuit 71 is a circuit that outputs a first one-shot pulse in response to the rising edge of the input voltage VIN from a low level to a high level. The output of the first one-shot pulse output circuit 71 is connected to the gates of transistor MN3 and transistor MN8, which will be described later.
[0028] The output of inverter 9 is connected to the input of the second one-shot pulse output circuit 72. The input terminal IN is connected to the input of inverter 9, and the inverted input voltage VIN is input to the input of the second one-shot pulse output circuit 72. The second one-shot pulse output circuit 72 is a circuit that outputs a second one-shot pulse in accordance with the falling edge of the input voltage VIN from a high level to a low level. The output of the second one-shot pulse output circuit 72 is connected to the gate of transistor MN4 and transistor MN10, which will be described later.
[0029] Next, an example of the first and second one-shot pulse output circuits 71 and 72 described above will be explained with reference to Figure 2. As shown in the figure, the first and second one-shot pulse output circuits 71 and 72 each have an inverter 701, a current source 702, transistors MP20 and MN20, a capacitor C, an inverter 703, and an AND circuit 704. The input of inverter 701 becomes the input of the first and second one-shot pulse output circuits 71 and 72, and the input voltage VIN or the inverted input voltage VIN is supplied. The current source 702 supplies the current Iref2. Transistor MP20 is composed of a P-channel field-effect transistor. Transistor MN20 is composed of an N-channel field-effect transistor.
[0030] Transistors MP20 and MN20 have their gates connected to each other and their drains connected to each other. The gates of transistors MP20 and MN20 are connected to the output of inverter 701. The source of transistor MP20 is connected to current source 702, and the source of transistor MN20 is connected to GND. Capacitor C is connected between the drains of transistors MP20 and MN20 and GND. The input of inverter 703 is connected to capacitor C and the drains of transistors MP20 and MN20. The input of AND gate 704 is connected to the inputs of the first and second one-shot pulse output circuits 71 and 72 and the output of inverter 703. The output of AND gate 704 becomes the output of the first and second one-shot pulse output circuits 71 and 72.
[0031] As described above, when the input voltage VIN or the inverted input voltage VIN switches from a low level (GND) to a high level (VDD1), the gates of transistors MP20 and MN20 become low, turning transistor MP20 on and transistor MN20 off. This causes the capacitor C to start charging due to the current Iref2. As long as capacitor C is not charged and the voltage across it does not exceed the inverter voltage, inverter 703 outputs a high level, and AND circuit 704 outputs high-level first and second one-shot pulses. On the other hand, when capacitor C is charged and the voltage across it exceeds the inverter voltage, the output of inverter 703 switches to a low level, AND circuit 704 outputs a low level, and the output of the first and second one-shot pulses stops.
[0032] Subsequently, when the input voltage VIN or the inverted input voltage VIN switches from a high level to a low level, the gates of transistors MP20 and MN20 become high, turning off transistor MP20 and turning on transistor MN20. This discharges capacitor C. With the above configuration, the first and second one-shot pulse output circuits 71 and 72 can output first and second one-shot pulses that are high for a certain period of time corresponding to the current Iref2 and the capacitance of capacitor C. The certain period is set to be longer than the time from when the input voltage VIN switches from a high level to a low level, and from a low level to a high level, until the output voltage VOUT switches from a high level to a low level, and from a low level to a high level.
[0033] Returning to Figure 1, the second transistor control circuit 8 will be described. The second transistor control circuit 8 turns on transistor MN3 during the output of the first one-shot pulse and turns on transistor MP5 when the output of the first one-shot pulse stops. In addition, the second transistor control circuit 8 turns on transistor MN4 during the output of the second one-shot pulse and turns on transistor MP6 when the output of the second one-shot pulse stops.
[0034] The second transistor control circuit 8 includes transistor MP7, resistors R1 and R2, high-voltage transistor MN8, transistor MP9, resistors R3 and R4, high-voltage transistor MN10, and a current mirror circuit 81. Transistors MP7 and MP9 are composed of P-channel field-effect transistors. Transistors MN8 and MN10 are composed of N-channel field-effect transistors.
[0035] Transistor MP7, acting as the seventh transistor, has the positive terminal of the second power supply 22 connected to its source and the drain connected to the gate of transistor MP5. Resistor R1, acting as the first resistor, is connected between the drain of transistor MP7 and the negative terminal of the third power supply 23. Resistor R2, acting as the second resistor, is connected between the positive terminal of the second power supply 22 and the gate of transistor MP7. Transistor MN8, acting as the eighth transistor, is connected between resistor R2 and the negative terminal of the first power supply 21, and the output of the first one-shot pulse output circuit 71 is connected to its gate.
[0036] Transistor MP9, acting as the ninth transistor, has the positive terminal of the second power supply 22 connected to its source and the drain connected to the gate of transistor MP6. Resistor R3, acting as the third resistor, is connected between the drain of transistor MP9 and the negative terminal of the third power supply 23. Resistor R4, acting as the fourth resistor, is connected between the positive terminal of the second power supply 22 and the gate of transistor MP9. Transistor MN10, acting as the tenth transistor, is connected between resistor R4 and the negative terminal of the first power supply 21 and the output of the second one-shot pulse output circuit 72 is connected to its gate.
[0037] The current mirror circuit 81 folds the current Iref from the current source 82 in half and supplies it to transistors MN8 and MN10, respectively. The current mirror circuit 81 includes the current source 82 and transistors MN17 to MN19.
[0038] The current source 82 has the positive terminal of the first power supply 21 connected to one end and supplies the current Iref. Transistors MN17 to MN19 are composed of N-channel field-effect transistors. Transistor MN17 has the current source 82 connected to its drain, the negative terminal of the first power supply 21 connected to its source, and its gate and drain connected to the source. Transistors MN18 and MN19 have the gate and drain of transistor MN17 connected to their gates, and the negative terminal of the first power supply 21 connected to their sources. The drain of transistor MN18 is connected to the source of transistor MN8. The drain of transistor MN19 is connected to the source of transistor MN10.
[0039] With the above configuration, transistors MN3 and MN8 are turned on during the output of the first one-shot pulse. When transistor MN8 is turned on, the current Iref from the current mirror circuit 81 flows through resistor R2. When current Iref flows through resistor R2, transistor MP7 is turned on, which can turn off transistor MP5. When the output of the first one-shot pulse is stopped, transistors MN3 and MN8 are turned off. When transistor MN8 is turned off, the current to resistor R2 is cut off. When the current to resistor R2 is cut off, transistor MP7 is turned off, which can turn on transistor MP5.
[0040] Furthermore, during the output of the second one-shot pulse, transistors MN4 and MN10 are turned on. When transistor MN10 is turned on, current Iref from the current mirror circuit 81 flows through resistor R4. When current Iref flows through resistor R4, transistor MP9 is turned on, which can turn off transistor MP6. During the period when the output of the second one-shot pulse is stopped, transistors MN4 and MN10 are turned off. When transistor MN10 is turned off, the current to resistor R4 is cut off. When the current to resistor R4 is cut off, transistor MP9 is turned off, which can turn on transistor MP6.
[0041] Next, the operation of the level conversion circuit 1 with the above configuration will be explained with reference to the timing chart in Figure 3. First, we will explain the case when the input voltage VIN switches from L level (GND) to H level (VDD1). When the input voltage VIN switches from L level to H level, the first one-shot pulse output circuit 71 outputs a first one-shot pulse to the gates of transistors MN3 and MN8. When the first one-shot pulse is output, transistor MN3 turns on and transistor MP5 turns off. At this time, transistor MN4 is off and transistor MP6 is on.
[0042] As described above, when transistor MN3 is turned on and transistor MN4 is turned off, transistors MP11 and MP12 turn on and transistors MP13 and MP14 turn off. Therefore, (VDD2-VGSMP11) is output from node A and VDD2 is output from node B, transistor MP1 turns on and transistor MP2 turns off. When transistor MP1 turns on and transistor MP2 turns off, as shown in Table 1, a high level (VDD2) is output from latch circuit 3 and the output voltage VOUT becomes a high level (VDD2).
[0043] Next, after a certain period of time has elapsed since the input voltage VIN switched from a low level to a high level, the output of the first one-shot pulse, which is output from the first one-shot pulse output circuit 71 to the gates of transistors MN3 and MN8, is stopped. When the output of the first one-shot pulse is stopped, transistor MN3 turns off and transistor MP5 turns on. At this time, transistor MN4 remains off and transistor MP6 remains on.
[0044] As described above, when transistors MN3 and MN4 are turned off, transistors MP11 to MP14 are also turned off, but since transistors MP5 and MP6 are on, VDD2 is output from nodes A and B. As a result, transistors MP1 and MP2 are turned off, and as shown in Table 1, a high-level output is maintained from latch circuit 3, and the high level of the output voltage VOUT is maintained.
[0045] Next, we will explain the case when the input voltage VIN switches from a high level (VDD1) to a low level (GND). When the input voltage VIN switches from a high level to a low level, the second one-shot pulse output circuit 72 outputs a second one-shot pulse to the gates of transistors MN4 and MN10. When the second one-shot pulse is output, transistor MN4 turns on and transistor MP6 turns off. At this time, transistor MN3 is off and transistor MP5 is on.
[0046] As described above, when transistor MN4 is turned on and transistor MN3 is turned off, transistors MP13 and MP14 turn on and transistors MP11 and MP12 turn off. Therefore, VDD2 is output from node A and (VDD2 - VGSMP13) is output from node B, and transistor MP1 turns off and transistor MP2 turns on. When transistor MP1 is off and transistor MP2 is on, as shown in Table 1, a low level (VL2) is output from latch circuit 3, and the output voltage VOUT becomes a low level (VL2).
[0047] Next, after a certain period of time has elapsed since the input voltage VIN switched from a high level to a low level, the output of the second one-shot pulse, which is output from the second one-shot pulse output circuit 72 to the gates of transistors MN4 and MN10, is stopped. When the output of the second one-shot pulse is stopped, transistor MN4 turns off and transistor MP6 turns on. At this time, transistor MN3 remains off and transistor MP5 remains on.
[0048] As described above, when transistors MN3 and MN4 are turned off, transistors MP11 to MP14 are also turned off, but since transistors MP5 and MP6 are on, VDD2 is output from nodes A and B. As a result, transistors MP1 and MP2 are turned off, and as shown in Table 1, a low level output is maintained from latch circuit 3, and the low level of the output voltage VOUT is maintained.
[0049] According to the embodiment described above, when the input voltage VIN switches from a high level to a low level and from a low level to a high level, current I1 flows through nodes A and B and current Iref flows through transistors MN8 and MN10 only for a certain period of time while the first and second one-shot pulses are output. When the output of the first and second one-shot pulses stops, the currents flowing through nodes A and B and through transistors MN8 and MN10 are cut off. This makes it possible to save power.
[0050] Furthermore, the minimum operating voltage of VDD3 is given by equation (1) below, enabling low-voltage operation similar to conventional level conversion circuits. VDD3>VGSMP16+VGSMN16 …(1) VGSMP16: Gate-source voltage of transistor MP16 VGSMN16: Gate-source voltage of transistor MN16
[0051] Furthermore, according to the embodiment described above, the second transistor control circuit 8 includes transistors MP7, MN8, MP9, MP10, and resistors R1 to R4. This allows for the on / off control of transistors MN3, MN4, MP5, MP6 with a simple configuration and while saving power.
[0052] According to the embodiment described above, the second transistor control circuit 8 has a current mirror circuit 81. This makes it possible to reduce the current flowing through transistors MN8 and MN10 to a current Iref that is lower than the current I1, thereby saving power.
[0053] Furthermore, according to the embodiment described above, the first transistor control circuit 5 is composed of transistors MP11 to MP14. This allows for the on / off control of transistors MP1 and MP2 with a simple configuration.
[0054] Furthermore, the present invention is not limited to the embodiments described above, and can be modified, improved, etc., as appropriate. In addition, the material, shape, dimensions, number, placement, etc. of each component in the embodiments described above are arbitrary and not limited, as long as they can achieve the present invention.
[0055] According to the embodiment described above, the current mirror circuit 81 folded back the current Iref. The folded-back current only needs to be a current corresponding to the current Iref, and does not need to be equal to the current Iref.
[0056] In the embodiment described above, the first transistor control circuit 5 was composed of transistors MP11 to MP14, but is not limited to this. For example, it may be composed of a resistor and a Zener diode provided between the positive terminal of the second power supply 22 and nodes A and B, respectively. The resistor and Zener diode are connected in parallel. In this case, the outputs of nodes A and B switch between VDD2 and VDD2-VDZ depending on the supply and interruption of current to nodes A and B. VDZ is the Zener voltage of the Zener diode.
[0057] In the embodiments described above, transistors MP1, MP2, MN3, MN4, MP5~MP7, MN8, MP9, MN10, MP11~MP16, MN15~MN19, MP20, and MN20 were composed of field-effect transistors, but are not limited to this. Transistors MP1, MP2, MN3, MN4, MP5~MP7, MN8, MP9, MN10, MP11~MP16, MN15~MN19, MP20, and MN20 may be composed of bipolar transistors. In this case, the "gate" of the transistor can be read as "base," the "source" as "emitter," and the "drain" as "collector" in the explanation.
[0058] According to the embodiment described above, a current mirror circuit 81 was provided, but this is not the only option. The current mirror circuit 81 is not essential and may be omitted. [Explanation of Symbols]
[0059] 1. Level conversion circuit 3. Latch Circuit 5. First Transistor Control Circuit 8. Second transistor control circuit 21 1st power supply 22 2nd power supply 23 Third power supply 71. First One-Shot Pulse Output Circuit 72 Second One-Shot Pulse Output Circuit 81 Current Mirror Circuit 82 Current source Node A (First Node) Node B (Second Node) MP1 transistor (first transistor) MP2 transistor (second transistor) MN3 transistor (third transistor) MN4 transistor (4th transistor) MP5 transistor (5th transistor) MP6 transistor (6th transistor) MP7 transistor (7th transistor) MN8 transistor (8th transistor) MP9 transistor (9th transistor) MN10 transistor (10th transistor) MP11 transistor (11th transistor) MP12 transistor (12th transistor) MP13 transistor (13th transistor) MP14 transistor (14th transistor) R1 Resistor (First Resistor) R2 resistance (second resistance) R3 resistor (3rd resistor) R4 resistor (4th resistor) VIN Input Voltage VOUT output voltage
Claims
1. A level conversion circuit that converts an input voltage having amplitudes of a first high voltage and a first low voltage to an output voltage having amplitudes of a second high voltage and a second low voltage, A first transistor having a first node connected to its gate or base, and the positive terminal of a second power supply that supplies the second high voltage from its positive terminal connected to its source or emitter, A second transistor having a second node connected to its gate or base and the positive terminal of the second power supply connected to its source or emitter, A latch circuit that outputs the second high voltage when the first transistor is on and the second transistor is off, outputs the second low voltage when the first transistor is off and the second transistor is on, and holds the output when the first transistor is off and the second transistor is off, A third transistor connected between the first node and the negative terminal of a first power supply that supplies the first high voltage from the positive terminal and the first low voltage from the negative terminal, A fourth transistor connected between the second node and the negative terminal of the first power supply, A first transistor control circuit is provided between the positive terminal of the second power supply and the first and second nodes, which turns on the first transistor and turns off the second transistor when the third transistor is on and the fourth transistor is off, and turns off the first transistor and turns on the second transistor when the third transistor is off and the fourth transistor is on. A fifth transistor connected between the positive terminal of the second power supply and the first node, A sixth transistor connected between the positive terminal of the second power supply and the second node, A first one-shot pulse output circuit that outputs a first one-shot pulse in response to the rise of the input voltage from the first low voltage to the first high voltage, A second one-shot pulse output circuit that outputs a second one-shot pulse in accordance with the falling edge of the input voltage from the first high voltage to the first low voltage, The system includes a second transistor control circuit that turns on the third transistor and turns off the fifth transistor while the first one-shot pulse is output, turns off the third transistor and turns on the fifth transistor while the first one-shot pulse is stopped, turns on the fourth transistor and turns off the sixth transistor while the second one-shot pulse is output, and turns off the fourth transistor and turns on the sixth transistor while the second one-shot pulse is stopped. Level conversion circuit.
2. In the level conversion circuit described in claim 1, The aforementioned second transistor control circuit is A seventh transistor connected between the positive terminal of the second power supply and the gate or base of the fifth transistor, A first resistor connected between the seventh transistor and the negative terminal of the third power supply for supplying the second low voltage from the negative terminal, A second resistor connected between the positive terminal of the second power supply and the gate or base of the seventh transistor, An eighth transistor is connected between the gate or base of the seventh transistor and the negative terminal of the first power supply, and the first one-shot pulse output circuit is connected to the gate or base of the eighth transistor, A ninth transistor connected between the positive terminal of the second power supply and the gate or base of the sixth transistor, A third resistor connected between the ninth transistor and the negative terminal of the third power supply, A fourth resistor connected between the positive terminal of the second power supply and the gate or base of the ninth transistor, The present invention has a tenth transistor connected between the gate or base of the ninth transistor and the negative terminal of the first power supply, with the second one-shot pulse output circuit connected to its gate or base. Level conversion circuit.
3. In the level conversion circuit described in claim 2, The aforementioned second transistor control circuit is The circuit includes a current source that receives power from the first power source and supplies current, and a current mirror circuit that folds back the current supplied from the current source or a current corresponding to the current supplied from the current source and supplies it to the eighth transistor and the tenth transistor. Level conversion circuit.
4. In the level conversion circuit according to any one of claims 1 to 3, The first transistor control circuit is, An eleventh transistor whose source or emitter is connected to the positive terminal of the second power supply, and whose drain or collector is connected to the first node and gate or base, A 12th transistor whose source or emitter is connected to the positive terminal of the second power supply, whose gate or base is connected to the gate or base of the 11th transistor, and whose drain or collector is connected to the second node, A 13th transistor whose source or emitter is connected to the positive terminal of the second power supply, and whose drain or collector is connected to the second node and gate or base, A 14th transistor having a source or emitter connected to the positive terminal of the second power supply, a gate or base connected to the gate or base of the 13th transistor, and a drain or collector connected to the first node. Level conversion circuit.