Level conversion circuit
The level conversion circuit addresses the issues of circuit scale and power consumption by employing a transistor control circuit and current mirror to manage transistor states and current flow, resulting in a more efficient and compact design.
Patent Information
- Authority / Receiving Office
- JP · JP
- Patent Type
- Patents
- Current Assignee / Owner
- NISSHINBO MICRO DEVICES INC
- Filing Date
- 2022-08-12
- Publication Date
- 2026-07-07
AI Technical Summary
Conventional level conversion circuits face issues of increased circuit scale and high power consumption due to the need for high-voltage-resistant transistors and continuous current flow through multiple resistors when input and output voltages are at the low level.
A level conversion circuit design that includes P-channel and N-channel field effect transistors, a latch circuit, transistor control circuit, current mirror circuit, and one-shot pulse output circuits to manage transistor states and current flow, reducing the number of high-voltage transistors and optimizing current paths.
The circuit achieves reduced circuit size and power consumption by minimizing the number of high-voltage transistors and controlling current flow, while maintaining efficient voltage level conversion.
Smart Images
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Abstract
Description
Technical Field
[0001] The present invention relates to a level conversion circuit.
Background Art
[0002] Fig. 4 shows a conventional level conversion circuit (see, for example, Fig. 1 of Patent Document 1). When an input voltage having an amplitude between H level (VDD1) and L level (GND) is input to the input terminal IN, the conventional level conversion circuit outputs an output voltage having an amplitude between H level (VDD2) and L level (VL2 = VDD2 - VDD3) from the output terminal OUT. In Fig. 4, MP21 to MP29 are P-channel field effect transistors, MN21 to MN28 are N-channel field effect transistors, R1 to R7 are resistors, AND1 and AND2 are AND circuits, and INV1 to INV7 are inverters.
[0003] The conventional level conversion circuit has a problem that transistors MN25, MN26, MN27, and MP29 need to be composed of high-voltage-resistant transistors, resulting in an increase in circuit scale. Also, the conventional level conversion circuit has a problem of high power consumption because when the input voltage and the output voltage are at the L level, transistors MP24, MN21, MP29, MN27, and MN28 are turned on and current continues to flow through the four resistors R1, R5, R6, and R7 as indicated by the arrows.
Prior Art Documents
Patent Documents
[0004]
Patent Document 1
Summary of the Invention
Problems to be Solved by the Invention
[0005] The present invention has been made in view of the above circumstances, and an object thereof is to provide a level conversion circuit that reduces the circuit scale and decreases the power consumption. [Means for solving the problem]
[0006] To achieve the aforementioned objectives, the level conversion circuit according to the present invention is characterized by the following [1] to [3]. [1] A level conversion circuit that converts an input voltage having amplitudes of a first high voltage and a first low voltage to an output voltage having amplitudes of a second high voltage and a second low voltage, The first node is connected to the gate or base, and the second high voltage is connected to the source or emitter. From the positive electrode The first transistor to which the positive terminal of the second power supply is connected, A second transistor having a second node connected to its gate or base and the positive terminal of the second power supply connected to its source or emitter, The second high voltage is output when the first transistor is on and the second transistor is off; the second low voltage is output when the first transistor is off and the second transistor is on; and the output is maintained when the first transistor is off and the second transistor is off. A latch circuit and The input voltage is supplied to the gate or base, and the first node and the first high voltage The first low voltage is supplied from the positive electrode and from the negative electrode. A third transistor connected between the negative terminals of the first power supply, The inverted input voltage is supplied to the gate or base of a fourth transistor connected between the second node and the negative terminal of the first power supply, A transistor control circuit is provided between the positive terminal of the second power supply and the first and second nodes, which turns on the first transistor and turns off the second transistor when the third transistor is on and the fourth transistor is off, and turns off the first transistor and turns on the second transistor when the third transistor is off and the fourth transistor is on. A current mirror circuit having a current source that receives power from the first power supply, and which folds back the current from the current source or a current corresponding to the current from the current source and supplies it to the third transistor and the fourth transistor, respectively, A first one-shot pulse output circuit that outputs a first one-shot pulse in response to either the rising edge of the input voltage from the first low voltage to the first high voltage or the falling edge from the first high voltage to the first low voltage, The first one-shot pulse is input to the gate or base of a fifth transistor, which is connected between the source or emitter of one of the third and fourth transistors and the negative terminal of the first power supply. It is a level conversion circuit. [2] In the level conversion circuit described in [1], A second one-shot pulse output circuit outputs a second one-shot pulse in accordance with the other of the rising edge of the input voltage from the first low voltage to the first high voltage and the falling edge from the first high voltage to the first low voltage, The second one-shot pulse is input to the gate or base of a sixth transistor, which is connected between the source or emitter of the other of the third and fourth transistors and the negative terminal of the first power supply. It is a level conversion circuit. [3] In the level conversion circuit described in [1] or [2], The aforementioned transistor control circuit is A seventh transistor whose source or emitter is connected to the positive terminal of the second power supply, and whose drain or collector is connected to the first node and gate or base, An eighth transistor whose source or emitter is connected to the positive terminal of the second power supply, whose gate or base is connected to the gate or base of the seventh transistor, and whose drain or collector is connected to the second node, A ninth transistor whose source or emitter is connected to the positive terminal of the second power supply, and whose drain or collector is connected to the second node and gate or base, A 10th transistor having a source or emitter connected to the positive terminal of the second power supply, a gate or base connected to the gate or base of the 9th transistor, and a drain or collector connected to the first node. It is a level conversion circuit. [Effects of the Invention]
[0007] According to the present invention, it is possible to provide a level conversion circuit that reduces the circuit scale and also reduces the power consumption.
[0008] As described above, the present invention has been briefly explained. Furthermore, the details of the present invention will be further clarified by reading through the embodiments for carrying out the invention described below (hereinafter referred to as "embodiments") with reference to the accompanying drawings.
Brief Explanation of Drawings
[0009] [Figure 1] FIG. 1 is a circuit diagram showing an embodiment of the level conversion circuit of the present invention. [Figure 2] FIG. 2 is a circuit diagram showing the details of the first and second one-shot pulse output circuits shown in FIG. 1. [Figure 3] FIG. 3 is a time chart of each voltage and current of the level conversion circuit shown in FIG. 1. [Figure 4] FIG. 4 is a circuit diagram showing an example of a conventional level conversion circuit.
Embodiments for Carrying out the Invention
[0010] Specific embodiments of the present invention will be described below with reference to each figure.
[0011] FIG. 1 is a circuit diagram showing an embodiment of the level conversion circuit 1 of the present invention. The level conversion circuit 1 is a circuit that converts an input voltage VIN having an amplitude of H level (VDD1) and L level (GND) input to an input terminal IN into an output voltage VOUT having an amplitude of H level (VDD2) and L level (VL2 = VDD2 - VDD3) and outputs it from an output terminal OUT. VDD1 is a power supply voltage supplied from a first power supply 21. VDD2 is a power supply voltage supplied from a second power supply 22. VDD3 is a power supply voltage supplied from a third power supply 23 and is provided to supply VL2. For example, GND = 0V, VDD1 = 5V, VDD2 = 30V, and VDD3 = 3V. In the present embodiment, VDD1 corresponds to the first high voltage, GND corresponds to the first low voltage, VDD2 corresponds to the second high voltage, and VL2 corresponds to the second low voltage.
[0012] The level conversion circuit 1 includes transistors MP1, MP2, a latch circuit 3, an inverter circuit 4, transistors MN3, MN4, a transistor control circuit 5, a current mirror circuit 6, first and second one-shot pulse output circuits 71, 72, and transistors MN5, MN6.
[0013] The transistors MP1, MP2 as the first and second transistors are composed of P-channel field effect transistors. The gate of the transistor MP1 is connected to a node A as a first node, the source is connected to the positive electrode of the second power supply 22, and VDD2 is supplied. The gate of the transistor MP2 is connected to a node B as a second node, the source is connected to the positive electrode of the second power supply 22, and VDD2 is supplied.
[0014] Latch circuit 3 is a circuit to which the voltage between VDD2 and VL2 is applied. Latch circuit 3 latches the output based on the on / off state of transistors MP1 and MP2, and outputs voltages with amplitudes of H level (VDD2) and L level (VL2) (details will be described later). Latch circuit 3 has transistors MP11, MP12, MN11, and MN12. Transistors MP11 and MP12 are composed of P-channel field-effect transistors, and transistors MN11 and MN12 are composed of N-channel field-effect transistors.
[0015] Transistors MP11 and MP12 have the positive terminal of the second power supply 22 connected to their source, and are supplied with VDD2. Transistors MN11 and MN12 have the negative terminal of the third power supply 23 connected to their source, and are supplied with VL2. Also, the drains of transistors MP11 and MN11 are connected to each other, and the gates are connected to each other. Also, the drains of transistors MP11 and MN11 are connected to the gates of transistors MP12 and MN12. The drains of transistors MP12 and MN12 are connected to the gates of transistors MP11 and MN11.
[0016] The drain of transistor MP1 is connected to the gates of transistors MP11 and MN11, and the drains of transistors MP12 and MN12. The drain of transistor MP2 is connected to the drains of transistors MP11 and MN11, and the gates of transistors MP12 and MN12. The drains of transistors MP12 and MN12 become the output of latch circuit 3.
[0017] With the above configuration, when transistor MP1 is ON and transistor MP2 is OFF, the latch circuit 3 turns transistors MP11 and MN12 OFF and transistors MN11 and MP12 ON, outputting a high level (VDD2). When transistors MP1 and MP2 are switched OFF from this state, the OFF state of transistors MP11 and MN12 and the ON state of transistors MN11 and MP12 are maintained, and the high level (VDD2) output is maintained. Also, when transistor MP1 is OFF and transistor MP2 is ON, the latch circuit 3 turns transistors MP11 and MN12 ON and transistors MN11 and MP12 OFF, outputting a low level (VL2). When transistors MP1 and MP2 are switched OFF from this state, the ON state of transistors MP11 and MN12 and the OFF state of transistors MN11 and MP12 are maintained, and the low level (VL2) output is maintained.
[0018] Inverter circuit 4 inverts the output of latch circuit 3 twice and outputs it as output voltage VOUT. Inverter circuit 4 has two inverters 41 and 42. Inverter 41 has its input connected to the output of latch circuit 3. Inverter 42 has its input connected to the output of inverter 41 and its output connected to the output terminal OUT.
[0019] The third and fourth transistors, MN3 and MN4, are composed of high-voltage N-channel field-effect transistors. Transistor MN3 is connected between node A and the negative terminal of the first power supply 21. Transistor MN4 is connected between node B and the negative terminal of the first power supply 21. More specifically, transistor MN3 has the negative terminal of the first power supply 21 connected to its source via transistor MN14 (described later) and node A connected to its drain. Transistor MN4 has the negative terminal of the first power supply 21 connected to its source via transistor MN15 (described later) and node B connected to its drain.
[0020] The transistor control circuit 5 has transistors MP7 to MP10 as the 7th to 10th transistors, which are composed of P-channel field-effect transistors. Transistors MP7 and MP8 are current mirrored. Transistor MP7 has the positive terminal of the second power supply 22 connected to its source, and its gate and drain connected to the same terminal. The drain of transistor MP7 is connected to node A. Transistor MP8 has the positive terminal of the second power supply 22 connected to its source, and its gate is connected to the gate and drain of transistor MP7. The drain of transistor MP8 is connected to node B.
[0021] Transistors MP9 and MP10 are in current mirror connection. Transistor MP9 has the positive terminal of the second power supply 22 connected as its source, and its gate and drain connected as well. The drain of transistor MP9 is connected to node B. Transistor MP10 has the positive terminal of the second power supply 22 connected as its source, and the gate and drain of transistor MP9 connected as its gate. The drain of transistor MP10 is connected to node A.
[0022] When transistor MN3 is ON and transistor MN4 is OFF, transistor control circuit 5 turns on transistors MP7 and MP8, and turns off transistors MP9 and MP10. As a result, transistor control circuit 5 outputs a low level (VDD2-VGSMP7) from node A and a high level (VDD2) from node B, controlling transistor MP1 to turn ON and transistor MP2 to turn OFF. VGSMP7 is the gate-source voltage of transistor MP7, and is a voltage greater than or equal to the threshold voltage of transistor MP1.
[0023] Furthermore, when transistor MN3 is off and transistor MN4 is on, transistors MP7 and M8 are turned off, and transistors MP9 and MP10 are turned on. As a result, transistor control circuit 5 outputs a high level (VDD2) from node A and a low level (VDD2-VGSMP9) from node B, controlling transistor MP1 to turn off and transistor MP2 to turn on. VGSMP9 is the gate-source voltage of transistor MP9, and is a voltage greater than or equal to the threshold voltage of transistor MP2.
[0024] The current mirror circuit 6 is a circuit to which the voltage between VDD1 and GND is applied. The current mirror circuit 6 folds the current Iref from the current source 61 in half and supplies it to transistors MN3 and MN4, respectively. The current mirror circuit 6 has a current source 61 and transistors MN13 to MN15.
[0025] The current source 61 has the positive terminal of the first power supply 21 connected to one end and supplies the current Iref. Transistors MN13 to MN15 are composed of N-channel field-effect transistors. Transistor MN13 has the current source 61 connected to its drain, the negative terminal of the first power supply 21 connected to its source, and its gate and drain connected to the source. Transistors MN14 and MN15 have the gate and drain of transistor MN13 connected to their gates, and the negative terminal of the first power supply 21 connected to their sources. The drain of transistor MN14 is connected to the source of transistor MN3. The drain of transistor MN15 is connected to the source of transistor MN4.
[0026] With the above configuration, the current Iref is folded back into the drain current of transistor MN14 and supplied to transistor MN3. Furthermore, the current Iref is folded back into the drain current of transistor MN15 and supplied to transistor MN4.
[0027] The first one-shot pulse output circuit 71 has the input terminal IN connected to its input, and the input voltage VIN is input to it. The first one-shot pulse output circuit 71 is a circuit that outputs a first one-shot pulse in response to the rising edge of the input voltage VIN from a low level to a high level. The output of the first one-shot pulse output circuit 71 is connected to the gate of transistor MN5, which will be described later.
[0028] The output of inverter 8 is connected to the input of the second one-shot pulse output circuit 72. The input terminal IN is connected to the input of inverter 8, and the inverted input voltage VIN is input to the input of the second one-shot pulse output circuit 72. The second one-shot pulse output circuit 72 is a circuit that outputs a second one-shot pulse in accordance with the falling edge of the input voltage VIN from a high level to a low level. The output of the second one-shot pulse output circuit 72 is connected to the gate of transistor MN6, which will be described later.
[0029] Next, an example of the first and second one-shot pulse output circuits 71 and 72 described above will be explained with reference to Figure 2. As shown in the figure, the first and second one-shot pulse output circuits 71 and 72 each have an inverter 701, a current source 702, transistors MP16 and MN16, a capacitor C, an inverter 703, and an AND circuit 704. The input of inverter 701 becomes the input of the first and second one-shot pulse output circuits 71 and 72, and the input voltage VIN or the inverted input voltage VIN is supplied. The current source 702 supplies the current Iref2. Transistor MP16 is composed of a P-channel field-effect transistor. Transistor MN16 is composed of an N-channel field-effect transistor.
[0030] Transistors MP16 and MN16 have their gates connected to each other and their drains connected to each other. The gates of transistors MP16 and MN16 are connected to the output of inverter 701. The source of transistor MP16 is connected to current source 702, and the source of transistor MN16 is connected to GND. Capacitor C is connected between the drains of transistors MP16 and MN16 and GND. The input of inverter 703 is connected to capacitor C and the drains of transistors MP16 and MN16. The input of AND gate 704 is connected to the inputs of the first and second one-shot pulse output circuits 71 and 72 and the output of inverter 703. The output of AND gate 704 becomes the output of the first and second one-shot pulse output circuits 71 and 72.
[0031] As described above, when the input voltage VIN or the inverted input voltage VIN switches from a low level (GND) to a high level (VDD1), the gates of transistors MP16 and MN16 become low, turning transistor MP16 on and transistor MN16 off. This causes the capacitor C to start charging due to the current Iref2. As long as capacitor C is not charged and the voltage across it does not exceed the inverter voltage, inverter 703 outputs a high level, and AND circuit 704 outputs high-level first and second one-shot pulses. On the other hand, when capacitor C is charged and the voltage across it exceeds the inverter voltage, the output of inverter 703 switches to a low level, AND circuit 704 outputs a low level, and the output of the first and second one-shot pulses stops.
[0032] Subsequently, when the input voltage VIN or the inverted input voltage VIN switches from a high level to a low level, the gates of transistors MP16 and MN16 become high, turning transistor MP16 off and transistor MN16 on. This discharges capacitor C. With the above configuration, the first and second one-shot pulse output circuits 71 and 72 can output first and second one-shot pulses that are high for a certain period of time corresponding to the current Iref2 and the capacitance of capacitor C. It is preferable that this certain period is set to be longer than the time from when the input voltage VIN switches from a high level to a low level, and from a low level to a high level, until the output voltage VOUT switches from a high level to a low level, and from a low level to a high level.
[0033] Returning to Figure 1, let's continue the explanation of the level conversion circuit 1. Transistor MN5 has its source connected to the negative terminal of the first power supply 21, and its drain connected to the drain of transistor MN14 and the source of transistor MN3. The gate of transistor MN5 is input to the first one-shot pulse output by the first one-shot pulse output circuit 71.
[0034] The source of transistor MN6 is connected to the negative terminal of the first power supply 21, and its drain is connected to the drain of transistor MN15 and the source of transistor MN4. The gate of transistor MN6 is input to the second one-shot pulse output by the second one-shot pulse output circuit 72.
[0035] With the above configuration, while a one-shot pulse is output from the first one-shot pulse output circuits 71 and 72, transistors MN5 and MN6 are turned on, increasing the current flowing through nodes A and B.
[0036] Next, the operation of the level conversion circuit 1 with the above configuration will be explained with reference to the timing chart in Figure 3. First, we will explain the case when the input voltage VIN switches from L level (GND) to H level (VDD1). When the input voltage VIN switches from L level to H level, transistor MN3 switches from off to on, and transistor MN4 switches from on to off. Also, a first one-shot pulse is output to the gate of transistor MN5, and transistor MN5 turns on. Transistor MN6 remains off.
[0037] When transistors MN3 and MN5 are turned on, the current IA flowing through node A becomes I1 + Iref, where I1 is the drain current of transistor MN5. This current IA causes the potential of node A to drop from VDD1 to (VDD2 - VGSMP7). On the other hand, when transistors MN4 and MN6 are turned off, the current IB flowing through node B is interrupted and becomes 0. When current IB is interrupted, the potential of node B is raised to VDD2.
[0038] When node A drops to (VDD2-VGSMP7), transistor MP1 turns on. Also, when node B rises to VDD2, transistor MP2 turns off. When transistor MP1 is on and transistor MP2 is off, transistors MP12 and MN11 turn on and transistors MP11 and MN12 turn off. As a result, the drains of transistors MP12 and MN12 (output of latch circuit 3) become high level (VDD2), and the drains of transistors MP11 and MN11 become low level (VL2). When the output of latch circuit 3 becomes high level and exceeds the threshold voltage of inverter 41, the output voltage VOUT switches from low level (VL2) to high level (VDD2).
[0039] After a certain period of time has elapsed since the input voltage VIN switched from a low level to a high level, the output of the first one-shot pulse stops, and transistor MN5 turns off. When transistor MN5 turns off, the current IA flowing through node A drops to Iref, but because current continues to flow, transistor MN3 remains on, and the output voltage VOUT remains at a high level.
[0040] Next, we will explain what happens when the input voltage VIN switches from a high level (VDD1) to a low level (GND). When the input voltage VIN switches from a high level to a low level, transistor MN3 switches from on to off, and transistor MN4 switches from off to on. Also, a second one-shot pulse is output to the gate of transistor MN6, turning transistor MN6 on. Transistor MN5 remains off.
[0041] When transistors MN4 and MN6 are turned on, the current IB flowing through node B becomes I1 + Iref, where I1 is the drain current of transistor MN6. This current IB causes the potential of node B to drop from VDD2 to (VDD2 - VGSMP9). On the other hand, when transistors MN3 and MN5 are turned off, the current IA flowing through node A is interrupted and becomes 0. When current IA is interrupted, the potential of node A is raised to VDD2.
[0042] When node B drops to (VDD2-VGSMP9), transistor MP2 turns on. Also, when node A rises to VDD2, transistor MP1 turns off. When transistor MP1 is off and transistor MP2 is on, transistors MP12 and MN11 turn off and transistors MP11 and MN12 turn on. As a result, the drains of transistors MP12 and MN12 (output of latch circuit 3) become low level (VL2), and the drains of transistors MP11 and MN11 become high level (VDD2). When the output of latch circuit 3 becomes low level and falls below the threshold voltage of inverter 41, the output voltage VOUT switches from high level (VDD2) to low level (VL2).
[0043] After a certain period of time has elapsed since the input voltage VIN switched from a high level to a low level, the output of the second one-shot pulse stops, and transistor MN6 turns off. When transistor MN6 turns off, the current IB flowing through node B drops to Iref, but because current continues to flow, transistor MN4 remains on, and the output voltage VOUT remains at a low level.
[0044] According to the embodiment described above, by providing the first and second one-shot pulse output circuits 71 and 72 and transistors MN5 and MN6, the current flowing to nodes A and B is increased when the input voltage VIN switches from H level to L level and from L level to H level, thereby shortening the transition time of the potential of nodes A and B from H level to L level and from L level to H level, and shortening the transition time of the output voltage from H level to L level and from L level to H level.
[0045] Furthermore, after the output of the first and second one-shot pulses stops, the current flowing through node A or node B can be reduced from current I1 + Iref to current Iref. In addition, the current flow path can be limited to two locations: the current source 61 and node A or node B, thereby reducing power consumption. Moreover, the number of large, high-voltage transistors MN3 and MN4 can be reduced to two, thereby reducing the circuit size.
[0046] Furthermore, the minimum operating voltage of VDD3 is given by equation (1) below, enabling low-voltage operation similar to conventional level conversion circuits. VDD3>VGSMP12+VGSMN12 …(1) VGSMP12: Gate-source voltage of transistor MP12 VGSMN12: Gate-source voltage of transistor MN12
[0047] Furthermore, according to the embodiment described above, the transistor control circuit 5 is composed of transistors MP7 to MP10. This allows for the on / off control of transistors MP1 and MP2 with a simple configuration.
[0048] Furthermore, the present invention is not limited to the embodiments described above, and can be modified, improved, etc., as appropriate. In addition, the material, shape, dimensions, number, placement, etc. of each component in the embodiments described above are arbitrary and not limited, as long as they can achieve the present invention.
[0049] According to the embodiment described above, the current mirror circuit 6 folded back the current Iref. The folded-back current only needs to be a current corresponding to the current Iref, and does not need to be equal to the current Iref.
[0050] In the embodiment described above, the level conversion circuit 1 was provided with two first and second one-shot pulse output circuits 71 and 72, but it is not limited to this. Only one of the two first and second one-shot pulse output circuits 71 and 72 may be provided. In this case, only one of the transistors MN5 and MN6 is provided, and the output of one of the first and second one-shot pulse output circuits 71 and 72 is supplied to the gate.
[0051] In the embodiment described above, the transistor control circuit 5 was composed of transistors MP7 to MP10, but is not limited to this. For example, it may be composed of a resistor and a Zener diode provided between the positive terminal of the second power supply 22 and nodes A and B, respectively. The resistor and Zener diode are connected in parallel. In this case, the outputs of nodes A and B switch between VDD2 and VDD2-VDZ depending on whether transistors MN3 and MN4 are on or off. VDZ is the Zener voltage of the Zener diode.
[0052] In the embodiments described above, transistors MP1, MP2, MN3~MN6, MP7~MP10, MP11, MP12, MN11, MN12, MN13~MN15 were composed of field-effect transistors, but are not limited to this. Transistors MP1, MP2, MN3~MN6, MP7~MP10, MP11, MP12, MN11, MN12, MN13~MN15 may be composed of bipolar transistors. In this case, the "gate" of the transistor can be read as "base," the "source" as "emitter," and the "drain" as "collector" in the explanation. [Explanation of Symbols]
[0053] 1. Level conversion circuit 3. Latch Circuit 5. Transistor Control Circuits 6. Current Mirror Circuit 21 1st power supply 22 2nd power supply 61 Current source 71. First One-Shot Pulse Output Circuit 72 Second One-Shot Pulse Output Circuit Node A (First Node) Node B (Second Node) Iref current MP1 transistor (first transistor) MP2 transistor (second transistor) MN3 transistor (third transistor) MN4 transistor (4th transistor) MN5 transistor (5th transistor) MN6 transistor (6th transistor) MP7 transistor (7th transistor) MP8 transistor (8th transistor) MP9 transistor (9th transistor) MP10 transistor (10th transistor) VIN Input Voltage VOUT output voltage
Claims
1. A level conversion circuit that converts an input voltage having amplitudes of a first high voltage and a first low voltage to an output voltage having amplitudes of a second high voltage and a second low voltage, A first transistor having a first node connected to its gate or base, and the positive terminal of a second power supply that supplies the second high voltage from its positive terminal connected to its source or emitter, A second transistor having a second node connected to its gate or base and the positive terminal of the second power supply connected to its source or emitter, A latch circuit that outputs the second high voltage when the first transistor is on and the second transistor is off, outputs the second low voltage when the first transistor is off and the second transistor is on, and holds the output when the first transistor is off and the second transistor is off, The input voltage is supplied to the gate or base of a third transistor connected between the first node and the negative terminal of a first power supply that supplies the first high voltage from the positive terminal and the first low voltage from the negative terminal, The inverted input voltage is supplied to the gate or base of a fourth transistor connected between the second node and the negative terminal of the first power supply, A transistor control circuit is provided between the positive terminal of the second power supply and the first and second nodes, which turns on the first transistor and turns off the second transistor when the third transistor is on and the fourth transistor is off, and turns off the first transistor and turns on the second transistor when the third transistor is off and the fourth transistor is on. A current mirror circuit having a current source that receives power from the first power source, and which folds back the current from the current source or a current corresponding to the current from the current source and supplies it to the third transistor and the fourth transistor, respectively, A first one-shot pulse output circuit that outputs a first one-shot pulse in response to either the rising edge of the input voltage from the first low voltage to the first high voltage or the falling edge from the first high voltage to the first low voltage, The first one-shot pulse is input to the gate or base of a fifth transistor, which is connected between the source or emitter of one of the third and fourth transistors and the negative terminal of the first power supply. Level conversion circuit.
2. In the level conversion circuit described in claim 1, A second one-shot pulse output circuit outputs a second one-shot pulse in accordance with the other of the rising edge of the input voltage from the first low voltage to the first high voltage and the falling edge from the first high voltage to the first low voltage, The second one-shot pulse is input to the gate or base of a sixth transistor, which is connected between the source or emitter of the other of the third and fourth transistors and the negative terminal of the first power supply. Level conversion circuit.
3. In the level conversion circuit according to claim 1 or 2, The aforementioned transistor control circuit is A seventh transistor whose source or emitter is connected to the positive terminal of the second power supply, and whose drain or collector is connected to the first node and gate or base, An eighth transistor whose source or emitter is connected to the positive terminal of the second power supply, whose gate or base is connected to the gate or base of the seventh transistor, and whose drain or collector is connected to the second node, A ninth transistor whose source or emitter is connected to the positive terminal of the second power supply, and whose drain or collector is connected to the second node and gate or base, A 10th transistor having a source or emitter connected to the positive terminal of the second power supply, a gate or base connected to the gate or base of the 9th transistor, and a drain or collector connected to the first node. Level conversion circuit.