Multilayer capacitor

Abstract

To provide a multilayer capacitor having improved material properties and improved geometry.SOLUTION: A multilayer capacitor 1 having at least two segments 2A and 2B is provided, each segment including a dielectric layer 5 made of ceramic and an electrode layer disposed therebetween, overlapping in layer order, and comprising a plurality of segments. The segments are arranged one on top of the other, and the outermost dielectric layer of the two segments forms a coupling region 12. In the coupling region 12, the segments are firmly coupled to each other parallel to the layer plane, the coupling region comprising a stress relief region 13, which occupies at least the entire passive region of the multilayer capacitor and comprises a plurality of capacitor elements 2. The capacitor elements 2 are connected to each other in such a way that they can be assembled and disassembled at the contact surfaces.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present invention relates to a ceramic multilayer capacitor comprising a dielectric layer and electrodes disposed between them. [Background technology]

[0002] Examples of multilayer capacitors are known to those skilled in the art from the prior art.

[0003] In multilayer ceramic capacitors with piezoelectric properties, deformation of the electroceramic material generally occurs when a capacitor voltage is applied.

[0004] Periodic deformation can lead to material fatigue, which in turn can result in the fracture of ceramic materials.

[0005] Furthermore, known multilayer capacitors have various additional technical challenges in their use. [Overview of the Initiative] [Problems that the invention aims to solve]

[0006] Therefore, the object of the present invention is to provide a multilayer capacitor having improved material properties and improved geometric shape. [Means for solving the problem]

[0007] This problem is solved, at least in part, by the multilayer capacitor disclosed in claim 1.

[0008] Further embodiments can be seen from further claims.

[0009] A multilayer capacitor including a capacitor element having at least two segments is disclosed. The segments each have a dielectric layer made of ceramic and an electrode layer disposed therebetween, and they are arranged to overlap in a layer sequence. In this case, the electrode layer includes different electrodes including at least a first and a second electrode.

[0010] The different electrodes, i.e., for example, the first and the second electrodes, overlap in the active region. The region where the different electrodes do not overlap is called the passive region.

[0011] In the passive region, for example, only electrodes of the same type, i.e., only the first electrode or only the second electrode, or only any other uniform type of electrode, overlap.

[0012] Additionally or alternatively, the passive region can be a region of the capacitor element where no electrode is arranged. Such a region can be, for example, a peripheral region adjacent to the outer surface of the capacitor element. This is because, in most cases, the electrodes do not extend across the entire width of the capacitor element.

[0013] Inside the capacitor element, a plurality of segments are arranged to overlap in the stacking direction, and the outermost dielectric layers of two segments form a bonding region, in which the segments are firmly bonded to each other parallel to the layer plane. The bonding region is formed, for example, by the lowermost dielectric layer of the upper segment and the uppermost dielectric layer of the lower segment.

[0014] The two dielectric layers are firmly bonded to each other, for example, by sintering. By sintering the segments arranged to overlap together, the adjacent dielectric layers are physically and chemically bonded to each other.

[0015] Any number of segments can be bonded to each other. In that case, one bonding region is formed between every two segments.

[0016] The coupling region includes a stress relaxation region located in a plane parallel to the electrodes. The stress relaxation region occupies at least the entire passive region of the capacitor.

[0017] In the stress relaxation region, the coupling between segments is weakened or interrupted. The stress relaxation region keeps the mechanical stress within the multilayer capacitor low. In this case, the segment thickness is preferably small enough that the mechanical stress within the segment does not cause crack formation within the capacitor.

[0018] Preferably, this weakening is more pronounced in the stacking direction corresponding to the magnetic field direction of the capacitor. Weakening can be achieved by forming gaps or by using materials with different moduli, preferably materials with smaller moduli. Alternatively, weakening can be achieved by inserting a material that is harder or more brittle than the ceramic. This material may break when a load is applied.

[0019] Such mechanical stresses arise, for example, when a capacitor voltage is applied. In particular, mechanical stress can be expected between the active and passive regions because they are electrically loaded in different ways. If there is no stress relaxation region inside the capacitor, such a voltage will be added up across the entire capacitor without interference.

[0020] By weakening or interrupting the coupling of segments, mechanical stresses are prevented from being added in a manner that would cause damage or cracking within the capacitor, particularly in the passive region.

[0021] In one embodiment, the stress relaxation region is formed as a region parallel to the layer plane between the segments, and within this layer plane, the segments are not firmly bonded to one another.

[0022] This makes it easy to achieve the aforementioned weakening of the connections between segments.

[0023] In one embodiment, the stress relaxation region is structured. In particular, the stress relaxation region may have at least one recess. For example, a bonding region is formed inside this recess, and in this bonding region, the segments are firmly bonded to each other, and in particular, firmly sintered to each other.

[0024] In one embodiment, the stress relaxation region is formed as a gap between segments.

[0025] In particular, dielectric layers of different segments may be separated from each other in the stress relaxation region. Dielectric layers may be adjacent to each other in the stress relaxation region and may not be bonded to each other, or may be only partially bonded, or may be bonded only with reduced adhesion strength.

[0026] In at least one embodiment, the width of the gap between segments is smaller than the thickness of the dielectric layer. The individual layer planes of the capacitor element typically each have the same layer thickness.

[0027] In one embodiment of a multilayer capacitor, the stress relaxation region includes a material whose elastic modulus differs from that of the dielectric layer.

[0028] To manufacture a multilayer capacitor, green sheets, particularly ceramic green sheets, are prepared to form a dielectric layer. A first paste, for example, containing an organic or inorganic material, is applied, for example, to at least one green sheet that will later form the dielectric layer on the outside of the segments, and printed, for example. The first paste is preferably applied only to areas where stress relaxation regions are to be provided.

[0029] A second metal paste for the electrode material is printed onto another green sheet, which will later form the dielectric layer inside the segment. The printing and layering can be carried out so that the electrodes in the laminate are coated alternately and slightly offset from each other, so that these electrodes can later be brought into contact in a comb-like manner on one side of each exit surface.

[0030] The green sheets are arranged to form a laminate, which is then sintered. Preferably, the first paste is formed such that the co-sintering of the dielectric layer is completely or partially prevented in the area where the first paste is applied, resulting in the formation of a stress relaxation region.

[0031] The layered and pressed laminate can then be subdivided into individual capacitors in a mass production process.

[0032] After cutting, the binder is first burned out (debinding) from the disassembled capacitor. Then, a firing process (sintering) is carried out. In this case, the ceramic powder is sintered at a temperature of preferably 900°C to 1200°C to obtain its final, mainly crystalline structure. The individual dielectric layers bond together during the process to form a monolithic structure. The dielectric layers of overlapping segments are also strongly bonded to each other.

[0033] It is only through this firing process that the ceramic acquires its desired dielectric properties. Following the firing process, a cleaning step is performed, followed in at least one embodiment by coating the external contacts.

[0034] In one embodiment, the stress relaxation region is formed in all regions adjacent to at least the outer surface of the capacitor element.

[0035] In one embodiment, the depth to which the stress relaxation region extends from the outer surface into the capacitor element is approximately equal to the stacking height of the segment adjacent to the stress relaxation region, or the dimension between the uppermost and lowermost electrodes within the adjacent segment. The adjacent segments typically have the same stacking height.

[0036] In a further embodiment, the depth of the passive region on the outer surface of the capacitor is approximately equal to the stacking height of the adjacent segments.

[0037] In one embodiment, the depth to which the stress relaxation region extends from the outer surface into the capacitor element corresponds to twice the depth of the passive region on the outer surface of the capacitor. Therefore, the depth of the stress relaxation region depends on the depth of the passive region.

[0038] Such dimensions in the stress relaxation region prevent the accumulation of mechanical stress in a manner that would cause cracks or similar fatigue phenomena within the capacitor.

[0039] Additionally or alternatively, the stress relaxation region may, in one embodiment, include further sections not directly formed on the outer surface of the capacitor element. The dimensions of the stress relaxation region should, again, correspond at least to the dimensions described in the previous paragraph.

[0040] In one embodiment, the stress relaxation region is located in a region where different electrodes overlap, at least partially. That is, the stress relaxation region is formed in the active region of the capacitor element, at least partially.

[0041] In this embodiment, the stress relaxation region further includes all regions of the coupling region located in the passive region of the capacitor element.

[0042] The expanded stress relaxation region further reduces the mechanical stress between individual segments.

[0043] In one embodiment, the stress relaxation region has at least one section that is not adjacent to the outer surface of the capacitor element.

[0044] In one embodiment, the bonding region includes a plurality of stress relaxation regions bounded by each other.

[0045] In one embodiment, the coupling region includes a plurality of mutually bounded stress relaxation regions that are at least partially not adjacent to the outer surface of the capacitor element.

[0046] The last three embodiments described are particularly advantageous when the capacitor diameter is large.

[0047] The expanded stress relaxation region or multiple stress relaxation regions within the bonded region further reduces the mechanical stress between individual segments.

[0048] In one embodiment of a multilayer capacitor, the first and second electrodes overlap at least partially.

[0049] In the overlapping region, the first and second electrodes form an active region, in which an electric field acts and therefore mechanical stress is generated within the dielectric layer.

[0050] In one embodiment, the electrode comprises one or more of the group consisting of copper, silver, nickel, platinum, and palladium. These metals are suitable, in particular, due to their high conductivity.

[0051] For easy and inexpensive manufacturing, it is preferable to sinter the entire multilayer capacitor in a single step, as described above. Therefore, the sintering process is carried out after the individual layers have been stacked.

[0052] To enable such a method, the sintering temperature of the ceramic used in the dielectric layer must not exceed the melting temperature of the metal used in the electrodes. This can be achieved by selecting an appropriate electrode metal or ceramic.

[0053] In at least one embodiment, two separate external contacts for contact between the first and second electrodes are coated on the exit surface on the outer surface of the capacitor element, where the electrodes emerge from the capacitor element.

[0054] The external contacts are preferably applied to the outer surface opposite to the multilayer capacitor.

[0055] Any possible third or further electrodes, conversely, are not in contact with the external contacts.

[0056] In one embodiment of a multilayer capacitor, each segment includes at least three different types of electrode layers, wherein a first electrode layer contains first and second electrodes facing each other and separated by a dielectric section, a second electrode layer contains only the first electrode, and a third electrode layer contains only the second electrode, with each first electrode layer forming the outermost electrode layer in the stacking direction of each segment.

[0057] The first and second electrodes are positioned opposite each other within the first electrode layer, in a direction perpendicular to the stacking direction of the multilayer capacitor. Dielectric layers are formed between each electrode layer.

[0058] An advantage of the above-described embodiment is that no electric field is generated in the outer section of the segment or between the two segments. This is because the first and second electrodes each have the same electric polarization as the adjacent external contact.

[0059] Furthermore, the electrodes of the first electrode layer are partially adjacent to electrodes with the same electric polarization, even within the segment. Therefore, an electric field is not formed over a relatively large area. Consequently, individual layers within the active region of the segment also do not have an electric field.

[0060] Therefore, the undesirable movement of charged particles from the outside into the capacitor can be avoided. This has the advantage of greater stability against material changes induced by moisture.

[0061] In one embodiment, the multilayer capacitor includes at least one third electrode that is not in contact with any of the external contacts, and the third electrode layer overlaps with the first and second electrodes.

[0062] These types of electrodes are also called "floating" electrodes (or "schwebende" electrodes in German).

[0063] In one embodiment, the multilayer capacitor includes at least one third electrode that is not adjacent to any of the outer surfaces of the capacitor elements.

[0064] Preferably, each segment of a multilayer capacitor, in particular, has a plurality of first electrodes, a plurality of second electrodes, and a plurality of third electrodes.

[0065] In one embodiment, the capacitor has at least one series connection of two capacitances. In particular, the first capacitance can be formed by the overlap of at least one first electrode and at least one third electrode, and the second capacitance can be formed by the overlap of at least one second electrode and at least one third electrode.

[0066] In one embodiment, the multilayer capacitor includes additional electrodes located in the passive region of the capacitor and which do not overlap with electrodes of different polarities.

[0067] Therefore, no electric field is generated between these electrodes. Such electrodes are called passive electrodes or dummy electrodes.

[0068] Such dummy electrodes typically reduce the mechanical stress that occurs between regions with electrodes and regions without electrodes within the capacitor element.

[0069] Therefore, by using dummy electrodes and stress relaxation regions in combination, mechanical stress within the multilayer capacitor can be minimized, improving the capacitor's robustness. This allows for the optimization of the multilayer capacitor's thermomechanical and electrical load capacity.

[0070] In a further embodiment, the external contact includes a multilayer sputtered layer comprising layers of chromium, nickel, and at least one of silver or gold, which are applied on the exit surface in this order.

[0071] The chromium layer, applied directly to the exit surface, allows for high adhesion of the sputtered layer to the exit surface. The layer made of silver or gold has high conductivity and therefore functions primarily for electrical contact between electrodes. The aforementioned sputtered layer allows all electrodes of one type to be electrically connected to each other and thus connected in parallel.

[0072] The nickel-based intermediate layer functions as a diffusion barrier.

[0073] For example, all of the first electrodes, all emerging from the same first surface of the capacitor element, can be electrically connected to each other via a first sputtered layer. Furthermore, all of the second electrodes, all emerging from a second surface, can be electrically connected or connected in parallel via a further second sputtered layer, so that, for example, the entire laminate containing all the first electrodes and all the second electrodes forms a single multilayer capacitor.

[0074] In one embodiment, the external contact further includes a fine copper grid coated on top of the sputtered layer.

[0075] The copper grid covers the entire sputtered layer. Therefore, the copper grid can prevent crack formation within the sputtered layer or even peeling of the sputtered layer in the event of mechanical deformation of the capacitor element.

[0076] In one embodiment, the external contact further includes a metal sheet, through which the capacitor element is in contact with the outside. The metal sheet is mounted on top of the sputtered layer.

[0077] In one embodiment, a metal sheet is mounted on the sputtered layer by soldering.

[0078] In a further embodiment, the metal sheet is coated on top of the sputtered layer with a sintered silver layer.

[0079] The sputtered layer described above typically has a thickness in the nanometer range, while the silver layer has a thickness in the micrometer range. Such a sintered silver layer covering the entire sputtered layer holds the sputtered layer together when the capacitor element deforms, preventing, for example, the sputtered layer from peeling off.

[0080] The silver layer further secures the metal sheet to the sputtered layer. Therefore, no further soldering is required. For this purpose, silver is applied on top of the sputtered layer, and the metal sheet is placed directly on top of it. Only after the metal sheet is in place is the silver layer sintered at the lowest possible pressure.

[0081] In at least one embodiment, the silver layer is sintered at a low pressure such that a residual porosity of about 35% is achieved.

[0082] Such porosity is small enough to only slightly reduce the electrical and thermal conductivity of silver. Due to its high electrical and thermal conductivity, the silver layer further enables good electrical connection to the sputtered layer of the metal sheet. However, in addition, silver with the aforementioned porosity has sufficient ductility to ensure thermomechanical stress relaxation.

[0083] Furthermore, the sintered silver layer exhibits less material fatigue when subjected to mechanical or thermomechanical loads, compared, for example, a soldered layer.

[0084] Since the process temperature in sintering is generally lower than in soldering, the resulting thermomechanical stress is also lower, and the process can be carried out relatively easily and inexpensively.

[0085] The high melting point of sintered silver, up to 962°C in the case of pure silver, ensures high temperature stability of the silver layer, which allows for further process steps at high temperatures.

[0086] In one embodiment, the metal sheet includes two copper layers and an Invar layer placed between them.

[0087] Copper has particularly good electrical and thermal conductivity.

[0088] An iron-nickel alloy containing approximately 1 / 3 nickel and 2 / 3 iron is called Invar. This material has a particularly small coefficient of thermal expansion, especially close to that of ceramics. When combined with copper, it can ensure sufficient conductivity at connection points despite Invar's low conductivity.

[0089] In place of Invar, another iron-nickel alloy or iron-nickel-cobalt alloy can also be used.

[0090] To manufacture the aforementioned metal sheet, for example, a copper layer is laid out on top of an Invar sheet.

[0091] The outer surface of the copper layer may be silver-plated to improve the connection between the copper and the sintered silver layer. In one embodiment, the silver plating is applied by electroplating.

[0092] In one embodiment, the metal sheet of the external contact includes a copper layer having a meandering geometric shape.

[0093] The copper layer is applied directly on top of the silver layer. The copper layer preferably has a meandering, grid-like geometric shape. The copper layer can also be silver-plated. Silver plating is preferably carried out by electroplating. The copper layer can be sintered directly together with the silver layer.

[0094] Copper is preferably used for the external contacts of capacitors due to its excellent thermal and electrical conductivity.

[0095] In one embodiment, the multilayer capacitor has a contact surface (side) to at Includes a separable capacitor element that can be assembled and disassembled as desired, and has contact surfaces (side) It is positioned perpendicular to the layer plane and the external contact point.

[0096] Therefore, multilayer capacitors of any size can be flexibly constructed. The capacitor elements described above can be mass-produced in uniform sizes and then assembled according to requirements.

[0097] The individual capacitor elements can be fixed, for example, via a sintered silver layer mounted on their outer surface, which extends across the outer surface of all the capacitor elements and thus bundles them together.

[0098] In one embodiment, the ceramic is an antiferroelectric.

[0099] The dielectric layer can exhibit piezoelectric or electrostrictive behavior, resulting in deformation of the layer when a voltage is applied to the multilayer capacitor.

[0100] In one embodiment, the ceramic includes lead zirconate titanate. This typically crystallizes in a perovskite structure. Such a ceramic is preferably an antiferroelectric that can be used in the above-described multilayer capacitor.

[0101] In one embodiment, the ceramic has the following composition, which has advantageous properties when used in a capacitor: Pb (y-1.5a-0.5b+c+0.5d-0.5e-f) Ca a A b (Zr 1-x Ti x ) (1-c-d-e-f) E c Fe d Nb e W f O3 Here, A is selected from the group consisting of Na, K, and Ag; E is selected from the group consisting of Cu, Ni, Hf, Si, and Mn; and 0.05 ≦ x ≦ 0.3; 0 < a < 0.14; 0 ≦ b ≦ 0.12; 0 ≦ c ≦ 0.12; 0 ≦ d ≦ 0.12; 0 ≦ e ≦ 0.12; 0 ≦ f ≦ 0.12; 0.9 ≦ y ≦ 1.5, and 0.001 < b + c + d + e + f holds.

[0102] The above-described ceramic has a low sintering temperature of 900°C to 1200°C. Further, the ceramic is characterized by high stability and low material fatigue.

[0103] In one embodiment, the ceramic has the following composition, which has similar advantageous properties when used in a capacitor: Pb (1-1.5a-0.5b+1.5d+e+0.5f) A a E b (Zr 1-x Ti x ) (1-c-d-e-f) Li dG e Fe f Si c O3+ y PbO Here, A is selected from the group consisting of La, Nd, Y, Eu, Gd, Tb, Dy, Ho, Er, and Yb. E is selected from the group consisting of Na, K, and Ag. G is selected from the group consisting of Cu, Ni, Co, and Mn. and, 0.1 ≤ x ≤ 0.3; 0 <a≦0.12; 0 ≤ b ≤ 0.12; 0 ≤ c ≤ 0.12; 0 ≤ d ≤ 0.12; 0 <e≦0.12; 0 ≤ f ≤ 0.12; 0≦y≦1, and 0 <b+d+e+f This holds true.

[0104] In a further embodiment, the ceramic has the following composition, which has advantageous properties similar to those used in capacitors: Pb (1-1.5a+e) A a (Zr 1-x Ti x ) (1-c-e) E e Si c O3+ y PbO Here, A is selected from the group consisting of La, Nd, Y, Eu, Gd, Tb, Dy, Ho, Er, and Yb. E is selected from the group consisting of Cu and Ni. and, 0.05 ≤ x ≤ 0.3; 0 <a≦0.12; 0 ≤ c ≤ 0.12; 0.001≦e≦0.12, and 0≦y<1 This holds true.

[0105] In a further embodiment, the ceramic contains sodium strontium titanate. Such a ceramic is also, advantageously, an antiferroelectric that can be used in the multilayer capacitors described above.

[0106] In one embodiment, the ceramic has the following composition, which has advantageous properties when used in a capacitor: [Pb (1-r) (Ba x Sr y Ca z ) r (1-1.5a-1.5b-0.5c) (X a Y b )A c (Zr 1-d Ti d )O3 Here, X and Y each represent a rare earth metal selected from the group consisting of La, Nd, Y, Eu, Gd, Tb, Dy, Ho, Er, and / or Yb; A represents a monovalent ion; x + y + z = 1 0 ≤ x; 0 ≤ y; 0 ≤ z; 0 < r ≤ 0.3; 0 < d ≤ 1; 0 < a ≤ 0.2; 0 ≤ b ≤ 0.2, and 0 ≤ c ≤ 0.2 hold.

[0107] In a further embodiment, the ceramic has the following composition, which also has advantageous properties when used in a capacitor: (Bi a Na b Sr c )(Mg d Ti 1-d )O3 Here, 0.10 ≤ a ≤ 0.65; 0 < b ≤ 0.45; 0 ≤ c ≤ 0.85; 0 < d < 0.20, and 0.95 ≤ a + b + c ≤ 1.05 hold.​

[0108] In a further embodiment, the ceramic has the following composition, which also has advantageous properties when used in a capacitor: (Bi a Na b Sr c )(Zn d Ti 1-d )O3 where 0.09 ≦ a ≦ 0.58, 0.09 ≦ b ≦ 0.42, 0.05 ≦ c ≦ 0.84; 0 < d < 0.08, and 0.95 ≦ a + b + c ≦ 1.05 holds.

[0109] In addition to the above-described composition, further compositions not explicitly described are possible.

[0110] A capacitor having the above characteristics is suitable for use as a DC link capacitor or a snubber capacitor.

[0111] Due to the characteristics of the capacitor, it is possible in some applications to omit an additional snubber capacitor when used as a DC link capacitor.

[0112] A further use of the above-described capacitor is as a filter capacitor. Due to its high-frequency characteristics, interference signals can be sufficiently attenuated and filtered up to the MHz range.

[0113] Hereinafter, the present invention will be described in detail based on examples. The present invention is not limited to the described examples.

Brief Description of the Drawings

[0114] [Figure 1] 1 is a schematic side view of a first embodiment of a multilayer capacitor according to the present invention that does not include first and second electrodes in one segment. [Figure 2] This is a schematic side view of a second embodiment of a multilayer capacitor, which includes first and second electrodes in two segments. [Figure 3] This is a schematic top view of a second embodiment of a multilayer capacitor, which includes first and second electrodes in two segments. [Figure 4] This is a schematic side view of a third embodiment of a multilayer capacitor, which includes first and second electrodes in two segments. [Figure 5] This is a schematic top view of a third embodiment of a multilayer capacitor, which includes first and second electrodes in two segments. [Figure 6] This is a schematic side view of a fourth embodiment of a multilayer capacitor, which includes first, second, and third electrodes in two segments. [Figure 7] This is a schematic top view of a fourth embodiment of a multilayer capacitor, in which the first, second, and third electrodes are located in two segments. [Figure 8] This is a schematic side view of a fifth embodiment of a multilayer capacitor, which includes first and second electrodes in two segments. [Figure 9] This is a schematic top view of a fifth embodiment of a multilayer capacitor, which includes first and second electrodes in two segments. [Figure 10] This is a schematic side view of a sixth embodiment of a multilayer capacitor, which includes first and second electrodes in two segments. [Figure 11] This is a schematic top view of a sixth embodiment of a multilayer capacitor, which includes first and second electrodes in two segments. [Figure 12] This is a schematic side view of a seventh embodiment of a multilayer capacitor, which includes the first to sixth electrodes in two segments. [Figure 13] This is a schematic top view of a seventh embodiment of a multilayer capacitor, which includes the first to sixth electrodes in two segments. [Figure 14] This is a schematic side view of an eighth embodiment of a multilayer capacitor, in which the first and second and fourth and fifth electrodes are located in two segments. [Figure 15]This is a schematic top view of an eighth embodiment of a multilayer capacitor, in which the first and second and fourth and fifth electrodes are located in two segments. [Figure 16] This is a schematic side view of a ninth embodiment of a multilayer capacitor, including external contacts. [Figure 17] This is a schematic side view of the metal sheet of the external contact of the ninth embodiment of a multilayer capacitor. [Modes for carrying out the invention]

[0115] Figure 1 shows a first embodiment of the multilayer capacitor 1. The figure is substantially limited to depicting the capacitor element 2. Further components, such as external contacts, are not shown in Figure 1.

[0116] The illustrated capacitor 1 is constructed similarly to the example of a multilayer capacitor according to the present invention, but does not include a coupling region and a stress relaxation region.

[0117] The capacitor element 2 includes a laminate comprising three first electrodes 3, three second electrodes 4, and a dielectric layer 5 disposed between or around these electrodes. The layers are arranged in an overlapping manner in a defined stacking direction.

[0118] The first electrode 3 and the second electrode 4 extend from the rectangular capacitor element 2 on two opposing sides. These sides are referred to as the first and second exit surfaces 6 / 7. The exit surfaces 6 / 7 are positioned perpendicular to the stacking direction.

[0119] At the outlet surface 6 / 7, each pair of electrodes is connected to one another via conductive external contacts 8. Each external contact 8 covers a large portion of the outlet surface 6 / 7. In other embodiments, the external contacts 8 may cover a smaller portion of the outlet surface 6 / 7 or the entire outlet surface 6 / 7.

[0120] Since electrodes 3 / 4 do not reach the opposing outlet surfaces 7 / 6, two distinct regions are created within the multilayer capacitor 1. In the central region of capacitor element 2, the first and second electrodes 3 / 4 overlap. These regions are called the active region 9A. In the regions adjacent to the outlet surfaces, only the first electrode 3 or only the second electrode 4 exists, respectively. These regions are called the passive region 9B.

[0121] Perpendicular to the exit surface 6 / 7 and layer plane On the two sides of the capacitor element 2 perpendicular to the polarity, there are adjacent regions without electrodes. These regions are similarly called passive regions 9B (see Figure 3).

[0122] The overlapping electrodes 3 / 4 function as a capacitor when a voltage is applied via the external contact 8. The voltage between the first and second electrodes 3 / 4 creates an electric field in the active region 9A of the multilayer capacitor 1.

[0123] It should be noted that, even in the active region 9A, the electric field does not need to exist throughout the entire stack height. Rather, the electric field acts only between electrodes with different electric polarizations, that is, for example, within the dielectric layer 5 located between the first and second electrodes 3 / 4. An electric field is also generated between the internal electrodes and the external contacts if the electric polarizations are different.

[0124] The dielectric layer 5 of this multilayer capacitor 1 is made of an antiferroelectric ceramic material. In an electric field, polarization of the domains in the crystalline structure of the ceramic is induced.

[0125] The electrodes are made of conductive materials such as copper, silver, nickel, palladium, or platinum.

[0126] Polarization causes lattice deformation in the ceramic. This lattice deformation generates mechanical stress within the multilayer capacitor 1. Due to the small stacking height, these mechanical stresses can be ignored in the first example.

[0127] The ceramic material in the examples is a perovskite ceramic. Perovskite ceramics typically have antiferroelectric properties. Depending on the ceramic composition corresponding to any one of claims 17 to 24, further advantageous properties for capacitors, such as high mechanical stability and a long service life, can be achieved.

[0128] The multilayer capacitor 1 shown in Figures 2a and 2b substantially corresponds to the multilayer capacitor 1 of the first example.

[0129] In the top view of Figure 3, perpendicular to the exit surface 6 / 7 and layer plane The sides 10 / 11, which are perpendicular to the capacitor element 2 and introduced at its tip, are also depicted.

[0130] In addition to the capacitor shown in Figure 1, the capacitors in Figures 2 and 3 have a second segment, which is arranged to overlap in the stacking direction. Each segment in the second embodiment corresponds to the segments in the first example.

[0131] The segments are coupled via coupling regions 12. Within the coupling regions 12, there exists a stress relaxation region 13. Therefore, the second embodiment is an embodiment of the claimed invention. The features and characteristics of the second example, corresponding to the multilayer capacitor 1 of the first example, will not be described again.

[0132] The coupling region 12 contains the same dielectric ceramic material as the dielectric layers of segments 2A and 2B of the capacitor element 2.

[0133] The coupling region 12 includes the bottom dielectric layer of the first segment 2A and the top dielectric layer of the second segment 2B, which are arranged overlapping in the stacking direction. There are no electrodes inside the coupling region 12.

[0134] At the edge of the coupling region, there is a continuous stress relaxation region 13 along the entire outer circumference of the capacitor element 2. The stress relaxation region 13 is located between the lowest dielectric layer of the first segment 2A and the uppermost dielectric layer of the second segment 2B.

[0135] The depth of the stress relaxation region 13, measured from the outer surface of the capacitor element 2 to the innermost part of the capacitor element 2, preferably corresponds to the stacking height of the segments.

[0136] Therefore, it can be ensured that the mechanical stress resulting from the deformation of the ceramic in the electric field does not accumulate beyond the segment, for example, leading to cracks in the material.

[0137] The stress relaxation region 13 encompasses all passive regions 9B of the multilayer capacitor 1. That is, the stress relaxation region 13 is arranged parallel to all sections within the coupling region 12 that contain only one type of electrode or do not contain an electrode. Furthermore, the stress relaxation region 13 partially extends into the active region 9A of the capacitor element 2.

[0138] Viewed from the stacking direction, the active region 9A has a rectangular shape, as shown in Figure 3. The passive region 9B forms a rectangular frame surrounding the active region 9A. The stress relaxation region 13 surrounds the passive region 9B and further forms a rectangular frame that partially overlaps with the active region 9A.

[0139] The stress relaxation region 13 is a region in which the stacked dielectric layers 5 are not firmly bonded to each other but only partially.

[0140] To manufacture such a multilayer capacitor 1 according to the second embodiment, a ceramic green sheet containing a perovskite-type material is prepared for forming a dielectric layer 5. A first paste containing an organic material is printed on the top green sheet of the second segment 2B.

[0141] A second metal paste for forming electrodes is printed onto a desired area on another green sheet. The green sheets are arranged to form a single laminate, which is then sintered.

[0142] The first organic paste is formed such that the co-sintering of the dielectric layer 5 is completely or partially prevented in the area where the first paste is applied, and as a result, a stress relaxation region 13 is formed therein.

[0143] Figures 4 and 5 show further embodiments of the multilayer capacitor 1 according to the present invention.

[0144] The essential features of Example 3 correspond to those of Example 2. These features will not be explained again.

[0145] In this example, the stress relaxation region 13 includes an outer section 13A along the outer circumference of the capacitor element 2, as well as an inner section 13B extending between the outer surfaces parallel to the exit surfaces 6 / 7 of the capacitor element 2. The width of this inner section can be arbitrarily varied. In this embodiment, the width of the inner section exceeds the width of the outer section.

[0146] The inner section of the stress relaxation region 13 is positioned perfectly parallel to the active region 9A of the multilayer capacitor 1.

[0147] Such additional inner sections of the stress relaxation region 13 can effectively avoid the accumulation of mechanical stresses within the capacitor 1, even when the dimensions of individual layers are large or the stacking height is high.

[0148] The stress relaxation region 13, when viewed in the stacking direction, has the shape of a rectangular frame with its long sides connected by crossbeams. The crossbeams correspond to the inner section of the stress relaxation region 13.

[0149] It should be noted that in the illustrated structure of the third embodiment of capacitor 1, undesirable movement of charged particles from the outside to the inside of the capacitor may occur. These charged particles may be, for example, protons present on the outer surface of capacitor 1 due to moisture. This is because an electric field may be formed in the outermost dielectric layer 5A of capacitor 1 between the uppermost second electrode 4A and the first external contact. This effect may be further amplified if the external contact also covers a portion of the upper surface 1A of capacitor 1 due to, for example, errors during coating.

[0150] Figures 6 and 7 show a fourth embodiment of the multilayer capacitor 1, whose features partially coincide with those of the previously described embodiment. These features will not be explained again.

[0151] Unlike the previously described embodiments, the multilayer capacitor 1 in the fourth embodiment includes a third electrode 14 in addition to the first and second electrodes. The third electrode 14 is an internal, so-called floating electrode that is not adjacent to the outer surface of the capacitor element 2. Therefore, the third electrode 14 is not contacted from the outside.

[0152] Unlike the previously described embodiment, the first and second electrodes 3 / 4 are located in the same layer plane, but are further separated by a dielectric section.

[0153] A layer plane containing a third electrode 14 is positioned between the layer planes containing the first and second electrodes.

[0154] In this way, a multilayer capacitor 1 is formed, which includes two capacitors connected in series. These are a first capacitor 1B formed between the first and third electrodes, and a second capacitor 1C formed between the third and second electrodes.

[0155] A passive region 9B exists between the two active regions 9A of capacitors 1B and 1C, and only the third electrode 14 exists in this passive region; therefore, different types of electrodes do not overlap.

[0156] In this embodiment, the stress relaxation region 13 is embodied in the same manner as in the third embodiment. Therefore, the stress relaxation region 13 includes an outer section along the outer circumference of the capacitor element 2 and an inner section.

[0157] The additional inner section further covers the entire passive region 9B of capacitor element 2 with a stress relaxation region 13. Furthermore, the stress relaxation region 13 extends to the areas outside the two active regions 9A of capacitors 1B and 1C.

[0158] An advantage of the fourth embodiment described above is that no electric field is generated between the outermost first or second electrodes 3A / 4A of each segment 2A / 2B of capacitor 1 and the adjacent external contacts, because they each have the same electric polarization. Therefore, the individual layers inside the active region 9A also do not have an electric field.

[0159] Therefore, the undesirable movement of charged particles from the outside into the inside of the capacitor 1 can be avoided. Such charged particles may be, for example, protons that may be present on the outer surface of the capacitor 1 due to moisture.

[0160] Figures 8 and 9 show a fifth example of the multilayer capacitor 1. Features corresponding to the previously described embodiments will not be explained again.

[0161] The illustrated multilayer capacitor 1 also includes only first and second electrodes. However, the electrodes have different dimensions. Within the first layer plane, the first and second electrodes are formed facing each other and are separated by a dielectric section. These first layer planes are embodied similarly to the fourth embodiment.

[0162] The first layer planes each form the first and last layer planes of each segment. Since the first and second electrodes 3B and 4B each have the same electric polarization as the adjacent external contacts, no electric field is generated here in the outer section of segment 2A / 2B or between the two segments.

[0163] Furthermore, unlike electrodes 3A and 4A, electrodes 3B and 4B are not adjacent to electrodes with opposite electric polarization within capacitor 1. Therefore, an electric field is not formed over a relatively large area. Consequently, the individual layers within the active region 9A also do not have an electric field.

[0164] An advantage of the above-described embodiment is that no electric field is generated between the outermost first or second electrodes 3A / 4A / 3B / 4B of each segment 2A / 2B of the capacitor 1 and the adjacent external contacts, because they each have the same electric polarization. Therefore, the undesirable movement of charged particles from the outside into the inside of the capacitor 1 can be avoided.

[0165] This has the advantage of greater stability against material changes induced by moisture.

[0166] The distance between the first and second electrodes in the first layer plane corresponds to at least the thickness of the dielectric layer 5 in the stacking direction. Preferably, the distance is 1.5 to 3 times this thickness. This makes it possible to avoid, for example, direct current from the first electrode 3B to the opposing second electrode 4A.

[0167] This spacing determines the maximum dimension of the electrodes in the first layer plane. The minimum dimension of the same electrode corresponds to the depth of the passive region 9B along the outer circumference of the capacitor. Preferably, the electrode depth corresponds to at least twice this depth.

[0168] In addition, there is a second layer plane where only the first electrode 3 exists, and a third layer plane where only the second electrode 4 exists. In these layer planes, each electrode extends to approximately the opposite exit surface. The distance from the electrode to the opposite exit surface corresponds to the depth of the passive region along the outer periphery of the layer plane. These layer planes are fabricated in the same manner as in the third embodiment.

[0169] The second and third layer planes are arranged in an alternating overlapping configuration. A dielectric layer 5 is located between them.

[0170] The bonding region 12 and the stress relaxation region 13 are embodied in the same manner as in the example described above. The stress relaxation region 13 includes an outer frame-like section and an inner cross-beam-like section.

[0171] The outer passive region 9B and a portion of the inner active region 9A are covered by a stress relaxation region 13, as illustrated in Figure 5.

[0172] Unlike the fourth embodiment, in this case, there is no passive region 9B in the center of the capacitor element 2.

[0173] Figures 10 and 11 show a sixth embodiment of the multilayer capacitor 1. The individual segments are embodied in the same manner as in the fourth embodiment. However, the sixth embodiment differs from the fourth embodiment in the form of the stress relaxation region 13.

[0174] In the fourth embodiment, in addition to the outer section of the stress relaxation region 13A, there is only a single section of the stress relaxation region 13B inside the capacitor, whereas the sixth embodiment has a number of different sections 13B inside. All of these sections 13B are connected to each other or to the outer section 13A of the stress relaxation region. They are preferably embodied in such a way that uniform relaxation of mechanical stress is possible. The inner sections 13B of the stress relaxation region can be arranged parallel to each other or intersect. The number of sections, as well as their shape and dimensions, can be arbitrarily varied.

[0175] Figures 12 and 13 show further embodiments of the multilayer capacitor 1. Embodiment 7 substantially corresponds to Embodiment 4. It includes first, second, and third electrodes 3, 4, and 14.

[0176] Unlike the fourth embodiment, the seventh embodiment further includes fourth, fifth, and sixth electrodes 15, 16, and 17. These are dummy electrodes that fill the passive region 9B without forming an active region 9A themselves.

[0177] The fourth and fifth electrodes 15 and 16 are located in the passive region outside the capacitor element 2. They are positioned near the external contacts and can make contact with them. The fourth and fifth electrodes do not generate an electric field because they only overlap with electrodes of the same polarity.

[0178] The fourth electrode 15, which is in contact with the first external contact, overlaps only with the fourth electrode 15 or the first electrode 3.

[0179] The fifth electrode 16, which is in contact with the second external contact, overlaps only with the fifth electrode 16 or the second electrode 4.

[0180] The sixth electrode 17 is located in the center of the capacitor element 2 between the first and second electrodes 3 and 4, and is positioned within the same layer plane as the first and second electrodes. The sixth electrode 17 overlaps only with the further sixth electrode 17 and the third electrode 14. Therefore, since there is no overlap of different electrodes with different polarities in this region, this is also a passive region 9B of the capacitor element 2. In this embodiment, the sixth electrode is positioned to overlap precisely in the stacking direction.

[0181] The distance from the dummy electrode to the active electrode is perpendicular to the electric field direction and corresponds to at least the thickness of the dielectric layer 5, preferably 1.5 to 3 times the thickness of the dielectric layer 5.

[0182] By using dummy electrodes, the mechanical stress and strain (Pressverzug) that typically occur between the region with electrodes and the region without electrodes are reduced.

[0183] Therefore, by using dummy electrodes and stress relaxation regions, mechanical stress within the multilayer capacitor 1 can be minimized, improving the robustness of the capacitor. This allows for the optimization of the thermomechanical and electrical load capacity of the multilayer capacitor 1.

[0184] Figures 14 and 15 show an eighth embodiment of the multilayer capacitor 1, which is substantially a combination of the fifth and seventh embodiments.

[0185] In addition to the first and second electrodes 3 and 4, in this embodiment, fourth and fifth electrodes 15 and 16 are provided along the outer circumference of the electrode layer. The fourth and fifth electrodes 15 and 16 are also located in the same layer as the first and second electrodes 3 and 4.

[0186] The fourth and fifth electrodes 15 and 16 are formed as dummy electrodes, similar to Example 7. They each overlap only with electrodes of the same polarity. The distance of the fourth and fifth electrodes 15 and 16 to the active electrode is preferably 1.5 to 3 times the thickness of the dielectric layer 5, but at least the thickness of the dielectric layer 5, in order to avoid current between the active electrode and the dummy electrode facing it.

[0187] Therefore, the electrodes 15A and 16B of the outermost segment layers serve the same purpose as the electrodes 3A and 4B of the fifth embodiment, but are embodied at the minimum appropriate depth.

[0188] Since the layers containing the first and fourth electrodes or the second and fifth electrodes always have the same electrode shape, or the electrodes are simply arranged in a mirror image of each other, the same stencil can be used each time to print the electrode layers.

[0189] Figure 16 shows a ninth embodiment of the multilayer capacitor 1. The capacitor element 2 can be implemented in accordance with one of the examples described above.

[0190] An external contact 8 is further coated on the exit surfaces of electrodes 6 and 7. The external contact 8 includes multiple layers. Immediately above the exit surfaces 6 / 7, a sputtered layer 8A is coated, covering the entire exit surfaces 6 / 7. The sputtered layer 8A includes three layers consisting of chromium, nickel, and silver.

[0191] The sputtered layer 8A described above allows all the first electrodes or all the second electrodes to be electrically connected to each other and therefore connected in parallel.

[0192] On top of the sputtered layer 8A, a metal sheet 18 for external contact is coated with a sintered silver layer 19.

[0193] The sintered silver layer 19 covering the entire sputtered layer 8A bundles the sputtered layer 8A together when the capacitor element 2 deforms, preventing, for example, the sputtered layer 8A from peeling off.

[0194] In this embodiment, the silver layer 19 has a thickness of approximately 20 μm to 30 μm. The porosity of the silver in the layer is 35%.

[0195] The silver layer 19 further fixes the metal sheet 18 to the sputtered layer 8A. Therefore, soldering is unnecessary. For this purpose, silver is applied to the sputtered layer, and the metal sheet 18 is placed immediately on top of it. Only after the metal sheet 18 is placed is the silver layer 19 sintered.

[0196] Due to its high conductivity, the silver layer 19 further enables good electrical connection of the metal sheet 18 to the sputtered layer 8A.

[0197] To improve the adhesion of the metal sheet 18 to the silver layer 19, the surface of the metal sheet 18 is silver-plated in this embodiment. Preferably, the surface is electrically silver-plated. Thus, an electroplated silver layer 20 is formed on the surface of the metal sheet 18, positioned between the metal sheet 18 and the silver layer 19. The thickness of the electroplated silver layer 20 is 5 μm to 10 μm.

[0198] In this embodiment, the metal sheet 18 of the external contact includes two copper layers 18B and an Invar layer 18A placed between them, as shown in the detailed view of Figure 17. Instead of Invar, the intermediate layer may include another iron-nickel alloy or iron-nickel-cobalt alloy.

[0199] The central Invar layer provides the metal sheet 18 with the necessary mechanical strength. The small thermal expansion of the Invar prevents the generation of mechanical stress during temperature changes. Therefore, crack formation in the external contacts of the capacitor or in the ceramic can be effectively prevented.

[0200] An outer copper layer 18B is applied to the Invar layer 18A, preferably by being spread with a roller. The copper layer 18B has high thermal conductivity and high electrical conductivity. Therefore, an external contact can be provided that has a small coefficient of thermal expansion and thus high mechanical stability on the one hand, and high thermal conductivity and electrical conductivity on the other hand.

[0201] The copper layer 18B is coated on both sides of the Invar layer 18A with equal thickness. By evenly coating both sides with copper, the formation of a bimetallic strip, which has undesirable properties for this application, is avoided. The copper-Invar-copper layer thickness ratio is preferably 1:3:1. In this example, a metal sheet with a total thickness of 0.15 mm is used. The thickness of the Invar layer 18A is 90 μm, and the thickness of the copper layer 18B is 30 μm each.

[0202] By substantially using silver and copper in the aforementioned layer structure of the external contact, an external contact with high electrical and thermal conductivity is achieved.

[0203] The aforementioned layer structure further allows for adaptation of the thermal expansion coefficient, enhancing thermomechanical load capacity and thus durability, and improving maximum current carrying capacity. This results in optimized fault tolerance during operation.

[0204] Capacitors with the above characteristics are suitable for use as DC link capacitors or snubber capacitors. Their small parasitic capacitance, particularly low equivalent series inductance, and the ability to mount the capacitor close to the semiconductor allow for a smaller rectifier circuit. This allows for good attenuation of induced overvoltages during the switch-off process. Due to the capacitor's characteristics, it is possible to omit an additional snubber capacitor in some applications when used as a DC link capacitor.

[0205] A further application of the aforementioned capacitors is as filter capacitors. Due to their high-frequency characteristics, interfering signals can be effectively attenuated and filtered up to the MHz range, far beyond the operating frequency of the power converter.

[0206] In further embodiments not shown, a copper layer is applied on top of the silver layer 19 instead of the metal sheet 18. In this example, the copper layer has a meandering grid-like geometric shape. The copper layer is also silver-plated. The silver plating is carried out by electroplating. The copper layer is sintered directly together with the silver layer. [Explanation of Symbols]

[0207] 1. Multilayer capacitor Top surface of a 1A capacitor 1B First capacitor 1C Second capacitor 2 Capacitor elements 2A, 2B segments 3,3A,3B First electrode 4,4A,4B Second electrode 5. Dielectric layer 6. First exit surface 7. Second exit surface 8 External Contacts 8A Sputtering layer 9A Active Area 9B Passive Area 10,11 Side view 12 Combined area 13. Stress relaxation region 13A Outer section of the stress relaxation region 13B Inner section of the stress relaxation region 14. Third electrode 15A, 15B: Fourth electrode 16A, 16B Fifth electrode 17. The sixth electrode 18 Metal sheet 18A Invar layer 18B copper layer 19 Silver layer 20 Electroplated silver layer

Claims

1. A multilayer capacitor (1) comprising a plurality of capacitor elements (2) each having at least two segments (2A, 2B), each segment comprising a dielectric layer (5) made of ceramic and an electrode layer disposed between them, and comprising a plurality of layer planes arranged in a layer order and overlapping, the electrode layer comprising different electrodes including at least first and second electrodes (3, 4), the different electrodes overlapping in the active region (9A), and the different electrodes not overlapping in the passive region (9B), and the plurality of segments A multilayer capacitor in which the two segments are arranged overlapping in the stacking direction, the outermost dielectric layer of the two segments forms a coupling region (12), in which the segments are firmly coupled to each other parallel to the layer plane, the coupling region includes a stress relaxation region (13), the stress relaxation region occupies at least the entire passive region of the multilayer capacitor, and the plurality of capacitor elements (2) are coupled to each other at the sides (10, 11) of the capacitor elements (2) perpendicular to the layer plane and the external contact (8).

2. The multilayer capacitor according to claim 1, wherein the stress relaxation region is formed as a region parallel to the layer plane between the segments, and within the layer plane, the segments are not firmly bonded to one another.

3. The multilayer capacitor according to claim 1 or 2, wherein the stress relaxation region is formed as a gap between the segments.

4. The multilayer capacitor according to claim 1 or 2, wherein the stress relaxation region includes a material whose elastic modulus is different from that of the dielectric layer.

5. The multilayer capacitor according to any one of claims 1 to 4, wherein the stress relaxation region is formed in at least the entire region (13A) adjacent to the outer surface of the capacitor element.

6. The multilayer capacitor according to any one of claims 1 to 5, wherein the stress relaxation region is formed at least partially in the active region.

7. The multilayer capacitor according to claim 5, or claim 6, incorporating claim 5, wherein the stress relaxation region has at least one section (13B) that is not adjacent to the outer surface of the capacitor element.

8. The multilayer capacitor according to any one of claims 1 to 7, wherein the coupling region includes a plurality of stress relaxation regions bounded by each other.

9. The multilayer capacitor according to claim 8, wherein the stress relaxation regions bounded by each other are not, at least partially, adjacent to the outer surface of the capacitor element.

10. The multilayer capacitor according to any one of claims 1 to 9, wherein the first and second electrodes overlap at least partially.

11. The electrode comprises copper or silver, as described in any one of claims 1 to 10, in the multilayer capacitor.

12. A multilayer capacitor according to any one of claims 1 to 11, wherein each segment comprises at least three different types of electrode layers, the first and second electrodes are formed opposite each other in a first electrode layer and separated by a dielectric section, only the first electrode is formed in the second electrode layer, and only the second electrode is formed in the third electrode layer, and the first electrode layer each forms the outermost electrode layer in the stacking direction of each segment.

13. A multilayer capacitor according to any one of claims 1 to 12, comprising further electrodes (15, 16, 17), wherein the further electrodes are located in the passive region of the multilayer capacitor and do not overlap with electrodes of different polarities.

14. Furthermore, two separate external contacts (8) for contact between the first and second electrodes are coated on the exit surfaces (6, 7) on the outer surface of the capacitor element from which electrodes protrude from the capacitor element, according to any one of claims 1 to 13.

15. The multilayer capacitor according to claim 14, comprising at least one third electrode (14) that is not in contact with any of the external contacts, wherein the third electrode overlaps with the first and second electrodes.

16. The multilayer capacitor according to claim 14 or 15, wherein the external contact includes a multilayer sputtered layer (8A), the sputtered layer (8A) includes a layer made of chromium, nickel, and at least one of silver or gold, and the layers are coated on the outlet surface in this order.

17. The multilayer capacitor according to claim 16, wherein the external contact includes a metal sheet (18) mounted on the sputtered layer by soldering.

18. The multilayer capacitor according to claim 16, wherein the external contact includes a metal sheet (18) mounted on the sputtered layer by a sintered silver layer (19).

19. The multilayer capacitor according to claim 17 or 18, wherein the metal sheet comprises two copper layers (18B) and an Invar layer (18A) disposed between them.

20. The multilayer capacitor according to any one of claims 17 to 19, wherein the metal sheet includes a copper layer having a meandering geometric shape.

21. The multilayer capacitor according to any one of claims 1 to 20, wherein the ceramic is an antiferroelectric.

22. The multilayer capacitor according to any one of claims 1 to 21, wherein the ceramic comprises lead zirconate titanate.

23. The multilayer capacitor according to any one of claims 1 to 22, wherein the ceramic comprises strontium sodium titanate.

24. The multilayer capacitor according to any one of claims 1 to 23, wherein the multilayer capacitor is used as a DC link capacitor and / or a snubber capacitor and / or a filter capacitor.

25. The multilayer capacitor according to any one of claims 1 to 24, wherein the coupling region (12) includes a plurality of stress relaxation regions (13B) that intersect but are not at least partially adjacent to the outer surface of the capacitor element (2).

26. The multilayer capacitor according to any one of claims 1 to 25, wherein dummy electrodes (15, 16, 17) that do not overlap with electrodes of different polarities are arranged in the passive region (9B) within the same layer plane as the first and second electrodes (3, 4).

27. A multilayer capacitor (1) comprising a capacitor element (2) having at least two segments (2A, 2B), each segment comprising a dielectric layer (5) made of ceramic and an electrode layer disposed between them, and comprising a plurality of layer planes arranged in a layered order and overlapping, the electrode layer comprising different electrodes including at least first and second electrodes (3, 4), the different electrodes overlapping in the active region (9A), and the different electrodes not overlapping in the passive region (9B), and the plurality of segments, A multilayer capacitor in which the two segments are arranged overlapping in the stacking direction, the outermost dielectric layer of the two segments forms a coupling region (12), in which the segments are firmly coupled to each other parallel to the layer plane, the coupling region includes a plurality of stress relaxation regions (13), the stress relaxation regions occupy at least the entire passive region of the multilayer capacitor, the stress relaxation regions (13) are not at least partially adjacent to the outer surface of the capacitor element (2), and the stress relaxation regions (13) intersect.

28. A multilayer capacitor (1) comprising a capacitor element (2) having at least two segments (2A, 2B), each segment comprising a dielectric layer (5) made of ceramic and an electrode layer disposed between them, and comprising a plurality of layer planes arranged in a layer order and overlapping, the electrode layer comprising different electrodes including at least first and second electrodes (3, 4), the different electrodes overlapping in the active region (9A) and the different electrodes not overlapping in the passive region (9B), the plurality of segments arranged in an overlapping direction in the stacking direction, the outermost dielectric layer of the two segments forming a coupling region (12), in the coupling region (12) the segments are firmly coupled to each other parallel to the layer plane, the coupling region comprising a stress relaxation region (13), the stress relaxation region occupying at least the entire passive region of the multilayer capacitor, and the stress relaxation region comprising a material whose elastic modulus is different from that of the dielectric layer.

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