Sampling phase-locked loop

Abstract

In a particular aspect, the sampler includes a sampling capacitor, a pre-charge switch coupled to the sampling capacitor, one or more discharge circuits coupled to the sampling capacitor, and a reference voltage circuit coupled to the sampling capacitor, The reference voltage circuit is configured to generate a reference voltage based on a supply voltage and generate a voltage difference between the voltage on the sampling capacitor and the reference voltage.

Description

[Technical Field]

[0001] Cross-reference of related applications

[0001] This application claims priority and benefit to Nonprovisional Application No. 17 / 340,914, filed with the United States Patent and Trademark Office on 7 June 2021 and issued by the United States Patent and Trademark Office on 15 March 2022 as Patent No. 11,277,140, ​​the entire contents of which Nonprovisional Application are incorporated herein by reference as if it were described in its entirety below, and for all applicable purposes. Background of the Invention

[0002] field

[0002] The aspects of this disclosure relate in general to phase-locked loops (PLLs), and more particularly to sampling PLLs. [Background technology]

[0003]

[0003] A phase-locked loop (PLL) can be used to generate a signal having a desired frequency by multiplying the frequency of a reference signal by a corresponding amount. For example, a PLL can be used in a wireless device to generate a local oscillator signal having a desired frequency. [Overview of the project]

[0004]

[0004] Hereafter, a simplified overview of one or more implementations is presented to provide a basic understanding of such implementations. This “Outline of the Invention” is not intended to be a comprehensive overview of all conceivable implementations, nor is it intended to identify the main or important elements of all implementations, nor to specify the scope of any or all implementations. Its sole purpose is to present in a simplified form several concepts of one or more implementations as an introduction to the “Modes for Carrying Out the Invention” that will be presented later.

[0005]

[0005] The first aspect relates to a sampler. The sampler includes a sampling capacitor, a precharge switch coupled to the sampling capacitor, one or more discharge circuits coupled to the sampling capacitor, and a reference voltage circuit coupled to the sampling capacitor. The reference voltage circuit is configured to generate a reference voltage based on a supply voltage and to generate a voltage difference between the voltage on the sampling capacitor and the reference voltage.

[0006]

[0006] A second aspect relates to an apparatus. This apparatus includes a sampling capacitor, a precharge switch coupled to the sampling capacitor, one or more discharge circuits coupled to the sampling capacitor, and a reference voltage circuit coupled to the sampling capacitor. The reference voltage circuit includes a first capacitor, a second capacitor, a first switch coupled between the first and second capacitors, a second switch coupled in parallel with the second capacitor, and a difference circuit coupled to the sampling capacitor and the first capacitor.

[0007]

[0007] A third aspect relates to a sampling method. This method includes charging a sampling capacitor to a supply voltage, discharging a portion of the charge on the sampling capacitor based on a phase error to generate a sampling voltage, generating a reference voltage based on the supply voltage, and generating a difference voltage between the sampling voltage and the reference voltage.

[0008]

[0008] A fourth aspect relates to an apparatus for sampling. The apparatus includes means for charging a sampling capacitor to a supply voltage, means for discharging a portion of the charge on the sampling capacitor based on a phase error in order to generate a sampling voltage, means for generating a reference voltage based on the supply voltage, and means for generating a difference voltage between the sampling voltage and the reference voltage. [Brief explanation of the drawing]

[0009] [Figure 1]

[0009] An embodiment of a phase-locked loop (PLL) according to a particular aspect of the present disclosure is shown. [Figure 2]

[0010] This disclosure provides an exemplary implementation of a loop filter according to a specific aspect of this disclosure. [Figure 3]

[0011] This disclosure provides exemplary implementations of the sampler according to specific aspects of this disclosure. [Figure 4]

[0012] This disclosure provides an exemplary implementation of a sampler that uses phase interpolation, according to a particular aspect of this disclosure. [Figure 5]

[0013] An embodiment of a reference voltage circuit according to a particular aspect of this disclosure is shown. [Figure 6]

[0014] Another embodiment of the reference voltage circuit according to a particular aspect of this disclosure is shown. [Figure 7]

[0015] This disclosure illustrates exemplary implementations of switches within a sampler according to specific aspects of this disclosure. [Figure 8]

[0016] This is a timing diagram showing exemplary signals in the exemplary sampler shown in Figure 7, according to a particular aspect of this disclosure. [Figure 9]

[0017] This disclosure illustrates exemplary implementations of a phase detector according to specific aspects of this disclosure. [Figure 10]

[0018] An exemplary wireless device is shown according to a particular aspect of this disclosure. [Figure 11]

[0019] This is a diagram of an environment including electronic devices, including transceivers, according to a particular aspect of this disclosure. [Figure 12]

[0020] This flowchart shows a sampling method according to a particular aspect of this disclosure. [Modes for carrying out the invention]

[0010]

[0021] In connection with the accompanying drawings, the "Modes for Carrying Out the Invention" described below are intended as descriptions of various configurations and are not intended to represent the only configuration capable of practicing the concepts described herein. The "Modes for Carrying Out the Invention" include specific details aimed at providing a thorough understanding of the various concepts. However, it will be apparent to those skilled in the art that these concepts can be practiced without these specific details. In some cases, well-known structures and components are shown in block diagram form to avoid obscuring such concepts.

[0011]

[0022] FIG. 1 shows an embodiment of a phase-locked loop (PLL) 110 according to a particular aspect of the present disclosure. The PLL 110 can be used, for example, in a wireless device to generate a local oscillator signal (e.g., for frequency upconversion and / or frequency downconversion). In this embodiment, the PLL 110 includes a phase detector 120, a sampler 130, a loop filter 135, a voltage controlled oscillator (VCO) 140, and a frequency divider 150. The phase detector 120 may also be referred to as a phase frequency detector (PFD), a phase comparator, or by another term.

[0012]

[0023] The phase detector 120 has a first input 122, a second input 124, and an output 126. The first input 122 is configured to receive a reference signal (labeled "ref"). The reference signal (e.g., a reference clock signal) can come from a crystal oscillator (not shown) or another source. The sampler 130 has an input 132 coupled to the output 126 of the phase detector 120 and an output 134. The loop filter 135 is coupled between the output 134 of the sampler 130 and the control input 142 of the VCO 140. As further discussed below, the VCO 140 has a frequency ("f" VCOconfigured to generate an output signal having the label ")". This output signal is output at the output 144 of the VCO 140, which is coupled to the output 112 of the PLL 110. Therefore, in this embodiment, the output signal of the VCO 140 provides the output signal of the PLL 110.

[0013]

[0024] The divider 150 has an input 152 and an output 154. The input 152 of the divider 150 is coupled to the output 144 of the VCO 140, and the output 154 of the divider 150 is coupled to the second input 124 of the phase detector 120. Therefore, in this embodiment, the output signal of the VCO 140 is fed back to the second input 124 of the phase detector 120 via the feedback loop 155 through the divider 150. In one embodiment, the divider 150 is configured to divide the frequency of the output signal of the VCO 140 by a division ratio N to generate a feedback signal (labeled "fb"). Therefore, in this embodiment, the feedback signal has a frequency approximately equal to f VCO / N. The feedback signal is output at the output 154 of the divider 150 and input to the second input 124 of the phase detector 120.

[0014]

[0025] During operation, the phase detector 120 receives a reference signal at the first input 122 and a feedback signal at the second input 124. The phase detector 120 is configured to detect the phase error between the reference signal and the feedback signal, generate a phase error signal indicating the detected phase error, and output the phase error signal at the output 126. In some implementations, the phase error signal includes pulses having a width that is a function of the detected phase error. In one embodiment, the detected phase error can be represented as the time error (i.e., time difference) between an edge (e.g., rising edge or falling edge) of the feedback signal and an edge (e.g., rising edge or falling edge) of the reference signal. In this embodiment, the width of the pulse is equal to or proportional to the time error between the edge of the feedback signal and the edge of the reference signal.

[0015]

[0026] The sampler 130 is configured to sample the phase error signal from the phase detector 120 and output the sampled phase error signal to the loop filter 135. The sampled phase error signal can be a voltage or a current. The loop filter 135 filters the sampled phase error signal into a voltage that is input to the control input 142 of the VCO 140, thereby controlling the output frequency of the VCO 140.

[0016]

[0027] The feedback loop 155 of the PLL 110 causes the phase detector 120, sampler 130, and loop filter 135 to adjust the voltage at the control input 142 of the VCO 140 in a direction that reduces the phase error between the feedback signal and the reference signal. When the PLL 110 is locked, the output frequency of the VCO 140 is approximately equal to the frequency of the reference signal multiplied by the division ratio N of the frequency divider 150. In other words, the output frequency is given by the following equation: f VCO =N·f ref (1) Here, f ref is the reference frequency (i.e., the frequency of the reference signal). Therefore, in this embodiment, the output frequency of VCO140 is a multiple of the reference frequency and can be set to a desired frequency by appropriately setting the division ratio N of the frequency divider 150 based on equation (1).

[0017]

[0028] In one embodiment, the frequency division ratio N of the frequency divider 150 is an integer of 2 or more. In this embodiment, the output frequency of the VCO 140 is an integer multiple of the reference frequency.

[0018]

[0029] In some implementations, the PLL 110 further includes a delta-sigma modulator (DSM) 160 to achieve a non-integer division ratio using a frequency divider 150. As used herein, the term “non-integer division ratio” may refer to a division ratio that includes a fractional part. In this embodiment, the DSM 160 has an input 162 and an output 164. The output 164 of the DSM 160 is coupled to a control input 156 of the frequency divider 150. In this embodiment, the frequency divider 150 is configured to set the division ratio N of the frequency divider 150 to one of a plurality of integer values ​​based on a division ratio control signal received from the DSM 160 via the control input 156.

[0019]

[0030] During operation, the DSM160 is configured to receive a frequency control signal (e.g., a frequency control word) indicating a desired non-integer division value. The DSM160 then modulates the division ratio of the divider 150 over multiple cycles of the reference signal such that the average of the division ratios is approximately equal to the desired non-integer division value. The DSM160 can modulate the division ratio by using the division ratio control signal to vary the integer value of the division ratio over multiple cycles of the reference signal such that the average of the division ratios is approximately equal to the desired non-integer division value. For example, the DSM160 can achieve an average non-integer division value of 6.25 over four cycles of the reference signal by setting the division ratio of the divider 150 to 6 for three of the four cycles and to 7 for one of the four cycles. The DSM160 can be implemented using a first-order DSM, a second-order multi-state noise shaping (MASH) DSM, a third-order MASH DSM, or another type of DSM. In this embodiment, the frequency divider 150 and DSM160 implement a "fractional N-type frequency divider".

[0020]

[0031] Figure 2 shows an exemplary implementation of the loop filter 135 in a particular embodiment. In this embodiment, the loop filter 135 includes a capacitor 210 and an integration path 220. Furthermore, the control input 142 of the VCO 140 includes a first control input 142-1 and a second control input 142-2.

[0021]

[0032] In this embodiment, the first terminal 212 of capacitor 210 is coupled to the node between the output 134 of sampler 130 and the first control input 142-1 of VCO 140, and the second terminal 214 of capacitor 210 is coupled to ground (or some reference voltage configured to function as ground). The voltage on capacitor 210 (labeled "vtune") is input to the first control input 142-1 of VCO 140 to adjust the output frequency of VCO 140.

[0022]

[0033] The integration path 220 is coupled between the output 134 of the sampler 130 and the second control input 142-2 of the VCO 140. The integration path 220 is configured to integrate the voltage vtune and, based on that integral, further adjust the output frequency of the VCO 140 via the second control input 142-2. In the embodiment shown in Figure 2, the integration path 220 includes an analog-to-digital converter (ADC) 225 and an accumulator 230. The ADC 225 is configured to convert the voltage vtune into a digital signal, and the accumulator 230 is configured to integrate that digital signal. Therefore, in this embodiment, the integration path 220 performs integration in the digital domain.

[0023]

[0034] However, it should be understood that the loop filter 135 is not limited to the exemplary implementation shown in Figure 2. For example, in other implementations, the loop filter 135 may include a low-pass filter (e.g., a resistor-capacitor (RC) filter) coupled to the output 134 of the sampler 130.

[0024]

[0035] In one embodiment, the VCO140 may include an inductor-capacitor (LC) tank (not shown), in which case the output frequency of the VCO140 is adjusted by adjusting the capacitance of the LC tank. In this embodiment, the LC tank may include one or more capacitors (e.g., varactors) whose capacitance is adjusted by a voltage vtune via a first control input 142-1, and one or more capacitors (e.g., a capacitor bank) whose capacitance is adjusted by the output of an integration path 220 via a second control input 142-2. However, it should be understood that the VCO140 is not limited to this embodiment, and the VCO140 can be implemented using other types of VCO circuits.

[0025]

[0036] Figure 3 shows an exemplary implementation of the sampler 130 in a particular embodiment. In this embodiment, the sampler 130 includes a discharge circuit 308, a sampling capacitor 320, a precharge switch 325, and a sampling switch 330.

[0026]

[0037] As will be discussed further below, the discharge circuit 308 is configured to discharge the sampling capacitor 320 based on the phase error signal from the phase detector 120 to generate a sampled voltage (labeled "Vs") that indicates the phase error between the reference signal and the feedback signal. In the embodiment shown in Figure 3, the discharge circuit 308 includes a transistor 310 and a resistor 315. The gate of the transistor 310 is coupled to the input 132 of the sampler 130, and the resistor 315 is coupled between the drain of the transistor 310 and the first terminal 322 of the sampling capacitor 320. In this embodiment, the source of the transistor 310 is coupled to ground, and the second terminal 324 of the sampling capacitor 320 is coupled to ground. However, it should be understood that the sampler 130 is not limited to the embodiment shown in Figure 3. In other implementations, the resistor 315 can be coupled between the source of the transistor 310 and the first terminal 322 of the sampling capacitor 320, and the drain of the transistor 310 can be coupled to ground. Although Figure 3 shows a single discharge circuit 308, the sampler 130 may include multiple discharge circuits connected in parallel, and it should be understood that in this case, each discharge circuit may include its own resistor and its own transistor.

[0027]

[0038] A precharge switch 325 is coupled between the output 344 of the voltage regulator 340 and the first terminal 322 of the sampling capacitor 320, and a sampling switch 330 is coupled between the first terminal 322 of the sampling capacitor 320 and the output 134 of the sampler 130. In this embodiment, the voltage regulator 340 has an input 342 coupled to a power rail 350. The voltage regulator 340 is configured to generate a regulated supply voltage Vdd at the output 344 of the voltage regulator 340 from the voltage on the power rail 350. Therefore, in this embodiment, the supply voltage Vdd is supplied to the sampler 130. The voltage regulator 340 can be implemented using a low-dropout (LDO) regulator, a switching regulator, or another type of voltage regulator.

[0028]

[0039] In this embodiment, the precharge switch 325 and the sampling switch 330 are controlled by a controller 360. In this regard, the controller 360 is coupled to the control input 327 of the precharge switch 325 and to the control input 332 of the sampling switch 330. In this embodiment, the controller 360 is configured to control the on / off state of the precharge switch 325 via the control input 327 and to control the on / off state of the sampling switch 330 via the control input 332. The precharge switch 325 can be implemented using a transistor, transmission gate, or other type of switch having a gate coupled to the control input 327. Similarly, the sampling switch 330 can be implemented using a transistor, transmission gate, or other type of switch having a gate coupled to the control input 332.

[0029]

[0040] To sample the phase error signal, the sampling capacitor 320 is first precharged to the supply voltage Vdd during the precharge phase. To achieve this, the controller 360 enables the sampling capacitor 320 to be precharged to the supply voltage Vdd via the precharge switch 325 by turning on the precharge switch 325. The controller 360 can also turn off the sampling switch 330 during the precharge phase. After the sampling capacitor 320 has been precharged, the controller 360 turns off the precharge switch 325.

[0030]

[0041] After the pre-charge phase, the gate of transistor 310 is driven by a phase error signal from the phase detector 120. In one embodiment, the phase error signal includes a pulse having a width that is a function of the detected phase error between the reference signal and the feedback signal (e.g., the time error between the edge of the feedback signal and the edge of the reference signal). In this embodiment, the phase error signal turns on transistor 310 for a duration equal to the pulse width, which is a function of the detected phase error. Therefore, transistor 310 is turned on for a duration that is a function of the detected phase error.

[0031]

[0042] When transistor 310 is turned on by the phase error signal, transistor 310 connects resistor 315 to ground. This causes a portion of the charge on sampling capacitor 320 to discharge to ground through resistor 315. During this stage, the precharge switch 325 and sampling switch 330 remain off. The sampled voltage as a function of time is given by the following equation:

[0032]

number

[0033] Here, Vs(t) is the sampled voltage as a function of time, t is the time from the start of discharge, R is the resistance of resistor 315, and C is the capacitance of sampling capacitor 320.

[0034]

[0043] The amount of charge discharged from the sampling capacitor 320 is a function of the duration that the transistor 310 is turned on by a phase error signal, which is a function of the detected phase error. Consequently, the amount of charge discharged from the sampling capacitor 320 is a function of the detected phase error. Therefore, the sampled voltage Vs on the sampling capacitor 320 at the end of the discharge is a function of the detected phase error and thus provides phase error information. In one embodiment, the sampled voltage Vs at the end of the discharge is given by the following equation:

[0035]

number

[0036] Here, Δt is the pulse width of the phase error signal, and Vs in equation (3) is the sampled voltage at the end of the discharge. In this embodiment, the pulse width Δt can be approximately equal to the time error between the edge of the feedback signal and the edge of the reference signal. After the phase error signal has been sampled (i.e., after transistor 310 has been turned off at the end of the pulse), controller 360 turns on sampling switch 330 to couple sampling capacitor 320 to output 134 of sampler 130.

[0037]

[0044] In certain embodiments, during each cycle of the reference signal, the phase detector 120 detects the phase error between the reference signal and the feedback signal and outputs the corresponding phase error signal to the sampler 130. The sampler 130 then samples the phase error signal and outputs the corresponding sampled voltage Vs. Therefore, in these embodiments, the phase error is detected and sampled once per cycle of the reference signal.

[0038]

[0045] As described above, non-integer division values ​​can be achieved by modulating the division ratio of the frequency divider 150 using the DSM160. However, modulating the division ratio of the frequency divider 150 introduces quantization errors into the feedback signal. These quantization errors degrade performance by causing variations in the time error between the reference signal and the feedback signal. These quantization errors can be substantially offset by performing phase interpolation in the sampler 130, as will be discussed further below.

[0039]

[0046] Figure 4 shows an exemplary implementation of a sampler 130 and a phase detector 120 employing phase interpolation according to a particular aspect of the present disclosure. In this embodiment, the sampler 130 includes a plurality of discharge circuits 308-1 to 308-M coupled in parallel between a first terminal 322 of a sampling capacitor 320 and ground. Each of the discharge circuits 308-1 to 308-M includes a respective transistor 310-1 to 310-M and a respective resistor 315-1 to 315-M coupled between the drain or source of each of those transistors 310-1 to 310-M and the first terminal 322 of the sampling capacitor 320. In this embodiment, input 132 of sampler 130 includes a plurality of inputs 132-1 to 132-M, in which case each of inputs 132-1 to 132-M is coupled to one of each of the discharge circuits 308-1 to 308-M, more specifically, to the gate of transistors 310-1 to 310-M of one of each of the discharge circuits 308-1 to 308-M.

[0040]

[0047] In this embodiment, the phase detector 120 includes a delay circuit 410, a first pulse circuit 420, a second pulse circuit 430, and a plurality of multiplexers 450-1 to 450-M. The first pulse circuit 420 has a first input 422, a second input 424, and an output 426. The first input 422 is coupled to the first input 122 of the phase detector 120, and the second input 424 is coupled to the second input 124 of the phase detector 120. Therefore, the first input 422 receives a reference signal, and the second input 424 receives a feedback signal. In Figure 4, this feedback signal is referred to as "fb1" inside the phase detector 120.

[0041]

[0048] The second pulse circuit 430 has a first input 432, a second input 434, and an output 436. The first input 432 is coupled to the first input 122 of the phase detector 120 and therefore receives a reference signal. The delay circuit 410 is coupled between the second input 124 of the phase detector 120 and the second input 434 of the second pulse circuit 430. The delay circuit 410 is configured to delay the feedback signal (for example, with a delay equal to about one cycle (i.e., period) of the VCO 140) and output the resulting delayed feedback signal (labeled "fb2") to the second input 434 of the second pulse circuit 430. In one embodiment, the delay circuit 410 can be implemented using a delay flip-flop that is clocked by the output signal of the VCO 140.

[0042]

[0049] Each of the multiplexers 450-1 to 450-M has a first input 452-1 to 452-M, a second input 454-1 to 454-M, an output 456-1 to 456-M, and a select input 458-1 to 458-M. The first input 452-1 to 452-M of each of the multiplexers 450-1 to 450-M is coupled to the output 426 of the first pulse circuit 420, and the second input 454-1 to 454-M of each of the multiplexers 450-1 to 450-M is coupled to the output 436 of the second pulse circuit 430. In the embodiment shown in Figure 4, the output 126 of the phase detector 120 includes a plurality of outputs 126-1 to 126-M, in which case each of the outputs 126-1 to 126-M is coupled to one of the inputs 132-1 to 132-M of the sampler 130. In this embodiment, each of the outputs 456-1 to 456-M of the multiplexer 450-1 to 450-M is coupled to one of the outputs 126-1 to 126-M. As shown in Figure 4, each of the outputs 456-1 to 456-M of the multiplexer 450-1 to 450-M is coupled to one of the discharge circuits 308-1 to 308-M, and more specifically, to the gates of transistors 310-1 to 310-M of one of the discharge circuits 308-1 to 308-M.

[0043]

[0050] Each of the selectable inputs 458-1 to 458-M of the multiplexer 450-1 to 450-M is a digital code d <m-1:0>It is configured to receive each bit of the digital code d. Each of the multiplexers 450-1 to 450-M is configured to select either the respective first input 452-1 to 452-M or the respective second input 454-1 to 454-M based on the bit value of each bit, and to couple the selected input to the respective output 456-1 to 456-M. For example, a high bit value can trigger the selection of the respective first input 452-1 to 452-M, while a low bit value can trigger the selection of the respective second input 454-1 to 454-M, or vice versa. As will be discussed further below, the digital code d <m-1:0>This controls the phase interpolation in sampler 130.

[0044]

[0051] During operation, the first pulse circuit 420 is configured to detect a first time error between a reference signal and a feedback signal fb1, generate a first pulse having a width approximately equal to the first time error, and output the first pulse at output 426. For example, the first pulse circuit 420 can be configured to generate the rising edge of the first pulse at the edge of the feedback signal fb1 (e.g., the rising edge or the falling edge), and to generate the falling edge of the first pulse at the edge of the reference signal (e.g., the rising edge or the falling edge).

[0045]

[0052] The second pulse circuit 430 is configured to detect a second time error between the reference signal and the feedback signal fb2, generate a second pulse having a width approximately equal to the second time error, and output the second pulse at output 436. For example, the second pulse circuit 430 can be configured to generate the rising edge of the second pulse at the edge of the feedback signal fb2 (e.g., the rising edge or falling edge) and to generate the falling edge of the second pulse at the edge of the reference signal (e.g., the rising edge or falling edge). Due to the presence of the delay circuit 410, the rising edge of the second pulse is shifted with a delay (e.g., about one cycle of the VCO 140) relative to the rising edge of the first pulse. In combination with the multiplexers 450-1 to 450-M, the delay circuit 410 enables phase interpolation to cancel out the effects of quantization errors caused by modulation of the division ratio of the frequency divider 150, as will be discussed further below.

[0046]

[0053] Therefore, in this embodiment, the first inputs 452-1 to 452-M of each multiplexer 450-1 to 450-M receive a first pulse from the first pulse circuit 420, and the second inputs 454-1 to 454-M of each multiplexer 450-1 to 450-M receive a second pulse from the second pulse circuit 430. Each of the multiplexers 450-1 to 450-M receives a digital code d <m-1:0>Based on the bit value of each bit, a first or second pulse is selected, and the selected pulse is output to the gates of the respective transistors 310-1 to 310-M. Therefore, in this embodiment, the digital code d <m-1:0>This controls the number of transistors 310-1 to 310-M driven by the first pulse and the number of transistors 310-1 to 310-M driven by the second pulse by controlling the pulse selection of the multiplexers 450-1 to 450-M.

[0047]

[0054] In this embodiment, the sampler 130 performs phase interpolation between the feedback signal fb1 and the feedback signal fb2, in this case the digital code d <m-1:0>However, phase interpolation is controlled by controlling the number of transistors 310-1 to 310-M driven by the first pulse and the number of transistors 310-1 to 310-M driven by the second pulse. Phase interpolation results in a sampled voltage Vs given by the following equation:

[0048]

number

[0049] Here, k is the number of transistors 310-1 to 310-M driven by the first pulse, M is the total number of transistors 310-1 to 310-M, and T VCO Δt is the cycle (i.e., period) of VCO140, and Δt is the time error between the feedback signal fb2 and the reference signal. In this embodiment, the rising edge of the feedback signal fb1 and the rising edge of the feedback signal fb2 are equal to T VCO Because they are separated by an interval of T, the first pulse is T VCO Note that the first pulse has a width approximately equal to +Δt, and the second pulse has a width approximately equal to Δt.

[0050]

[0055] As shown in equation (4), phase interpolation is performed on the digital code d <m-1:0>The sampled voltage Vs is adjusted by adjusting the number k of transistors 310-1 to 310-M driven by the first pulse. In certain embodiments, the sampled voltage Vs can be adjusted using phase interpolation to compensate for the effects of quantization errors caused by modulation of the division ratio of the frequency divider 150.

[0051]

[0056] In this regard, the PLL 110 may include a phase interpolation (PI) control circuit 470 configured in a particular manner to cancel out quantization errors using phase interpolation. In the embodiment shown in Figure 4, the PI control circuit 470 has a plurality of outputs 472-1 to 472-M, in which case each of the outputs 472-1 to 472-M is coupled to a selection input 458-1 to 458-M of each of the multiplexers 450-1 to 450-M. For ease of explanation, the individual connections between the PI control circuit 470 and the multiplexers 450-1 to 450-M are not explicitly shown in Figure 4.

[0052]

[0057] During operation, the PI control circuit 470 determines the number k of transistors 310-1 to 310-M that need to be driven by the first pulse in order to cancel out the effects of quantization errors caused by the modulation of the frequency division ratio by the DSM160. For example, the DSM160 can generate a DSM error signal that indicates the quantization error caused by the modulation of the frequency division ratio, and input this DSM error signal to the PI control circuit 470. In this embodiment, the PI control circuit 470 can determine the number k of transistors 310-1 to 310-M that need to be driven by the first pulse in order to cancel out the quantization error indicated by the DSM error signal. The PI control circuit 470 then generates a digital code d corresponding to the determined number k. <m-1:0>It generates and its digital code d <m-1:0>These can be output to the multiplexers 450-1 to 450-M via their respective outputs 472-1 to 472-M. In response, the multiplexers 450-1 to 450-M drive k of the transistors 310-1 to 310-M with the first pulse and the remaining transistors 310-1 to 310-M (i.e., Mk of the transistors 310-1 to 310-M) with the second pulse.

[0053]

[0058] In this embodiment, to sample the phase error signal, the controller 360 turns on the precharge switch 325 to precharge the sampling capacitor 320 to the supply voltage Vdd via the precharge switch 325. After the sampling capacitor 320 is precharged, the controller 360 turns off the precharge switch 325, and the gates of transistors 310-1 to 310-M are turned on, in this case, as described above, the digital code d <m-1:0>Based on this, k transistors 310-1 to 310-M are driven by the first pulse, and the remaining transistors 310-1 to 310-M (i.e., Mk transistors 310-1 to 310-M) are driven by the second pulse. This causes a portion of the charge on the sampling capacitor 320 to discharge to ground through resistors 315-1 to 315-M, resulting in the sampled voltage Vs given by equation (4) above. After the phase error signal has been sampled, the controller 360 turns on the sampling switch 330 to couple the sampling capacitor 320 to the output 134 of the sampler 130. By performing the above procedure in each cycle of the reference signal, the phase error can be detected and sampled in each cycle of the reference signal.

[0054]

[0059] The challenge with respect to the sampler 130 is that the supply voltage Vdd, provided by the voltage regulator 340 (e.g., an LDO regulator) to precharge the sampling capacitor 320, fluctuates due to the finite bandwidth of the voltage regulator 340. Fluctuation (i.e., variation) of the supply voltage Vdd degrades the performance of the sampler 130 and introduces phase noise by changing the sampled voltage Vs with respect to a given phase error for each cycle of the reference signal. Therefore, it is necessary to reduce the dependence of the sampler 130's sampled voltage Vs on the cycle-by-cycle fluctuation of the supply voltage Vdd from the voltage regulator 340.

[0055]

[0060] Aspects of this disclosure reduce the effects of supply voltage fluctuations by generating a reference voltage based on the supply voltage. A control voltage vtune is generated by subtracting the reference voltage Vref from the sampled voltage Vs. Since the reference voltage Vref is generated based on the supply voltage, the reference voltage tracks changes in the sampled voltage Vs caused by supply voltage fluctuations. As a result, the effects of supply voltage fluctuations are offset by subtracting the reference voltage Vref from the sampled voltage Vs, as will be discussed further below.

[0056]

[0061] Figure 5 shows an embodiment in which the sampler 130 further includes a reference voltage circuit 515, according to a particular aspect of the present disclosure. The reference voltage circuit 515 is configured to generate a reference voltage Vref based on a supply voltage and to generate a voltage difference between the sampling voltage Vs and the reference voltage Vref, as will be discussed further below.

[0057]

[0062] The reference voltage circuit 515 includes a first capacitor 530, a second precharge switch 550, a second capacitor 540, a first switch 560, a second switch 570, and a difference circuit 520. The second precharge switch 550 is coupled between the first terminal 532 of the first capacitor 530 and the output 344 of the voltage regulator 340. The second terminal 534 of the first capacitor 530 is coupled to ground. The second capacitor 540 and the second switch 570 are coupled in parallel. The first switch 560 is coupled between the first terminal 532 of the first capacitor 530 and the first terminal 542 of the second capacitor 540. The second terminal 544 of the second capacitor 540 is coupled to ground.

[0058]

[0063] In this embodiment, the controller 360 controls the second precharge switch 550, the first switch 560, and the second switch 570. In this regard, the controller 360 is coupled to the control input 552 of the second precharge switch 550, the control input 562 of the first switch 560, and the control input 572 of the second switch 570. In this embodiment, the controller 360 is configured to control the on / off state of the second precharge switch 550 via the control input 552, the on / off state of the first switch 560 via the control input 562, and the on / off state of the second switch 570 via the control input 572. The second precharge switch 550, the first switch 560, and the second switch 570 can each be implemented using a transistor, a transmission gate, or another type of switch. In the following discussion, the precharge switch 325 will be referred to as the first precharge switch 325.

[0059]

[0064] The difference circuit 520 has a first input 522 connected to the sampling capacitor 320, a second input 524 connected to the first capacitor 530, and an output 526 connected to the output 134 of the sampler 130. As will be discussed further below, the difference circuit 520 is configured to generate a voltage difference between a sampled voltage Vs on the sampling capacitor 320 and a reference voltage Vref (for example, by subtracting the reference voltage Vref from the sampled voltage Vs) and output that voltage difference at output 526.

[0060]

[0065] During the pre-charge phase, the controller 360 turns off the first switch 560 to isolate the first capacitor 530 from the second capacitor 540, and turns on the second switch 570 to discharge the second capacitor 540 to ground. The controller 360 also turns on the first pre-charge switch 325 to pre-charge the sampling capacitor 320 to the supply voltage Vdd, and turns on the second pre-charge switch 550 to pre-charge the first capacitor 530 to the supply voltage Vdd. Therefore, during the pre-charge phase, both the sampling capacitor 320 and the first capacitor 530 are pre-charged to the supply voltage Vdd. In some implementations, the first pre-charge switch 325 and the second pre-charge switch 550 can be turned on and off synchronously.

[0061]

[0066] During the sampling phase, the controller 360 turns off the first precharge switch 325. The discharge circuits 308-1 to 308-M discharge a portion of the charge on the sampling capacitor 320 based on the phase error detected by the phase detector 120 (not shown in Figure 5) to generate the sampled voltage Vs (for example, based on equation (4)). In some implementations, the discharge circuits 308-1 to 308-M perform phase interpolation (for example, to cancel out quantization errors), as discussed above with reference to Figure 4. However, it should be understood that in other implementations, the discharge circuits 308-1 to 308-M can discharge the sampling capacitor 320 based on the detected phase error without performing phase interpolation (for example, all transistors 310-1 to 310-M can be driven by the same pulse). It should also be understood that the sampler 130 may contain any number of discharge circuits.

[0062]

[0067] During the charge sharing phase, the controller 360 turns off the second switch 570 and the second precharge switch 550, and turns on the first switch 560. Turning on the first switch 560 enables charge sharing between the first capacitor 530 and the second capacitor 540. This charge sharing generates a reference voltage Vref given by the following equation:

[0063]

number

[0064] Here, C1 is the capacitance of the first capacitor 530, and C2 is the capacitance of the second capacitor 540. As shown in equation (5), the reference voltage Vref is based on the supply voltage Vdd and therefore follows the changes in the sampled voltage Vs due to fluctuations in the supply voltage Vdd. This is because the first capacitor 530 is precharged with the same supply voltage Vdd as the sampling capacitor 320, and therefore is subject to the same fluctuations in the supply voltage Vdd as the sampled voltage Vs. In some implementations, the charge sharing stage may overlap with the sampling stage. In other implementations, the charge sharing stage may occur after the sampling stage, as will be discussed further below.

[0065]

[0068] Next, the difference circuit 520 subtracts the reference voltage Vref from the sampled voltage Vs and outputs the resulting voltage difference (i.e., Vs-Vref) at output 526. Since the reference voltage Vref tracks the change in the sampled voltage Vs caused by supply voltage fluctuations, this subtraction cancels out the effects of supply voltage fluctuations when the condition Vs-Vref=0 is met. The condition Vs-Vref=0 can be maintained by the PLL loop itself when the PLL 110 is locked.

[0066]

[0069] In embodiments where the PLL 110 includes an integration path 220, this condition can be maintained by the integration path 220 if the PLL 110 is locked. This is because the integration path 220 brings about the condition Vs-Vref=0 by adjusting the output frequency of the VCO 140 such that the voltage vtune is reduced to approximately zero at low frequencies. The condition Vs-Vref=0 locks the phase error between the reference signal and the feedback signal to a fixed phase error based on the ratio of the capacitance of the first capacitor 530 to the capacitance of the second capacitor 540 (i.e., C1 and C2). Since this phase error is fixed, it has little to no effect on the PLL's ability to maintain a VCO output frequency equal to the reference frequency multiplied by a desired division value.

[0067]

[0070] By sharing charge between the first capacitor 530 and the second capacitor 540, the reference voltage Vref can be set to a desired ratio of the supply voltage Vdd by appropriately setting the capacitance of the first capacitor 530 and / or the capacitance of the second capacitor 540 based on equation (5). In one embodiment, the reference voltage Vref can be set to a voltage that maximizes the gain of the sampler 130 when the condition Vs-Vref=0 is satisfied. In this embodiment, the gain of the sampler 130 can be maximized when the discharge time of the sampling capacitor 320 during the sampling stage is approximately equal to the RC time constant of the sampler 130. By substituting the RC time constant for time t in equation (2), a voltage approximately equal to Vdd / e can be obtained. Therefore, in this embodiment, the gain can be maximized by setting the voltage of the reference voltage Vref to approximately Vdd / e by appropriately setting the capacitance of the first capacitor 530 and / or the capacitance of the second capacitor 540 based on equation (5).

[0068]

[0071] Figure 6 shows an exemplary implementation of the difference circuit 520 in a particular embodiment. In this embodiment, the difference circuit 520 includes a third switch 610 coupled between the first terminal 322 of the sampling capacitor 320 and the first terminal 532 of the first capacitor 530, and a fourth switch 620 coupled between the second terminal 534 of the first capacitor 530 and the output 134 of the sampler 130. In this embodiment, the sampler 130 may also include a fifth switch 630 coupled between the second terminal 534 of the first capacitor 530 and ground. The fifth switch 630 may also be coupled between the second terminal 544 of the second capacitor 540 and ground, as shown in the embodiment of Figure 6.

[0069]

[0072] In this embodiment, the controller 360 controls the third switch 610, the fourth switch 620, and the fifth switch 630. In this regard, the controller 360 is coupled to the control input 612 of the third switch 610, the control input 622 of the fourth switch 620, and the control input 632 of the fifth switch 630. In this embodiment, the controller 360 is configured to control the on / off state of the third switch 610 via the control input 612, the on / off state of the fourth switch 620 via the control input 622, and the on / off state of the fifth switch 630 via the control input 632. The third switch 610, the fourth switch 620, and the fifth switch 630 can each be implemented using a transistor, a transmission gate, or another type of switch.

[0070]

[0073] In this embodiment, the second precharge switch 550 is omitted. This is because the first capacitor 530 can be precharged via the third switch 610 of the difference circuit 520, as will be discussed further below. However, it should be noted that in other implementations, the second precharge switch 550 may be included to precharge the first capacitor 530.

[0071]

[0074] During the pre-charge phase, the controller 360 turns on the pre-charge switch 325, the third switch 610, the fifth switch 630, and the second switch 570. The controller 360 then turns off the fourth switch 620 and the first switch 560. During the pre-charge phase, the sampling capacitor 320 is pre-charged to the supply voltage Vdd via the pre-charge switch 325, the first capacitor 530 is pre-charged to the supply voltage Vdd via the pre-charge switch 325 and the third switch 610, and the second capacitor 540 is discharged to ground via the second switch 570 and the fifth switch 630. Therefore, during the pre-charge phase, both the sampling capacitor 320 and the first capacitor 530 are pre-charged to the supply voltage Vdd. In some implementations, the pre-charge switch 325 and the third switch 610 can be turned on synchronously.

[0072]

[0075] During the sampling phase, the controller 360 turns off the precharge switch 325 and the third switch 610. The discharge circuits 308-1 to 308-M discharge a portion of the charge on the sampling capacitor 320 based on the phase error detected by the phase detector 120 (not shown in Figure 6) to generate the sampled voltage Vs (for example, based on equation (4)).

[0073]

[0076] During the charge sharing phase, the controller 360 turns off the second switch 570 and turns on the first switch 560. Turning on the first switch 560 enables charge sharing between the first capacitor 530 and the second capacitor 540, thereby generating a reference voltage Vref (for example, based on equation (4)). During the charge sharing phase, the controller 360 turns off the third switch 610 and the fourth switch 620 and turns on the fifth switch 630. In some implementations, the charge sharing phase may overlap with the sampling phase. In other implementations, the charge sharing phase may be started after the end of the sampling phase. For example, the sampling phase may generate noise on the ground rail. In this embodiment, to prevent noise on the ground rail from affecting the charge sharing phase, the charge sharing phase may be started after the end of the sampling phase.

[0074]

[0077] During the differential phase, the controller 360 turns on the third switch 610 and the fourth switch 620, and turns off the fifth switch 630. This connects the first capacitor 530 in series with the sampling capacitor 320, and the voltage difference Vs-Vref is obtained at the output 134 of the sampler 130 by subtracting the reference voltage Vref on the first capacitor 530 from the sampled voltage Vs on the sampling capacitor 320. During the differential phase, the precharge switch 325 and the second switch 570 are turned off. In some implementations, the reference voltage is also present on the second capacitor 540 due to charge sharing, so the first switch 560 can be turned on during the differential phase. In other implementations, the first switch 560 can also be turned off during the differential phase.

[0075]

[0078] By executing the above switching sequence once for each cycle of the reference signal, the phase error can be sampled once for each cycle of the reference signal. As described above, since the reference voltage Vref tracks the supply voltage fluctuations, the voltage difference Vs-Vref improves the performance of the PLL110 by canceling out the effects of the supply voltage fluctuations for each cycle.

[0076]

[0079] Figure 7 shows an exemplary implementation of a switch according to a particular aspect of the present disclosure. In this embodiment, the precharge switch 325 is implemented using a p-type field-effect transistor (PFET) 710, the second switch 570 is implemented using an n-type field-effect transistor (NFET) 745, the fourth switch 620 is implemented using an NFET 740, and the fifth switch 630 is implemented using an NFET 750. In this embodiment, the third switch 610 is implemented using a transmission gate including NFETs 722 and 727 coupled in parallel, and the first switch 560 is implemented using a transmission gate including NFETs 732 and 737 coupled in parallel.

[0077]

[0080] The control inputs of switches 325, 570, 620, and 630 are located at the gates of their respective transistors. In the embodiment shown in Figure 7, the control inputs of switches 325, 570, 620, and 630 are driven by control signals preb, pre, ph4, and ph2, respectively, where preb and pre are complementary signals. The gates of NFET 722 and PFET 727 in the third switch 610 are driven by complementary control signals ph3 and ph3b, respectively. The gates of NFET 732 and PFET 737 in the first switch 560 are driven by complementary control signals ph1 and ph1b, respectively. These control signals are generated by controller 360 (not shown in Figure 7).

[0078]

[0081] Figure 8 is a timing diagram showing an embodiment of the signal in sampler 130 according to a particular aspect of the present disclosure. Between times t1 and t2 (e.g., the pre-charge phase), the pre-charge switch 325 is turned on, and the third switch 610 is turned on. As a result, the sampling capacitor 320 is pre-charged to the supply voltage Vdd via the pre-charge switch 325, thereby raising the voltage Vs on the sampling capacitor 320 to Vdd. Furthermore, the first capacitor 530 is pre-charged to the supply voltage Vdd via the pre-charge switch 325 and the third switch 610.

[0079]

[0082] In this embodiment, the rising edge 810 of the control signal preb triggers the falling edge 815 of the control signal ph3. This is done so that the third switch 610 is left on for a short time after the precharge switch 325 is turned off, which helps to ensure that the voltage on the sampling capacitor 320 and the voltage on the first capacitor 530 are approximately the same after precharging.

[0080]

[0083] Furthermore, during the interval between time t1 and t2, the second switch 570 is turned on. This is because the second switch 570 is implemented using an NFET 745 in this embodiment and is driven by a control signal pre (not shown in Figure 8), which is the complement of the control signal preb. As a result, the second capacitor 540 is discharged to ground.

[0081]

[0084] During time t3 to t4 (e.g., the sampling stage), the discharge circuits 308-1 to 308-M discharge a portion of the charge on the sampling capacitor 320 based on the phase error detected by the phase detector 120 to generate a sampled voltage Vs indicating the sampled phase error. In this embodiment, as described above with reference to FIG. 4, in order to perform phase interpolation, k of the discharge circuits 308-1 to 308-M are driven by the first pulse (labeled "pulse 1"), and the remaining discharge circuits 308-1 to 308-M (i.e., M-k of the discharge circuits 308-1 to 308-M) are driven by the second pulse (labeled "pulse 2"). In this embodiment, the rising edge 820 of the first pulse and the rising edge 825 of the second pulse are separated by an interval of one cycle T of the VCO140 VCO apart.

[0082]

[0085] At time t5, when the first switch 560 is turned on, charge sharing between the first capacitor 530 and the second capacitor 540 becomes possible, and a reference voltage Vref is generated (e.g., based on Equation (5)). In one embodiment, turning on the first switch 560 can be triggered by the rising edge of a reference signal.

[0083]

[0086] At time t6, the fifth switch 630 is turned off. As a result, the second terminal 534 of the first capacitor 530 and the second terminal 544 of the second capacitor 540 are disconnected from the ground, floating the first capacitor 530 and the second capacitor 540. Also, when the third switch 610 is turned on, a voltage difference Vs-Vref is generated.

[0084]

[0087] At time t7, the fourth switch 620 is turned on, and the voltage difference Vs-Vref is coupled to the output 134 of the sampler 130. As a result, the voltage difference Vs-Vref is transferred to the output 134 of the sampler 130. At time t8, the fourth switch 620 is turned off in order to sample the phase error for the next cycle of the reference signal.

[0085]

[0088] Figure 9 shows another exemplary implementation of a phase detector 120 supporting phase interpolation in a particular embodiment. In this embodiment, the phase detector 120 includes a delay circuit 910, a plurality of multiplexers 950-1 to 950-M, and a plurality of flip-flops (FFs) 960-1 to 960-M.

[0086]

[0089] Each of the multiplexers 950-1 to 950-M has a first input 952-1 to 952-M, a second input 954-1 to 954-M, an output 956-1 to 956-M, and a select input 958-1 to 958-M. The first inputs 952-1 to 952-M of each of the multiplexers 950-1 to 950-M are coupled to the second input 124 of the phase detector 120, and thus receive a feedback signal. In Figure 9, this feedback signal is referred to as "fb1" inside the phase detector 120.

[0087]

[0090] The delay circuit 910 is coupled between the second input 124 of the phase detector 120 and the respective second inputs 954-1 to 954-M of the multiplexers 950-1 to 950-M. The delay circuit 910 is configured to delay the feedback signal (for example, with a delay equal to approximately one cycle (i.e., period) of the VCO 140) and output the resulting delayed feedback signal (labeled "fb2") to the respective second inputs 954-1 to 954-M of the multiplexers 950-1 to 950-M. In one embodiment, the delay circuit 910 can be implemented using a delay flip-flop that is clocked by the output signal of the VCO 140.

[0088]

[0091] Each of the multiplexers 950-1 to 950-M, specifically the selectable inputs 958-1 to 958-M, uses digital code d <m-1:0>It is configured to receive each bit of the digital code d. <m-1:0>This controls phase interpolation. Each of the multiplexers 950-1 to 950-M is configured to select either the respective first input 952-1 to 952-M or the respective second input 954-1 to 954-M based on the bit value of each bit, and to couple the selected input to the respective output 956-1 to 956-M. Therefore, each of the multiplexers 950-1 to 950-M is configured to select either the feedback signal fb1 or the feedback signal fb2 based on each bit, and to output the selected feedback signal at the respective output 956-1 to 956-M.

[0089]

[0092] Each of the flip-flops 960-1 to 960-M has its respective signal input 962-1 to 962-M, its respective clock input 966-1 to 966-M, its respective reset input 968-1 to 968-M, and its respective output 964-1 to 964-M. Each of the signal inputs 962-1 to 962-M of the flip-flops 960-1 to 960-M is coupled to the output 956-1 to 956-M of each of the multiplexers 950-1 to 950-M. Therefore, each of the multiplexers 950-1 to 950-M is connected to the digital code d <m-1:0>Based on each bit, it controls whether feedback signal fb1 or feedback signal fb2 is input to the signal inputs 962-1 to 962-M of the respective flip-flops 960-1 to 960-M.

[0090]

[0093] Each of the flip-flops 960-1 to 960-M has a clock input 966-1 to 966-M that receives a clock signal (labeled "clk"). In certain embodiments, the clock signal can be the output signal of the VCO 140. Each of the flip-flops 960-1 to 960-M has a reset input 968-1 to 968-M that is coupled to the first input 122 of the phase detector 120 and therefore receives a reference signal. In certain embodiments, each of the flip-flops 960-1 to 960-M is configured to reset its respective output 964-1 to 964-M to zero on the rising edge of the reference signal. Each of the flip-flops 960-1 to 960-M has an output 964-1 to 964-M which is coupled to one of the outputs 126-1 to 126-M of the phase detector 120, and each of these outputs is coupled to the gate of one of the discharge circuits 308-1 to 308-M which is coupled to one of the transistors 310-1 to 310-M.

[0091]

[0094] During operation, each of the multiplexers 950-1 to 950-M uses digital code d <m-1:0>Based on each bit, either feedback signal fb1 or feedback signal fb2 is selected, and the selected feedback signal is output to the signal inputs 962-1 to 962-M of the respective flip-flops 960-1 to 960-M.

[0092]

[0095] Each of the flip-flops 960-1 to 960-M retiming the selected feedback signal from each multiplexer 950-1 to 950-M with the clock signal, and outputs the rising edge of the respective pulse at the edge of the retiming feedback signal. The edge of the retiming feedback signal can be either a rising or falling edge. Then, each of the flip-flops 960-1 to 960-M outputs the falling edge of the respective pulse at the rising edge of the reference signal received at each reset input 968-1 to 968-M. This is because each of the flip-flops 960-1 to 960-M is configured to reset its respective output 964-1 to 964-M to zero at the rising edge of the reference signal.

[0093]

[0096] The pulses from each of the flip-flops 960-1 to 960-M drive the gates of transistors 310-1 to 310-M, one of each of the discharge circuits 308-1 to 308-M. In this embodiment, the digital code d <m-1:0>This controls the number of transistors 310-1 to 310-M driven by pulses generated from feedback signal fb1, and the number of transistors 310-1 to 310-M driven by pulses generated from feedback signal fb2. This is digital code d <m-1:0>This is because it controls the number of flip-flops 960-1 to 960-M that receive the feedback signal fb1, and the number of flip-flops 960-1 to 960-M that receive the feedback signal fb2. As a result, digital code d <m-1:0>Phase interpolation between feedback signals fb1 and fb2 is provided, controlled by [the specified method].

[0094]

[0097] Digital Code d <m-1:0>This can be generated by the PI control circuit 470, as described above in a specific manner with reference to Figure 4. As described above, the PI control circuit 470 generates the digital code d in order to compensate for the effects of quantization errors caused by the modulation of the frequency division ratio by the DSM160. <m-1:0>It can generate [this].

[0095]

[0098] In the above embodiment, the delay circuit 910 may have a delay of approximately one cycle of the VCO140 and can be implemented using a delay flip-flop clocked by the output of the VCO140. However, it should be understood that the delay circuit 910 is not limited to this embodiment. In other implementations, the delay circuit 910 may have a delay approximately equal to two cycles of the VCO140, or another multiple of the VCO140 cycles.

[0096]

[0099] Figure 10 shows a wireless device 1010 capable of using an exemplary PLL 110 in a particular embodiment. The wireless device 1010 may include a transmitter 1030 and a receiver 1035 for wireless communication (e.g., with a base station). The wireless device 1010 may also include a baseband processor 1070, a radio frequency (RF) coupling circuit 1025, an antenna 1015, a reference signal generator 1090, a first PLL 1080, and a second PLL 1085. Although Figure 10 shows one transmitter 1030, one receiver 1035, and one antenna 1015, it should be understood that the wireless device 1010 may include any number of transmitters, receivers, and antennas.

[0097]

[0100] In the embodiment shown in Figure 10, the transmitter 1030 has an input 1032 coupled to a baseband processor 1070 and an output 1034 coupled to an antenna 1015 via an RF coupling circuit 1025. The transmitter 1030 may include a mixer 1040 and a power amplifier 1045. The mixer 1040 is coupled between the input 1032 and the power amplifier 1045, and the power amplifier 1045 is coupled between the mixer 1040 and the output 1034. In one embodiment, the mixer 1040 is configured to receive a baseband signal from the baseband processor 1070 via the input 1032 and to frequency upconvert the baseband signal to an RF transmit signal by mixing the baseband signal with a local oscillator signal. The power amplifier 1045 is configured to amplify the RF transmit signal and output the amplified RF transmit signal at output 1034 for transmission via the antenna 1015. It should be understood that transmitter 1030 may include one or more additional components not shown in Figure 10. For example, in some implementations, transmitter 1030 may include one or more filters, phase shifters, and / or one or more additional amplifiers in the signal path between the input 1032 and output 1034 of transmitter 1030.

[0098]

[0101] In the embodiment shown in Figure 10, the receiver 1035 has an input 1036 coupled to an antenna 1015 via an RF coupling circuit 1025, and an output 1038 coupled to a baseband processor 1070. The receiver 1035 may include a low-noise amplifier 1050 and a mixer 1055. The low-noise amplifier 1050 is coupled between the input 1036 and the mixer 1055, and the mixer 1055 is coupled between the low-noise amplifier 1050 and the output 1038. In one embodiment, the low-noise amplifier 1050 is configured to receive an RF signal from the antenna 1015 via the RF coupling circuit 1025, amplify the RF signal, and output the amplified RF signal to the mixer 1055. The mixer 1055 is configured to frequency down-convert the RF signal to a baseband signal by mixing the RF signal with a local oscillator signal. It should be understood that the receiver 1035 may include one or more additional components not shown in Figure 10. For example, in some implementations, the receiver 1035 may include one or more filters, phase shifters, and / or one or more additional amplifiers in the signal path between the input 1036 and output 1038 of the receiver 1035.

[0099]

[0102] The RF coupling circuit 1025 is coupled between the output 1034 of the transmitter 1030 and the antenna 1015. The RF coupling circuit 1025 is also coupled between the antenna 1015 and the input 1036 of the receiver 1035. In one embodiment, the RF coupling circuit 1025 can be implemented using a duplexer configured to couple the RF signal from the output 1034 of the transmitter 1030 to the antenna 1015, and the RF signal received from the antenna 1015 to the input 1036 of the receiver 1035. In other implementations, the RF coupling circuit 1025 may include one or more switches configured to couple the transmitter 1030 and the receiver 1035 to the antenna 1015 one at a time.

[0100]

[0103] The reference signal generator 1090 is configured to generate and output reference signals for the first PLL 1080 and the second PLL 1085. The reference signal generator 1090 may include a crystal oscillator or another type of circuit configured to generate reference signals.

[0101]

[0104] The first PLL 1080 is coupled between the reference signal generator 1090 and the mixer 1040 of the transmitter 1030. The first PLL 1080 is configured to receive a reference signal from the reference signal generator 1090 and generate a local oscillator signal for the mixer 1040 by multiplying the frequency of the reference signal. The first PLL 1080 can be implemented using an exemplary PLL 110 in any one or more of the embodiments shown in Figures 1 to 9, in which case the first input 122 is coupled to the reference signal generator 1090 to receive the reference signal and the output 112 is coupled to the mixer 1040.

[0102]

[0105] The second PLL 1085 is coupled between the reference signal generator 1090 and the mixer 1055 of the receiver 1035. The second PLL 1085 is configured to receive a reference signal from the reference signal generator 1090 and generate a local oscillator signal for the mixer 1055 by multiplying the frequency of the reference signal. The second PLL 1085 can be implemented using an exemplary PLL 110 in any one or more of the embodiments shown in Figures 1 to 9, in which case the first input 122 is coupled to the reference signal generator 1090 to receive the reference signal and the output 112 is coupled to the mixer 1055.

[0103]

[0106] Figure 11 is a diagram of the environment 1100, including electronic devices 1102 and a base station 1104. Electronic devices 1102 include a wireless transceiver 1196, which may include an exemplary transmitter 1030, receiver 1035, and PLLs 1080 and 1085 shown in Figure 10. In certain embodiments, electronic devices 1102 may correspond to the wireless device 1010 shown in Figure 10.

[0104]

[0107] Within environment 1100, the electronic device 1102 communicates with base station 1104 via wireless link 1106. As shown in the figure, the electronic device 1102 is shown as a smartphone. However, the electronic device 1102 can be implemented as any suitable computing device or other electronic device, such as a cellular base station, broadband router, access point, cellular phone or mobile phone, gaming device, navigation device, media device, laptop computer, desktop computer, tablet computer, server computer, network-attached storage (NAS) device, smart home appliance, vehicle-based communication system, Internet of Things (IoT) device, sensor or security device, asset tracker, etc.

[0105]

[0108] Base station 1104 communicates with electronic device 1102 via wireless link 1106, which can be implemented as any suitable type of wireless link. Although shown as a base station tower in a cellular radio network, base station 1104 may represent or be implemented as another device, such as a satellite, terrestrial broadcasting tower, access point, peer-to-peer device, mesh network node, fiber optic line, or another electronic device as broadly described above. Therefore, electronic device 1102 may communicate with base station 1104 or another device via wired connection, wireless connection, or a combination thereof. Wireless link 1106 may include a downlink of data or control information communicated from base station 1104 to electronic device 1102, and an uplink of other data or control information communicated from electronic device 1102 to base station 1104. Wireless Link 1106 can be implemented using any suitable communication protocol or standard, such as the 3rd Generation Partnership Project Long-Term Evolution (3GPP® LTE®, 3GPP NR 5G), IEEE 802.11, Bluetooth®, etc.

[0106]

[0109] The electronic device 1102 includes a processor 1180 and a memory 1182. The memory 1182 may be part of or form part of a computer-readable storage medium. The processor 1180 may include any type of processor, such as an application processor or a multicore processor, configured to execute processor-executable instructions (e.g., code) stored in the memory 1182. The memory 1182 may include any preferred type of data storage medium, such as volatile memory (e.g., random access memory; RAM), non-volatile memory (e.g., flash memory), optical media, or magnetic media (e.g., disk or tape). In the context of this disclosure, the memory 1182 is implemented to store instructions 1184, data 1186, and other information of the electronic device 1102.

[0107]

[0110] The electronic device 1102 may also include input / output (I / O) ports 1190. The I / O ports 1190 enable data exchange or interaction with other devices, networks, or users, or between components of the device.

[0108]

[0111] The electronic device 1102 may further include a signal processor (SP) 1192 (e.g., a digital signal processor (DSP)). The signal processor 1192 may function similarly to the processor 1180 and may work in conjunction with the memory 1182 to execute instructions and / or process information.

[0109]

[0112] For communication purposes, the electronic device 1102 also includes a modem 1194, a wireless transceiver 1196, and one or more antennas (e.g., antenna 1015). The wireless transceiver 1196 uses RF wireless signals to provide connectivity to each network and other electronic devices connected to that network. The wireless transceiver 1196 can facilitate communication over any suitable type of wireless network, such as a wireless local area network (LAN) (wireless local area network; WLAN), a peer-to-peer (P2P) network, a mesh network, a cellular network, a wireless wide area network (WWAN), a navigation network (e.g., the Global Positioning System (GPS) or another Global Navigation Satellite System (GNSS)), and / or a wireless personal area network (WPAN).

[0110]

[0113] Figure 12 shows a sampling method 1200 in a specific embodiment. Method 1200 can be performed by a sampler 130.

[0111]

[0114] In block 1210, the sampling capacitor is charged to the supply voltage. For example, the sampling capacitor (e.g., sampling capacitor 320) can be charged to the supply voltage (e.g., Vdd) by turning on a precharge switch (e.g., precharge switch 325) coupled between the supply voltage and the sampling capacitor. The precharge switch can be turned on by the controller 360. The supply voltage can be supplied by the voltage regulator 340.

[0112]

[0115] In block 1220, a portion of the charge on the sampling capacitor is discharged based on a phase error to generate the sampling voltage. For example, the sampling capacitor can be discharged by one or more discharge circuits (e.g., discharge circuits 308-1 to 308-M) based on a phase error. This phase error can be the phase error between the reference signal and the feedback signal of the phase-locked loop (PLL). The feedback signal can be generated by dividing the output signal of the PLL's VCO (e.g., VCO140).

[0113]

[0116] In block 1230, a reference voltage is generated based on the supply voltage. For example, this reference voltage can be generated by the reference voltage circuit 515.

[0114]

[0117] In block 1240, a differential voltage is generated between the sampling voltage and the reference voltage. For example, this differential voltage can be generated by the differential circuit 520.

[0115]

[0118] In certain embodiments, discharging a portion of the charge on a sampling capacitor based on a phase error may include receiving a phase error signal indicating a phase error and driving one or more discharge circuits with the phase error signal, the one or more discharge circuits being coupled to the sampling capacitor. In one embodiment, each of the one or more discharge circuits includes a transistor (e.g., one of each of transistors 310-1 to 310-M) and a resistor (e.g., one of each of resistors 315-1 to 315-M) coupled between the sampling capacitor and the transistor. In this embodiment, the phase error signal may include one or more pulses (e.g., pulse 1 and / or pulse 2 in Figure 8), and the gate of each transistor in the one or more discharge circuits is driven by one of those one or more pulses. In one embodiment, the phase error signal may include a first pulse and a second pulse (e.g., pulse 1 and pulse 2 in Figure 8, respectively), in which case the rising edge of the first pulse and the rising edge of the second pulse are separated by an interval of one or more cycles of the VCO 140. In this embodiment, as described above, in order to cancel out the quantization error, k gates of transistors 310-1 to 310-M are driven by a first pulse and Mk gates of transistors 310-1 to 310-M are driven by a second pulse, based on the DSM error signal.

[0116]

[0119] In certain embodiments, generating a reference voltage may include charging a first capacitor (e.g., first capacitor 530) to a supply voltage, discharging a second capacitor (e.g., second capacitor 540), and sharing charge between the first and second capacitors to generate the reference voltage. For example, charge sharing may include turning on a switch (e.g., first switch 560) coupled between the first capacitor 530 and the second capacitor 540. In one embodiment, the charging of the first capacitor overlaps in time with the charging of the sampling capacitor, so that fluctuations in the supply voltage over time are at least partially followed in the reference voltage.

[0117]

[0120] In certain embodiments, generating a differential voltage between a sampling voltage and a reference voltage may include turning on a first switch (e.g., a third switch 610) coupled between a sampling capacitor (e.g., sampling capacitor 320) and a first terminal (e.g., a first terminal 532) of a first capacitor (e.g., a first capacitor 530), and turning on a second switch (e.g., a fourth switch 620) coupled between the output (e.g., output 134) of a sampler (e.g., sampler 130) and a second terminal (e.g., a second terminal 534) of the first capacitor. In these embodiments, charging the first capacitor to a supply voltage may include turning on a precharge switch (e.g., a precharge switch 325) coupled between the supply voltage and the sampling capacitor, and turning on a first switch (e.g., a third switch 610).

[0118]

[0121] In certain embodiments, generating a differential voltage between a sampling voltage and a reference voltage may include subtracting the reference voltage from the sampling voltage.

[0119]

[0122] Please understand that this disclosure is not limited to the illustrative terminology used above to describe the aspects of this disclosure. For example, a phase detector may also be called a phase comparator, a phase frequency detector (PFD), or by other terms. A frequency divider may also be called an N-division circuit or by other terms. The division ratio of a frequency divider may also be called a divisor or by other terms.

[0120]

[0123] The controller 360 and the PI control circuit 470 can each be implemented using a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic device, a separate hardware component (e.g., a logic gate), or any combination thereof, designed to perform the functions described herein. The functions described herein can be performed by the processor executing software containing code for performing those functions. This software can be stored on a computer-readable storage medium such as RAM, ROM, EEPROM®, an optical disk, and / or a magnetic disk.

[0121]

[0124] Examples of implementation forms are described in the following numbered clauses:

[0125] 1. It is a sampler,

[0126] A sampling capacitor and

[0127] A precharge switch coupled to the sampling capacitor,

[0128] One or more discharge circuits coupled to the sampling capacitor,

[0129] A reference voltage circuit coupled to a sampling capacitor,

[0130] A reference voltage is generated based on the supply voltage.

[0131] A sampler comprising a reference voltage circuit configured to generate a voltage difference between the voltage on a sampling capacitor and a reference voltage.

[0132] 2. A sampler according to Clause 1, wherein a precharge switch is coupled between the voltage regulator and the sampling capacitor, and the voltage regulator is configured to supply the supply voltage.

[0133] 3. Each of the one or more discharge circuits is

[0134] Each transistor and

[0135] A sampler according to clause 1 or 2, comprising a sampling capacitor and a resistor coupled between each transistor.

[0136] 4. A sampler according to clause 3, wherein, for each of the one or more discharge circuits, the gate of each transistor is coupled to a phase detector.

[0137] 5. The reference voltage circuit is

[0138] At least one capacitor,

[0139] A sampler comprising a sampling capacitor and a difference circuit coupled to at least one capacitor, configured to generate a voltage difference, according to any one of the clauses 1 to 4.

[0140] 6. Further comprising a first switch and a second switch, and at least one capacitor,

[0141] The first capacitor is coupled to the differential circuit,

[0142] A sampler according to Clause 5, comprising a second capacitor, wherein a first switch is coupled between the first capacitor and the second capacitor, and the second switch is coupled in parallel with the second capacitor.

[0143] 7. One or more discharge circuits are coupled to a phase detector,

[0144] The difference circuit is coupled to the filter.

[0145] A sampler under Article 5 or 6.

[0146] 8. A device,

[0147] A sampling capacitor and

[0148] A precharge switch coupled to the sampling capacitor,

[0149] One or more discharge circuits coupled to the sampling capacitor,

[0150] A reference voltage circuit coupled to a sampling capacitor,

[0151] The first capacitor and,

[0152] The second capacitor,

[0153] A first switch is coupled between the first capacitor and the second capacitor,

[0154] A second switch is connected in parallel with the second capacitor,

[0155] An apparatus comprising a reference voltage circuit, which includes a sampling capacitor and a difference circuit coupled to a first capacitor.

[0156] 9. The apparatus of Clause 8, further comprising a voltage regulator, wherein a precharge switch is coupled between the voltage regulator and the sampling capacitor.

[0157] 10. The apparatus of Clause 8 or 9, further comprising a controller, wherein in the pre-charge phase, the controller is configured to turn on the pre-charge switch, turn off the first switch, and turn on the second switch.

[0158] 11. The apparatus of Clause 10, wherein, during the charge sharing stage, the controller is configured to turn off the precharge switch, turn on the first switch, and turn off the second switch.

[0159] 12. The difference circuit,

[0160] A third switch is coupled between the sampling capacitor and the first terminal of the first capacitor,

[0161] The apparatus according to clause 8 or 9, comprising a fourth switch coupled between the second terminal of the first capacitor and the output of the sampler.

[0162] 13. The apparatus of Clause 12, further comprising a controller, wherein in the pre-charge phase, the controller is configured to turn on the pre-charge switch, turn off the first switch, turn on the second switch, turn on the third switch, and turn off the fourth switch.

[0163] 14. The apparatus of Clause 13, wherein, during the charge sharing stage, the controller is configured to turn off the precharge switch, turn on the first switch, turn off the second switch, turn off the third switch, and turn off the fourth switch.

[0164] 15. The apparatus of Clause 13 or 14, wherein, during the sampling stage, the controller is configured to turn off the precharge switch, the third switch, and the fourth switch.

[0165] 16. Any one of the devices described in clauses 13 to 15, wherein, in the differential phase, the controller is configured to turn off the precharge switch, turn off the second switch, turn on the third switch, and turn on the fourth switch.

[0166] 17. Any one of the devices from clauses 12 to 16, further comprising a fifth switch, the reference voltage circuit being coupled between the second terminal of the first capacitor and ground.

[0167] 18. The apparatus of clause 8, further comprising a second precharge switch coupled to the first capacitor.

[0168] 19. The apparatus of clause 18, further comprising a voltage regulator, wherein a first precharge switch is coupled between the voltage regulator and the sampling capacitor, and a second precharge switch is coupled between the voltage regulator and the first capacitor.

[0169] 20. The apparatus of Clause 18 or 19, further comprising a controller, wherein in the pre-charge phase, the controller is configured to turn on a first pre-charge switch, turn on a second pre-charge switch, turn off the first switch, and turn on the second switch.

[0170] 21. The apparatus of Clause 20, wherein, during the charge sharing stage, the controller is configured to turn off the first precharge switch, turn off the second precharge switch, turn on the first switch, and turn off the second switch.

[0171] 22. Any one of the devices from clauses 8 to 21, further comprising a phase detector having an output coupled to one or more discharge circuits.

[0172] 23. Voltage-controlled oscillator (VCO),

[0173] A loop filter is coupled between the difference circuit and the VCO input,

[0174] The system further comprises a frequency divider coupled between the output of the VCO and the input of the phase detector.

[0175] The apparatus of Clause 22.

[0176] 24. The apparatus of clause 23, comprising an integration path in which a loop filter is coupled between a difference circuit and the input of a VCO.

[0177] 25. The phase detector has a first input configured to receive a reference signal and a second input configured to receive a feedback signal, and the phase detector,

[0178] A delay circuit having an input coupled to the second input of a phase detector and an output,

[0179] A first pulse circuit having a first input coupled to the first input of a phase detector, a second input coupled to the second input of a phase detector, and an output,

[0180] A second pulse circuit having a first input coupled to the first input of a phase detector, a second input coupled to the output of a delay circuit, and an output,

[0181] Any one of the devices according to clauses 22 to 24, comprising a plurality of multiplexers, each having a first input coupled to the output of a first pulse circuit, a second input coupled to the output of a second pulse circuit, and an output coupled to one of one or more discharge circuits.

[0182] 26. The apparatus of Clause 25, each multiplexer having a selection input configured to receive each bit of a digital code, and each multiplexer configured to select either the first input or the second input of the multiplexer based on the bit value of each bit, and to combine the selected inputs to their respective outputs.

[0183] 27. Voltage-controlled oscillator (VCO),

[0184] A loop filter is coupled between the difference circuit and the VCO input,

[0185] The system further comprises a frequency divider coupled between the output of the VCO and the second input of the phase detector.

[0186] The apparatus of Article 25 or 26.

[0187] 28. The phase detector has a first input configured to receive a reference signal and a second input configured to receive a feedback signal, and the phase detector,

[0188] A delay circuit having an input coupled to the second input of a phase detector and an output,

[0189] A plurality of multiplexers, each having a first input coupled to the second input of a phase detector, a second input coupled to the output of a delay circuit, and an output,

[0190] Any one of the devices according to clauses 22 to 24, comprising a plurality of flip-flops, each having a signal input coupled to one output of a plurality of multiplexers, a reset input coupled to a first input of a phase detector, a clock input configured to receive a clock signal, and an output coupled to one of one or more discharge circuits.

[0191] 29. The apparatus of Clause 28, wherein the clock signal comprises the output signal of a voltage-controlled oscillator (VCO).

[0192] 30. The apparatus of Clause 28 or 29, comprising a selection input, each multiplexer configured to receive each bit of a digital code, and each multiplexer configured to select either the first input or the second input of the multiplexer based on the bit value of each bit, and to combine the selected inputs to their respective outputs.

[0193] 31. Voltage-controlled oscillator (VCO),

[0194] A loop filter is coupled between the difference circuit and the VCO input,

[0195] The system further comprises a frequency divider coupled between the output of the VCO and the second input of the phase detector.

[0196] One of the devices specified in clauses 28-30.

[0197] 32. Each of the one or more discharge circuits is

[0198] Each transistor and

[0199] One of the devices according to clauses 8 to 31, comprising a sampling capacitor and a resistor coupled between each transistor.

[0200] 33. The apparatus of clause 32, further comprising a phase detector, wherein, with respect to each of one or more discharge circuits, the gate of each transistor is coupled to the output of the phase detector.

[0201] 34. A phase detector having a first input, a second input, and an output, wherein the first input is configured to receive a reference signal and the output is coupled to one or more discharge circuits,

[0202] Voltage-controlled oscillator (VCO),

[0203] A loop filter is coupled between the difference circuit and the VCO input,

[0204] The system further comprises a frequency divider coupled between the output of a VCO and a second input of a phase detector, the frequency divider being configured to divide the output signal of the VCO in order to generate a feedback signal.

[0205] Any one of the devices specified in clauses 8-21, 32, and 33.

[0206] 35. The apparatus of clause 34, wherein the phase detector is configured to generate a phase error signal indicating the phase error between a reference signal and a feedback signal.

[0207] 36. The apparatus of clause 35, wherein the phase error signal comprises one or more pulses, and each of one or more discharge circuits is driven by one of the one or more pulses.

[0208] 37. The apparatus of clause 36, wherein one or more pulses comprise a first pulse and a second pulse, and a phase detector is configured to selectively output either the first pulse or the second pulse to each of one or more discharge circuits.

[0209] 38. The phase detector comprises a delay circuit configured to generate a delayed feedback signal based on a feedback signal,

[0210] The phase detector is further configured to generate a first pulse based on the phase error between a reference signal and a feedback signal, and to generate a second pulse based on the phase error between the reference signal and a delayed feedback signal.

[0211] The apparatus of Article 37.

[0212] 39. A sampling method,

[0213] Charge the sampling capacitor to the supply voltage,

[0214] To generate the sampling voltage, a portion of the charge on the sampling capacitor is discharged based on the phase error,

[0215] Generating a reference voltage based on the supply voltage,

[0216] A method comprising generating a differential voltage between a sampling voltage and a reference voltage.

[0217] 40. The method of Clause 39, wherein generating a reference voltage comprises charging at least one capacitor to a supply voltage.

[0218] 41. Discharging a portion of the charge on the sampling capacitor based on the phase error,

[0219] Receiving a phase error signal indicating a phase error,

[0220] The method of clause 39 or 40, comprising driving one or more discharge circuits with a phase error signal, wherein one or more discharge circuits are coupled to a sampling capacitor.

[0221] 42. Each of the one or more discharge circuits is

[0222] Each transistor and

[0223] The method of clause 41, comprising a sampling capacitor and a resistor coupled between each transistor.

[0224] 43. The method of clause 42, wherein the phase error signal comprises one or more pulses, and each transistor of one or more discharge circuits is driven by one of the one or more pulses.

[0225] 44. To generate a reference voltage,

[0226] Charge the first capacitor to the supply voltage,

[0227] Discharging the second capacitor,

[0228] One of the methods from clauses 39 to 43, comprising sharing a charge between a first capacitor and a second capacitor in order to generate a reference voltage.

[0229] 45. Generating the difference voltage between the sampling voltage and the reference voltage is

[0230] Turning on the first switch, which is coupled between the sampling capacitor and the first terminal of the first capacitor,

[0231] The method of clause 44, comprising turning on a second switch coupled between the output of a sampler and the second terminal of a first capacitor.

[0232] 46. ​​Charging the first capacitor to the supply voltage,

[0233] Turning on the precharge switch, which is coupled between the supply voltage and the sampling capacitor,

[0234] The method of clause 45, comprising turning on a first switch.

[0235] 47. One of the methods from clauses 39 to 46, wherein generating a differential voltage between a sampling voltage and a reference voltage comprises subtracting the reference voltage from the sampling voltage.

[0236] 48. A device for sampling,

[0237] A means for charging the sampling capacitor to the supply voltage,

[0238] Means for discharging a portion of the charge on a sampling capacitor based on the phase error in order to generate a sampling voltage,

[0239] Means for generating a reference voltage based on the supply voltage,

[0240] An apparatus comprising means for generating a differential voltage between a sampling voltage and a reference voltage.

[0241] 49. The apparatus of Clause 48, wherein the means for generating a reference voltage comprises means for charging at least one capacitor to a supply voltage.

[0122]

[0242] Within the scope of this disclosure, the term “exemplary” is used to mean “serving as an example, illustration, or representation.” No implementation or aspect described herein as “exemplary” should necessarily be construed as being preferable or advantageous to any other aspect of this disclosure. Similarly, the term “aspect” does not require that all aspects of this disclosure include the features, advantages, or modes of operation discussed. The term “coupled” is used herein to refer to a direct or indirect electrical coupling between two structures. Also, the term “earthing” may refer to DC earthing or alternating current (AC) earthing, and therefore should be understood as encompassing both possibilities.

[0123]

[0243] The above description in this disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to this disclosure will be readily apparent to a person skilled in the art, and the general principles defined herein can be applied to other modifications without departing from the spirit or scope of this disclosure. Therefore, this disclosure is not intended to be limited to the embodiments described herein, but should be given the broadest scope consistent with the principles and novel features disclosed herein. The invention described in the original claims of this application is listed below. [C1] It is a sampler, A sampling capacitor and A precharge switch coupled to the sampling capacitor, One or more discharge circuits coupled to the sampling capacitor, A reference voltage circuit coupled to the sampling capacitor, and in this case, the reference voltage circuit A reference voltage is generated based on the supply voltage. A sampler comprising a device configured to generate a voltage difference between the voltage on the sampling capacitor and the reference voltage. [C2] The sampler according to C1, wherein the precharge switch is coupled between a voltage regulator and the sampling capacitor, and the voltage regulator is configured to supply the supply voltage. [C3] Each of the one or more discharge circuits is Each transistor and The sampler according to C1, comprising the sampling capacitor and each of the transistors, each of which is coupled to a resistor. [C4] The sampler according to C3, wherein, with respect to each of the one or more discharge circuits, the gate of each transistor is coupled to a phase detector. [C5] The above reference voltage circuit, At least one capacitor, The sampler according to C1, comprising the sampling capacitor and a difference circuit coupled to the at least one capacitor, wherein the difference circuit is configured to generate the voltage difference. [C6] Further comprising a first switch and a second switch, the at least one capacitor is coupled to the first capacitor which is coupled to the difference circuit, The sampler according to C5, further comprising a second capacitor, wherein the first switch is coupled between the first capacitor and the second capacitor, and the second switch is coupled in parallel with the second capacitor. [C7] The one or more discharge circuits are coupled to a phase detector, The difference circuit is coupled to the filter. Sampler as described in C5. [C8] A device, A sampling capacitor and A precharge switch coupled to the sampling capacitor, One or more discharge circuits coupled to the sampling capacitor, A reference voltage circuit coupled to the sampling capacitor, and in this case, the reference voltage circuit The first capacitor and, The second capacitor, A first switch coupled between the first capacitor and the second capacitor, A second switch is connected in parallel with the second capacitor, An apparatus comprising the sampling capacitor and a difference circuit coupled to the first capacitor. [C9] The apparatus according to C8, further comprising a voltage regulator, wherein the precharge switch is coupled between the voltage regulator and the sampling capacitor. [C10] The apparatus according to C8, further comprising a controller, wherein in the pre-charge phase, the controller is configured to turn on the pre-charge switch, turn off the first switch, and turn on the second switch. [C11] The apparatus according to C10, wherein, during the charge sharing stage, the controller is configured to turn off the precharge switch, turn on the first switch, and turn off the second switch. [C12] The difference circuit is A third switch is coupled between the sampling capacitor and the first terminal of the first capacitor, The apparatus according to C8, further comprising a fourth switch coupled between the second terminal of the first capacitor and the output of the sampler. [C13] The apparatus according to C12, further comprising a controller, wherein in the pre-charge phase, the controller is configured to turn on the pre-charge switch, turn off the first switch, turn on the second switch, turn on the third switch, and turn off the fourth switch. [C14] The apparatus according to C13, wherein, during the charge sharing stage, the controller is configured to turn off the precharge switch, turn on the first switch, turn off the second switch, turn off the third switch, and turn off the fourth switch. [C15] The apparatus according to C13, wherein, during the sampling stage, the controller is configured to turn off the precharge switch, the third switch, and the fourth switch. [C16] The apparatus according to C13, wherein in the differential stage, the controller is configured to turn off the precharge switch, turn off the second switch, turn on the third switch, and turn on the fourth switch. [C17] The apparatus according to C12, further comprising a fifth switch which is coupled between the second terminal of the first capacitor and ground to the reference voltage circuit. [C18] The apparatus according to C8, further comprising a second precharge switch coupled to the first capacitor. [C19] The apparatus according to C18, further comprising a voltage regulator, wherein the first precharge switch is coupled between the voltage regulator and the sampling capacitor, and the second precharge switch is coupled between the voltage regulator and the first capacitor. [C20] The apparatus according to C18, further comprising a controller, wherein in the pre-charge phase, the controller is configured to turn on the first pre-charge switch, turn on the second pre-charge switch, turn off the first switch, and turn on the second switch. [C21] The apparatus according to C20, wherein, during the charge sharing stage, the controller is configured to turn off the first precharge switch, turn off the second precharge switch, turn on the first switch, and turn off the second switch. [C22] The apparatus according to C8, further comprising a phase detector having an output coupled to one or more discharge circuits. [C23] Voltage-controlled oscillator (VCO), A loop filter is coupled between the difference circuit and the input of the VCO, A frequency divider is coupled between the output of the VCO and the input of the phase detector, The apparatus described in C22, further comprising the above. [C24] The phase detector has a first input configured to receive a reference signal and a second input configured to receive a feedback signal, and the phase detector has a delay circuit having an input coupled to the second input of the phase detector and an output, A first pulse circuit having a first input coupled to the first input of the phase detector, a second input coupled to the second input of the phase detector, and an output; a second pulse circuit having a first input coupled to the first input of the phase detector, a second input coupled to the output of the delay circuit, and an output; The apparatus according to C22, comprising a plurality of multiplexers, each multiplexer having a first input coupled to the output of the first pulse circuit, a second input coupled to the output of the second pulse circuit, and an output coupled to each of the one or more discharge circuits. [C25] The apparatus according to C24, each multiplexer having a selection input configured to receive each bit of a digital code, and each multiplexer being configured to select either the first input or the second input of the multiplexer based on the bit value of the respective bit, and to couple the selected input to the respective output. [C26] The phase detector has a first input configured to receive a reference signal and a second input configured to receive a feedback signal, and the phase detector has a delay circuit having an input coupled to the second input of the phase detector and an output, A plurality of multiplexers, each having a first input coupled to the second input of the phase detector, a second input coupled to the output of the delay circuit, and an output. The apparatus according to C22, comprising a plurality of flip-flops, each flip-flop having a signal input coupled to one of the outputs of the plurality of multiplexers, a reset input coupled to the first input of the phase detector, a clock input configured to receive a clock signal, and an output coupled to one of the one or more discharge circuits. [C27] The apparatus according to C26, each multiplexer having a selection input configured to receive each bit of a digital code, and each multiplexer being configured to select the respective first input or the respective second input of the multiplexer based on the bit value of the respective bit, and to couple the selected input to the respective output. [C28] Each of the one or more discharge circuits is Each transistor and The apparatus according to C8, comprising the sampling capacitor and each of the transistors, each of which is coupled to a resistor. [C29] The apparatus according to C28, further comprising a phase detector, wherein with respect to each of the one or more discharge circuits, the gate of each transistor is coupled to the output of the phase detector. [C30] A phase detector having a first input, a second input, and an output, wherein the first input is configured to receive a reference signal and the output is coupled to one or more discharge circuits. Voltage-controlled oscillator (VCO), A loop filter is coupled between the difference circuit and the input of the VCO, A frequency divider is coupled between the output of the VCO and the second input of the phase detector, wherein the frequency divider is configured to divide the output signal of the VCO in order to generate a feedback signal. The apparatus described in C8, further comprising the above. [C31] A sampling method, Charge the sampling capacitor to the supply voltage, To generate a sampling voltage, a portion of the charge on the sampling capacitor is discharged based on the phase error, To generate a reference voltage based on the aforementioned supply voltage, A method comprising generating a difference voltage between the sampling voltage and the reference voltage. [C32] The method according to C31, wherein generating the reference voltage comprises charging at least one capacitor to the supply voltage. [C33] To generate the aforementioned reference voltage, The first capacitor is charged to the supply voltage, Discharging the second capacitor, The method for C31, comprising sharing charge between the first capacitor and the second capacitor in order to generate the reference voltage. [C34] The difference voltage between the sampling voltage and the reference voltage is generated. Turning on the first switch which is coupled between the sampling capacitor and the first terminal of the first capacitor, The method of C33, comprising turning on a second switch coupled between the output of the sampler and the second terminal of the first capacitor. [C35] Charging the first capacitor to the supply voltage Turning on the precharge switch coupled between the supply voltage and the sampling capacitor, The method according to C34, comprising turning on the first switch. [C36] The method according to C31, wherein generating the difference voltage between the sampling voltage and the reference voltage is performed by subtracting the reference voltage from the sampling voltage. [C37] A device for sampling, A means for charging the sampling capacitor to the supply voltage, Means for discharging a portion of the charge on the sampling capacitor based on the phase error in order to generate a sampling voltage, Means for generating a reference voltage based on the aforementioned supply voltage, An apparatus comprising means for generating a difference voltage between the sampling voltage and the reference voltage. [C38] The apparatus according to C37, wherein the means for generating the reference voltage comprises means for charging at least one capacitor to the supply voltage.

Claims

1. It is a device, A sampling capacitor and A precharge switch coupled to the sampling capacitor, One or more discharge circuits coupled to the sampling capacitor, The circuit comprises a reference voltage circuit coupled to the sampling capacitor, The sampling capacitor is precharged with a supply voltage, and one or more discharge circuits discharge the sampling capacitor to generate a sampling voltage. The aforementioned reference voltage circuit The first capacitor and, The second capacitor, A first switch coupled between the first capacitor and the second capacitor, A second switch is connected in parallel with the second capacitor, The sampling capacitor and the difference circuit coupled to the first capacitor are provided, The reference voltage circuit generates a reference voltage based on the supply voltage, and the difference circuit generates a voltage difference between the sampling voltage and the reference voltage. Device.

2. A voltage regulator wherein the precharge switch is coupled between the voltage regulator and the sampling capacitor, The apparatus according to claim 1, further comprising the following:

3. A controller configured such that, in the pre-charge stage, the controller turns on the pre-charge switch, turns off the first switch, and turns on the second switch, and in the charge sharing stage, the controller turns off the pre-charge switch, turns on the first switch, and turns off the second switch. The apparatus according to claim 1, further comprising the following:

4. The difference circuit, A third switch is coupled between the sampling capacitor and the first terminal of the first capacitor, The apparatus according to claim 1, further comprising: a fourth switch coupled between the second terminal of the first capacitor and the output of the apparatus.

5. The system further includes a controller, which is configured to turn on the precharge switch, turn off the first switch, turn on the second switch, turn on the third switch, and turn off the fourth switch during the precharge phase. During the charge sharing phase, the controller is configured to turn off the precharge switch, turn on the first switch, turn off the second switch, turn off the third switch, and turn off the fourth switch, or During the sampling phase, the controller is configured to turn off the precharge switch, the third switch, and the fourth switch, or The apparatus according to claim 4, wherein, in the differential stage, the controller is configured to turn off the precharge switch, turn off the second switch, turn on the third switch, and turn on the fourth switch.

6. The apparatus according to claim 4, further comprising a fifth switch coupled between the second terminal of the first capacitor and ground in the reference voltage circuit.

7. The present invention further comprises a second precharge switch coupled to the first capacitor, The system further comprises a voltage regulator, wherein the precharge switch is coupled between the voltage regulator and the sampling capacitor, and the second precharge switch is coupled between the voltage regulator and the first capacitor, or The system further includes a controller, which is configured to turn on the precharge switch, turn on the second precharge switch, turn off the first switch, and turn on the second switch during the precharge phase, or The apparatus according to claim 1, wherein, during the charge sharing stage, the controller is configured to turn off the precharge switch, turn off the second precharge switch, turn on the first switch, and turn off the second switch.

8. The apparatus according to claim 1, further comprising a phase detector having an output coupled to one or more discharge circuits.

9. Voltage-controlled oscillator (VCO), A loop filter is coupled between the difference circuit and the input of the VCO, A frequency divider is coupled between the output of the VCO and the input of the phase detector, The apparatus according to claim 8, further comprising the following:

10. The phase detector has a first input configured to receive a reference signal and a second input configured to receive a feedback signal, and the phase detector has, A delay circuit having an input coupled to the second input of the phase detector and an output, A first pulse circuit having a first input coupled to the first input of the phase detector, a second input coupled to the second input of the phase detector, and an output, A second pulse circuit having a first input coupled to the first input of the phase detector, a second input coupled to the output of the delay circuit, and an output, A plurality of multiplexers, each having a first input coupled to the output of the first pulse circuit, a second input coupled to the output of the second pulse circuit, and an output coupled to one of the one or more discharge circuits, Equipped with, The apparatus according to claim 8, wherein each multiplexer has a selection input configured to receive each bit of a digital code, and each multiplexer is configured to select either the first input or the second input of the multiplexer based on the bit value of the respective bit, and to couple the selected input to the respective output.

11. The phase detector has a first input configured to receive a reference signal and a second input configured to receive a feedback signal, and the phase detector has, A delay circuit having an input coupled to the second input of the phase detector and an output, A plurality of multiplexers, each having a first input coupled to the second input of the phase detector, a second input coupled to the output of the delay circuit, and an output. A plurality of flip-flops, each having a signal input coupled to one of the outputs of the plurality of multiplexers, a reset input coupled to the first input of the phase detector, a clock input configured to receive a clock signal, and an output coupled to one of the one or more discharge circuits, Equipped with, The apparatus according to claim 8, wherein each multiplexer has a selection input configured to receive each bit of a digital code, and each multiplexer is configured to select either the first input or the second input of the multiplexer based on the bit value of the respective bit, and to couple the selected input to the respective output.

12. Each of the one or more discharge circuits is Each transistor and The sampling capacitor and each of the transistors are coupled with their respective resistors, The apparatus according to claim 1, further comprising a phase detector, wherein with respect to each of the one or more discharge circuits, the gate of each transistor is coupled to the output of the phase detector.

13. A phase detector having a first input, a second input, and an output, wherein the first input is configured to receive a reference signal, and the output is coupled to one or more discharge circuits. Voltage-controlled oscillator (VCO), A loop filter is coupled between the difference circuit and the input of the VCO, A frequency divider is coupled between the output of the VCO and the second input of the phase detector, wherein the frequency divider is configured to divide the output signal of the VCO in order to generate a feedback signal. The apparatus according to claim 1, further comprising the following:

14. A sampling method, Charge the sampling capacitor to the supply voltage, To generate a sampling voltage, a portion of the charge on the sampling capacitor is discharged based on the phase error, To generate a reference voltage based on the aforementioned supply voltage, To generate the difference voltage between the sampling voltage and the reference voltage, The system is equipped with the ability to generate the reference voltage, The first capacitor is charged to the supply voltage, Discharging the second capacitor, In order to generate the aforementioned reference voltage, the first capacitor and the second capacitor share charge, A method that includes [a certain feature].

15. Generating the aforementioned reference voltage comprises charging at least one capacitor to the aforementioned supply voltage, or The method according to claim 14, wherein generating the difference voltage between the sampling voltage and the reference voltage is performed by subtracting the reference voltage from the sampling voltage.

16. The difference voltage between the sampling voltage and the reference voltage is generated. Turning on the first switch which is coupled between the sampling capacitor and the first terminal of the first capacitor, Turning on the second switch, which is coupled between the output of the sampler and the second terminal of the first capacitor, The first capacitor is charged to the supply voltage, Turning on the precharge switch coupled between the supply voltage and the sampling capacitor, Turning on the first switch, The method according to claim 14, comprising:

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