Lead frame capacitor

Abstract

The electronic device (100) includes a package structure (120) having conductive leads (102), first and second dies (106, 108) within the package structure (120), and first and second conductive plates (104, 105) electrically coupled to the respective first and second dies (106, 108), spaced apart from each other, and having respective first and second sides (110, 114) directly facing each other. A portion of the package structure (120) extends between the first side (110) of the first conductive plate (104) and the second side (114) of the second conductive plate (105) to form capacitors (C1, C2). The other side of the first conductive plate (104) does not directly face the side of the second conductive plate (105), and the other side of the second conductive plate (105) does not directly face the side of the first conductive plate (104).

Description

Technical Field

[0001] Signal insulation is used in various applications where signal transmission has to cross an insulating barrier, for example, between circuits of different voltage domains. Integrating insulating components into a manufactured semiconductor die involves using silicon dioxide as a dielectric material for a capacitive insulating barrier with galvanic insulation, which adds cost and complexity to the manufacturing process. Capacitors are formed within the silicon metal layer during the silicon wafer manufacturing process, and the capacitor structure depends on the geometry and design rules of a particular manufacturing process node. Also, device design often can only be fabricated using a subset of process nodes with qualified insulating components in a given manufacturing facility. Structures manufactured at each identified process node require insulation qualification and certification, resulting in high costs. Integrated insulating components often require special development by the process team and often employ special design rules. Some applications may use a wafer manufacturing process optimized for specific needs such as high power and / or high voltage, but these processes may not be compatible with robust insulation dielectric requirements. New designs often cannot utilize processes optimized for specific needs such as power and high voltage without redesigning the insulating components for those manufacturing process nodes and subsequent insulation requalification and certification. Also, integrating insulating components in semiconductor wafer manufacturing can lead to a relatively large minimum die size for the insulating die.

Summary of the Invention

[0002] In one embodiment, the electronic device includes an insulating structure created using a patterned lead frame to provide a low-cost, compact insulating solution that does not affect the semiconductor wafer manufacturing process and does not require additional substrate-level components. In one example, the electronic device includes a package structure having conductive leads, first and second dies within the package structure, and first and second conductive plates having first and second sides that are electrically coupled to the respective first and second dies, spaced apart from each other and facing each other directly, wherein a portion of the package structure extends between the first side of the first conductive plate and the second side of the second conductive plate to form a capacitor. The other side of the first conductive plate does not face the side of the second conductive plate, and the other side of the second conductive plate does not face the side of the first conductive plate.

[0003] In one example, the first side of the first conductive plate extends in a first plane, the second side of the second conductive plate extends in a second plane, and the first and second planes are parallel to each other. In one example, the first and second conductive plates are coplanar in a third plane perpendicular to the first and second planes. In one implementation, the package structure has first and second opposing sides spaced apart from each other along a first direction, conductive leads spaced apart from each other along a perpendicular second direction, and the second side of the second conductive plate is spaced apart from the first side of the first conductive plate along one of the first and second directions.

[0004] In another example, the second side of the second conductive plate is spaced apart from the first side of the first conductive plate along a third direction perpendicular to the first and second directions. In one implementation, the first conductive plate has a first portion having a first side and a second portion, and the first and second portions of the first conductive plate are not coplanar. Also in another example, the second conductive plate has a first portion having a second side and a second portion, and the first and second portions of the second conductive plate are not coplanar. In another implementation, the electronic device further includes an embedded dielectric insert within the package structure, and the first or second conductive plate is on or within the embedded dielectric insert. In one implementation, multiple conductive plates are on or within the embedded dielectric insert.

[0005] Another embodiment relates to a method comprising arranging a lead frame, performing connection and molding processes, and a separation process. The lead frame is arranged such that the first side of the first conductive plate is spaced apart from and directly faces the second side of the second conductive plate, the other side of the first conductive plate does not directly face the side of the second conductive plate, and the other side of the second conductive plate does not directly face the side of the first conductive plate. In one example, the connection process electrically connects a first bond wire to the first die and the first conductive plate, and a second bond wire electrically connects a second die and the second conductive plate. The molding process forms a package structure enclosing the first and second dies, the first and second bond wires, and portions of the first and second conductive plates. The separation process separates the first conductive plate, the second conductive plate, and the conductive leads from the rest of the lead frame.

[0006] In one example, positioning a lead frame includes positioning the first lead frame relative to a second lead frame or dielectric insert such that the first side of the first conductive plate of the first lead frame is spaced apart from and directly faces the second side of the second conductive plate of the second lead frame or dielectric insert. In one implementation, positioning a lead frame includes positioning the first lead frame relative to a dielectric insert such that the first side of the first conductive plate of the first lead frame is spaced apart from and directly faces the second side of the second conductive plate of the dielectric insert. This implementation also includes positioning the second lead frame relative to a dielectric insert such that the first side of the third conductive plate of the second lead frame is spaced apart from and directly faces the second side of the fourth conductive plate of the dielectric insert, with the other side of the third conductive plate not directly facing the side of the fourth conductive plate, and the other side of the fourth conductive plate not directly facing the side of the third conductive plate.

[0007] Another embodiment relates to a system having first and second electronic circuits or different voltage domains, and an insulating device coupled to the first and second electronic circuits. The insulating device includes a package structure having conductive leads, first and second dies within the package structure, and first and second conductive plates electrically coupled to the respective first and second dies, spaced apart from each other and having respective first and second sides facing each other, wherein a portion of the package structure extends between the first side of the first conductive plate and the second side of the second conductive plate to form a capacitor. The other side of the first conductive plate does not directly face the side of the second conductive plate, and the other side of the second conductive plate does not directly face the side of the first conductive plate.

[0008] In one example, the first side of the first conductive plate extends in a first plane, the second side of the second conductive plate extends in a second plane, the first and second planes are parallel to each other, and the first and second conductive plates lie on the same plane in a third plane perpendicular to the first and second planes.

[0009] In another example, the first conductive plate has a first portion having a first side and a second portion, and the first and second portions of the first conductive plate are on the same plane.

[0010] In another example, the insulating device includes an embedded dielectric insert within a package structure, where one of a first conductive plate and a second conductive plate is located on or within the embedded dielectric insert. [Brief explanation of the drawing]

[0011] [Figure 1] This is a cutaway top view of a packaged electronic device comprising first and second semiconductor dies and an insulating capacitor formed by a planar conductive plate from a starting lead frame.

[0012] [Figure 2] Figure 1 is a schematic diagram of the circuitry mounted on the semiconductor die and insulating capacitor within the packaged electronic device.

[0013] [Figure 3] This is a flowchart showing the process for manufacturing packaged electronic devices.

[0014] [Figure 4] Figure 3 shows partial plan views of the packaged electronic device shown in Figure 1 at various stages of manufacturing according to the method described in Figure 3. [Figure 5] Figure 3 shows partial plan views of the packaged electronic device shown in Figure 1 at various stages of manufacturing according to the method described in Figure 3. [Figure 6] Figure 3 shows partial plan views of the packaged electronic device shown in Figure 1 at various stages of manufacturing according to the method described in Figure 3. [Figure 7] Figure 3 shows partial plan views of the packaged electronic device shown in Figure 1 at various stages of manufacturing according to the method described in Figure 3.

[0015] [Figure 8] Perspective views of the packaged electronic devices of FIGS. 1, 2, and 4-7.

[0016] [Figure 9] Top perspective view of another exemplary packaged electronic device having first and second semiconductor dies and an insulating capacitor having a conductive plate vertically spaced from first and second starting lead frames.

[0017] [Figure 10] Top perspective view of first and second starting lead frames used in manufacturing the packaged electronic device of FIG. 9.

[0018] [Figure 11] Top perspective view of another exemplary packaged electronic device having first and second semiconductor dies, a conductive plate vertically spaced from first and second starting lead frames, and an insulating capacitor having an insert with additional conductive capacitor plates.

[0019] [Figure 12] Top perspective view of first and second starting lead frames and an insert structure used in manufacturing the packaged electronic device of FIG. 11.

[0020] [Figure 13] Schematic diagram of a power conversion system having insulated primary and secondary circuits and a control or feedback signal path including the packaged electronic device of FIG. 1.

BEST MODE FOR CARRYING OUT THE INVENTION

[0021] In the drawings, like reference numerals throughout indicate like elements, and various features The figures are not necessarily drawn to a fixed scale. Furthermore, the term "coupled" includes indirect or direct electrical or mechanical connections or combinations thereof. For example, when a first device couples with or is coupled to a second device, the connection may be via a direct electrical connection or via an indirect electrical connection through one or more intervening devices and connections. The operating characteristics of one or more of the various circuits, systems, and / or components are described below in the context of the functions that arise in some cases from the configuration and / or interconnections of various structures when the circuit elements are powered and operating.

[0022] Figure 1 shows a packaged electronic device 100 having conductive features formed from a start lead frame 101 (e.g., copper wire, aluminum, etc.), which includes conductive leads 102, a pair of first conductive plates 104, and a pair of second conductive plates 105. In another example, only a single first conductive plate 104 and a single second conductive plate 105 are included. In yet another example, two or more first conductive plates 104 and two or more second conductive plates 105 are included. The electronic device further includes a first die mounting pad 106 and a second die mounting pad 107, which are also originally part of the start lead frame 101 under manufacture. The electronic device 100 includes a first die 108 mounted on the first die mounting pad 106 and a second die 109 mounted on the second die mounting pad 107. In this example, each of the first conductive plates 104 includes a first side portion 110. Dies 108 and 109 may be any suitable semiconductor-based circuit dies, such as those formed by semiconductor processing of a starting wafer, which include transistors, resistors, capacitors, or other electronic components integrated into a die structure having conductive features (e.g., copper or aluminum bond pads) that enable bond wires or flip-chip electrical connections.

[0023] The electronic device 100 further includes electrical connections between the first and second dies 108, 109 and various leads and conductive plates. In the illustrated implementation, bond wires 111 connect conductive features (e.g., bond pads) of the first die 108 to each of the first set of conductive leads 102, thereby making an electrical circuit connection to a host printed circuit board (not shown) to which the electronic device 100 is soldered. Other bond wires 111 connect conductive features of the second die 109 to the second set of conductive leads 102. In the illustrated implementation, the first set of conductive leads 102 coupled to the first die 108 is on the first side of the electronic device 100 (e.g., the left side in Figure 1), and the second set of conductive leads 102 coupled to the second die 109 is on the opposite second side of the electronic device 100 (e.g., the right side in Figure 1), but this is not a strict requirement for all possible implementations. The electronic device 100 also includes a pair of first bond wires 112, each of which is bonded between a conductive feature of the first die 108 and one of the first conductive plates 104. Additionally, a pair of second bond wires 113 are each bonded between a conductive feature of the second die 109 and one of the second conductive plates 105.

[0024] In this example, each second conductive plate 105 has a second side 114. In one example, the first side 110 of each conductive plate 104 extends in a first plane (e.g., the YZ plane in Figure 1, where the Z direction is outside the plane of the paper in the figure). In this example, the second side 114 of each second conductive plate 105 extends in a second plane (e.g., also the YZ plane), and the first and second planes are parallel to each other. In other examples, the first and second planes are not strictly parallel to each other. In yet another example, one or both sides 110 and / or 114 are not planes. In the illustrated implementation, each second side 114 of the second conductive plate 105 is spaced apart from and directly faces the first side 110 of each first conductive plate 104. Furthermore, the other sides of the first conductive plate 104 do not directly face the sides of the respective second conductive plates 105, and the other sides of the respective second conductive plates 105 do not directly face the sides of the respective first conductive plates 104. When used herein, the directly facing sides are conductive plate sides that face each other in a straight line without the intervening conductive structure. The electronic device 100 further includes a non-conductive package structure 120. In one example, the package structure 120 is or includes a molding compound. A portion of the package structure 120 extends between the first side 110 of each first conductive plate 104 and the second side 114 of each second conductive plate 105 to form the respective capacitors Cl and C2, as schematically shown by dashed lines in Figure 1. The intervening package structure 120 between the respective plate sides 110 and 114 provides a dielectric that, together with the conductive material of the respective plates 104 and 105, forms a capacitor structure that acts to insulate the first and second circuits of the first and second dies 108 and 109. In the operation of the electronic device 100, the exemplary capacitors C1 and C2 provide galvanic capacitive isolation between the first and second voltage domains of the respective first and second dies 108 and 109.

[0025] In other implementations, a single insulating capacitor is provided within the electronic device 100 using corresponding first and second plates 104 and 105, along with their respective first and second sides 110 and 114. In other examples, three or more insulating capacitors are provided by the arrangement of the corresponding sides 110 and 114 of the respective first and second plates 104 and 105, where the first side 110 of the first conductive plate 104 is spaced apart from and directly faces the second side 114 of the second conductive plate 105, the other side of the first conductive plate 104 does not directly face the side of the second conductive plate 105, and the other side of the second conductive plate 105 does not directly face the side of the first conductive plate 104.

[0026] In one example, as shown in Figure 1, a single starting lead frame 101 is used to create the first and second conductive plates 104 and 105. In this example, the first conductive plate 104 and the second conductive plate 105 are coplanar in a third plane (e.g., the XY plane) perpendicular to the first and second planes of their respective plate surfaces 110 and 114, but this is not a requirement for all possible implementations. In the example in Figure 1, further insulation is provided between the respective plates 104 and 105 and between the first and second voltage domains of the respective first and second dies 108 and 109 along the lateral direction. In other implementations, for example, vertical capacitor plate spacing and insulation direction are provided, as shown and described below in relation to Figures 9 to 12. In the example in Figure 1, the package structure 120 has first and second opposing sides along which each lead 102 is positioned, and the first and second sides of the package structure 120 are spaced apart from each other along a first direction (e.g., the X direction in Figure 1), with portions of the conductive leads 102 exposed to the outside of the package structure 120 along each of the first and second sides of the package structure 120. In one example, the leads are generally coplanar with the outside of the package structure 120 and partially exposed along the bottom and sides, as in the case of leadless package types including quad flat no-lead (QFN) packages or pre-molded packages such as MIS, RLF, etc. In this example, the conductive leads 102 are spaced apart from each other along a second direction (e.g., the Y direction in Figure 1) along each of the first and second sides of the package structure 120, where the second direction Y is perpendicular to the first direction X. Furthermore, in the illustrated example, the second side portion 114 of the second conductive plate 105 is spaced apart from the first side portion 110 of the first conductive plate 104 along the first direction X. In other examples, lateral capacitor plate spacings are possible along different directions in the XY plane, such as along the first (Y) direction.

[0027] Figure 2 shows an isolated communication circuit 200 implemented within semiconductor dies 108 and 109 and isolation capacitors C1 and C2 in the packaged electronic device 100 of Figure 1. In a particular application, capacitors C1 and C2 in Figure 1 provide a single or multi-channel digital isolator created using a custom patterned lead frame 101. In operation, one or more signals are transferred between different voltage domain circuits of the first die 108 and the second die 109 using lateral capacitive coupling between lead frame metal areas 104 and 105. The isolated communication circuit 200 includes, for example, a high-frequency data channel with a bandwidth from 100 kbps to 150 Mbps and a low-frequency channel with a bandwidth from DC to 100 kbps. In one exemplary implementation, a single-ended input signal entering the high-frequency data channel is split into differential signals via an inverter gate at the input. The following capacitor-resistor network distinguishes the signal into small, narrow transients, which are converted into rail-to-rail differential pulses by two comparators. The comparator outputs drive a NOR gate flip-flop with an output that supplies power to a multiplexer. Decision logic (DCL) at the drive output of the flip-flop measures the duration between signal transients. If the duration between two consecutive transients exceeds a certain time limit (for example, in the case of a low-frequency signal), the DCL forces the output multiplexer to switch from a high-frequency to a low-frequency channel. In one example, a low-frequency input signal is pulse-width modulated (PWM) using the carrier frequency of an internal oscillator to generate a sufficiently high frequency that can pass through a capacitive barrier. Once the input is modulated, a low-pass filter (LPF) removes the high-frequency carrier from the actual data before sending it to the output multiplexer. In this example, the mold compound or any other encapsulant used to form the package structure 120 acts as an insulating dielectric barrier with an insulating gap designed to provide a robust high dielectric strength barrier across humidity, temperature, and reliability stress conditions.The initial lead frame 101 can be patterned with a desired custom design for mutual capacitance for circuit performance as needed for a given circuit application. Capacitor isolation can be combined with any process manufacturing node for functional silicon or other semiconductor processing used to create dies 108 and 109. In this regard, the lead frame 101 can be adapted to a specific isolation application without changing the manufacturing process used to produce dies 108 and 109, and the manufacturing of semiconductor dies is simplified and cost-effective compared to integrated isolation component solutions. Furthermore, the described examples can be manufactured using existing package assembly processes and equipment, thereby providing a compact and cost-effective isolation solution.

[0028] See also Figures 3 to 7, Figure 3 shows a method 300 for manufacturing a packaged electronic device, and Figures 4 to 7 show an example 100 of the packaged electronic device of Figure 1 at various stages of manufacturing according to method 300. Method 300 begins in 302 of Figure 3 by positioning one or more lead frames, for example, the lead frame 101 of Figure 4, such that the first side 110 of the first conductive plate 104 is spaced apart from and directly facing the second side 114 of the second conductive plate 105, the other side of the first conductive plate 104 does not directly face the side of the second conductive plate 105, and the other side of the second conductive plate 105 does not directly face the side of the first conductive plate 104. In 304, a die mounting process is carried out, mounting the first die 108 onto the first die mounting pad and the second die 109 onto the second die mounting pad 107, as shown in Figure 5. Method 300 continues in 306 by performing a connection process. In one example shown in Figure 6, the connection process is a wire bonding process that electrically connects a first bond wire 112 to a first die 108 and a first conductive plate 104. The wire bonding process also electrically connects a second bond wire 113 to a second die 109 and a second conductive plate 105. In the example in Figure 6, the wire bonding process in 306 interconnects multiple bond wires 111, 112 and 113 between conductive features (e.g., bond pads) of dies 108 and 109 with leads 102 and / or conductive plates 104 and 105 to form an electrical circuit including insulating capacitors Cl and C2.

[0029] Method 300 continues with a molding process in 308 of Figure 3 to form a molded package structure 120. In the example in Figure 7, the molding process creates individual molded package structures 120 for each prospective electronic device area of ​​the lead frame assembly. Each individual package structure 120 in this example encloses a first die 108, a second die 109, a first bond wire 112, a second bond wire 112, a portion of the first conductive plate 104, and a portion of the second conductive plate 105. Some implementations also include lead trimming and forming operations in 310 of Figure 3, but this is not a strict requirement for all possible implementations. In 312, Method 300 further includes separating the first conductive plate 104, the second conductive plate 105, and the conductive leads 102 from the rest of the lead frame 101, for example, by laser cutting or sawing. Figure 8 shows an example of a separated packaged electronic device 100.

[0030] See also Figures 9 and 10, another illustrative packaged electronic device 900 in Figure 9 includes a lead frame-based insulating capacitor formed by the arrangement and positioning of conductive plates 104 and 105 of the respective first and second lead frames 1001 and 1002 shown in Figure 10. This example provides vertical capacitor plate spacing along the Z direction, with each first conductive plate 104 of the first lead frame 1001 having an upward-facing, substantially planar first side, and each corresponding second conductive plate 105 of the second lead frame 1002 having a downward-facing, substantially planar second side. The electronic device 900 in this example includes the aforementioned leads 102, die mounting pads 106 and 107, semiconductor dies 108 and 109, and a molded package structure 120, as well as bond wires (not shown in Figure 9) that provide interconnections between the die 108 and leads 102 and conductive plates 104 and 105, forming an electrical circuit having two isolated voltage domains and capacitor connections via four capacitors generated by four conductive plates 104 and four conductive plates 105, respectively, separated by the dielectric material of the package structure 120.

[0031] Similar to the electronic device 100 in Figure 1, each downward-facing second side of the second conductive plate 105 is spaced apart from and directly faces the upward-facing first side of each first conductive plate 104. Furthermore, the other sides of the first conductive plate 104 do not directly face the sides of each second conductive plate 105, and the other sides of each second conductive plate 105 do not directly face the sides of each first conductive plate 104. Also, in the examples of Figures 9 and 10, the package structure 120 has first and second opposing sides spaced apart from each other along a first direction X, and portions of the conductive leads 102 are exposed to the outside of the package structure 120 along the respective first and second sides of the package structure 120. The conductive leads 102 are also spaced apart from each other along a second direction Y along the respective first and second sides of the package structure 120. In this example, the second side of each second conductive plate 105 is spaced perpendicularly from the first side of each first conductive plate 104 along a third direction Z perpendicular to the first direction X and the second direction Y. In other implementations, the first and second conductive plates are spaced laterally from each other, such as along the Y direction.

[0032] As shown in Figure 10, each first conductive plate 104 has a first portion having a first side and a second portion joined to the first portion by a bent portion, and the first and second portions of each first conductive plate 104 are not on the same plane. Similarly, each second conductive plate 105 has a first portion including a second side and a second portion joined to the first portion by a bent portion, and the first and second portions of each second conductive plate 105 are not on the same plane. During manufacturing (for example, in 302 according to the above-exemplary method 300), the first lead frame 1001 is positioned relative to the second lead frame 1002 as shown in Figure 10, such that the first side of the first conductive plate 104 of the first lead frame 1001 is spaced apart from and directly facing the respective second sides of the second conductive plate 105 of the second lead frame 1002, the other side of the first conductive plate 104 does not directly face the respective sides of the second conductive plate 105, and the other side of the second conductive plate 105 does not directly face the side of the first conductive plate 104.

[0033] See also Figures 11 and 12, Figure 11 shows another exemplary packaged electronic device 1100 having first and second semiconductor dies 108 and 109, insulating capacitors having conductive plates perpendicularly spaced from first and second start lead frames 1101 and 1102, and a dielectric insert 1103 having additional first and second conductive capacitor plates 1104 and 1105, respectively. Figure 12 shows the first and second start lead frames 1101 and 1102 and the insert structure 1103 used in manufacturing the packaged electronic device 1100 of Figure 11. In one example, the insert structure 1103 has first and second top conductive plates 1104 and 1105, respectively, separated by a dielectric medium. The insert structures 1103, 1104, and 1105 can be manufactured by a variety of methods, including, but not limited to, dual-level laminate structures, pre-molded lead frames (PMLF), MIS, etc. In various implementations, one or more of the first conductive plate 1104 and the second conductive plate 1105 are located on or within the embedded dielectric insert 1103.

[0034] The electronic device 1100 has the aforementioned leads 102, die mounting pads 106 and 107, semiconductor dies 108 and 109, and a molded package structure 120, as well as bond wires 111, 112 and 113 that provide interconnections between the die 108 and the leads 102 and conductive plates 104, 1104, 105 and 1105, and forms an electrical circuit having two isolated voltage domains and capacitor connections via four conductive plates 104 and 105, respectively, separated by the dielectric of the package structure 120, and four capacitors generated by the associated conductive plates 1104 and 1105 of the insert structure 1103. In this example, the package structure 120 has first and second opposing sides spaced apart from each other along a first direction X, and portions of the conductive leads 102 are exposed to the outside of the package structure 120 along the respective first and second package structure sides. In this example, the conductive leads 102 are spaced apart from each other along the second direction Y, and the second sides of each second conductive plate 105, 1105 are spaced apart from the first sides of each first conductive plate 104, 1104 along the third direction Z. This example also provides vertical capacitor plate spacing, but this is not a strict requirement for all possible implementations using the insert structure.

[0035] During manufacturing (for example, in 302 according to the above-exemplary method 300), the first lead frame 1101, the second lead frame 1102, and the dielectric insert structure 1103 are positioned relative to each other such that the first side of the first conductive plate 104 of the first lead frame 1001 is spaced apart from and directly faces the respective second sides of the second conductive plate 1105 of the dielectric insert 1103, the other side of the first conductive plate 104 does not directly face the side of the second conductive plate 1105, and the other side of the second conductive plate 1105 does not directly face the side of the first conductive plate 104. The relative positioning at 302 in this example also provides that the first side of the third conductive plate 105 of the second lead frame 1102 is spaced apart from and directly facing the second side of the fourth conductive plate 1104 of the dielectric insert 1103, the other side of the third conductive plate 105 does not directly face the side of the fourth conductive plate 1104, and the other side of the fourth conductive plate 1104 does not directly face the side of the third conductive plate 105.

[0036] Figure 13 shows a power conversion system 1300 having isolated primary and secondary circuits and a control or feedback signal path including the packaged electronic device 100 of Figure 1. This example includes a DC power supply 1302 having an output coupled to a first end of the primary winding of an isolation transformer 1304. A second end of the primary winding is coupled to a primary-side switching circuit 1306. The secondary winding of the transformer 1304 is coupled to a secondary circuit 1308, for example, to implement a flyback switching power conversion system 1300. The secondary circuit 1308 is coupled to provide regulated output power for driving a load 1310. The electronic device 100 in this example is an isolation device that supplies feedback signals or switching control signals from the secondary circuit 1308 to the primary-side switching circuit 1306. In one example, the secondary circuit 1308 provides the isolation device 100 with a signal to the output or load-side voltage domain, for example, representing a zero crossing of the switching circuit coupled to the secondary winding of the transformer 1304. In this example, the isolation device 100 provides an isolation signal to the primary-side switching circuit 1306, which in turn initiates a new switching cycle to close the switch in order to allow current to flow through the primary winding of the transformer 1304. In another example, the secondary circuit 1308 provides the isolation device 100 with a feedback signal representing the output voltage or output current of the load 1310, and the primary-side switching circuit 1306 adjusts the output voltage or output current in a closed-loop manner according to the feedback signal from the isolation device 100.

[0037] The described examples provide a global, low-cost isolation solution for signal isolation, with applicability across package types and footprints. These examples can also be used to provide high-voltage isolation within a single package electronic device 100, 900, 1100 without the need to integrate capacitor isolation components on or within semiconductor dies 108 and 109, thereby reducing the cost and complexity of die manufacturing. Furthermore, the described electronic devices 100, 900, 1100 provide integration within the packaged electronic device itself, thereby reducing or avoiding the extra costs and substrate space associated with the use of optical couplers or other external isolation components. The described examples provide signal isolation using leadframe metal structures for solutions where the silicon manufacturing process is unknown. The resulting solutions also have a significantly lower cost than the integration of isolation components in the silicon manufacturing process. Additionally, the electronic devices 100, 900, and 1100 can be manufactured using existing leadframe manufacturing and assembly infrastructure and processes, and can be adapted to a wide variety of design and application examples. These isolation solutions can be extended to all leadframe and / or lamination-based package types and form factors while providing a robust isolation barrier. The examples described offer a technical solution to the traditional problems of high cost, long cycle times, and development limitations based on isolation technology, for individual design, qualification, and approval requirements for each process node, by eliminating isolation component dependency from the silicon manufacturing process node and integrating the isolation solution into the leadframe itself.

[0038] Modifications may be made to the described examples within the scope of the claims of the present invention, and other implementations are also possible.

Claims

1. It is an electronic device, A package structure having opposing first and second sides spaced apart from each other along a first direction, A conductive lead partially exposed to the outside of the package structure, including a portion exposed to the outside of the package structure along each of the first and second sides of the package structure, and spaced apart from each other along each of the first and second sides of the package structure in a second direction perpendicular to the first direction, Within the package structure, a first die is attached to a first die mounting pad, A second die is attached to a second die mounting pad within the package structure, A first conductive plate within the package structure, having a first side portion, and including a first part and a second part having the first side portion, wherein the first and second parts are not on the same plane, A second conductive plate in the package structure, having a second side that is spaced apart from the first side of the first conductive plate and directly faces the first side of the first conductive plate, wherein the second side of the second conductive plate is spaced apart from the first side of the first conductive plate along a third direction perpendicular to the first and second directions, Within the package structure, a first bond wire is bonded to the first die and the first conductive plate, A second bond wire is coupled to the second die and the second conductive plate within the package structure, Includes, A portion of the package structure extends between the first side of the first conductive plate and the second side of the second conductive plate to form a capacitor. An electronic device in which the other side of the first conductive plate does not directly face the side of the second conductive plate, and the other side of the second conductive plate does not directly face the side of the first conductive plate.

2. The electronic device according to claim 1, An electronic device in which the first side of the first conductive plate extends into a first plane, the second side of the second conductive plate extends into a second plane, and the first and second planes are parallel to each other.

3. The electronic device according to claim 2, An electronic device in which the first conductive plate and the second conductive plate lie on the same plane in a third plane perpendicular to the first and second planes.

4. The electronic device according to claim 1, An electronic device wherein the second conductive plate has a first part having a second side portion and a second part, and the first and second parts of the second conductive plate are not on the same plane.

5. The electronic device according to claim 1, An electronic device in which the first side of the first conductive plate extends into a first plane, the second side of the second conductive plate extends into a second plane, and the first and second planes are parallel to each other.

6. The electronic device according to claim 1, The package structure further includes an embedded dielectric insert, An electronic device in which one of the first conductive plate and the second conductive plate is on or within the embedded dielectric insert.

7. The electronic device according to claim 6, An electronic device further comprising a plurality of conductive plates on or within the embedded dielectric insert.

8. The electronic device according to claim 6, An electronic device in which the first side of the first conductive plate extends into a first plane, the second side of the second conductive plate extends into a second plane, and the first and second planes are parallel to each other.

9. The electronic device according to claim 1, An electronic device in which the first side of the first conductive plate extends into a first plane, the second side of the second conductive plate extends into a second plane, and the first and second planes are parallel to each other.

10. It is a system, A first electronic circuit in the first voltage domain, The second electronic circuit in the second voltage domain, An insulating device coupled to the first and second electronic circuits, Package structure and A set of first conductive leads partially exposed on the outside of the package structure, the set of first conductive leads coupled to the first electronic circuit, A set of second conductive leads partially exposed on the outside of the package structure, the set of second conductive leads coupled to the second electronic circuit, A first die, which is attached to a first die mounting pad within the package structure, and which is coupled to the first set of conductive leads, A second die, which is attached to a second die mounting pad within the package structure, and which is coupled to the set of second conductive leads, A first conductive plate within the package structure, having a first side portion, A second conductive plate within the package structure, the second conductive plate having a second side portion that is spaced apart from the first side portion of the first conductive plate and directly faces the first side portion of the first conductive plate, Within the package structure, a first bond wire is bonded to the first die and the first conductive plate, A second bond wire is coupled to the second die and the second conductive plate within the package structure, The insulating device includes, Includes, A portion of the package structure extends between the first side of the first conductive plate and the second side of the second conductive plate to form a capacitor. The other side of the first conductive plate does not directly face the side of the second conductive plate, and the other side of the second conductive plate does not directly face the side of the first conductive plate. A system wherein the first conductive plate includes a first part having a first side and a second part, and the first and second parts of the first conductive plate are not on the same plane.

11. The system according to claim 10, The first side of the first conductive plate extends into a first plane, the second side of the second conductive plate extends into a second plane, and the first and second planes are parallel to each other. A system in which the first conductive plate and the second conductive plate lie on the same plane in a third plane perpendicular to the first and second planes.

12. The system according to claim 10, The insulating device further includes an embedded dielectric insert within the package structure, A system in which one of the first conductive plate and the second conductive plate is on or within the embedded dielectric insert.

13. It is a device, A first lead frame including a first conductive plate having a first portion, A second lead frame including a second conductive plate having a second portion, A dielectric insert comprising a dielectric layer and third and fourth conductive plates on the dielectric layer, wherein a third portion of the third conductive plate faces a first portion of the first conductive plate via the dielectric layer, and a fourth portion of the fourth conductive plate faces a second portion of the second conductive plate via the dielectric layer, The first semiconductor die, The second semiconductor die, A first conductive element coupled to the first semiconductor die and the first conductive plate, A second conductive element coupled to the second semiconductor die and the second conductive plate, A package structure enclosing the first semiconductor die, the second semiconductor die, the first conductive element, the second conductive element, the dielectric insert, a part of the first conductive plate, and a part of the second conductive plate, A device including a device.

14. The apparatus according to claim 13, The other portion of the first conductive plate does not directly face the portion of the third conductive plate, and the other portion of the third conductive plate does not directly face the portion of the first conductive plate. An apparatus in which the other portion of the second conductive plate does not directly face the portion of the fourth conductive plate, and the other portion of the fourth conductive plate does not directly face the portion of the second conductive plate.

15. The apparatus according to claim 14, The first lead frame further includes a fifth conductive plate having a fifth portion, and the second lead frame further includes a sixth conductive plate having a sixth portion. The dielectric insert further includes seventh and eighth conductive plates on the dielectric layer, An apparatus in which the fifth portion of the fifth conductive plate faces the seventh portion of the seventh conductive plate via the dielectric layer, and the sixth portion of the sixth conductive plate faces the eighth portion of the eighth conductive plate via the dielectric layer.

16. The apparatus according to claim 15, The other portion of the fifth conductive plate does not directly face the portion of the seventh conductive plate, and the other portion of the seventh conductive plate does not directly face the portion of the fifth conductive plate. An apparatus in which the other portion of the sixth conductive plate does not directly face the portion of the eighth conductive plate, and the other portion of the eighth conductive plate does not directly face the portion of the sixth conductive plate.

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