Pin strap detection circuit

Abstract

To provide an integrated circuit.SOLUTION: An integrated circuit (100) includes an input pin (114) and an analog-to-digital converter (ADC) (104) including an input terminal coupled to the input pin and an output terminal. The integrated circuit further includes a logic circuit (102) including an input terminal coupled to the output terminal of the ADC, a first output terminal, and a second output terminal. The integrated circuit further includes a resistive circuit (103). In an example, a resistive circuit includes: a resistor (106) coupled between an input pin and a first node (118); a first switch (108) coupled between the first node and a reference voltage pin (112); and a second switch (110) coupled between the first node and a ground pin (116).SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] Some electrical components include multiple operating modes, operating settings, or other characteristics that can be programmed after the manufacture of the electrical component. These settings may be set by a consumer of the electrical component who implements the electrical component within a larger circuit, device, or system. As the number of available settings for an electrical component increases, the consumer may desire that the electrical component be programmed easily and accurately.

Summary of the Invention

[0002] Aspects of the present specification provide an integrated circuit. In at least some examples, the integrated circuit includes an input pin and an analog-to-digital converter (ADC) including an input terminal and an output terminal coupled to the input pin. The integrated circuit further includes a logic circuit including an input terminal, a first output terminal, and a second output terminal coupled to the output terminal of the ADC. The integrated circuit further includes a resistor circuit. In one example, the resistor circuit includes a resistor coupled between the input pin and a first node, a first switch coupled between the first node and a reference voltage pin, and a second switch coupled between the first node and a ground pin.

[0003] Other aspects of this specification provide integrated circuits. In at least some examples, the integrated circuit includes an input pin and an ADC having an input terminal and an output terminal coupled to the input pin. The integrated circuit also includes a resistor circuit having an output terminal coupled to the input pin and a first input terminal. The integrated circuit also includes a logic circuit having an input terminal coupled to the output terminal of the ADC and a first output terminal coupled to the first input terminal of the resistor circuit. The logic circuit is configured to generate a first ADC control signal that controls the ADC to determine a voltage present at the input pin using a first value of the resistor present at the input pin. The logic circuit is further configured to generate a control signal that controls the resistor circuit to change the first value of the resistor to a second value of the resistor. The circuit is further configured to generate a second ADC control signal that controls the ADC to determine a second voltage present at the input pin as changed according to the second value of the resistor, and to determine the first value of the resistor based at least in part on the voltage present at the input pin, the second voltage present at the input pin, the resistance of the resistor circuit, and a reference voltage.

[0004] Other aspects of this specification provide systems. In at least some examples, the system includes programmable electrical components and voltage dividers. The programmable electrical components include an ADC including an input pin, a reference voltage pin, a ground pin, an input terminal coupled to the input pin, and an output terminal, and a resistor circuit including an output terminal coupled to the input pin, a first input terminal, and a logic circuit. The logic circuit includes an input terminal coupled to the output terminal of the ADC and a first output terminal coupled to the first input terminal of the resistor circuit. The logic circuit is configured to generate a first ADC control signal that controls the ADC to determine a voltage present at the input pin using a first value of resistance present at the input pin. The logic circuit is further configured to generate a control signal that controls the resistor circuit to change the first value of resistance to a second value of resistance. The logic circuit is further configured to generate a second ADC control signal that controls the ADC to determine a second voltage present at the input pin as changed according to the second value of resistance, and to determine the first value of resistance based in part on the voltage present at the input pin, the second voltage present at the input pin, the resistance of the resistor circuit, and a reference voltage present at the reference voltage pin. The voltage divider is coupled between the reference voltage pin and the ground pin, and has an output coupled to the input pin. [Brief explanation of the drawing]

[0005] Refer to the attached drawings for detailed explanations of various examples.

[0006] [Figure 1] Schematic diagrams of illustrative electrical components in several examples are shown.

[0007] [Figure 2] Schematic diagrams of illustrative resistor circuits in several examples are shown.

[0008] [Figure 3] Schematic diagrams of illustrative resistor circuits in several examples are shown.

[0009] [Figure 4]The following shows example signal timing diagrams in several cases.

[0010] [Figure 5] A flowchart illustrating an example of a pin strap detection method in several cases is shown. [Modes for carrying out the invention]

[0011] For electrical components intended to be programmable after manufacturing, one such approach to programming the component is pin-strap detection. Pin-strap detection is, in some examples, a process in which a known reference voltage (VREF) output by an electrical component performing pin-strap detection is monitored at the input terminal of the electrical component to determine the voltage present at that input terminal. In some examples, the output terminal of the electrical component from which the VREF is provided is the VREF pin of the electrical component. In other examples, the VREF is provided by any suitable source, and its value is known to the electrical component through either reporting to the electrical component, control performed by the electrical component, or measurement by the electrical component. The various voltages present at the input terminal correspond to or map to specific settings of the electrical component so that they are communicated to the user of the electrical component through a datasheet or other instructions for implementing the electrical component in a circuit. To program the electrical component, the user may couple a voltage divider between the VREF pin and a ground (GND) pin or node. The output of the voltage divider is then coupled to the input terminal of the electrical component such that the ratio of resistances in the voltage divider controls the voltage present at the input terminal. Generally, the amount of resistance of the voltage divider between the VREF pin and the input terminal is called the top resistance (RTOP), and the amount of resistance of the voltage divider between the input terminal and the GND pin is called the bottom resistance (RBOT). RTOP and RBOT can each be provided by one or more elements having a measurable impedance. For example, RTOP and / or RBOT can each be implemented by a single resistor, a potentiometer, multiple coupled resistors, or any other suitable element capable of providing a measurable amount of impedance or resistance. By changing the values ​​of RTOP and / or RBOT, the user can control the voltage present at the input terminal, thereby programming the electrical components.

[0012] The pin-strap detection process described above offers two-stage flexibility in measurement. For example, in addition to the voltage measurement described above, the RTOP or RBOT value can also be determined. Several approaches exist for pin-strap detection of the resistance of a voltage divider resistor, but these approaches have problems such as limited accuracy and / or relatively high cost (e.g., the die surface area consumed to implement the approach). One such approach involves sending VREF to a buffer and mirroring the buffer's output current to an internal resistor (RINT) housed within the electrical component by a current mirror. The voltage across RINT is measured to determine RBOT. However, this approach can be very inaccurate. For example, as the voltage present at the input terminal increases, the buffer offset increases, resulting in an increased percentage error in RBOT determination. Therefore, buffers are often implemented as low-offset amplifiers, and when combined with current mirrors, they have a larger die surface area compared to resistors and / or other components such as transistors. Increased size also increases the cost of manufacturing the electrical component, which in some cases contradicts customer requirements for the minimum size of the electrical component.

[0013] At least some aspects of this specification provide pin-strap detection circuits. In at least some examples, the pin-strap detection circuits of this specification are suitable for detecting the voltage present at an input terminal with 5-bit precision and the RBOT with 4-bit precision. In other examples, the pin-strap detection circuits of this specification are suitable for detecting the voltage present at an input terminal with greater than 5-bit precision and the RBOT with greater than 4-bit precision, based on a minimized component process and temperature fluctuations of the pin-strap detection circuit and / or resistors providing RTOP and RBOT. For example, the input terminal of an analog-to-digital converter (ADC) is coupled to an input terminal to generate a digital signal representing the voltage present at the input terminal. In at least some examples, this digital signal representing the voltage present at the input terminal is called the pin voltage (VP), for example, when RINT is not coupled in parallel with RBOT or RTOP. In other examples, the digital signal representing the voltage present at the input terminal is called the sensed voltage (VS), for example, when RINT is coupled in parallel with RBOT or RTOP. In at least some examples, the digital signal is provided to a digital core or other processing element. A digital core or processing element processes a digital code to generate one or more additional values. For example, a digital core processes a VP to generate a VCODE, which is used to determine the VS. The digital code is processed by the VS and used to determine the RBOT and, accordingly, the RCODE. In at least some examples, the voltage present at the input terminal may vary due to resistor tolerances or other factors. Therefore, in at least some examples, a digital core uses fewer bits than the total 11 bits of the VP (e.g., only the least significant 5 bits) when generating a VCODE used when programming the settings of the digital core or another component or device. In some examples, the bit precision of the VCODE with respect to the VP increases when fewer bits than the total bits of the VP are used to generate a VCODE used when programming the settings.

[0014] In some examples, VS is measured after VP so that the ADC generates two distinct digital codes. In other examples, VP is measured after VS. In at least one example, the ADC generates VP by measuring the voltage present on the input pin. In at least several examples, after the ADC generates VP, the digital core generates VCODE based on VP. The digital core further determines the value of VCODE with respect to one or more threshold values. Based on that determination, the digital core generates and outputs a control signal (e.g., a switch control signal). The control signal controls a switch in the pin-strap detection circuit to couple RENT in parallel with RTOP or RBOT, enabling the measurement of VS. The ADC then measures the voltage present on the input node and generates VS. After the ADC generates VS, the digital core processes VS, VP, VREF, and / or RINT to generate a digital code (RCODE) representing RBOT. In at least several examples, RINT has a value configured so that VS has a value closer to VREF / 2 than VP. Setting VS to a value closer to VREF / 2 than VP maximizes the resolution of detectable RBOT values. Based on the VCODE and RCODE values, the digital core is programmed with specific settings corresponding to the VCODE and RCODE values. As described above, in at least some examples, fewer bits than all bits of the VCODE are used when programming the digital core. For example, about 5 or more bits of the VCODE (e.g., the least significant 5 bits of the VCODE) and about 4 bits of the RCODE (e.g., the least significant 4 bits of the RCODE) are used when programming the digital core. This provides an improvement in the number of settings for electrical components that can be precisely set using an input provided on one pin of the electrical component. The improvement in the number of settings that can be programmed using one pin is at least in part due to the improved accuracy of RBOT and RCODE determination according to the pin-strap detection described herein.

[0015] Referring here to Figure 1, a schematic diagram of an exemplary electrical component 100 is shown. In at least some examples, electrical component 100 represents any electrical component comprising one or more elements, one or more of which are arranged on a semiconductor die and / or surrounded by a component package having a certain number of pins exposed on the outside of the component package for coupling with the elements arranged on the semiconductor die. Electrical component 100 may have any suitable primary functionality, and the scope of its functionality is not limited herein. For example, electrical component 100 may be an analog component, a digital component, or a combination of the two, and is configured to provide specific processing and / or control functionality. In at least one example, electrical component is a power controller, such as a DC-to-DC power controller, or a component thereof. To implement its primary functionality, electrical component 100 may further include various supporting functionalities. For example, electrical component 100 may include functionality for a user to specify one or more desired settings for the operation of electrical component 100. This selection may be carried out according to a pin-strapping methodology in which voltage and / or resistance are detected at a pin and mapped to a predefined setting or function of the electrical component 100 corresponding to the voltage and / or resistance.

[0016] In at least one exemplary architecture, the electrical component 100 includes a logic circuit 102, a resistor circuit 103, and an ADC 104. The resistor circuit 103 includes a resistor 106, a switch 108, and a switch 110. In at least several examples, the resistor circuit 103 further includes a logic circuit 105. In several examples, the logic circuit 102 is a circuit capable of performing processing and / or decision-making, such as a digital core. The logic circuit 105 is a circuit capable of or suitable for performing a logical OR operation according to a plurality of input signals to generate an asserted output signal when any of the plurality of input signals is asserted. In at least several examples, the resistor 106 has a resistance of RINT. Although the resistor 106 is illustrated as a single resistor with a defined value, it may instead be a programmable resistor (e.g., a potentiometer) with a resistance value controlled by the logic circuit 102 or any other suitable control device. Alternatively or additionally, resistor 106 may represent any combination of parallel and / or series-connected components having a measurable and / or definable amount of resistance. Furthermore, in at least some examples, electrical component 100 includes a VREF pin 112, an input pin 114, and a GND pin 116. The VREF pin 112, input pin 114, and GND pin 116 provide an interface to electrical component 100 in some examples, allowing a user to interact with electrical component 100 or components within electrical component 100 via one or more components outside of electrical component 100. In at least some examples, input pin 114 is versatile so that, after performing pin-strap detection according to this specification, input pin 114 may be used in electrical component 100 for other purposes, the scope of which is not limited herein.

[0017] In some examples, the ADC104 has an input terminal coupled to input pin 114 and an output terminal coupled to the input terminal of logic circuit 102. In at least some examples, the ADC104 has one or more additional input terminals, such as when the ADC104 is a multi-channel ADC. For example, the ADC104 may include another input terminal coupled to VREF pin 112. If the ADC104 is a multi-channel ADC, the ADC104 is configured to include or be coupled to a multiplexer (not shown) at its input terminals so that the ADC104 receives the output of a multiplexer as its input signal. The multiplexer is coupled to the nodes to the input terminals of the ADC104 as described herein. For example, the multiplexer includes the respective input terminals coupled to input pin 114 and VREF pin 112. The ADC 104 (or multiplexer) further includes a control input that receives control signals (e.g., one or more ADC control signals) from the logic circuit 102 to control which analog input signals are converted to digital signals by the ADC 104. Although shown in Figure 1 as a single coupling to the control signals between the logic circuit 102 and the ADC 104, in various examples, there may be any number of couplings based on the number of channels in the ADC 104 (e.g., the many unique input terminals of the multiplexer) or any other appropriate criterion. The resistor 106 has a first terminal coupled to input pin 114 and a second terminal coupled to node 118. The switch 108 is coupled between node 118 and VREF pin 112 and is configured to receive and be controlled by the first control signal (e.g., switch control signal) received from the logic circuit 102. The switch 110 is coupled between node 118 and GND pin 116 and is configured to receive and be controlled by the second control signal (e.g., switch control signal) received from the logic circuit 102. Switches 108 and 110 may each be implemented according to any suitable technique, the scope of which is not limited herein. In at least one example, switches 108 and 110 are each implemented as solid-state devices, such as transistors, using any suitable processing technique.

[0018] Although not shown in electrical component 100, in at least some examples, electrical component 100 includes circuit elements for providing VREF of a known value to the VREF pin 112. The circuit elements for electrical component 100 for generating and / or providing VREF at the VREF pin 112 may be implemented in a number of suitable architectures, the scope of which is not limited herein. Electrical component 100 does not include a voltage divider 120, but is configured to be coupled to a voltage divider 120. The voltage divider 120 includes resistors 122 and 124. As described above with respect to resistor 106, resistors 122 and 124 each represent any one or more coupled components that provide a measurable and / or defined amount of resistance. As further suggested above, the resistance of resistor 122 is called RTOP, and the resistance of resistor 124 is called RBOT.

[0019] In an example of the operation of the electrical component 100, the electrical component 100 is programmable according to multiple settings in order to provide various functionalities. In some examples, the electrical component 100 may be programmable according to tens, hundreds, or thousands of settings. In some examples, the settings are programmed into the electrical component 100 based at least in part on a mapping between a specific setting and the voltage and / or resistance present on the input pin 114. For example, based on the voltage measured at the input pin 114 and the determination of RBOT, the electrical component 100 is programmed by the logic circuit 102 with a specific setting that maps to the measured voltage and the determined RBOT.

[0020] To program the electrical components, in at least some examples, the user connects resistor 122 between VREF pin 112 and input pin 114, and resistor 124 between input pin 114 and GND pin 116. Electrical component 100 provides VREF to VREF pin 112, causing the voltage modified by voltage divider 120 to be present at input pin 114. The voltage present at input pin 114 is called VP as described above and is determined based on the value of VREF and the values ​​of RBOT and RTOP. In at least some examples, ADC 104 detects the voltage present at VREF pin 112 and generates a digital signal representation of VREF. ADC 104 provides the digital signal representation of VREF to logic circuit 102, which uses it, for example, as a variable in an expression for generating RCODE by logic circuit 102, as will be described in more detail elsewhere in this specification. ADC 104 detects the voltage present at input pin 114 in analog form and generates VP in digital form based on the detected voltage. The ADC104 then provides the VP to the logic circuit 102. In some examples, the logic circuit 102 generates and stores the VCODE for use when programming the electrical components 100. In at least some examples, the logic circuit 102 further stores the VP for later use, such as when determining the RCODE.

[0021] After determining the VCODE, in at least some examples, the electrical component 100 determines the RCODE. In at least some implementations, the RCODE is a digital value representation of the RBOT. In other implementations, the RCODE is a digital value representation of the RTOP. To generate the RCODE, the logic circuit 102 or another suitable control device controls one of the switches 108 or 110 to close, forming a conductive path across each of the switches 108 or 110. If the switches 108 and 110 are normally open devices, they are controlled to close when a signal received from the logic circuit 102 is asserted. Alternatively, in other examples, the switches 108 or 110 are configured to close when a signal received from the logic circuit 102 is deasserted. When either switch 108 or switch 110 is closed, the other switch 108 and switch 110 are opened, and as a result, in some examples, at any given time, neither switch 108 nor switch 110 is closed, or only one of them is closed. Thus, by closing switch 108 or switch 110, resistor 106 is connected in parallel with resistor 122 or resistor 124, respectively. If VP is known based on measurements previously performed for VCODE determination, etc., and the value of resistor 106 is known based on the fact that it is a component included in electrical component 100, then the value of RTOP or RBOT can be determined.

[0022] For example, after closing either switch 108 or switch 110, a new voltage is present at input pin 114, altered from the value that existed before closing switch 108 or switch 110 (e.g., represented as VP in the digital domain). ADC 104 detects the new voltage at input pin 114 in analog form and generates VS based on the detected new voltage. ADC 104 then provides VS to logic circuit 102, which, in some examples, determines the RCODE based at least partially on VS. For example, in some implementations, logic circuit 102 implements an expression that determines the RCODE based on the received digital code, a previously determined and / or stored VP, VREF, and a known RENT. In an example where switch 108 connects resistor 106 in parallel with resistor 122, logic circuit 102 determines the RCODE based on expression 1 below. In the example where switch 110 connects resistor 106 in parallel with resistor 124, the logic circuit 102 determines the RCODE based on the following equation 2. TIFF0007886669000002.tif21125

[0023] In other examples, logic circuit 102 accesses a look-up table stored in a memory (not shown) to determine the value of RCODE based on VS and VP. For example, the look-up table includes either VS or VP on the horizontal axis of the look-up table and the other of VS or VP on the vertical axis of the look-up table. The intersection in the look-up table for a particular VS and VP indicates the value of RCODE for that particular combination of VS and VP. In an implementation where logic circuit 102 uses a look-up table instead of implementing Equation 1 and / or Equation 2, logic circuit 102 may not include mathematical engine capabilities (e.g., the ability to perform mathematical calculations). By not including mathematical engine capabilities, in at least some examples, the physical size of logic circuit 102 is reduced (resulting in cost reduction), the power consumption by logic circuit 102 is reduced and / or the time to determine RCODE is shortened.

[0024] In some cases, logic circuit 102 determines whether to close switch 108 or switch 110 based on the value of VCODE. For example, if VCODE is greater than a threshold, logic circuit 102 controls and closes either switch 108 or switch 110. If VCODE is less than a threshold, logic circuit 102 controls and closes the other of switch 108 or switch 110. In some implementations, when the decimal value of VCODE is less than approximately 16, logic circuit 102 generates and outputs the control signal CONNECT_VREF, controlling and closing switch 108. Furthermore, when the decimal value of VCODE is greater than approximately 15, logic circuit 102 generates and outputs the control signal CONNECT_GND, controlling and closing switch 110. More generally, in at least some implementations, when the decimal value of VCODE is less than approximately VREF / 2, logic circuit 102 generates and outputs the control signal CONNECT_VREF, controlling and closing switch 108. The logic circuit 102 further generates and outputs the control signal CONNECT_GND when the decimal value of VCODE is greater than approximately VREF / 2, thereby controlling and closing switch 110. Alternatively, in another example, the logic circuit 102 determines whether to close switch 108 or switch 110 based on the value of VP. In such an example, VP is replaced with VCODE in the description herein of the generation of CONNECT_VREF or CONNECT_GND.

[0025] Based on the above scheme, by coupling resistor 106 in parallel with resistor 122 or resistor 124, in at least some examples, logic circuit 102 causes VS to have a value closer to VREF / 2 than VP. In at least some examples, causing VS to have a value closer to VREF / 2 than VP improves the resolution of detectable changes at RBOT. For example, when the value of VP is very close to VREF, RBOT becomes significantly larger than RTOP (e.g., RBOT >> RTOP). In this situation, a small change in the value of the voltage present at input pin 114 causes a large change in RBOT. Therefore, the potential error caused by ADC 104 during the generation of VS causes a large error in RBOT detection. However, coupling resistor 106 in parallel with resistor 124 limits RBOT to a lower value, and thus brings the value of the voltage present at the input pin closer to VREF / 2. In such an example, the error caused by ADC 104 during the generation of VS reduces the error in RBOT detection, thereby improving the resolution of RBOT detection.

[0026] Similarly, when the value of VP is close to the value present at GND pin 116, RTOP >> RBOT. In this situation, a small change in RBOT causes a large change in VS. By coupling resistor 106 in parallel with resistor 122, RTOP is limited to a lower value, thereby bringing the value of VS closer to VREF / 2. In such an example, the error caused by ADC 104 during the generation of VS reduces the error in RBOT detection, thereby improving the RBOT detection resolution. For example, if ADC 104 introduces an error in the value of VS, due to the large change in VS measured by ADC 104, the impact of the error increases. However, since the value of VP is close to the value present at GND pin 116, and thus the value of VS is close to VREF / 2, for a large change in VS, only a small change occurs in RBOT, so the corresponding error in RBOT is minimized.

[0027] In some cases, there is a variation in RINT from the expected or ideal value of the resistance. In at least some cases, if left uncompensated, the percentage error from the expected or ideal value in RINT is directly converted to the same percentage error in the detected or calculated RBOT, and thus becomes the error in RCODE. Therefore, in at least some cases, it is advantageous to determine and / or compensate for this variation. To determine the variation, in at least some cases, the electrical component 100 includes a calibration or test operation mode. To enter the calibration mode of operation, logic circuit 102 generates and outputs a control signal TEST_EN with an asserted value. The control signal is received by logic circuit 105, and when asserted, it closes switch 110, connecting resistor 106 in parallel with resistor 124. While operating in test mode, resistors with known values ​​are used as resistors 122 and 124. Then logic circuit 102 determines RINT. Since the values ​​of resistors 122 and 124 are known, and the expected RINT is known, the logic circuit 102 can then determine the variation in the actual value of RINT from the expected value of RINT. In at least some examples, the logic circuit 102 stores a value indicating the variation as a RINT offset in a storage element (not shown), such as a register, one-time programmable (OTP) memory, or other suitable memory or data storage structure. In subsequent normal operation (e.g., when not operating in test mode), the logic circuit 102 modifies RINT according to the RINT offset in the calculations of Equations 1 and 2. In at least some examples, the determination of the RINT offset compensates for the variation in the actual value of RINT with an accuracy of about 0.2% or less from the expected value of RINT.

[0028] Referring now to Figure 2, a schematic diagram of the exemplary resistor circuit 200 is shown. In at least some examples, the resistor circuit 200 replaces resistor 106, switch 108, and switch 110 of the electrical component 100 in Figure 1. For example, in at least some implementations, the resistor circuit 200 is suitable to be implemented as resistor circuit 103 (for example, instead). Thus, when describing the resistor circuit 200, at least some components and / or signals of the electrical component 100 may be referenced.

[0029] The resistor circuit 200 includes, in some examples, resistors 202, 204, 206, 208, switches 210, 212, 214, and 216. In at least one exemplary architecture, resistor 202 and switch 210 are connected in series between input pin 114 and VREF pin 112. Resistor 204 and switch 212 are also connected in series between input pin 114 and VREF pin 112. Resistor 206 and switch 214 are connected in series between input pin 114 and GND pin 116. Resistor 208 and switch 216 are also connected in series between input pin 114 and GND pin 116. Although not shown, switches 210, 212, 214, and 216 are configured, in some examples, to receive their respective control signals from the logic circuit 102 to control the state (e.g., open or closed) of switches 210, 212, 214, and 216. Two resistor and switch pairs are shown and described as being coupled between input pin 114 and each of the VREF pin 112 and GND pin 116, but in various other examples, any number of resistor and switch pairs are coupled between input pin 114 and each of the VREF pin 112 and GND pin 116. In some examples, the same number of resistor and switch pairs are coupled between input pin 114 and each of the VREF pin 112 and GND pin 116. In another example, a different number of resistor and switch pairs are coupled between input pin 114 and either VREF pin 112 or GND pin 116 than are coupled between VREF pin 112 or GND pin 116 and the other pin.

[0030] In at least some examples of the operation of the resistor circuit 200, such as when the ADC 104 is an 11-bit ADC, the maximum decimal value of the VCODE is 31. Based on the decimal value of the VCODE, the logic circuit 102 controls one of switches 210, 212, 214, or 216 to close, and leaves the remaining switches 210, 212, 214, or 216 open or open. For example, when the maximum value of the VCODE is 31, the logic circuit 102 controls switch 210 to close (opening switches 212, 214, and 216), when the decimal value of the VCODE is between 0 and 7 (including 0 and 7), the logic circuit 102 further controls switch 212 to close (and controls switches 210, 214, and 216 to open) when the decimal value of the VCODE is between 8 and 15 (including 8 and 15). The logic circuit 102 further controls switch 214 to close (and switches 210, 212, and 216 to open) when the decimal value of VCODE is between 16 and 23 (including 16 and 23). The logic circuit 102 further controls switch 216 to close (and switches 210, 212, and 214 to open) when the decimal value of VCODE is between 24 and 31 (including 24 and 31).

[0031] Generally, the logic circuit 102 generates one or more control signals that control one or more switches of the resistor circuit 200 so that the value of VS approaches VREF / 2. For example, in at least some implementations, resistors 202, 204, 206, and 208 have different resistance values ​​optimized for a certain value or range of values ​​of VCODE. By determining the value of VCODE, the logic circuit 102 then controls switches 210, 212, 214, and / or 216 so that they have a state configured to approach VREF / 2. For example, based on the state of switches 210, 212, 214, and 216, the amount of resistance connected in parallel with resistor 222 or resistor 224 changes. Changing the amount of resistance connected in parallel with resistor 222 or resistor 224 brings the value of VS closer to VREF / 2 than the previously measured value of VP. The least significant 5 bits of the previously measured VP are stored as VCODE by logic circuit 102 when switches 210, 212, 214, and 216 are opened, respectively.

[0032] Referring now to Figure 3, a schematic diagram of an exemplary resistor circuit 300 is shown. In at least some examples, the resistor circuit 300 replaces resistor 106, switch 108, and switch 110 of the electrical component 100 in Figure 1. For example, in at least some implementations, the resistor circuit 300 is suitable to be implemented as resistor circuit 103 (for example, instead). Thus, in the description of the resistor circuit 300, at least some components and / or signals of the electrical component 100 may be referenced.

[0033] In at least one example, the resistive circuit 300 includes a resistor 302 and a voltage source 304. The resistor 302 is coupled between the output terminal of the voltage source 304 and the input pin 114. In some examples, the resistive circuit 300 further includes a switch coupled between the resistor 302 and the input pin 114. In some examples, the voltage source 304 is a digital-to-analog converter (DAC). In other examples, the voltage source 304 is any component, circuit, or device capable of outputting a signal having a controllable value. For example, the output signal of the voltage source 304 may be controllable from a minimum of approximately 0 volts (e.g., substantially equal to what is present on the GND pin 116) to a maximum of approximately VREF (e.g., substantially equal to the value present on the VREF pin 112). In some examples, the voltage source 304 is controlled to produce an output signal having a value determined based on the value of VCODE. For example, based on the value of VCODE and the known resistance value of resistor 302, the logic circuit 102 controls the voltage source 304 to generate an output signal configured such that the absolute value of the difference between VS and VREF / 2 is less than the absolute value of the difference between VCODE and VREF / 2. Alternatively, VCODE may also be replaced with VP and used to control the voltage source 304. In at least some examples, the voltage source 304 is controlled based on a signal received from the logic circuit 102. In at least some examples, switch 306 is configured to disconnect resistor 302 and voltage source 304 from input pin 114 under certain circumstances. For example, as described elsewhere in this specification, when VP is determined by the logic circuit 102, switch 306 opens based on a control signal received from the logic circuit 102, disconnecting resistor 302 and voltage source 304 from input pin 114. Subsequently, as described elsewhere in this specification, once the RCODE is determined by the logic circuit 102, the switch 306 closes based on the control signal received from the logic circuit 102, connecting the resistor 302 and the voltage source 304 to the input pin 114.

[0034] Referring now to Figure 4, an illustrative timing diagram 400 is shown. In at least some examples, the timing diagram 400 represents at least some signals present in or associated with the electrical component 100 in Figure 1. Thus, when describing the timing diagram 400, at least some components and / or signals of the electrical component 100 may be referenced.

[0035] Timing diagram 400 illustrates an exemplary pin strap detection sequence and device configuration based on the results of pin strap detection. Timing diagram 400 shows the control signals ADC_PINSTRAP_EN and ADC_VREF_EN. Timing diagram 400 also shows VP, VCODE, CONNECT_VREF, CONNECT_GND, VS, and RCODE, each as previously described herein.

[0036] As already explained with respect to Figure 1, ADC104 can be a multi-channel ADC. In such an example, ADC_PINSTRAP_EN is a signal output by logic circuit 102 that controls ADC104 to output a VP based on the voltage present at input pin 114. For example, when ADC_PINSTRAP_EN is asserted (e.g., has a logic high), ADC104 measures the voltage present at input pin 114 and generates a VP. In some examples, VP generation is performed by ADC104 performing a dynamic average to mitigate the possibility of inaccuracies in the VP value resulting from instantaneous fluctuations in the voltage value present at input pin 114. Similarly, ADC_VREF_EN is a signal output by logic circuit that controls ADC104 to generate a digital signal representation of VREF based on the voltage present at VREF pin 112. When ADC_VREF_EN is asserted (e.g., has a logic high), ADC104 measures the voltage present at VREF node 112 and generates a digital signal representation of VREF. In some examples, the generation of the digital signal representation of VREF is performed by the ADC104 performing a dynamic average to mitigate the possibility of inaccuracies in the value of VREF resulting from instantaneous fluctuations in the value VREF present at the VREF pin 112. For illustrative purposes in timing diagram 400, it is assumed that VP is less than VREF / 2, and therefore logic circuit 102 asserts CONNECT_VREF. However, in other examples, VP may instead be greater than VREF / 2, and therefore the states of CONNECT_VREF and CONNECT_GND will be the opposite of those shown in timing diagram 400.

[0037] As illustrated in timing diagram 400, the pinstrap detection sequence generally involves seven operations. However, in some examples, there may be more or fewer operations, and each of those operations may involve one or more sub-operations not specifically shown in timing diagram 400, and timing diagram 400 may not be at a constant scale (for example, some operations may take longer than others). Furthermore, there may be delays between some operations that are not shown in timing diagram 400 (for example, a delay between the completion of one operation that generates a particular signal and the generation of a new signal based on that particular signal).

[0038] After startup, the electrical component 100 waits for the voltage present on input pin 114 to settle (e.g., stabilize). While waiting for the voltage present on input pin 114 to settle, the logic circuit 102 controls the ADC via the ADC_VREF_EN signal to generate a digital representation of VREF for storage and later use by the logic circuit 102. After the voltage present on input pin 114 has settled, the logic circuit 102 controls the ADC 104 to measure the voltage present on input pin 114 and generate VP. In at least some examples, the logic circuit 102 performs control via the ADC_PINSTRAP_EN signal. The ADC 104 performs the measurement of VP according to a dynamic averaging process, and upon completion, the ADC 104 generates and outputs VP as an 11-bit value (if the ADC 104 is an 11-bit ADC). The logic circuit 102 stores at least a portion of VP as VCODE and determines whether VP is greater than or less than VREF / 2. A portion of the VP stored as VCODE may be determined according to any appropriate characteristics such as the tolerance of resistors 122 and 124, but in at least one example, at least the least 5 bits of the VP are stored as VCODE. Based on the value of VP relative to VREF / 2, the logic circuit 102 asserts either CONNECT_VREF or CONNECT_GND. In timing diagram 400, CONNECT_VREF is asserted. The electrical component 100 waits again for the voltage present at input pin 114 to settle. After the voltage present at input pin 114 has settled again, the logic circuit 102 controls the ADC 104 to measure the voltage present at input pin 114 and generate VS. In at least some examples, the logic circuit 102 performs control via the ADC_PINSTRAP_EN signal. ADC104 performs a measurement of VS according to a dynamic averaging process, and upon completion, ADC104 generates and outputs VS as an 11-bit value (if ADC104 is an 11-bit ADC). After the generation of VS, logic circuit 102 generates RCODE as at least a 4-bit value.Subsequently, in at least some examples, the logic circuit 102 configures an electrical component 100 or another device according to the stored VCODE and the determined RCODE. The values ​​of both VCODE and RCODE uniquely correspond to one or more specific settings of the configured electrical component 100 or another device.

[0039] Referring now to Figure 5, a flowchart of the exemplary method 500 is shown. Method 500 is a pin strap detection method in several examples. In at least several examples, Method 500 is implemented in or at least partially by the electrical component 100 (or its components) of Figure 1. Accordingly, in the description of Method 500, at least several components and / or signals of the electrical component 100 may be referenced.

[0040] In operation 502, VREF is sampled. In at least some examples, VREF is sampled by controlling ADC104 to measure VREF and generate a digital code representing VREF using the channel of ADC104 coupled to VREF pin 112. In some examples, the control is performed by logic circuit 102 which outputs a channel selection signal to ADC104, causing ADC104 to sample the channel of ADC104 coupled to VREF pin 112.

[0041] In operation 504, the input pin voltage is sampled to generate a VP. In at least some examples, the input pin voltage is sampled by controlling the ADC 104 to measure the input pin voltage and generate a VP as a digital representation of the input pin voltage using the channel of the ADC 104 coupled to input pin 114. In some examples, the control is performed by a logic circuit 102 that outputs a channel selection signal to the ADC 104, causing the ADC 104 to sample the channel of the ADC 104 coupled to input pin 114. Sampling the input pin voltage is a hardware operation that causes the ADC 104 to generate a VP based on the analog value present at input pin 114, in at least some examples. The VP is provided to the logic circuit 102 by the ADC 104 as one or more electrical impulses representing one or more digital bits, in at least some examples.

[0042] In operation 506, the VCODE is calculated. In at least some examples, the VCODE is calculated by the logic circuit 102 by manipulating the digital code received from the ADC 104 (by storing a portion of the digital code as the VCODE). For example, if the ADC 104 outputs a digital code with 11 bits, in some implementations, only the least significant 5 bits of the digital code (or more commonly, fewer bits than all 11 bits of the digital code) may be used for programming one or more settings, even though all 11 bits are used for other calculations (such as calculating the RCODE). Thus, in at least some examples, the VCODE is calculated to contain fewer bits than all bits of the VP. In at least some examples, fewer bits than all 11 bits of the digital code are used in programming to compensate for potential errors or inaccuracies resulting from tolerances (e.g., about 1%) in the actual values ​​of RTOP and RBOT from their ideal values. If resistors with lower tolerance (e.g., higher precision) are used for resistors 122 and 124, then in at least some examples, a digital code with more than the least significant 5 bits may be used to program one or more settings. In other examples, logic circuit 102 may generate a VCODE by directly storing all bits of the VP as the VCODE. In at least some examples, after generating the VCODE from the VP, logic circuit 102 stores the VCODE in a storage element. In at least some examples, logic circuit 102 also stores the received VP on which the VCODE is based. The storage element may be a register, a cache, or any other volatile or non-volatile storage component or device. In at least some examples, the VCODE is a digital value that is accurate to at least 5 bits.

[0043] In operation 508, a control signal is generated. In at least some examples, the control signal is generated by logic circuit 102. In at least some implementations, logic circuit 102 generates the control signal based on the value of VCODE relative to a threshold. For example, in one implementation of operation 508, logic circuit 102 determines whether VCODE is less than or greater than a threshold and generates a control signal. For example, if VCODE is less than a threshold, logic circuit generates an asserted first control signal and a deasserted second control signal. If VCODE is greater than a threshold, logic circuit generates a deasserted first control signal and an asserted second control signal. In at least some examples, the threshold is a digital value representing VREF / 2.

[0044] In operation 510, an internal resistor (e.g., resistor 106) is coupled in parallel with the resistors of the voltage divider 120. For example, when the first control signal is asserted, the internal resistor is coupled in parallel with resistor 122 between the VREF pin 112 and the input pin 114. When the second control signal is asserted, the internal resistor is coupled in parallel with resistor 124 between the input pin 114 and the GND pin 116. In at least some examples, coupling the internal resistor in parallel with the resistors of the voltage divider 120 causes the voltage value of the signal present at the input pin 114 to change to a value closer to VREF / 2 than the voltage of the signal present at the input pin 114 in operation 504. In at least some examples, when the first control signal is asserted, the switch that receives the first control signal closes, coupling the internal resistor in parallel with resistor 122. Similarly, when the second control signal is asserted, the switch that receives the second control signal closes, connecting the internal resistor in parallel with resistor 124.

[0045] In operation 512, the input pin voltage is sampled to generate VS. In at least some examples, the input pin voltage is sampled by controlling ADC104 to measure the input pin voltage and generate VS as a digital representation of the input pin voltage using the channel of ADC104 coupled to input pin 114. In some examples, the control is performed by logic circuit 102 which outputs a channel selection signal to ADC104, causing ADC104 to sample the channel of ADC104 coupled to input pin 114. Sampling the input pin voltage is a hardware operation that causes ADC104 to generate VS based on the analog value present at input pin 114, in at least some examples. The generated digital code is provided to logic circuit 102 by ADC104 as one or more electrical impulses representing one or more digital bits, in at least some examples.

[0046] In operation 514, the resistance of the resistor in the voltage divider 120 is calculated. In at least some examples, the resistance is that of the bottom resistor of the voltage divider 120 (e.g., resistor 124). In other examples, the resistance is that of resistor 122. In some examples where the internal resistor is connected in series with resistor 122 in operation 510, the resistance of the resistor is determined according to Equation 1, as described above with respect to Figure 1. In an example where the internal resistor is connected in series with resistor 124 in operation 510, the resistance of the resistor is determined according to Equation 2, as described above with respect to Figure 1. In at least some examples, the resistance of the resistor is determined by logic circuit 102. In at least some examples, logic circuit 102 stores the resistance of the resistor as RCODE in a storage element. The storage element may be a register, a cache, or other volatile or non-volatile storage component or device. In at least some examples, the RCODE is a digital value accurate to at least 4 bits so that both the VCODE and the RCODE can accurately provide the electrical component 100 with at least 9 bits of programmability (e.g., at least 511 distinct values).

[0047] In operation 516, the device is programmed with settings according to the values ​​of VCODE and RCODE. For example, the logic circuit 102 may program itself, or another component of the electrical component 100 may be programmed (by either the logic circuit 102 or the other component) with specific settings according to VCODE and RCODE. In at least some examples, by controlling the value of VCODE based on the ratio of the resistance of the top resistor to the bottom resistor of the voltage divider, and by controlling the value of the selected resistor for RCODE, VCODE and RCODE together can provide a selection from at least 511 unique settings.

[0048] While the operation of Method 500 has been described and represented by numerical references, in various examples Method 500 includes additional operations not described herein. In some examples, any one or more operations described herein include one or more sub-operations (e.g., intermediate comparison, logical operation, output selection via multiplexer, format conversion, determination, etc.). In some examples, any one or more operations described herein are omitted. In some examples, any one or more operations described herein are performed in an order other than that presented herein (e.g., in reverse order, substantially simultaneously, overlapping, etc.). Each of these alternative examples is included within the scope of this specification.

[0049] In the foregoing description, the terms “include” and “incorporate” are used in an unrestricted manner and should therefore be interpreted as “include, but not limited to.” The term “combine” is used throughout this specification. This term may encompass connections, communications, or signaling paths that enable functional relationships consistent with the descriptions herein. For example, if device A generates a signal to control control device B to perform a certain action, in the first example device A is coupled to device B, and in the second example device A is coupled to device B via an intermediate component C, however, the intervening component C does not substantially alter the functional relationship between device A and device B via the control signal generated by device A, so that device B is controlled by device A via the control signal generated by device A. Devices “configured” to perform a certain task or function may be configured by the manufacturer at the time of manufacture to perform those functions (e.g., programmed and / or hardwired), or they may be configured (or reconfigurable) after manufacture by a user to perform those functions and / or other additional or alternative functions. Such configurations may be achieved through device firmware and / or software programming, through the configuration and / or layout of hardware components, through device interconnections, or through a combination thereof. Furthermore, a circuit or device said to include certain components may instead be configured to couple with those components to form the described circuit element or device. For example, a structure described as including one or more semiconductor elements (such as transistors), one or more passive elements (such as resistors, capacitors, and / or inductors), and / or one or more sources (such as voltage and / or current power supplies) may instead include only the semiconductor elements within a single physical device (e.g., a semiconductor die and / or integrated circuit (IC) package), which may be configured to couple with at least some of the passive elements and / or sources, thereby forming the described structure, for example, by an end user and / or a third party, either at the time of manufacture or at a later point in time.

[0050] Some components are described herein as belonging to a particular process technology, but these components may be interchangeable with components of other process technologies. A reconfigured circuit including the replaced components will provide the desired functionality that is at least partially similar to the functionality available before the component replacement. Unless otherwise specified, components shown as resistors generally represent one or more elements coupled in series and / or parallel to provide the amount of impedance represented by the illustrated resistors. Also, the term “ground voltage potential” includes chassis ground, earth ground, floating ground, virtual ground, digital ground, common ground, and / or any other form of ground connection applicable to or suitable for the teachings herein. Unless otherwise specified, “about,” “approximately,” or “substantially” preceding a value means + / - 10 percent of the stated value.

[0051] The above description is illustrative of the principles and various examples of this specification. Many changes and modifications will become apparent to those skilled in the art once the above description is fully understood. This specification encompasses all such changes and modifications.

Claims

1. It is an integrated circuit, An analog-to-digital converter (ADC) having an ADC input, an ADC output, and a control input, A resistor circuit having an input and an output coupled to the ADC input, A resistor having a first terminal and a second input coupled to the ADC input, wherein the resistance of the resistor is the resistance of the resistor circuit, A first switch coupled between the first terminal of the resistor and the reference voltage terminal, A second switch is coupled between the first terminal and the ground terminal of the resistor, The resistor circuit includes, A logic circuit having an input coupled to the ADC output, a first output coupled to the input of the resistor circuit, and a second output coupled to the control input, A first ADC control signal is generated at the second output. A control signal is generated at the first output, A second ADC control signal is generated at the second output. The first resistance at the ADC input is determined at least partially based on the second voltage at the ADC input, the resistance of the resistor circuit, and the reference voltage at the reference voltage terminal. The logic circuit is configured as follows: Includes, The ADC, In response to the first ADC control signal, the first voltage at the ADC input is determined by the first resistor at the ADC input. The second voltage is determined by a second resistor in the ADC input in response to the second ADC control signal. It is configured in such a way, An integrated circuit in which the resistor circuit is configured to modify the first resistor to the second resistor in response to the control signal.

2. The integrated circuit according to claim 1, A voltage divider coupled between the reference voltage terminal and the ground terminal, further comprising a resistor and having an output coupled to the ADC input, The aforementioned resistor circuit In response to the control signal, the first switch is controlled to couple the ADC input to the reference voltage terminal when the first voltage is less than a threshold. In response to the control signal, the second switch is controlled to connect the ADC input to the ground terminal when the first voltage is greater than the threshold. This configuration modifies the first resistor to the second resistor, An integrated circuit in which the threshold voltage is approximately half of the reference voltage, and the first resistance is the resistance of the resistor in the voltage divider.

3. It is an integrated circuit, An analog-to-digital converter (ADC) having an ADC input, an ADC output, and a control input, A resistor circuit having an input and an output coupled to the ADC input, A first resistor having a first terminal and a second terminal coupled to the ADC input, A first switch coupled between the second terminal of the first resistor and the reference voltage terminal, A second resistor having a first terminal and a second terminal coupled to the ADC input, A second switch coupled between the second terminal of the second resistor and the reference voltage terminal, A third resistor having a first terminal and a second terminal coupled to the ADC input, A third switch is coupled between the second terminal of the third resistor and the ground terminal, A fourth resistor having a first terminal and a second terminal coupled to the ADC input, A fourth switch is coupled between the second terminal of the fourth resistor and the ground terminal, The resistor circuit includes, A logic circuit having an input coupled to the ADC output, a first output coupled to the input of the resistor circuit, and a second output coupled to the control input, A first ADC control signal is generated at the second output. A control signal is generated at the first output, A second ADC control signal is generated at the second output. The first resistance at the ADC input is determined at least partially based on the second voltage at the ADC input, the resistance of the resistor circuit, and the reference voltage at the reference voltage terminal. The logic circuit is configured as follows: Includes, The ADC, In response to the first ADC control signal, the first voltage at the ADC input is determined by the first resistor at the ADC input. The second voltage is determined by a second resistor in the ADC input in response to the second ADC control signal. It is configured in such a way, An integrated circuit in which the resistor circuit is configured to modify the first resistor to the second resistor in response to the control signal.

4. The integrated circuit according to claim 3, A voltage divider coupled between the reference voltage terminal and the ground terminal, further comprising a resistor and having an output coupled to the ADC input, The first resistor, the second resistor, the third resistor, and the fourth resistor have different resistances from each other. The resistor circuit is configured to modify the first resistance to the second resistance by closing one of the first, second, third, or fourth switches in response to the control signal, based on the first voltage and the resistance values ​​of the first, second, third, or fourth resistors, respectively. An integrated circuit in which the first resistor is the resistor of the voltage divider.

5. It is an integrated circuit, An analog-to-digital converter (ADC) having an ADC input, an ADC output, and a control input, A resistor circuit having an input and an output coupled to the ADC input, A resistor having a first terminal and a second terminal coupled to the ADC input, A voltage source coupled between the second terminal of the resistor and the input of the resistor circuit, The resistor circuit includes, A logic circuit having an input coupled to the ADC output, a first output coupled to the input of the resistor circuit, and a second output coupled to the control input, A first ADC control signal is generated at the second output. A control signal is generated at the first output, A second ADC control signal is generated at the second output. The first resistance at the ADC input is determined at least partially based on the second voltage at the ADC input, the resistance of the resistor circuit, and the reference voltage at the reference voltage terminal. The logic circuit is configured as follows: Includes, The ADC, In response to the first ADC control signal, the first voltage at the ADC input is determined by the first resistor at the ADC input. The second voltage is determined by a second resistor in the ADC input in response to the second ADC control signal. It is configured in such a way, An integrated circuit in which the resistor circuit is configured to modify the first resistor to the second resistor in response to the control signal.

6. The integrated circuit according to claim 5, A voltage divider coupled between the reference voltage terminal and the ground terminal, further comprising a resistor and having an output coupled to the ADC input, The resistor circuit is configured to modify the first resistor to the second resistor by controlling the output voltage of the voltage source based on the first voltage. An integrated circuit in which the first resistor is the resistor of the voltage divider.

7. It is a system, A programmable electrical component, An analog-to-digital converter (ADC) having an ADC input, an ADC output, and a control input, A resistor circuit having an input and an output coupled to the ADC input, A logic circuit having an input coupled to the ADC input, a first output coupled to the input of the resistor circuit, and a second output coupled to the control input, A first ADC control signal is generated at the second output. A control signal is generated at the first output, A second ADC control signal is generated for the second output value. The first resistance at the ADC input is determined at least partially based on the second voltage at the ADC input, the resistance of the resistor circuit, and the reference voltage at the reference voltage terminal. The logic circuit is configured as follows: A voltage divider coupled between the reference voltage terminal and the ground terminal, having an output coupled to the ADC input, Including the programmable electrical components, The ADC, In response to the first ADC control signal, the first resistor determines the first voltage at the ADC input. The second voltage is determined by the second resistor in the ADC input. It is configured in such a way, A system in which the resistor circuit is configured to modify the first resistor to the second resistor in response to the control signal.

8. The system according to claim 7, The voltage divider includes a top resistor and a bottom resistor, The programmable electrical component is The ratio of the resistance of the top resistor to the resistance of the bottom resistor is modified to control the first voltage, Controlling the resistance of the resistor in the aforementioned voltage divider, A system that is programmable to at least one of 511 settings.

9. The system according to claim 7, A system wherein the logic circuit is further configured to determine the first resistance according to the reference voltage, the voltage at the ADC input when the resistor circuit is inactive, the voltage at the ADC input when the resistor circuit is coupled in the signal path between the ADC input and the reference voltage terminal or the signal path between the ADC input and the ground terminal, and the resistance of the resistor circuit.

Images