Demultiplexer
The demultiplexer design addresses the issue of increased insertion loss by using a combination of diplexers with optimized filter arrangements to efficiently separate multiple signals with reduced loss.
Patent Information
- Authority / Receiving Office
- JP · JP
- Patent Type
- Patents
- Current Assignee / Owner
- TDK CORP
- Filing Date
- 2022-10-18
- Publication Date
- 2026-07-08
AI Technical Summary
Existing demultiplexers face increased insertion loss in the passband when separating four or more signals due to the increase in the number of elements required, which worsens the performance of the filter between the common port and specific signal ports.
A demultiplexer configuration comprising a first diplexer, a second diplexer, and a third diplexer, each with specific filter arrangements to selectively pass signals within distinct frequency bands, reducing the number of elements and minimizing insertion loss.
The proposed demultiplexer design effectively reduces insertion loss in each passband by optimizing the signal paths and filter configurations, enhancing signal separation efficiency.
Smart Images
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Abstract
Description
Technical Field
[0001] The present invention relates to a demultiplexer configured to separate at least four signals.
Background Art
[0002] In small mobile communication devices, a configuration is widely used in which an antenna commonly used in a plurality of applications having different systems and operating frequency bands is provided, and a plurality of signals transmitted and received by this antenna are separated using a demultiplexer.
[0003] Generally, a demultiplexer that separates a first signal having a frequency within a first frequency band and a second signal having a frequency within a second frequency band higher than the first frequency band includes a common port, a first signal port, a second signal port, a first filter provided in a first signal path from the common port to the first signal port, and a second filter provided in a second signal path from the common port to the second signal port. As the first and second filters, for example, an LC resonator configured using an inductor and a capacitor is used.
[0004] In recent years, in small mobile communication devices, the operating frequency band has a tendency to increase with the adoption of new communication standards, and there is a demand to increase the number of signals separated by the demultiplexer. For example, Patent Document 1 discloses a diplexer that separates three signals, a quadplexer that separates four signals, a pentaplexer that separates five signals, and the like.
Prior Art Documents
Patent Documents
[0005]
Patent Document 1
Summary of the Invention
Problems to be Solved by the Invention
[0006] In particular, when there are four or more signals to be separated, the number of elements required for the demultiplexer increases. An increase in the number of elements along the signal path from the common port to a specific signal port leads to a problem where the insertion loss in the passband of the filter between the common port and the specific signal port worsens.
[0007] The present invention has been made in view of the above problems, and its object is to provide a demultiplexer configured to separate four signals, which is capable of reducing the insertion loss of the passband. [Means for solving the problem]
[0008] The demultiplexer of the present invention Input port, The first output port, The second output port, The third output port, The fourth output port, A first diplexer having a first input terminal connected to an input port, a first output terminal, and a second output terminal, A second diplexer having a second input terminal connected to a first output terminal, a third output terminal directly connected to a first output port, and a fourth output terminal directly connected to a second output port, A third diplexer having a third input terminal connected to a second output terminal, a fifth output terminal directly connected to a third output port, and a sixth output terminal directly connected to a fourth output port, It is equipped with. [Effects of the Invention]
[0009] The demultiplexer of the present invention includes first to third diplexers connected as described above. This provides the effect of reducing the insertion loss in the passband, according to the present invention. [Brief explanation of the drawing]
[0010] [Figure 1]This is a block diagram showing the configuration of a demultiplexer according to one embodiment of the present invention. [Figure 2] This is a circuit diagram showing an example of the circuit configuration of a demultiplexer according to one embodiment of the present invention. [Figure 3] This is a perspective view showing the external appearance of a demultiplexer according to one embodiment of the present invention. [Figure 4] This is an explanatory diagram showing the pattern formation surfaces of the first to third dielectric layers in a laminate of a demultiplexer according to one embodiment of the present invention. [Figure 5] This is an explanatory diagram showing the pattern formation surface of the fourth to sixth dielectric layers in a laminate of a demultiplexer according to one embodiment of the present invention. [Figure 6] This is an explanatory diagram showing the pattern formation surface of the 7th to 9th dielectric layers in a laminate of a demultiplexer according to one embodiment of the present invention. [Figure 7] This is an explanatory diagram showing the pattern formation surface of the 10th to 12th dielectric layers in a laminate of a demultiplexer according to one embodiment of the present invention. [Figure 8] This is an explanatory diagram showing the pattern formation surface of the 13th to 15th dielectric layers in a laminate of a demultiplexer according to one embodiment of the present invention. [Figure 9] This is an explanatory diagram showing the pattern formation surface of the 16th to 18th dielectric layers in a laminate of a demultiplexer according to one embodiment of the present invention. [Figure 10] This is an explanatory diagram showing the pattern formation surface of the 19th to 21st dielectric layers in a laminate of a demultiplexer according to one embodiment of the present invention. [Figure 11] This is an explanatory diagram showing the pattern formation surface of the 22nd to 24th dielectric layers in a laminate of a demultiplexer according to one embodiment of the present invention. [Figure 12] This is an explanatory diagram showing the pattern formation surface of the 25th to 27th dielectric layers in a laminate of a demultiplexer according to one embodiment of the present invention. [Figure 13] This is an explanatory diagram showing the pattern formation surface of the 28th dielectric layer in a laminate of a demultiplexer according to one embodiment of the present invention. [Figure 14]It is a perspective view showing the inside of a laminate of wavelength division multiplexers according to an embodiment of the present invention. [Figure 15] It is a circuit diagram showing the circuit configuration of a wavelength division multiplexer of the first comparative example. [Figure 16] It is a circuit diagram showing the circuit configuration of a wavelength division multiplexer of the second comparative example. [Figure 17] It is a characteristic diagram showing the passing attenuation characteristics of a model of an example. [Figure 18] It is a characteristic diagram showing the passing attenuation characteristics of a model of the first comparative example. [Figure 19] It is a characteristic diagram showing the passing attenuation characteristics of a model of the second comparative example.
Embodiments for Carrying Out the Invention
[0011] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. First, referring to FIG. 1, an outline of the configuration of a wavelength division multiplexer 1 according to an embodiment of the present invention will be described. FIG. 1 is a block diagram showing the configuration of the wavelength division multiplexer 1.
[0012] The wavelength division multiplexer 1 includes an input port 10, a first output port 11, a second output port 12, a third output port 13, and a fourth output port 14. The first output port 11 is a port through which signals having frequencies within the first passing band selectively pass. The second output port 12 is a port through which signals having frequencies within the second passing band selectively pass. The third output port 13 is a port through which signals having frequencies within the third passing band selectively pass. The fourth output port 14 is a port through which signals having frequencies within the fourth passing band selectively pass.
[0013] The second passband has a higher frequency band than the first passband. The fourth passband has a higher frequency band than the third passband. The third passband may have a higher frequency band than the second passband. Alternatively, the fourth passband may have a lower frequency band than the first passband. In this case, the third passband will also have a lower frequency band than the first passband. In the following explanation, we will assume that the third passband has a higher frequency band than the second passband.
[0014] The demultiplexer 1 further comprises a first diplexer 20, a second diplexer 30, and a third diplexer 40. The first diplexer 20 has an input terminal 20a and two output terminals 20b and 20c. The input terminal 20a of the first diplexer 20 is connected to the input port 10.
[0015] The second diplexer 30 has an input terminal 30a and two output terminals 30b and 30c. In terms of circuit configuration, the second diplexer 30 is provided between the output terminal 20b of the first diplexer 20 and the first and second output ports 11 and 12. The input terminal 30a of the second diplexer 30 is connected to the output terminal 20b of the first diplexer 20. The output terminal 30b of the second diplexer 30 is directly connected to the first output port 11. The output terminal 30c of the second diplexer 30 is directly connected to the second output port 12.
[0016] The third diplexer 40 has an input terminal 40a and two output terminals 40b and 40c. In terms of circuit configuration, the third diplexer 40 is located between the output terminal 20c of the first diplexer 20 and the third and fourth output ports 13 and 14. The input terminal 40a of the third diplexer 40 is connected to the output terminal 20c of the first diplexer 20. The output terminal 40b of the third diplexer 40 is directly connected to the third output port 13. The output terminal 40c of the third diplexer 40 is directly connected to the fourth output port 14.
[0017] In this application, the phrase "in terms of circuit configuration" refers to the arrangement on the circuit diagram, not the arrangement in the physical configuration. Furthermore, the phrase "directly connected" means that no other filters are provided between the output terminals and output ports of the connected diplexers.
[0018] The first diplexer 20 is configured to selectively pass signals in a frequency band that includes a second passband but does not include a third passband through the output terminal 20b, and to selectively pass signals in a frequency band that includes a third passband but does not include a second passband through the output terminal 20c. In this embodiment, the first diplexer 20 specifically includes a first filter 21 provided between the input terminal 20a and the output terminal 20b in the circuit configuration, and a second filter 22 provided between the input terminal 20a and the output terminal 20c in the circuit configuration. The first filter 21 is a filter that selectively passes signals in a frequency band that includes a first passband and a second passband but does not include a third passband. The second filter 22 is a filter that selectively passes signals in a frequency band that includes a third passband and a fourth passband but does not include a second passband.
[0019] The second diplexer 30 is configured to selectively pass signals with frequencies within the first passband to the output terminal 30b, and to selectively pass signals with frequencies within the second passband to the output terminal 30c. In this embodiment, the second diplexer 30 specifically includes a third filter 31 provided between the input terminal 30a and the output terminal 30b in the circuit configuration, and a fourth filter 32 provided between the input terminal 30a and the output terminal 30c in the circuit configuration. The third filter 31 is a filter that selectively passes signals with frequencies within the first passband. The fourth filter 32 is a filter that selectively passes signals with frequencies within the second passband.
[0020] The third diplexer 40 is configured to selectively pass signals with frequencies within a third passband through the output terminal 40b, and to selectively pass signals with frequencies within a fourth passband through the output terminal 40c. In this embodiment, the third diplexer 40 particularly includes a fifth filter 41 provided between the input terminal 40a and the output terminal 40b in the circuit configuration, and a sixth filter 42 provided between the input terminal 40a and the output terminal 40c in the circuit configuration. The fifth filter 41 is a filter that selectively passes signals with frequencies within a third passband. The sixth filter 42 is a filter that selectively passes signals with frequencies within a fourth passband.
[0021] The demultiplexer 1 further includes a first path P1 connecting the input port 10 and the first output port 11, a second path P2 connecting the input port 10 and the second output port 12, a third path P3 connecting the input port 10 and the third output port 13, and a fourth path P4 connecting the input port 10 and the fourth output port 14. The first and second paths P1 and P2 are the same path from the input terminal 20a of the first diplexer 20 to the input terminal 30a of the second diplexer 30. The third and fourth paths P3 and P4 are the same path from the input terminal 20a of the first diplexer 20 to the input terminal 40a of the third diplexer 40.
[0022] The first filter 21 is located in a path connecting the input terminal 20a and output terminal 20b of the first diplexer 20, and is provided in a path that constitutes a part of the first and second paths P1 and P2, respectively. The second filter 22 is located in a path connecting the input terminal 20a and output terminal 20c of the first diplexer 20, and is provided in a path that constitutes a part of the third and fourth paths P3 and P4, respectively.
[0023] The third and fourth filters 31 and 32 are located after the first filter 21. The first and second paths P1 and P2 branch off after the first filter 21. The third filter 31 is located on the first path P1. The fourth filter 32 is located on the second path P2.
[0024] The fifth and sixth filters 41 and 42 are located after the second filter 22. The third and fourth paths P3 and P4 branch off after the second filter 22. The fifth filter 41 is located on the third path P3. The sixth filter 42 is located on the fourth path P4.
[0025] The first signal, with a frequency within the first passband, input to input port 10, selectively passes through the first path P1, i.e., the first and third filters 21 and 31, and is output from the first output port 11. The second signal, with a frequency within the second passband, input to input port 10, selectively passes through the second path P2, i.e., the first and fourth filters 21 and 32, and is output from the second output port 12. The third signal, with a frequency within the third passband, input to input port 10, selectively passes through the third path P3, i.e., the second and fifth filters 22 and 41, and is output from the third output port 13. The fourth signal, with a frequency within the fourth passband, input to input port 10, selectively passes through the fourth path P4, i.e., the second and sixth filters 22 and 42, and is output from the fourth output port 14. In this way, the demultiplexer 1 separates the first to fourth signals.
[0026] Next, an example of the circuit configuration of the demultiplexer 1 will be described with reference to Figure 2. Figure 2 is a circuit diagram showing an example of the circuit configuration of the demultiplexer 1.
[0027] First, the configuration of the first diplexer 20 will be described. The first filter 21 of the first diplexer 20 includes inductors L21 and L22 and capacitors C21 and C22. One end of inductor L21 is connected to the input terminal 20a of the first diplexer 20. One end of inductor L22 is connected to the other end of inductor L21. The other end of inductor L22 is connected to the output terminal 20b of the first diplexer 20.
[0028] One end of capacitor C21 is connected to the connection point of inductors L21 and L22. The other end of capacitor C21 is connected to ground. Capacitor C22 is connected in parallel with inductor L22.
[0029] The second filter 22 of the first diplexer 20 includes inductors L23, L24, L25 and capacitors C23, C24, C25, C26. One end of inductor L23 is connected to the input terminal 20a of the first diplexer 20.
[0030] One end of capacitor C23 is connected to the other end of inductor L23. One end of capacitor C24 is connected to the other end of capacitor C23. One end of capacitor C25 is connected to one end of capacitor C23. The other end of capacitor C25 and one end of capacitor C26 are connected to the other end of capacitor C24. The other end of capacitor C26 is connected to the output terminal 20c of the first diplexer 20.
[0031] One end of inductor L24 is connected to the junction point of capacitors C23 and C24. One end of inductor L25 is connected to the junction point of capacitors C24 and C25. The other ends of inductors L24 and L25 are connected to ground.
[0032] Next, the configuration of the second diplexer 30 will be described. The third filter 31 of the second diplexer 30 includes inductors L31 and L32 and capacitors C31 and C32. One end of inductor L31 is connected to the input terminal 30a of the second diplexer 30. One end of inductor L32 is connected to the other end of inductor L31. The other end of inductor L32 is connected to the output terminal 30b of the second diplexer 30.
[0033] One end of capacitor C31 is connected to the connection point of inductors L31 and L32. The other end of capacitor C31 is connected to ground. Capacitor C32 is connected in parallel with inductor L32.
[0034] The fourth filter 32 of the second diplexer 30 includes inductors L33, L34 and capacitors C33, C34, C35. One end of inductor L33 is connected to the input terminal 30a of the second diplexer 30.
[0035] One end of capacitor C33 is connected to the other end of inductor L33. One end of capacitor C34 is connected to the other end of capacitor C33. The other end of capacitor C34 is connected to the output terminal 30c of the second diplexer 30. One end of capacitor C35 is connected to one end of capacitor C33. The other end of capacitor C35 is connected to the other end of capacitor C34.
[0036] One end of inductor L34 is connected to the junction point of capacitors C33 and C34. The other end of inductor L34 is connected to ground.
[0037] Next, the configuration of the third diplexer 40 will be described. The fifth filter 41 of the third diplexer 40 includes inductors L41 and L42 and capacitors C41 and C42. One end of inductor L41 is connected to the input terminal 40a of the third diplexer 40. One end of inductor L42 is connected to the other end of inductor L41. The other end of inductor L42 is connected to the output terminal 40b of the third diplexer 40.
[0038] One end of capacitor C41 is connected to the connection point of inductors L41 and L42. The other end of capacitor C41 is connected to ground. Capacitor C42 is connected in parallel with inductor L42.
[0039] The sixth filter 42 of the third diplexer 40 includes inductors L43, L44, L45 and capacitors C43, C44, C45, C46, C47, C48. One end of capacitor C43 is connected to the input terminal 40a of the third diplexer 40. One end of capacitor C44 is connected to the other end of capacitor C43. One end of capacitor C45 is connected to one end of capacitor C43. The other end of capacitor C45 is connected to the other end of capacitor C44.
[0040] One end of inductor L43 is connected to the junction point of capacitors C43 and C44. The other end of inductor L43 is connected to ground.
[0041] One end of inductor L44 is connected to the other end of capacitor C44. The other end of inductor L44 is connected to the output terminal 40c of the third diplexer 40.
[0042] One end of capacitor C46 and one end of capacitor C48 are connected to one end of inductor L44. One end of capacitor C47 and the other end of capacitor C48 are connected to the other end of inductor L44.
[0043] One end of inductor L45 is connected to the other ends of capacitors C46 and C47. The other end of inductor L45 is connected to ground.
[0044] Next, with reference to Figure 3, the other components of the demultiplexer 1 will be described. Figure 3 is a perspective view showing the external appearance of the demultiplexer 1.
[0045] The demultiplexer 1 further comprises a laminate 50 including multiple stacked dielectric layers and multiple conductors. The laminate 50 is for integrating the input port 10, the first to fourth output ports 11-14, and the first to third diplexers 20, 30, and 40. The first to third diplexers 20, 30, and 40 are each composed of multiple conductors.
[0046] The laminate 50 has a bottom surface 50A and an upper surface 50B located at both ends of the stacking direction T of the multiple dielectric layers, and four side surfaces 50C to 50F connecting the bottom surface 50A and the upper surface 50B. Side surfaces 50C and 50D face opposite each other, and side surfaces 50E and 50F also face opposite each other. Side surfaces 50C to 50F are perpendicular to the upper surface 50B and the bottom surface 50A.
[0047] Here, as shown in Figure 3, we define the X, Y, and Z directions. The X, Y, and Z directions are orthogonal to each other. In this embodiment, the direction parallel to the stacking direction T is defined as the Z direction. The direction opposite to the X direction is defined as the -X direction, the direction opposite to the Y direction is defined as the -Y direction, and the direction opposite to the Z direction is defined as the -Z direction. Furthermore, the expression "when viewed from the stacking direction T" means viewing the object from a position away in the Z or -Z direction.
[0048] As shown in Figure 3, the bottom surface 50A is located at the -Z end of the laminate 50. The top surface 50B is located at the Z end of the laminate 50. The side surface 50C is located at the -X end of the laminate 50. The side surface 50D is located at the X end of the laminate 50. The side surface 50E is located at the -Y end of the laminate 50. The side surface 50F is located at the Y end of the laminate 50.
[0049] The demultiplexer 1 further includes an input terminal 111, output terminals 113, 115, 116, 117, and ground terminals 112, 114, 118, 119 connected to ground. The input terminal 111, output terminals 113, 115, 116, 117, and ground terminals 112, 114, 118, 119 are located on the bottom surface 50A of the laminate 50.
[0050] Input terminal 111 is located near the corner where the bottom surface 50A intersects with side surfaces 50C and 50E. Output terminal 113 is located near the corner where the bottom surface 50A intersects with side surfaces 50D and 50E. Output terminal 115 is located near the corner where the bottom surface 50A intersects with side surfaces 50D and 50F. Output terminal 117 is located near the corner where the bottom surface 50A intersects with side surfaces 50C and 50F.
[0051] Ground terminal 112 is located between input terminal 111 and output terminal 113. Ground terminal 114 is located between output terminal 113 and output terminal 115. Output terminal 116 is located between output terminal 115 and output terminal 117. Ground terminal 118 is located between input terminal 111 and output terminal 117. Ground terminal 119 is located in the center of the bottom surface 50A.
[0052] Input terminal 111 corresponds to input port 10, output terminal 113 corresponds to the fourth output port 14, output terminal 115 corresponds to the third output port 13, output terminal 116 corresponds to the second output port 12, and output terminal 117 corresponds to the first output port 11. Therefore, input port 10 and the first to fourth output ports 11-14 are located on the bottom surface 50A of the laminate 50.
[0053] Next, with reference to Figures 4(a) to 13, an example of multiple dielectric layers and multiple conductors constituting the laminate 50 will be described. In this example, the laminate 50 has 28 stacked dielectric layers. Hereinafter, these 28 dielectric layers will be referred to as the 1st to 28th dielectric layers, from bottom to top. The 1st to 28th dielectric layers will also be denoted by reference numerals 51 to 78.
[0054] In Figures 4(a) to 12(b), the circles represent multiple through-holes. Each of the dielectric layers 51 to 76 has multiple through-holes formed within it. Each of the multiple through-holes is formed by filling the through-hole holes with conductive paste. Each of the multiple through-holes is connected to a conductive layer or another through-hole.
[0055] Figure 4(a) shows the pattern formation surface of the first dielectric layer 51. Input terminals 111, output terminals 113, 115, 116, 117, and ground terminals 112, 114, 118, 119 are formed on the pattern formation surface of the dielectric layer 51. Figure 4(b) shows the pattern formation surface of the second dielectric layer 52. Conductor layers 521, 522, 523, 524, 525, 526 are formed on the pattern formation surface of the dielectric layer 52.
[0056] Figure 4(c) shows the pattern formation surface of the third dielectric layer 53. Conductor layers 531, 532, 533, 534, 535, 536, 537, 538, and 539 are formed on the pattern formation surface of the dielectric layer 53. Conductor layer 532 is connected to conductor layer 531. Conductor layer 538 is connected to conductor layer 537.
[0057] Figure 5(a) shows the pattern formation surface of the fourth dielectric layer 54. Conductor layers 541, 542, 543, 544, 545, and 546 are formed on the pattern formation surface of the dielectric layer 54. Figure 5(b) shows the pattern formation surface of the fifth dielectric layer 55. Conductor layers 551, 552, 553, 554, and 555 are formed on the pattern formation surface of the dielectric layer 55. Figure 5(c) shows the pattern formation surface of the sixth dielectric layer 56. Conductor layers 561 and 562 are formed on the pattern formation surface of the dielectric layer 56.
[0058] Figure 6(a) shows the pattern formation surface of the seventh dielectric layer 57. Conductor layer 571 is formed on the pattern formation surface of dielectric layer 57. Figure 6(b) shows the pattern formation surface of the eighth dielectric layer 58. Conductor layers 581, 582, 583, 584, 585, and 586 are formed on the pattern formation surface of dielectric layer 58. Figure 6(c) shows the pattern formation surface of the ninth dielectric layer 59. Conductor layers 592, 594, 595, and 596 are formed on the pattern formation surface of dielectric layer 59.
[0059] Figure 7(a) shows the pattern formation surface of the 10th dielectric layer 60. Conductor layers 602, 604, and 605 are formed on the pattern formation surface of the dielectric layer 60. Figure 7(b) shows the pattern formation surface of the 11th dielectric layer 61. Conductor layers 611, 612, 613, 614, and 615 are formed on the pattern formation surface of the dielectric layer 61. Figure 7(c) shows the pattern formation surface of the 12th dielectric layer 62. Conductor layers 621, 622, 623, 624, and 625 are formed on the pattern formation surface of the dielectric layer 62.
[0060] Figure 8(a) shows the pattern formation surface of the 13th dielectric layer 63. Conductor layers 631, 632, 633, and 634 are formed on the pattern formation surface of the dielectric layer 63. Figure 8(b) shows the pattern formation surface of the 14th dielectric layer 64. Conductor layers 641, 642, 643, and 644 are formed on the pattern formation surface of the dielectric layer 64. Figure 8(c) shows the pattern formation surface of the 15th dielectric layer 65. Conductor layers 652 and 653 are formed on the pattern formation surface of the dielectric layer 65.
[0061] Figure 9(a) shows the pattern formation surface of the 16th dielectric layer 66. Conductor layers 662 and 663 are formed on the pattern formation surface of the dielectric layer 66. Figure 9(b) shows the pattern formation surface of the 17th dielectric layer 67. Conductor layers 674 and 675 are formed on the pattern formation surface of the dielectric layer 67. Figure 9(c) shows the pattern formation surface of the 18th dielectric layer 68. Conductor layers 684 and 685 are formed on the pattern formation surface of the dielectric layer 68.
[0062] Figure 10(a) shows the pattern formation surface of the 19th dielectric layer 69. Conductor layers 692, 693, 694, and 695 are formed on the pattern formation surface of the dielectric layer 69. Figure 10(b) shows the pattern formation surface of the 20th dielectric layer 70. Conductor layers 702, 703, 704, and 705 are formed on the pattern formation surface of the dielectric layer 70. Figure 10(c) shows the pattern formation surface of the 21st dielectric layer 71. Conductor layers 711, 712, 713, 714, and 715 are formed on the pattern formation surface of the dielectric layer 71.
[0063] Figure 11(a) shows the pattern formation surface of the 22nd dielectric layer 72. Conductor layers 721, 722, 723, 724, and 725 are formed on the pattern formation surface of dielectric layer 72. Figure 11(b) shows the pattern formation surface of the 23rd dielectric layer 73. Conductor layers 731, 732, 733, 734, 735, and 736 are formed on the pattern formation surface of dielectric layer 73. Figure 11(c) shows the pattern formation surface of the 24th dielectric layer 74. Conductor layers 741, 742, 743, 744, 745, and 746 are formed on the pattern formation surface of dielectric layer 74.
[0064] Figure 12(a) shows the pattern formation surface of the 25th dielectric layer 75. Conductor layers 751, 752, 753, and 754 are formed on the pattern formation surface of dielectric layer 75. Conductor layer 754 is connected to conductor layer 752. Figure 12(b) shows the pattern formation surface of the 26th dielectric layer 76. Conductor layers 761, 762, 763, 764, 765, and 766 are formed on the pattern formation surface of dielectric layer 76. Conductor layer 764 is connected to conductor layer 763. Conductor layer 766 is connected to conductor layer 764. In Figure 12(b), the boundary between two conductor layers is shown by a dotted line. Figure 12(c) shows the pattern formation surface of the 27th dielectric layer 77. Conductor layers 771, 772, and 773 are formed on the pattern formation surface of dielectric layer 77. Conductor layer 773 is connected to conductor layer 772.
[0065] Figure 13 shows the pattern formation surface of the 28th dielectric layer 78. A mark 781 is formed on the pattern formation surface of the dielectric layer 78.
[0066] The laminate 50 shown in Figure 3 is constructed by stacking dielectric layers 51 to 78, with the pattern-forming surface of the first dielectric layer 51 becoming the bottom surface 50A of the laminate 50, and the surface of the 28th dielectric layer 78 opposite to the pattern-forming surface becoming the top surface 50B of the laminate 50.
[0067] Each of the multiple through-holes shown in Figures 4(a) to 12(b) is connected to a conductor layer or another through-hole that overlaps in the stacking direction T when the first to 27th dielectric layers 51 to 77 are stacked. Furthermore, among the multiple through-holes shown in Figures 4(a) to 12(b), those located within a terminal or a conductor layer are connected to that terminal or conductor layer.
[0068] Figure 14 shows the interior of the laminate 50, which is constructed by stacking dielectric layers 51 to 78 from the first to the 28th layer. As shown in Figure 14, multiple conductor layers and multiple through-holes, as shown in Figures 4(a) to 12(c), are stacked inside the laminate 50. Note that mark 781 is omitted in Figure 14.
[0069] The laminate 50 is manufactured, for example, by a low-temperature co-firing method using ceramic materials for the dielectric layers 51 to 78. In this case, first, multiple ceramic green sheets are manufactured, each of which will later become the dielectric layers 51 to 78. Each ceramic green sheet has multiple pre-firing conductive layers that will later become multiple conductive layers, and multiple pre-firing through holes that will later become multiple through holes. Next, the multiple ceramic green sheets are stacked to create a green sheet laminate. Next, this green sheet laminate is cut to create a pre-firing laminate. Finally, the ceramic and conductive materials in this pre-firing laminate are fired using a low-temperature co-firing process to complete the laminate 50.
[0070] The following describes the correspondence between the circuit components of the demultiplexer 1 shown in Figure 2 and the internal components of the laminate 50 shown in Figures 4(b) to 12(c). First, the components of the first filter 21 will be described. Inductor L21 is composed of conductor layers 711, 721, 731, and 741. Inductor L22 is composed of conductor layers 611, 621, 631, and 641.
[0071] Capacitor C21 is composed of conductive layers 531, 541 and a dielectric layer 53 between these conductive layers. Capacitor C22 is composed of conductive layers 541, 551 and a dielectric layer 54 between these conductive layers.
[0072] Next, the components of the second filter 22 will be described. Inductor L23 is composed of conductor layers 692, 702, 712, 722, 732, and 742. Inductor L24 is composed of conductor layers 592, 602, 612, 622, 632, 642, 652, and 662. Inductor L25 is composed of conductor layers 613, 623, 633, 643, 653, and 663.
[0073] Capacitor C23 is composed of conductive layers 761, 771 and a dielectric layer 76 between these conductive layers. Capacitor C24 is composed of conductive layers 761, 772 and a dielectric layer 76 between these conductive layers. Capacitor C25 is composed of conductive layers 762, 772 and a dielectric layer 76 between these conductive layers. Capacitor C26 is composed of conductive layers 763, 773 and a dielectric layer 76 between these conductive layers.
[0074] Next, the components of the third filter 31 will be described. Inductor L31 is composed of conductor layers 693, 703, 713, 723, 733, and 743. Inductor L32 is composed of conductor layers 594, 604, 614, and 624.
[0075] Capacitor C31 is composed of conductive layers 532, 542, 552, 561 and dielectric layers 53, 54, 55 between these conductive layers. Capacitor C32 is composed of conductive layers 533, 542, 561, 571 and dielectric layers 53, 56 between these conductive layers.
[0076] Next, the components of the fourth filter 32 will be described. The inductor L33 is composed of conductor layers 595, 605, 615, and 625. The inductor L34 is composed of conductor layers 674, 684, 694, 704, 714, 724, 734, and 744.
[0077] Capacitor C33 is composed of conductive layers 553, 562 and dielectric layers 55 between these conductive layers. Capacitor C34 is composed of conductive layers 534, 543, 553 and dielectric layers 53, 54 between these conductive layers. Capacitor C35 is composed of conductive layers 535, 543 and dielectric layers 53 between these conductive layers.
[0078] Next, the components of the fifth filter 41 will be described. The inductor L41 is composed of conductor layers 715, 725, 735, and 745. The inductor L42 is composed of conductor layers 736 and 746, a plurality of through-holes connected in series connecting conductor layer 554 and conductor layer 736, and a plurality of through-holes connected in series connecting conductor layer 544 and conductor layer 736.
[0079] Capacitor C41 is composed of conductive layers 536, 544 and a dielectric layer 53 between these conductive layers. Capacitor C42 is composed of conductive layers 544, 554 and a dielectric layer 54 between these conductive layers.
[0080] Next, the components of the sixth filter 42 will be described. The inductor L43 is composed of conductor layers 675, 685, 695, and 705.
[0081] Capacitor C43 is composed of conductive layers 752 and 764 and a dielectric layer 75 between these conductive layers. Capacitor C44 is composed of conductive layers 753 and 764 and a dielectric layer 75 between these conductive layers. Capacitor C45 is composed of conductive layers 754 and 765 and a dielectric layer 75 between these conductive layers.
[0082] Inductor L44 is composed of conductor layers 634 and 644, multiple through-holes connected in series connecting conductor layer 586 and conductor layer 634, and multiple through-holes connected in series connecting conductor layer 546 and conductor layer 634. Inductor L45 is composed of conductor layer 525.
[0083] Capacitor C46 is composed of conductive layers 537 and 545 and a dielectric layer 53 between these conductive layers. Capacitor C47 is composed of conductive layers 538 and 546 and a dielectric layer 53 between these conductive layers. Capacitor C48 is composed of conductive layers 546 and 555 and a dielectric layer 54 between these conductive layers.
[0084] Next, the operation and effects of the demultiplexer 1 according to this embodiment will be described. The demultiplexer 1 according to this embodiment is equipped with first to third diplexers 20, 30, and 40 connected as described above. As a result, according to this embodiment, the insertion loss in each of the first to fourth passbands can be reduced. The effects of this embodiment will be described below in comparison with the demultiplexers of the first and second comparative examples.
[0085] First, the configuration of the demultiplexer 201 of the first comparative example will be described with reference to Figure 15. Figure 15 is a circuit diagram showing the circuit configuration of the demultiplexer 201 of the first comparative example. The demultiplexer 201 of the first comparative example is configured to separate a first signal with frequencies within the first passband, a second signal with frequencies within the second passband, a third signal with frequencies within the third passband, and a fourth signal with frequencies within the fourth passband, similar to the demultiplexer 1 of this embodiment. That is, the demultiplexer 201 of the first comparative example includes an input port 210, a first output port 211, a second output port 212, a third output port 213, and a fourth output port 214. The functions of the input port 210 and the first to fourth output ports 211 to 214 are the same as those of the input port 10 and the first to fourth output ports 11 to 14 in this embodiment.
[0086] The demultiplexer 201 further comprises a first diplexer 220, a second diplexer 230, and a third diplexer 240. The first diplexer 220 has an input terminal 220a and two output terminals 220b and 220c. The input terminal 220a of the first diplexer 220 is connected to the input port 210. The output terminal 220b of the first diplexer 220 is connected to the first output port 211.
[0087] The second diplexer 230 has an input terminal 230a and two output terminals 230b and 230c. The input terminal 230a of the second diplexer 230 is connected to the output terminal 220c of the first diplexer 220. The output terminal 230b of the second diplexer 230 is connected to the second output port 212.
[0088] The third diplexer 240 has an input terminal 240a and two output terminals 240b and 240c. The input terminal 240a of the third diplexer 240 is connected to the output terminal 230c of the second diplexer 230. The output terminal 240b of the third diplexer 240 is connected to the third output port 213. The output terminal 240c of the third diplexer 240 is connected to the fourth output port 214.
[0089] The first diplexer 220 includes a first filter 221 provided between the input terminal 220a and the output terminal 220b in the circuit configuration, and a second filter 222 provided between the input terminal 220a and the output terminal 220c in the circuit configuration. The first filter 221 is a filter that selectively passes signals with frequencies within a first passband. The second filter 22 is a filter that selectively passes signals in frequency bands that include second to fourth passbands but do not include the first passband.
[0090] The second diplexer 230 includes a third filter 231 provided between the input terminal 230a and the output terminal 230b in the circuit configuration, and a fourth filter 232 provided between the input terminal 230a and the output terminal 230c in the circuit configuration. The third filter 231 is a filter that selectively passes signals with frequencies within the second passband. The fourth filter 232 is a filter that selectively passes signals in frequency bands that include the third and fourth passbands but do not include the second passband.
[0091] The third diplexer 240 includes a fifth filter 241 provided between the input terminal 240a and the output terminal 240b in the circuit configuration, and a sixth filter 242 provided between the input terminal 240a and the output terminal 240c in the circuit configuration. The fifth filter 241 is a filter that selectively passes signals with frequencies within the third passband. The sixth filter 242 is a filter that selectively passes signals with frequencies within the fourth passband.
[0092] The specific circuit configurations of the first and second filters 221 and 222 of the first diplexer 220 are the same as the circuit configurations of the third and fourth filters 31 and 32 of the second diplexer 30 in this embodiment. By replacing the input terminal 30a, output terminals 30b and 30c, inductors L31, L32, L33, L34, and capacitors C31, C32, C33, C34, and C35 in the description of the circuit configurations of the third and fourth filters 31 and 32 with input terminal 220a, output terminals 220b and 220c, inductors L221, L222, L223, L224, and capacitors C221, C222, C223, C224, and C225, respectively, the circuit configurations of the first and second filters 221 and 222 will be described.
[0093] The specific circuit configurations of the third and fourth filters 231 and 232 of the second diplexer 230 are the same as those of the first and second filters 21 and 22 of the first diplexer 20 in this embodiment. By replacing the input terminal 20a, output terminals 20b and 20c, inductors L21, L22, L23, L24, L25, and capacitors C21, C22, C23, C24, C25, and C26 in the description of the circuit configurations of the first and second filters 21 and 22 with input terminal 230a, output terminals 230b and 230c, inductors L231, L232, L233, L234, L235, and capacitors C231, C232, C233, C234, C235, and C236, respectively, the circuit configurations of the third and fourth filters 231 and 232 can be described.
[0094] The specific circuit configurations of the fifth and sixth filters 241 and 242 of the third diplexer 240 are the same as those of the fifth and sixth filters 41 and 42 of the third diplexer 40 in this embodiment. If you replace the input terminal 40a, output terminals 40b, 40c, inductors L41, L42, L43, L44, L45 and capacitors C41, C42, C43, C44, C45, C46, C47, C48 in the circuit configuration description for the fifth and sixth filters 41 and 42 with input terminal 240a, output terminals 240b, 240c, inductors L241, L242, L243, L244, L245 and capacitors C241, C242, C243, C244, C245, C246, C247, C248 respectively, you will get the circuit configuration description for the fifth and sixth filters 241 and 242.
[0095] Next, the configuration of the second comparative example demultiplexer 301 will be described with reference to Figure 16. Figure 16 is a circuit diagram showing the circuit configuration of the second comparative example demultiplexer 301. Similar to the demultiplexer 1 according to this embodiment, the second comparative example demultiplexer 301 is configured to separate a first signal with frequencies within the first passband, a second signal with frequencies within the second passband, a third signal with frequencies within the third passband, and a fourth signal with frequencies within the fourth passband. That is, the second comparative example demultiplexer 301 includes an input port 310, a first output port 311, a second output port 312, a third output port 313, and a fourth output port 314. The functions of the input port 310 and the first to fourth output ports 311-314 are the same as those of the input port 10 and the first to fourth output ports 11-14 in this embodiment.
[0096] The demultiplexer 301 further comprises a first diplexer 320, a second diplexer 330, and a third diplexer 340. The first diplexer 320 has an input terminal 320a and two output terminals 320b and 320c. The input terminal 320a of the first diplexer 320 is connected to the input port 310. The output terminal 320c of the first diplexer 320 is connected to the fourth output port 314.
[0097] The second diplexer 330 has an input terminal 330a and two output terminals 330b and 330c. The input terminal 330a of the second diplexer 330 is connected to the output terminal 320b of the first diplexer 320. The output terminal 330c of the second diplexer 330 is connected to the third output port 313.
[0098] The third diplexer 340 has an input terminal 340a and two output terminals 340b and 340c. The input terminal 340a of the third diplexer 340 is connected to the output terminal 330b of the second diplexer 330. The output terminal 340b of the third diplexer 340 is connected to the first output port 311. The output terminal 340c of the third diplexer 340 is connected to the second output port 312.
[0099] The first diplexer 320 includes a first filter 321 provided between the input terminal 320a and the output terminal 320b in the circuit configuration, and a second filter 322 provided between the input terminal 320a and the output terminal 320c in the circuit configuration. The first filter 321 is a filter that selectively passes signals in a frequency band that includes the first to third passbands but does not include the fourth passband. The second filter 322 is a filter that selectively passes signals with frequencies within the fourth passband.
[0100] The second diplexer 330 includes a third filter 331 provided between the input terminal 330a and the output terminal 330b in the circuit configuration, and a fourth filter 332 provided between the input terminal 330a and the output terminal 330c in the circuit configuration. The third filter 331 is a filter that selectively passes signals in a frequency band that includes the first and second passbands but does not include the third passband. The fourth filter 332 is a filter that selectively passes signals with frequencies within the third passband.
[0101] The third diplexer 340 includes a fifth filter 341 provided between the input terminal 340a and the output terminal 340b in the circuit configuration, and a sixth filter 342 provided between the input terminal 340a and the output terminal 340c in the circuit configuration. The fifth filter 341 is a filter that selectively passes signals with frequencies within the first passband. The sixth filter 342 is a filter that selectively passes signals with frequencies within the second passband.
[0102] The specific circuit configurations of the first and second filters 321 and 322 of the first diplexer 320 are the same as the circuit configurations of the fifth and sixth filters 41 and 42 of the third diplexer 40 in this embodiment. If the input terminal 40a, output terminals 40b, 40c, inductors L41, L42, L43, L44, L45, and capacitors C41, C42, C43, C44, C45, C46, C47, C48 in the circuit configuration description of the fifth and sixth filters 41 and 42 are replaced with input terminal 320a, output terminals 320b, 320c, inductors L321, L322, L323, L324, L325, and capacitors C321, C322, C323, C324, C325, C326, C327, C328 respectively, the circuit configuration description of the first and second filters 321 and 322 will be obtained.
[0103] The specific circuit configurations of the third and fourth filters 331 and 332 of the second diplexer 330 are the same as those of the first and second filters 21 and 22 of the first diplexer 20 in this embodiment. By replacing the input terminal 20a, output terminals 20b and 20c, inductors L21, L22, L23, L24, L25, and capacitors C21, C22, C23, C24, C25, and C26 in the description of the circuit configurations of the first and second filters 21 and 22 with input terminal 330a, output terminals 330b and 330c, inductors L331, L332, L333, L334, L335, and capacitors C331, C332, C333, C334, C335, and C336, respectively, the circuit configurations of the third and fourth filters 331 and 332 can be described.
[0104] The specific circuit configurations of the fifth and sixth filters 341 and 342 of the third diplexer 340 are the same as those of the third and fourth filters 31 and 32 of the second diplexer 30 in this embodiment. By replacing the input terminal 30a, output terminals 30b and 30c, inductors L31, L32, L33, L34, and capacitors C31, C32, C33, C34, and C35 in the description of the circuit configurations of the third and fourth filters 31 and 32 with input terminal 340a, output terminals 340b and 340c, inductors L341, L342, L343, L344, and capacitors C341, C342, C343, C344, and C345, respectively, the circuit configurations of the fifth and sixth filters 341 and 342 can be described.
[0105] Next, we will describe the results of a simulation comparing the pass-through attenuation characteristics of the demultiplexer 1 according to this embodiment with the pass-through attenuation characteristics of the demultiplexers 201 and 301 of the first and second comparative examples. In the simulation, the model of the embodiment, the model of the first comparative example, and the model of the second comparative example were used. The model of the embodiment is the model of the demultiplexer 1 according to this embodiment, which has the circuit configuration shown in Figure 2. The model of the first comparative example is the model of the demultiplexer 201 of the first comparative example. The model of the second comparative example is the model of the demultiplexer 301 of the second comparative example. In the simulation, the pass-through attenuation characteristics between the input port and each of the first to fourth output ports were determined for each of the models of the embodiment, the model of the first comparative example, and the model of the second comparative example.
[0106] Figure 17 is a characteristic diagram showing the pass-through attenuation characteristics of the embodiment model. Figure 18 is a characteristic diagram showing the pass-through attenuation characteristics of the first comparative example model. Figure 19 is a characteristic diagram showing the pass-through attenuation characteristics of the second comparative example model. In Figures 17 to 19, the horizontal axis represents frequency and the vertical axis represents attenuation.
[0107] In Figure 17, reference numeral 101 indicates the pass-through attenuation characteristics between the input port 10 and the first output port 11. Reference numeral 102 indicates the pass-through attenuation characteristics between the input port 10 and the second output port 12. Reference numeral 103 indicates the pass-through attenuation characteristics between the input port 10 and the third output port 13. Reference numeral 104 indicates the pass-through attenuation characteristics between the input port 10 and the fourth output port 14.
[0108] In Figure 18, reference numeral 111 indicates the pass-through attenuation characteristics between the input port 210 and the first output port 211. Reference numeral 112 indicates the pass-through attenuation characteristics between the input port 210 and the second output port 212. Reference numeral 113 indicates the pass-through attenuation characteristics between the input port 210 and the third output port 213. Reference numeral 114 indicates the pass-through attenuation characteristics between the input port 210 and the fourth output port 214.
[0109] In Figure 19, reference numeral 121 indicates the pass-through attenuation characteristics between the input port 310 and the first output port 311. Reference numeral 122 indicates the pass-through attenuation characteristics between the input port 310 and the second output port 312. Reference numeral 123 indicates the pass-through attenuation characteristics between the input port 310 and the third output port 313. Reference numeral 124 indicates the pass-through attenuation characteristics between the input port 310 and the fourth output port 314.
[0110] Furthermore, in Figure 17, the arrow denoted by reference numeral 81 schematically indicates the first passband of the demultiplexer 1. The arrow denoted by reference numeral 82 schematically indicates the second passband of the demultiplexer 1. The arrow denoted by reference numeral 83 schematically indicates the third passband of the demultiplexer 1. The arrow denoted by reference numeral 84 schematically indicates the fourth passband of the demultiplexer 1. Although not shown in the figures, the first to fourth passbands of the demultiplexer 201 of the first comparative example and the first to fourth passbands of the demultiplexer 301 of the second comparative example are the same as the first to fourth passbands of the demultiplexer 1.
[0111] In the model of the embodiment, the attenuation at the upper frequency of the first passband was -0.62 dB. The attenuation at the lower frequency of the second passband was -0.87 dB, and the attenuation at the upper frequency of the second passband was -1.02 dB. The attenuation at the lower frequency of the third passband was -1.27 dB, and the attenuation at the upper frequency of the third passband was -1.05 dB. The attenuation at the lower frequency of the fourth passband was -1.25 dB, and the attenuation at the upper frequency of the fourth passband was -1.24 dB. In the model of the embodiment, the magnitude of the insertion loss (absolute value of attenuation) in each of the first to fourth passbands was sufficiently small.
[0112] In the first comparative example model, the attenuation at the upper frequency of the first passband was -0.52 dB. The attenuation at the lower frequency of the second passband was -0.87 dB, and the attenuation at the upper frequency of the second passband was -1.29 dB. Furthermore, the attenuation at the lower frequency of the third passband was -1.49 dB, and the attenuation at the upper frequency of the third passband was -1.44 dB. Also, the attenuation at the lower frequency of the fourth passband was -1.51 dB, and the attenuation at the upper frequency of the fourth passband was -2.00 dB. In the first comparative example model, the magnitude of the insertion loss in each of the first to third passbands was sufficiently small. However, in the first comparative example model, the magnitude of the insertion loss in the fourth passband was larger compared to the example model.
[0113] In the second comparative example model, the attenuation at the upper frequency of the first passband was -0.58 dB. The attenuation at the lower frequency of the second passband was -0.89 dB, and the attenuation at the upper frequency of the second passband was -1.30 dB. Furthermore, the attenuation at the lower frequency of the third passband was -1.45 dB, and the attenuation at the upper frequency of the third passband was -1.35 dB. Also, the attenuation at the lower frequency of the fourth passband was -0.92 dB, and the attenuation at the upper frequency of the fourth passband was -1.04 dB. In the second comparative example model, the magnitude of the insertion loss in each of the first, third, and fourth passbands was sufficiently small. However, in the second comparative example model, the magnitude of the insertion loss in the second passband was larger compared to the example model.
[0114] As can be seen from the simulation results, according to this embodiment, insertion loss can be reduced in all of the first to fourth passbands.
[0115] In the first comparative example, the demultiplexer 201, second, fourth, and sixth filters 222, 232, and 242 are provided between the input port 210 and the fourth output port 214. Similarly, in the second comparative example, the demultiplexer 301, first, third, and sixth filters 321, 331, and 342 are provided between the input port 310 and the second output port 312. Generally, as the number of filters increases, the number of elements also increases, resulting in a greater insertion loss.
[0116] In contrast, in this embodiment, the number of filters provided in each of the first to fourth paths P1 to P4 is two. In other words, in this embodiment, the number of elements provided in a particular path is kept low by preventing the number of filters provided in that particular path from becoming excessive.
[0117] Next, other features of the demultiplexer 1 according to this embodiment will be described. First, the first feature will be described. As shown in Figures 1 and 2, in the demultiplexer 1, a first filter group consisting of first and third filters 21 and 31 is configured between the input port 10 and the first output port 11. A second filter group consisting of first and fourth filters 21 and 32 is configured between the input port 10 and the second output port 12. A third filter group consisting of second and fifth filters 22 and 41 is configured between the input port 10 and the third output port 13. A fourth filter group consisting of second and sixth filters 22 and 42 is configured between the input port 10 and the fourth output port 14.
[0118] The first filter group has 8 stages, the second filter group has 8 stages, the third filter group has 11 stages, and the fourth filter group has 13 stages. In this embodiment, the difference between the number of stages in the fourth filter group (which has the most stages) and the number of stages in the first or second filter group (which has the fewest stages) is 5.
[0119] Next, the second feature will be described. In this embodiment, each of the first to third diplexers 20, 30, and 40 is an LC circuit including multiple inductors and multiple capacitors.
[0120] Next, the third feature will be described. In Figure 17, reference numeral 101H indicates the attenuation pole formed on the high-frequency side of the first passband 81 and closest to the first passband 81. Reference numeral 102L indicates the attenuation pole formed on the low-frequency side of the second passband 82 and closest to the second passband 82. Reference numeral 102H indicates the attenuation pole formed on the high-frequency side of the second passband 82 and closest to the second passband 82. Reference numeral 103L indicates the attenuation pole formed on the low-frequency side of the third passband 83 and closest to the third passband 83. Reference numeral 103H indicates the attenuation pole formed on the high-frequency side of the third passband 83 and closest to the third passband 83. Reference numeral 104L indicates the attenuation pole formed on the low-frequency side of the fourth passband 84 and closest to the fourth passband 84. Reference numeral 104H indicates an attenuation pole formed on the high-frequency side of the fourth passband 84 and closest to the fourth passband 84.
[0121] Furthermore, in Figure 17, the arrow denoted by reference numeral 91 schematically represents the first bandwidth, which includes the first passband 81 and has an upper limit of the attenuation pole 101H. The first bandwidth 91 exists in the pass-through attenuation characteristic between the input port 10 and the first output port 11.
[0122] The arrow denoted by the symbol 92 schematically indicates a second frequency band that includes the second passband 82 and has an attenuation pole 102L as its lower limit and an attenuation pole 102H as its upper limit. The second frequency band 92 exists in the pass-through attenuation characteristic between the input port 10 and the second output port 12.
[0123] The arrow denoted by the symbol 93 schematically represents a third frequency band that includes the third passband 83 and has an attenuation pole 103L as its lower limit and an attenuation pole 103H as its upper limit. The third frequency band 93 exists in the pass-through attenuation characteristics between the input port 10 and the third output port 13.
[0124] The arrow marked with the symbol 94 includes the fourth passband 84, with the attenuation pole 104L as the lower limit and the attenuation pole 104H as the upper limit. doThe fourth frequency band is schematically shown. The fourth frequency band 94 exists in the pass-through attenuation characteristic between the input port 10 and the fourth output port 14.
[0125] The second bandwidth 92 overlaps with the first and third bandwidths 91 and 93. That is, the second bandwidth 92 includes frequency bands present in both the first bandwidth 91 and the third bandwidth 93. This characteristic indicates that the second passband 82 is close in frequency band to both the first passband 81 and the third passband 83.
[0126] The third band 93 overlaps with the second and fourth bands 92 and 94. That is, the third band 93 includes frequency bands that are also present in the second band 92 and the fourth band 94. This characteristic indicates that the third passband 83 is close in frequency band to both the second passband 82 and the third passband 83.
[0127] The third characteristic is that the demultiplexer 1 is configured to separate signals in relatively close frequency bands.
[0128] It should be noted that the present invention is not limited to the above embodiments, and various modifications are possible. For example, the circuit configurations of the first to third diplexers 20, 30, and 40 are arbitrary, as long as the requirements of the claims are met.
[0129] As explained above, the demultiplexer of the present invention is Input port, The first output port, The second output port, The third output port, The fourth output port, A first diplexer having a first input terminal connected to an input port, a first output terminal, and a second output terminal, A second diplexer having a second input terminal connected to a first output terminal, a third output terminal directly connected to a first output port, and a fourth output terminal directly connected to a second output port, A third diplexer having a third input terminal connected to a second output terminal, a fifth output terminal directly connected to a third output port, and a sixth output terminal directly connected to a fourth output port, It is equipped with.
[0130] In the demultiplexer of the present invention, the first output port may be a port through which signals with frequencies within a first passband selectively pass. The second output port may be a port through which signals with frequencies within a second passband higher than the first passband selectively pass. The third output port may be a port through which signals with frequencies within a third passband selectively pass. The fourth output port may be a port through which signals with frequencies within a fourth passband higher than the third passband selectively pass. The first diplexer may be configured such that signals in a frequency band including the second passband but not the third passband selectively pass through the first output terminal, and signals in a frequency band including the third passband but not the second passband selectively pass through the second output terminal. The third passband may be a frequency band higher than the second passband.
[0131] Furthermore, in the demultiplexer of the present invention, the second diplexer may be configured such that signals with frequencies within the first passband selectively pass through the third output terminal, and signals with frequencies within the second passband higher than the first passband selectively pass through the fourth output terminal. The third diplexer may be configured such that signals with frequencies within the third passband selectively pass through the fifth output terminal, and signals with frequencies within the fourth passband higher than the third passband selectively pass through the sixth output terminal. The first diplexer may be configured such that signals in a frequency band including the second passband but not the third passband selectively pass through the first output terminal, and signals in a frequency band including the third passband but not the second passband selectively pass through the second output terminal. The third passband may be a frequency band higher than the second passband.
[0132] Furthermore, in the demultiplexer of the present invention, the first output port may be a port through which signals with frequencies within a first passband selectively pass through, the second output port may be a port through which signals with frequencies within a second passband higher than the first passband selectively pass through, the third output port may be a port through which signals with frequencies within a third passband higher than the second passband selectively pass through, and the fourth output port may be a port through which signals with frequencies within a fourth passband higher than the third passband selectively pass through. In this case, the pass-through attenuation characteristics between the input port and the first output port may include a first band that includes the first passband and is formed on the high-frequency side of the first passband, with the first attenuation pole closest to the first passband as its upper limit. The pass-through attenuation characteristics between the input port and the second output port may include a second frequency band that includes the second passband and is formed on the low-frequency side of the second passband, with the second attenuation pole closest to the second passband as its lower limit and the third attenuation pole closest to the second passband as its upper limit. The pass-through attenuation characteristics between the input port and the third output port may include a third frequency band that includes the third passband and is formed on the low-frequency side of the third passband, with the fourth attenuation pole closest to the third passband as its lower limit and the fifth attenuation pole closest to the third passband as its upper limit. The pass-through attenuation characteristics between the input port and the fourth output port may include a fourth frequency band that includes the fourth passband and is formed on the low-frequency side of the fourth passband, with the sixth attenuation pole closest to the fourth passband as its lower limit. The second band may include frequency bands that are also present in the first band and frequency bands that are also present in the third band. The third band may include frequency bands that are also present in the second band and frequency bands that are also present in the fourth band.
[0133] Furthermore, in the demultiplexer of the present invention, a first filter may be configured between the input port and the first output port, a second filter may be configured between the input port and the second output port, a third filter may be configured between the input port and the third output port, and a fourth filter may be configured between the input port and the fourth output port. In this case, when the filter with the most stages among the first, second, third, and fourth filters is designated as the first specific filter, and the filter with the fewest stages is designated as the second specific filter, the difference between the number of stages of the first specific filter and the number of stages of the second specific filter may be 5.
[0134] Furthermore, in the demultiplexer of the present invention, each of the first diplexer, the second diplexer, and the third diplexer may be an LC circuit including a plurality of inductors and a plurality of capacitors. [Explanation of Symbols]
[0135] 1...Splitter, 10...Input port, 11...First output port, 12...Second output port, 13...Third output port, 14...Fourth output port, 20...First diplexer, 21...First filter, 22...Second filter, 30...Third diplexer, 31...Third filter, 32...Fourth filter, 40...Third diplexer, 41...Fifth filter, 42...Sixth filter, 50...Laminate, 111...Input terminal, 112,114,118,119...Ground terminal, 113,115,116,117...Output terminals.
Claims
1. Input port, The first output port and The second output port, The third output port, The fourth output port, A first diplexer having a first input terminal connected to the input port, a first output terminal, and a second output terminal, A second diplexer having a second input terminal connected to the first output terminal, a third output terminal directly connected to the first output port, and a fourth output terminal directly connected to the second output port, A third diplexer having a third input terminal connected to the second output terminal, a fifth output terminal directly connected to the third output port, and a sixth output terminal directly connected to the fourth output port, A laminate comprising a plurality of stacked dielectric layers and a plurality of conductors, for integrating the input port, the first output port, the second output port, the third output port, the fourth output port, the first diplexer, the second diplexer and the third diplexer, Equipped with, The first diplexer includes a first filter provided between the first input terminal and the first output terminal in the circuit configuration, and a second filter provided between the first input terminal and the second output terminal in the circuit configuration. The second diplexer includes a third filter provided between the second input terminal and the third output terminal in the circuit configuration, and a fourth filter provided between the second input terminal and the fourth output terminal in the circuit configuration. The third diplexer includes a fifth filter provided between the third input terminal and the fifth output terminal in the circuit configuration, and a sixth filter provided between the third input terminal and the sixth output terminal in the circuit configuration. A demultiplexer characterized in that, among the first to sixth filters, two filters connected in series in the circuit configuration in each of the four paths connecting the input port and each of the first to fourth output ports are arranged within the laminate so that at least a portion of them are in close proximity without being connected by other filters.
2. The first output port is a port through which signals with frequencies within the first passband selectively pass. The second output port is a port through which signals with frequencies within a second passband higher than the first passband selectively pass through. The third output port is a port through which signals with frequencies within the third passband are selectively passed. The fourth output port is a port through which signals with frequencies within a fourth passband higher than the third passband selectively pass through. The demultiplexer according to claim 1, characterized in that the first diplexer is configured such that signals in a frequency band including the second passband but not the third passband selectively pass through the first output terminal, and signals in a frequency band including the third passband but not the second passband selectively pass through the second output terminal.
3. The demultiplexer according to claim 2, characterized in that the third passband has a higher frequency band than the second passband.
4. The second diplexer is configured such that signals with frequencies within the first passband selectively pass through the third output terminal, and signals with frequencies within the second passband higher than the first passband selectively pass through the fourth output terminal. The third diplexer is configured such that signals with frequencies within the third passband selectively pass through the fifth output terminal, and signals with frequencies within the fourth passband higher than the third passband selectively pass through the sixth output terminal. The demultiplexer according to claim 1, characterized in that the first diplexer is configured such that signals in a frequency band including the second passband but not the third passband selectively pass through the first output terminal, and signals in a frequency band including the third passband but not the second passband selectively pass through the second output terminal.
5. The demultiplexer according to claim 4, characterized in that the third passband has a higher frequency band than the second passband.
6. The first output port is a port through which signals with frequencies within the first passband selectively pass. The second output port is a port through which signals with frequencies within a second passband higher than the first passband selectively pass through. The third output port is a port through which signals with frequencies within a third passband higher than the second passband selectively pass through. The fourth output port is a port through which signals with frequencies within a fourth passband higher than the third passband selectively pass through. The pass-through attenuation characteristics between the input port and the first output port include a first passband, which is formed on the high-frequency side of the first passband and has a first attenuation pole closest to the first passband as its upper limit. The pass-through attenuation characteristics between the input port and the second output port include a second frequency band that includes the second passband and has a second attenuation pole formed on the low-frequency side of the second passband and closest to the second passband as its lower limit, and a third attenuation pole formed on the high-frequency side of the second passband and closest to the second passband as its upper limit. The pass-through attenuation characteristics between the input port and the third output port include a third frequency band that includes the third passband and has a fourth attenuation pole formed on the low-frequency side of the third passband and closest to the third passband as its lower limit, and a fifth attenuation pole formed on the high-frequency side of the third passband and closest to the third passband as its upper limit. The demultiplexer according to claim 1, characterized in that the pass-through attenuation characteristics between the input port and the fourth output port include a fourth band which includes the fourth passband and is formed on the low-frequency side of the fourth passband, with the sixth attenuation pole closest to the fourth passband as its lower limit.
7. The second band includes a frequency band that is also present in the first band and a frequency band that is also present in the third band. The demultiplexer according to claim 6, characterized in that the third band includes a frequency band that is also present in the second band and a frequency band that is also present in the fourth band.
8. The demultiplexer according to any one of claims 1 to 7, characterized in that each of the first diplexer, the second diplexer, and the third diplexer is an LC circuit including a plurality of inductors and a plurality of capacitors.