Die-to-die connectivity monitoring

Abstract

An input / output (I / O) sensor for a multi-IC module, the I / O sensor comprising: a delay circuit configured to receive a data signal from an interconnected portion of ICs of the multi-IC module and to generate a delayed data signal, the delay circuit comprising an adjustable delay line configured to delay the input signal by a set duration; a comparison circuit configured to generate a comparison signal by comparing the data signal with the delayed data signal; and processing logic configured to set the duration of the adjustable delay line and to identify a margin measurement of the data signal based on the comparison signal to determine an interconnect quality parameter.

Description

Technical Field

[0001] Cross-Reference to Related Applications This application claims the benefit of priority of U.S. Provisional Patent Application No. 63 / 012,457, titled "Die-to-Die (Tile) Connectivity Degradation Monitoring Based On Eye Measurement", filed on April 20, 2020, the content of which is incorporated herein by reference.

[0002] The present invention relates to the field of integrated circuits.

Background Art

[0003] Integrated circuits (ICs) typically include analog and digital electronic circuits on a flat semiconductor substrate such as a silicon wafer. Photolithography technology is used to print tiny transistors on the substrate, creating complex circuits of billions of transistors in a very small area, enabling the realization of state-of-the-art electronic circuit designs using ICs at both low cost and high performance. ICs are produced on an assembly line in a factory called a foundry, where the production of ICs such as complementary metal oxide semiconductor (CMOS) ICs is shared.

[0004] <00​​​​​

[0006] Some modern ICs are actually modules composed of multiple interconnected ICs (sometimes referred to as "chips" or "chiplets") configured to work together. A typical example is a memory IC interconnected with logic ICs, but many other types exist. There are also many die-to-die (i.e., IC-to-IC) connectivity technologies. One example is wafer-level integration, featuring high-density connectivity based on redistribution layers (RDLs) and integrated fan-out vias (TIVs), such as those sold by Taiwan Semiconductor Manufacturing Company (TSMC), Limited. Another example is system-level integration, featuring individual chips coupled via microbumps on a silicon interposer, such as Chip on Wafer on Substrate (CoWoS) technology sold by TSMC Limited and Embedded Interconnect Bridge (EMIB) technology sold by Intel Corporation. Both enable high-bandwidth memory (HBM) subsystems. A third example is through-silicon via (TSV) based three-dimensional (3D) chip stacking technology, such as the Chip on Wafer (CoW) and Wafer on Wafer (WoW) technologies sold by TSMC Limited, for example.

[0007] The aforementioned examples of the related technology and their associated limitations are illustrative and not exclusive. Other limitations of the related technology will become apparent to those skilled in the art by reading this specification and examining the figures. [Overview of the Initiative]

[0008] The following embodiments and aspects thereof are described and illustrated in conjunction with systems, tools, and methods that are intended to be illustrative and illustrative, without limiting their scope.

[0009] In one embodiment, an input / output (I / O) sensor for a multi-IC (integrated circuit) module is provided. The I / O sensor comprises a delay circuit configured to receive data signals from interconnected portions of ICs in the multi-IC module and generate a delayed data signal, the delay circuit having an adjustable delay line configured to delay an input signal for a set duration; a comparison circuit configured to generate a comparison signal by comparing a data signal with the delayed data signal; and processing logic configured to set the duration of the adjustable delay line and to identify a margin measurement of the data signal in order to determine interconnection quality parameters based on the comparison signal.

[0010] In this embodiment, the processing logic is configured to set an adjustable delay line for each of a plurality of durations, to determine whether the comparison signal for each duration indicates a pass or fail state, and to identify the minimum duration from the plurality of durations in which the comparison signal indicates a fail state.

[0011] In the embodiment, the processing logic is configured to repeatedly set an adjustable delay line for each of a plurality of durations and identify a minimum duration for each of a plurality of measurement cycles, and the processing logic is further configured to determine one or more of the lowest minimum duration over the plurality of measurement cycles, the highest minimum duration over the plurality of measurement cycles, and the sum of the minimum durations over the plurality of measurement cycles.

[0012] In the embodiment, the interconnection quality parameters include one or more of the following: eye pattern parameters, microbump resistance parameters, systematic effect parameters, and parameters indicating the symmetry of the differential signal.

[0013] In the embodiment, the margin measurement includes one or more of the following: data signal setup time up to the clock rising edge, data signal setup time up to the clock falling edge, data signal hold time up to the clock rising edge, and data signal hold time up to the clock falling edge.

[0014] In the embodiment, the comparator circuit comprises an XOR gate. In the embodiment, the adjustable delay line has a resolution of at least 1 ps with respect to duration and / or at least 16 configurations.

[0015] In one embodiment, a data signal is provided to an adjustable delay line as an input signal, and the data signal and the delayed data signal are sampled according to a clock signal. In another embodiment, a data signal is sampled according to a clock signal, the clock signal is provided to an adjustable delay line as an input signal to provide a delayed clock signal, and the delayed data signal is a data signal sampled according to the delayed clock signal.

[0016] In this embodiment, the delay circuit further comprises: a first state element configured to receive a first state element input signal and to provide a first state element output based on the first state element input signal and a first clock input; a second state element configured to receive a second state element input signal and to provide a second state element output based on the second state element input signal and a second clock input; and a multiplexing configuration configured to selectively (i) apply a data signal as an input signal to an adjustable delay line, the output of which is provided as the first state element input signal, the data signal as the second state element input signal, and the clock signal as the first and second clock inputs; or (ii) apply a clock signal as an input signal to an adjustable delay line, the output of which is provided as the first clock input, the data signal as the first and second state element input signals, and the clock signal as the second clock input.

[0017] In the embodiment, the multiplexing arrangement is further configured to selectively apply either (a) a positive clock signal or (b) a negative clock signal which is an inverted positive clock signal as the clock signal.

[0018] According to one embodiment, an input / output (I / O) block is provided, comprising a plurality of I / O sensors, wherein each I / O sensor is configured to receive different data signals from interconnected portions of ICs in a multi-IC module, as disclosed herein.

[0019] In this embodiment, the processing logic for each of the multiple I / O sensors is located in a control block that is common to all I / O sensors.

[0020] In this embodiment, each I / O sensor is configured to receive data signals from different pins of the interconnected portion of the ICs in the multi-IC module and to identify margin measurements for each pin in parallel with other modules.

[0021] According to one embodiment, an input / output (I / O) block for a multi-IC module is provided, the I / O block comprising a receive buffer configured to receive voltage signals from interconnected portions of semiconductor ICs and provide a receive buffer output, and an I / O sensor disclosed herein, the receive buffer output being provided to a delay circuit as a data signal input.

[0022] In the embodiment, the I / O sensor is further configured to receive a clock signal input, and a clock signal associated with a received voltage signal is provided as the clock signal input.

[0023] In this embodiment, the receive buffer is a first receive buffer configured to receive a first voltage signal from a first interconnected portion of a semiconductor IC and to provide a first receive buffer output, the I / O sensor is further configured to receive a clock signal input, and the I / O block is further configured to receive a second voltage signal from a second interconnected portion of a semiconductor IC and to provide a second receive buffer output, the second receive buffer output having a delay applied is provided as a clock signal input.

[0024] In this embodiment, the I / O sensor is a first I / O sensor, the clock signal input is a first clock signal input, the I / O block further comprises a second I / O sensor disclosed herein, the second receive buffer output is provided to a delay circuit as a data signal input, the second I / O sensor is further configured to receive a second clock signal input, and the first receive buffer output, to which a delay has been applied, is provided as a second clock signal input.

[0025] In the embodiment, the I / O block further comprises a multiplexed configuration configured to (a) apply a first receive buffer output to the I / O sensor as a data signal input and a second receive buffer output with a delay applied to it as a clock signal input to the I / O sensor, or a data signal is provided as a second state element input signal and a clock signal is provided as first and second clock inputs, or (b) apply a second receive buffer output to the I / O sensor as a data signal input and a first receive buffer output with a delay applied to it as a clock signal input to the I / O sensor.

[0026] In this embodiment, the first and second interconnected portions of the IC form a differential channel.

[0027] In an embodiment, the I / O block is located on an IC of a multi-IC module and is configured to interface with an external processor to store identified margin measurement values and / or to determine interconnect quality parameters.

[0028] According to an embodiment, an input / output (I / O) monitoring system including a plurality of I / O blocks is provided, each I / O block being as disclosed herein, and all of the plurality of I / O blocks being controlled by a common I / O controller.

[0029] According to an embodiment, an IC of a multi-IC module including an input / output (I / O) block as described herein or an input / output (I / O) monitoring system as described herein is provided.

[0030] In some embodiments, a computer-readable medium having stored thereon instructions for performing any of the method embodiments disclosed herein when the instructions are executed by a processor may be contemplated.

[0031] In addition to the above exemplary aspects and embodiments, further aspects and embodiments will become apparent by reference to the drawings and by consideration of the following detailed description. Those skilled in the art will understand that specific feature combinations and sub-combinations disclosed herein may be provided even if not explicitly described.

Brief Description of the Drawings

[0032] Exemplary embodiments are shown in the reference drawings. The dimensions of the components and features shown in the drawings are generally selected for the sake of presentation convenience and clarity and are not necessarily shown to scale. The drawings are listed below.

[0033] [Figure 1] A schematic block diagram of an inter-die connectivity monitoring system according to the present disclosure is shown. [Figure 2]This shows a schematic block diagram of the input / output (I / O) blocks for use in a die connectivity monitoring system. [Figure 3] A schematic circuit diagram of an I / O sensor, which forms part of the I / O block, is shown. [Figure 4] A waveform timing diagram for monitoring margin parameters regarding setup time is shown in this disclosure. [Figure 5] This disclosure shows a waveform timing diagram for monitoring margin parameters with respect to the hold time. [Figure 6] The waveform timing diagram shows the operation of the die connectivity monitoring system over the measurement cycle. [Figure 7] Figure 3 shows the waveform timing diagrams for the activation and reset of the I / O sensor. [Figure 8] A schematic block diagram of the I / O block controller, which forms part of the I / O block, is shown. [Figure 9] Figure 8 shows a schematic circuit diagram of a portion of the I / O block controller configured for automatic test pattern generation (ATPG) mode and sensor reset. [Figure 10] A schematic circuit diagram of an implementation of the I / O sensor according to this disclosure for monitoring the degradation of bidirectional or receive-only interconnect signal channels is shown. [Figure 11] A schematic circuit diagram of an I / O sensor implementation for monitoring the degradation of a transmit-only signal interconnection channel is shown. [Figure 12] This shows the waveform timing for three scenarios in degradation monitoring of transmit-only signal interconnect channels. [Figure 13] A schematic circuit diagram of an I / O sensor implementation for monitoring the degradation of differential interconnect receiving channels is shown. [Figure 14] A schematic circuit diagram of an I / O sensor implementation for monitoring the degradation of differential interconnect transmit channels is shown. [Modes for carrying out the invention]

[0034] Disclosed herein are devices, systems, and methods for measuring and / or estimating the integrity and / or degradation of input / output (I / O) margins and / or eye pattern parameters and / or multi-IC modules (sometimes referred to as "multi-chip modules") and / or optimizing the power and / or performance of such multi-IC modules.

[0035] As used herein, the term “multi-IC module” may describe a group of interconnected ICs that are integrated and packaged together and configured to cooperate through this interconnection to achieve a specific coupling function. The ICs in the module may communicate with each other, for example, via an interconnection bus. Their physical integration may be horizontal, vertical, or both.

[0036] The multi-IC modules to which this disclosure relates may consist of known or later introduced integration techniques that provide either direct connections between ICs or indirect connections via media such as specific interposers, substrates, or circuit boards. Multi-IC modules may also utilize both direct and indirect connections between various integrated IC pairs. Examples of multi-IC module integration techniques today include Chip on Wafer on Substrate (CoWoS), Wafer on Wafer (WoW), Chip On Wafer (CoW), and 3D ICs. However, embodiments of the present invention are certainly also beneficial to other types of multi-IC modules characterized by die-to-die (inter-IC) connectivity.

[0037] The disclosed devices, systems, and methods include die-to-die connectivity monitoring, particularly for determining the connectivity quality of high-speed die-to-die interconnects. Such interconnects may implement wide buses and / or low power (picojoules / bit). Quality issues may result in open circuits, short circuits, bridge short circuits (between signals), degradation of microbump resistors on the receiver side, and / or degradation of microbump resistors on the transmitter side. In such cases, a change in signal timing at the receiver is expected, and this change is detected by the monitoring system. The timing and power effects of this monitoring are minimal.

[0038] HBM3 (High Bandwidth Memory 3) is a type of die connectivity that implements various types of lanes (bidirectional lanes, receive-only lanes, transmit-only lanes, and differential lanes). As discussed herein, each of these lane types can be monitored in different ways.

[0039] The margin does not need to be measured by examining the timing difference between signals, but instead is measured by comparing the received data signal with a data signal delayed using an adjustable delay line set to provide a predetermined time delay. If the comparison result is a pass, the margin is greater than the delay applied to the data signal. The minimum delay applied to the data signal at which the comparison fails can be considered the margin. Using an adjustable delay line in this way allows for high resolution in margin measurements. Existing direct time measurements have relatively poor resolution, e.g., about 1 buffer delay, which, depending on the technique, can be in the range of 10 picoseconds (ps). In contrast, a resolution of about 2 ps (fraction of buffer delay) can be achieved using the technique of this disclosure.

[0040] The primary application is eye measurement for characterization, specifically measuring the margin or performance against fail per pin or lane. Input / output (I / O) sensors are located for each receiver in each lane. The delay of the adjustable delay line is gradually shifted (adjusted little by little) until a fail is detected. The I / O sensor can be configured for four modes to fully characterize the eye opening at the receiver side. To monitor degradation, the position of the adjustable delay line can be stored and compared with ongoing lifetime measurements. In eye width characterization, the position of the delay line can be used to measure the setup time against fail.

[0041] Generally, an I / O sensor can be considered as an I / O sensor for a semiconductor IC. The I / O sensor comprises a delay circuit configured to receive a data signal from an interconnected portion of a semiconductor IC (e.g., a pin or lane of one IC in a multi-IC module) and generate a delayed data signal. The delay circuit includes an adjustable delay line configured to delay the input signal for a set duration (however, as considered below, the delayed data signal does not necessarily have to be the output of the adjustable delay line). The I / O sensor further comprises a comparator circuit configured to generate a comparison signal by comparing the data signal with the delayed data signal. Furthermore, processing logic is provided, configured to set the duration of the adjustable delay line and, based on the comparison signal, identify a margin measurement of the data signal to determine interconnection quality parameters. According to this general sense, methods for manufacturing and / or operating an I / O sensor, including the corresponding steps of providing and / or configuring the I / O sensor, can also be provided as appropriate.

[0042] The processing logic may be configured to set an adjustable delay line for each of several durations, and for each set duration, to determine whether the comparison signal for that duration indicates a pass or a fail state. The processing logic may then be configured to identify the minimum of the multiple durations for which the comparison signal indicates a fail state. This minimum may correspond to a margin measurement.

[0043] Margin measurements may include one or more of the following: data signal setup time to the rising edge of the clock, data signal setup time to the falling edge of the clock, data signal hold time to the rising edge of the clock, and data signal hold time to the falling edge of the clock. Multiple margin measurements may be determined for the same interconnect (pin or lane), each of which may be for a different margin than those listed herein.

[0044] Interconnection quality parameters may include, for example, one or more of the following: eye pattern parameters, microbump resistance parameters, systematic effect parameters, and parameters indicating differential signal symmetry. These may be determined from margin measurements, along with other factors as an option.

[0045] Here, we will consider other specific characteristics. The generalized meaning will be further considered below.

[0046] Referring to Figure 1, this shows a schematic block diagram of a die-to-die connectivity monitoring system, although this is not specifically limited to 3D ICs. The same system can be used to monitor all types of die-to-die connectivity, not just 3D ICs. In 2.5D packaging, interconnects (lanes) connect adjacent chips, for example, a DRAM controller located in a System on Chip (SoC) to DRAM located in stacked DRAM (HBM3). In 3D packaging, interconnects (lanes) connect stacked chips, for example, a DRAM controller (first chip) located at the bottom of a stack to stacked SRAM dies. In other package types, connectivity can be described as a transmitter driving a line with a receiver at the end, and die-to-die connectivity monitoring systems can still be used. However, the system has an advantage for 3D ICs in that there are space limitations and the system can accommodate multiple receivers using a single I / O sensor.

[0047] The die-to-die connectivity monitoring system detects reliability issues on a pin-by-pin basis in mission mode and enables margin characteristic evaluation performance in four measurement modes per pin. Quality monitoring is based on (ongoing) tracking of the timing of the received signal (Rx signal) at the receiver. Monitoring is performed lane by lane with minimal timing and power penalty. Possible quality issues may relate to open pins, shorted pins, bridge shorts (between signals), degradation of microbump resistors on the receiver side, and / or degradation of microbump resistors on the transmitter side.

[0048] The die connectivity monitoring system supports [k] I / O blocks, each block supporting [n] I / O lanes. I / O lanes can be bidirectional (providing both transmission and reception), receive-only, transmit-only, and / or differential lanes. The measurement process for each block is managed by a dedicated controller (Prtn_tca_block_controller) located within the block. The block controller controls [n] I / O sensors (one per lane or pin).

[0049] Configuration data and control signals are passed from the block controller to the I / O sensors, and fail indicator data is passed from each I / O sensor to its respective block controller. During the measurement cycle, all [n] I / O sensors are activated in parallel, and the margin to fail for each [n] pin is measured. At the end of the measurement cycle, the controller holds the margin to fail for each pin, which in one embodiment is represented by a 6-bit digital readout.

[0050] All block controllers are controlled by a central full-chip (FC) controller (prtn_tca_top_ctrl). The FC controller generates a low-frequency clock (Prtn_clk) used to start the finite state machines (FSMs) within the block controllers. The low-frequency clock (Prtn_clk) signal is generated from the Advanced Peripheral Bus (APB) clock. Frequency division is programmable and is related to the APB clock. The FC controller also generates a central active-low reset signal (prtn_rst_n) for all block controllers. The FC controller collects data from each block controller and transmits the data to an external source via a serial bus (e.g., using APB, JTAG, I2C).

[0051] During the characterization phase, an offline data analysis system receives margin data via an external source and uses this data to measure or calculate one or more of the following: eye width per pin, eye height per pin, the effect of the clock duty cycle on the eye width per pin, and / or the jitter amplitude of the eye height per pin, the systematic effect per group of pins, and the symmetry of the differential signal.

[0052] In mission mode, the offline data analysis system receives margin data via an external source and uses this data to calculate eye width degradation and / or microbump resistance degradation at the receiver side, and / or microbump resistance and / or differential lane microbump degradation at the transmitter side. This may include one or more of outlier detection, systematic shift detection, alerts, and lane repairs.

[0053] Data analysis from numerous such die-to-die connectivity monitoring systems, each embedded in a different IC, can be advantageously performed by an analysis system. The analysis system may be a computerized system comprising one or more hardware processors (e.g., CPUs), random-access memory (RAM), one or more non-transient computer-readable storage devices, and a network interface controller (NIC). The storage devices may store program instructions and / or components configured to operate the hardware processors. The program instructions may include one or more software modules, such as data analysis modules, which analyze margin data received from ICs operating in the field.

[0054] In some embodiments, the software components may include an operating system having various software components and / or drivers for controlling and managing common system tasks (e.g., memory management, storage device control, power management, network communication, etc.) and facilitating communication between various hardware and software components.

[0055] The analysis system may operate by loading instructions for a data analysis module, executed by a processor, into RAM. These instructions allow the analysis system to receive and process margin data collected from multiple ICs via its network interface controller (e.g., via the Internet), and output statistical analysis of the data. The statistical analysis may indicate, for example, eye pattern parameters (including eye width), degradation rates, and lanes and / or pins that degrade or degrade faster. Based on the analysis performed by the system, one or more of the ICs may be reconfigured to adjust one or more of the following: data throughput, clock rate, and processing time. In this regard, the system may send messages to each IC being reconfigured via the system's NIC, a communication network (such as the Internet), and the communication interfaces of these ICs. These messages may include instructions on how to set or change internal IC parameters that affect data flow or clock speed. Instructions may be individual for each IC, for each of its specific margin data. Alternatively, the same instructions may be sent to multiple ICs classified as closely related to the statistical analysis.

[0056] The analysis systems described herein are merely exemplary embodiments of the present invention and may in practice be implemented as hardware only, software only, or a combination of both hardware and software. The analysis systems may have more or fewer components and modules than shown, or may be combinations of two or more components, or may have different configurations or arrangements of components. The analysis systems may include any additional components that enable them to function as an operable computer system, such as a motherboard, data bus, power supply, display, and input devices (e.g., keyboard, pointing device, touch-sensitive display). Furthermore, as is known in the art, the components of the analysis system may be located in the same location or distributed, or the analysis system may run as one or more cloud computing "instances," "containers," and / or "virtual machines."

[0057] Referring to Figure 2, a schematic block diagram of the I / O block is shown. This describes the connectivity of the block controller to the I / O sensors (the pin names of the I / O sensors are the same as the signal names). The signals will be discussed in more detail below.

[0058] The block controller (Prtn_tca_block_controller) is clocked by a phase-locked loop (PLL) divided clock (in one embodiment, a 10 GHz PLL clock and a division of 10 equals 1 GHz) and by a low-frequency clock (Prtn_clk) generated by the FC controller. The PLL clock is provided by the PLL block. Therefore, the divided clock is a derivative of the main clock used for data transmission. The two clocks are distinct.

[0059] The divided PLL clock is used for the Sensor-fail indicator signal and synchronization of the internal FSM. A low-frequency clock (Prtn_clk) is used for interfacing with the FC controller, acquiring commands, and reading measurements. As discussed below, each I / O sensor is clocked by the PLL clock (10 GHz as discussed above). The margin for fail data is related to the rising edge of this clock.

[0060] Referring to Figure 3, a schematic circuit diagram of the I / O sensor, which forms part of the I / O block, is shown. As discussed above, the primary input to the I / O sensor is the clock signal, which is the undivided clock provided by the PLL block. In practice, the clock signal can be provided in two forms: a positive clock signal (clkp) and a negative clock signal, which is the inverted form of the positive clock signal (clkn). Another input is the data signal (d_in) from the pin or lane being measured. The configuration signal (ptrn_io_sensor_cfg) is also provided as an input to the I / O sensor. The startup signal (ptrn_io_sensor_en) is a further input to the I / O sensor.

[0061] The main components of the I / O sensor are an adjustable delay line 10 and an XOR comparison logic gate that provides an output comparison signal (X0). The adjustable delay line provides an output signal (x_in_d), which is a version of the input delayed by a set configurable duration. Several state elements or sampling elements or flip-flops (FFs) are also provided, and the first state element (FF1) and the second state element (FF2) are the most relevant, as the outputs of these two states are the two inputs to the XOR comparison logic gate. The I / O sensor also includes a signal multiplexing arrangement 20 that constitutes the inputs to the adjustable delay line, the first state element (FF1), and the second state element (FF2). Each state element has two inputs: its respective data signal i4nput and its respective clock signal input. When the outputs of the first and second state elements are the same, the output comparison signal (X0) becomes a logic low value, indicating a pass result where the margin is less than the set delay duration. If the outputs of the first and second state elements are different, the output comparison signal (X0) becomes logically high, indicating a fail result where the margin is less than or equal to the set delay duration.

[0062] The input signals are processed to define further signals. The data signal (d_in) and the activation signal (ptrn_io_sensor_en) are provided as input to the first AND gate to define the processed data signal (d_in_i). The positive clock signal (clkp) and the activation signal (ptrn_io_sensor_en) are provided as input to the second AND gate to define the processed positive clock signal (clk_p_i). The negative clock signal (clkn) and the activation signal (ptrn_io_sensor_en) are provided as input to the third AND gate to define the processed negative clock signal (clk_n_i).

[0063] The signal multiplexing arrangement 20 comprises a first multiplexer (Mux1), a second multiplexer (Mux2), a third multiplexer (Mux3), a fourth multiplexer (Mux4), a fifth multiplexer (Mux5), a sixth multiplexer (Mux6), and a seventh multiplexer (Mux7). Naturally, the use of seven multiplexers is merely an illustrative example, and any number of multiplexers may be used as required by the specific implementation, while adhering to the principles described herein. The first multiplexer (Mux1) is controlled by a first 3-bit multiplexer control signal (S1) and provides a first multiplexer output by selecting between the inputs of a processed data signal (d_in_i), a processed positive clock signal (clk_p_i), and a processed negative clock signal (clk_n_i). The first multiplexer output is the input to an adjustable delay line.

[0064] A second multiplexer (Mux2) is controlled by a second 3-bit multiplexer control signal (S2) and provides a second multiplexer output by selecting between the inputs of a constant logic low signal (1'b0), a processed positive clock signal (clk_p_i), and a processed negative clock signal (clk_n_i). A third multiplexer (Mux3) is controlled by a third 3-bit multiplexer control signal (S3) and provides a third multiplexer output by selecting between the inputs of a processed data signal (d_in_i), a constant logic low signal (1'b0), and a constant logic low signal (1'b0).

[0065] The fourth multiplexer (Mux4), the fifth multiplexer (Mux5), the sixth multiplexer (Mux6), and the seventh multiplexer (Mux7) are all controlled by a 1-bit common control signal (C0). For each of these multiplexers, the listed first input is provided as an output when the common control signal is at a high logic level, and the listed second input is provided as an output when the common control signal is at a low logic level. The fourth multiplexer (Mux4) provides a fourth multiplexer output by selecting an input between the third multiplexer output and an adjustable delay line output signal (x_in_d). The fourth multiplexer output is a data input to the first state element (FF1). The fifth multiplexer (Mux5) provides a fifth multiplexer output by selecting an input between the adjustable delay line output signal (x_in_d) and the second multiplexer output. The fifth multiplexer output is a clock input to the first state element (FF1). The sixth multiplexer (Mux6) provides a sixth multiplexer output by selecting from the inputs between the third multiplexer output and the first multiplexer output. The sixth multiplexer output is a data input to the second state element (FF2). The seventh multiplexer (Mux6) provides a seventh multiplexer output by selecting from the inputs between the first multiplexer output and the second multiplexer output. The seventh multiplexer output is a clock input to the second state element (FF2).

[0066] I / O sensors can measure the relative timing characteristics of data signals and clock signals. With appropriate configuration of the signal multiplexing arrangement, it is possible to measure the data signal setup time up to the rising edge of the clock, the data signal setup time up to the falling edge of the clock, the data signal hold time up to the rising edge of the clock, and the data signal hold time up to the falling edge of the clock. These configurations will be discussed further below.

[0067] The I / O sensor is configured by setting configuration signals (the values ​​of the configuration bits in prtn_io_sensor_cfg[10:0]). The 11 configuration bits are responsible for three types of functions. Four configuration bits (prtn_io_sensor_cfg[3:0]) configure an adjustable delay line value that is dynamically changed during margin testing; five configuration bits (prtn_io_sensor_cfg[8:4]) are configured according to the operating frequency (equal to half the data rate) and do not change during margin testing; and two configuration bits (prtn_io_sensor_cfg[10:9]) configure the measurement mode.

[0068] Table 1 below shows an example of how the five configuration bits (prtn_io_sensor_cfg[8:4]) can be configured depending on the operating frequency. [Table 1]

[0069] During the measurement cycle (described in more detail below), the block controller uses four configurations reserved for this purpose (prtn_io_sensor_cfg[3:0]) to configure the internal adjustable delay line for each I / O sensor. This allows up to 16 different delay times to be set for margin measurement. The minimum delay line value is configured by prtn_io_sensor_cfg[3:0]=

[0000] , and the maximum delay line value is configured by prtn_io_sensor_cfg[3:0]=

[11111] .

[0070] Here, we will examine four different margin measurement modes in more detail. The first mode to consider is the measurement of the data signal setup time to the clock rising edge. In this mode, a first multiplexer (Mux1) is controlled to provide the first multiplexer output as the processed data signal (d_in_i), a second multiplexer (Mux2) is controlled to provide the second multiplexer output as the processed positive clock signal (clk_p_i), and a common control signal (C0) is set to a logic low value. The third multiplexer output is irrelevant and can be set to a constant logic low signal (1'b0). As a result, the first state element is configured to sample the delayed data signal by the positive clock signal, and the second state element is configured to sample the data signal (i.e., without delay) by the positive clock signal. Thus, the XOR comparison logic gate tests whether the data signal and the delayed data signal are the same when both are sampled by the same clock rising edge.

[0071] The setup time of the data signal to the falling edge of the clock is measured as follows: In this mode, a first multiplexer (Mux1) is controlled to provide the first multiplexer output as the processed data signal (d_in_i), a second multiplexer (Mux2) is controlled to provide the second multiplexer output as the processed negative clock signal (clk_n_i), and the common control signal (C0) is set to a logic low value. The third multiplexer output is irrelevant and can be set to a constant logic low signal (1'b0). As a result, the first state element is configured to sample the delayed data signal by the negative clock signal, and the second state element is configured to sample the data signal (i.e., without delay) by the negative clock signal. Thus, the XOR comparison logic gate tests whether the data signal and the delayed data signal are the same when both are sampled by the same clock negative rising edge.

[0072] Referring to Figure 4, a waveform timing diagram is shown for monitoring the margin parameter with respect to setup time. The top waveform shows the clock signal (clk) and the UI (unit interval) which defines the minimum data width. For example, a system using dual data rate (DDR) generates data on the clock rising and falling edges so that the UI is equal to the time interval between the clock rising and falling edges. The second waveform is the data signal (d_in). From this, we can see the setup time to the clock rising edge (ΔT_S_r) and the setup time to the clock falling edge (ΔT_S_f). The delayed data signal (x_in_d), which is the output from the adjustable delay line, is also shown, indicating a range of delays depending on the delay duration set on the adjustable delay line. The output comparison signal (X0) of the specific delayed data signal (x_in_d) is also shown, which in this case indicates a logic high, indicating that the margin is at least the set delay duration. The sensor output signal (SO) corresponds to the sensor fail indicator signal (ptrn_io_sensor_fail). This is a sticky bit that remains at a logically high level after the first fail until it is reset, and will be discussed further below.

[0073] The measurement of the data signal hold time until the rising edge of the clock is performed as follows. In this mode, a first multiplexer (Mux1) is controlled to provide the first multiplexer output as a processed positive clock signal (clk_p_i), a third multiplexer (Mux3) is controlled to provide the third multiplexer output as a processed data signal (d_in_i), and the common control signal (C0) is set to a logic high. The second multiplexer output is irrelevant and can be set to a constant logic low signal (1'b0). In this case, the output of the adjustable delay line is the delayed positive clock signal. The data signal is not provided as input to the adjustable delay line. As a result, the first state element is configured to sample the data signal by the delayed positive clock signal. Therefore, the output of the first state element is a delayed data signal with a delay introduced by sampling. The second state element is configured to sample the data signal by the positive clock signal (i.e., without delay). Therefore, the XOR comparison logic gate tests whether the data signal sampled by the rising edge of the clock is the same as the data signal sampled by the delayed rising edge of the clock (i.e., the delayed data signal).

[0074] The measurement of the data signal hold time to the falling edge of the clock is performed as follows: In this mode, a first multiplexer (Mux1) is controlled to provide the first multiplexer output as a processed negative clock signal (clk_n_i), a third multiplexer (Mux3) is controlled to provide the third multiplexer output as a processed data signal (d_in_i), and the common control signal (C0) is set to a logic high. The second multiplexer output is irrelevant and can be set to a constant logic low signal (1'b0). In this case, the output of the adjustable delay line is the delayed negative clock signal. The data signal is again not provided as input to the adjustable delay line. As a result, the first state element is configured to sample the data signal by the delayed negative clock signal. Therefore, the output of the first state element is again the delayed data signal with a delay introduced by sampling. The second state element is configured to sample the data signal by the negative clock signal (i.e., without delay). Therefore, the XOR comparison logic gate tests whether the data signal sampled by a negative clock rising edge is the same as the data signal sampled by a delayed negative clock rising edge (i.e., the delayed data signal).

[0075] Referring to Figure 5, a waveform timing diagram is shown for monitoring the margin parameter with respect to the hold time. The top waveform shows the clock signal (clk), and the second waveform is the data signal (d_in). From this, the hold time (ΔT_H_f) to the falling edge of the clock and the setup time (ΔT_H_r) to the rising edge of the clock can be determined. The delayed clock signal (x_in_d), which is the output from the adjustable delay line, is also shown, indicating a range of delays depending on the delay duration set on the adjustable delay line. The output comparison signal (X0) of the specific delayed clock signal (x_in_d) is also shown, which in this case indicates a logic high, indicating that the margin is at least the set delay duration. The sensor output signal (SO) is as discussed above with reference to Figure 4, and an example of its generation is detailed below.

[0076] As discussed above, two bits of the configuration signal (prtn_io_sensor_cfg) are used to configure the I / O sensor into one of four measurement modes. The first of these bits (prtn_io_sensor_cfg[9]) is a common control signal (C0) that configures the I / O sensor to set up or hold the measurement. If the common control signal (C0, prtn_io_sensor_cfg[9]) is logical low ([0]), the I / O sensor is then configured in setup measurement mode, and if the common control signal (C0, prtn_io_sensor_cfg[9])) is logical high ([1]), the I / O sensor is then set in hold measurement mode. The second of these bits (C1, prtn_io_sensor_cfg

[10] ) determines whether to use the rising or falling edge of the clock as the reference. If this second bit (C1, prtn_io_sensor_cfg

[10] ) is logically low ([0]), the I / O sensor is then configured in clock falling-edge (negative) measurement mode, and if this second bit (C1, prtn_io_sensor_cfg)

[10] ) is logically high ([1]), the I / O sensor is then configured in clock rising-edge (positive) measurement mode.

[0077] The I / O sensor can use these two configuration bits to configure a signal multiplexing arrangement by the following logical expression in Table 2. [Table 2]

[0078] Returning to the generalized meaning discussed above, further features can be considered. For example, the comparator circuit may comprise an XOR gate. The comparator signal may then be based on the output of the XOR gate. One input to the XOR gate may be a data signal, and the other input may be a delayed data signal. The adjustable delay line may have a resolution of at least 1 ps. Additionally or alternatively, the adjustable delay line may have at least 16 configurations for a given duration.

[0079] In a specific configuration, the data signal is supplied to an adjustable delay line as an input signal, and both the data signal and the delayed data signal are sampled according to the clock signal. In other configurations, the data signal is sampled according to the clock signal, and the clock signal is supplied to an adjustable delay line as an input signal to provide a delayed clock signal. The delayed data signal may then be a data signal sampled according to the delayed clock signal.

[0080] The delay circuit may further comprise: a first state element (e.g., a flip-flop) configured to receive a first state element input signal and provide a first state element output based on the first state element input signal and a first clock input; a second state element (e.g., a flip-flop) configured to receive a second state element input signal and provide a second state element output based on the second state element input signal and a second clock input; and a multiplexing arrangement. The multiplexing arrangement is advantageously configured to selectively apply one of two configurations. In the first configuration, a data signal is applied as an input signal to an adjustable delay line, the output of the adjustable delay line is provided as a first state element input signal, a data signal is provided as a second state element input signal, and clock signals are provided as first and second clock inputs. In the second configuration, the clock signal is applied to an adjustable delay line as an input signal, the output of the adjustable delay line is provided as a first clock input, the data signals are provided as first and second state element input signals, and the clock signal is provided as a second clock input. The multiplexing arrangement may be further configured to selectively apply either (a) a positive clock signal or (b) a negative clock signal which is an inverted positive clock signal as the clock signal.

[0081] In another general sense (which may be combined with other embodiments disclosed herein), an I / O block comprising multiple I / O sensors may be considered, each I / O sensor being disclosed herein and configured to receive its own distinct data signals from an interconnected portion of a semiconductor IC. The processing logic for each of the multiple I / O sensors may reside in a common control block. Each I / O sensor may be configured to receive its own data signals from different pins of an interconnected portion of a semiconductor IC and to identify margin measurements for its respective pins in parallel with other modules.

[0082] The I / O block may be located on a semiconductor IC. The I / O block may then be configured to interface with an external processor to store identified margin measurements and / or to determine interconnect quality parameters.

[0083] In another general sense (which may be combined with other disclosures herein), an I / O monitoring system comprising multiple I / O blocks may be provided, each I / O block as disclosed herein. Each of the multiple I / O blocks may then be controlled by a common I / O controller.

[0084] Some generalized meanings may be considered to be semiconductor ICs comprising an I / O block or an I / O monitoring system as described herein. As considered above, methods for manufacturing and / or operating I / O blocks, I / O monitoring systems, and / or semiconductor ICs may also be provided, including corresponding steps of providing and / or configuring I / O sensors accordingly.

[0085] The I / O sensor also includes a test verification section comprising a third state element (FF3), a fourth state element (FF4), an OR gate (OR1), and a fifth state element (FF5). An output comparison signal (X0) is provided as the first input to the OR gate (OR1), and the output of the OR gate (OR1) is the data input to the fifth state element (FF5). The clock input to the fifth state element (FF5) is the output of the seventh multiplexer (which is a positive clock signal when rising edge measurement is being performed, and a negative clock signal when falling edge measurement is being performed, as previously noted). The output of the fifth state element (FF5) is provided as the second input to the OR gate (OR1). This output (provided via a buffer) indicates a sensor fail indicator signal (ptrn_io_sensor_fail) that is held at a logical high value as soon as the output comparison signal (X0) goes high. This corresponds to the sensor output signal (SO) discussed above.

[0086] The sensor fail indicator signal (ptrn_io_sensor_fail) is a single bit transmitted from each I / O sensor, indicating that the configuration of the adjustable delay line is greater than the pin margin, i.e., the time difference between the data rising edge and the clock rising edge. As described above, the fail indicator is generated by the I / O sensor by using a sticky mechanism; that is, once a fail indicator occurs, it remains at a logical high level until the next I / O sensor reset (as discussed below). The sensor indicator is always related to the active or current configuration mode of the I / O sensor.

[0087] The third state element (FF3) and the fourth state element (FF4) form a two-stage synchronizer used to reset the fifth state element (FF5), thereby resetting the test failure signal (ptrn_io_sensor_fail). The clock inputs to both the third state element (FF3) and the fourth state element (FF4) are the outputs of the seventh multiplexer (as discussed above). The data input to the third state element (FF3) is a constant logic low signal (1'b0), and the data input to the fourth state element (FF4) is the output of the third state element (FF3). The input of the active-low asynchronous reset signal (ptrn_io_sensor_rst_n) is also provided as a set signal input to both the third state element (FF3) and the fourth state element (FF4). The output of the fourth state element (FF4) is provided to the fifth state element (FF5) as a reset signal. Thus, the fifth state element (FF5) is used to synchronize the sensor fail indicator signal to the high-speed clock. The serial structure of the third state element (FF3) and the fourth state element (FF4) is used to avoid metastability.

[0088] The block controller (prtn_tca_block_ctrl) generates a reset signal (prtn_io_sensor_rst_n) that is distributed to all I / O sensors in the block. The reset signal is related to the PLL-divided clock domain used for the clock of the block controller (prtn_tca_block_ctrl). To do this, the block controller may use a block reset signal (prtn_rst_n) generated by the FC controller (prtn_tca_top_ctrl) and synchronized with the PLL-divided clock.

[0089] The reset signal is generated by a block controller asynchronously with the I / O sensor operating clock (a 10GHz clock in this example) and is used as an asynchronous reset in the I / O sensor. Therefore, the reset assertion of the I / O sensor is asynchronous with the 10GHz clock. The reset must be asserted before changing the configuration of the adjustable delay line. The deassertion of the I / O sensor reset is synchronized with the I / O sensor operating clock (10GHz) within the I / O sensor. Synchronization is performed using a two-stage synchronizer located within each I / O sensor. The deassertion time for the reset is equal to two 10GHz clock cycles.

[0090] The I / O sensor is activated by setting the activation signal (prtn_io_sensor_en) to a high logic level ([1]). This is done one clock cycle (PLL divided clock cycle) before the reset assertion is released. When the I / O sensor is not activated, the activation signal (prtn_io_sensor_en) is set to a logic level ([0]) one clock cycle (PLL divided clock cycle) after the reset assertion.

[0091] Generally, an input / output (I / O) block of a semiconductor three-dimensional (3D) integrated circuit (IC) may be considered. An I / O sensor comprises a delay circuit configured to receive a data signal from an interconnected portion (which may be a bidirectional interface) of a semiconductor 3D IC and generate a delayed data signal, and a comparator circuit configured to generate a comparator signal by comparing the data signal with the delayed data signal. The delay circuit includes an adjustable delay line configured to delay the input signal for a set duration. The I / O sensor further comprises processing logic configured to set the duration of the adjustable delay line and to identify a margin measurement of the data signal to determine eye pattern parameters based on the comparator signal. Some or all of the processing logic may be located in the same location as the rest of the I / O sensor, or some or all of the processing logic may be located away from the I / O sensor. Some or all of the processing logic may be shared between one or more I / O sensors. Methods for measuring I / O margins, including steps to provide and / or operate the I / O sensors described herein, may also be understood.

[0092] Input / output (I / O) blocks comprising multiple I / O sensors are also considered. In this case, each I / O sensor may be configured to receive its respective different data signals, in particular, from different interconnected parts of the semiconductor 3D IC, e.g., different lanes or pins. If each I / O sensor is configured to receive its respective data signals from different pins of the interconnected parts of the semiconductor 3D IC, each I / O sensor may be configured to identify margin measurements for its respective pins in parallel with other sensors. Some or all of the processing logic for each of the multiple I / O sensors in the I / O block is advantageously located in a common control block. The I / O sensors and / or I / O blocks may reside on a semiconductor 3D IC. The I / O sensors and / or I / O blocks may then be configured to interface with an external processor to store the identified margin measurements and / or to determine the eye pattern parameters.

[0093] In a further embodiment, an input / output (I / O) monitoring system comprising multiple I / O blocks may also be considered. Each of the multiple I / O blocks may be controlled by a common I / O controller.

[0094] Further embodiments may be found in semiconductor three-dimensional (3D) integrated circuits (ICs) comprising input / output (I / O) sensors and / or I / O blocks and / or I / O monitoring systems as described herein.

[0095] Referring again to the I / O sensor (optionally, within an I / O block, I / O monitoring system, or 3D IC), further optional preferred and / or advantageous features may be considered.

[0096] Margin measurement may include, for example, one or more of the following: data signal setup time to the rising edge of the clock, data signal setup time to the falling edge of the clock, data signal hold time to the rising edge of the clock, and data signal hold time to the falling edge of the clock.

[0097] For each of the multiple durations, the processing logic may set an adjustable delay line for that duration and determine whether the comparison signal for that duration indicates a pass or a fail. The processing logic may then identify the minimum duration from the multiple durations for which the comparison signal indicates a fail. Optionally, the processing logic may repeat setting an adjustable delay line for each of the multiple durations and identifying the minimum duration for each of the multiple measurement cycles. The processing logic may then further determine one or more of the lowest minimum duration across the multiple measurement cycles, the highest minimum duration across the multiple measurement cycles, and the sum of the minimum durations across the multiple measurement cycles.

[0098] Optionally, the adjustable delay line has a resolution of at least 1 ps (optionally 2 ps, or with respect to the operating frequency) at the maximum operating frequency and / or at least 16 (optionally 32) configurations with respect to the duration.

[0099] In the embodiment, the comparator circuit comprises an XOR gate. A first input to the XOR gate may be provided by a (preferably sampled) data signal, and a second input to the XOR gate may be provided by a delayed data signal.

[0100] In a specific operating mode, the data signal is supplied to an adjustable delay line as an input signal, and both the data signal and the delayed data signal are sampled according to the clock signal. In other operating modes, the data signal is sampled according to the clock signal, and the clock signal is supplied to an adjustable delay line as an input signal to provide a delayed clock signal. The delayed data signal may then be a data signal sampled according to the delayed clock signal.

[0101] The operating mode can be controlled by a multiplexing configuration. For example, the delay circuit may further include a first state element configured to receive a first state element input signal and to provide a first state element output based on the first state element input signal and a first clock input; a second state element configured to receive a second state element input signal and to provide a second state element output based on the second state element input signal and a second clock input; and a multiplexing configuration configured to selectively (i) apply a data signal as an input signal to an adjustable delay line, the output of the adjustable delay line being provided as the first state element input signal, the data signal being provided as the second state element input signal, and the clock signal being provided as the first and second clock inputs, or (ii) apply a clock signal as an input signal to an adjustable delay line, the output of the adjustable delay line being provided as the first clock input, the data signal being provided as the first and second state element input signals, and the clock signal being provided as the second clock input. The multiplexing configuration may be further configured to selectively apply either (a) a positive clock signal or (b) a negative clock signal which is an inverted positive clock signal, as the clock signal.

[0102] While this disclosure has been generally considered here, further specific details will be considered again below.

[0103] Referring to Figure 6, a waveform timing diagram of the operation of the die connectivity monitoring system over a measurement cycle is shown. A measurement cycle defines the activity of the block controller during a measurement time interval. Each measurement cycle includes multiple [K] delay line cycles. Each delay line cycle includes multiple (16 in one embodiment) measurements, each having a different position on the adjustable delay line. The number of measurements per delay line cycle may be between 2 and 100 in a more general sense, or more specifically between 2 and 10, 2 and 20, 2 and 30, 2 and 40, 2 and 50, 5 and 10, 5 and 20, 10 and 20, 10 and 30, 10 and 40, 10 and 50, 20 and 30, 20 and 40, 20 and 50, 30 and 40, 30 and 50, 40 and 50, or other subranges between 2 and 100. In other embodiments, the number of measurements per delay line cycle may exceed 100.

[0104] When a measurement command is sent to the block controller (prtn_tca_block_ctrl), a measurement cycle begins, and when a read cycle is executed, it stops. A new measurement command is sent to execute a new measurement cycle. When the block controller receives a read command, it first disables the I / O sensor by setting the activation signal (ptrn_io_sensor_en) to a logic low level.

[0105] During each adjustable delay line cycle, the I / O sensor adjustable delay line is configured for each of the 16 positions. In other words, the I / O sensor adjustable delay line changes from the minimum delay value to the maximum delay value. The time interval at which each position is held is defined by the "WIN" parameter. The WIN parameter can be configured to one of 8, 16, 32, and 64, and the time interval is equal to the value obtained by multiplying the WIN configuration by the PLL output time interval and dividing by the clock cycle time.

[0106] Referring to Figure 7, the waveform timing diagram for I / O sensor startup and reset according to Figure 3 is shown. The time to set a new delay line value is the sum of the time it takes for the block controller (prtn_tca_block_ctrl) to reset the fifth state element (FF5) that controls the sensor fail indicator signal (ptrn_io_sensor_fail), the time to set a new delay line value (position of the adjustable delay line), and the guard band time. This is calculated as eight cycles of the PLL-divided clock (1 GHz in this example) according to the following sequence: Set the first cycle to the asynchronous reset signal (ptrn_io_sensor_rst_n)[2]; wait two cycles and reset the sensor fail indicator signal (ptrn_io_sensor_fail)[4]. The delay line cycle length is equal to [16 x WIN] + [32 x time to set a new adjustable delay line value].

[0107] Referring to Figure 8, a schematic block diagram of the I / O block controller, which forms part of the I / O block, is shown. This includes the first logic, a memory block, and the second logic. The third logic generates the start signal (ptrn_io_sensor_en), the active-low asynchronous reset signal (ptrn_io_sensor_rst_n), and four configuration bits (prtn_io_sensor_cfg[3:0]) that constitute the adjustable delay line value.

[0108] The synchronizer receives a 1-bit sensor fail indicator signal (ptrn_io_sensor_fail) for each of several (in this case 44, [43:0]) different sensors, a PLL (1GHz) clock signal, and an active-low asynchronous reset signal (ptrn_io_sensor_rst_n), generates a synchronous sensor fail signal (sensor_fail_sync[43:0]) for each sensor, and provides this synchronous sensor fail signal (sensor_fail_sync[43:0]) to the first logic. The first logic then determines the minimum delay line position that generates a sensor fail and provides this to the memory block. The memory block needs to store the minimum delay line position that generates a sensor fail during a complete delay line cycle per pin (16 delay line positions executed by 16 WIN intervals). The second logic can then use this to read from the memory block to the FC controller.

[0109] When the block controller's third logic (prtn_tca_block_ctrl) receives a start_measure command, it first enables the I / O sensor by setting the activation signal (ptrn_io_sensor_en) to a logic high value. Then, it starts the measurement cycle.

[0110] Four data types are generated by the block controller for each I / O sensor (pin), providing a total of 33 bits (or 31 bits depending on the count_length configuration). The first type is the lower minimum delay line position that generates a sensor fail during a complete measurement cycle ([N]x delay line cycles), requiring 5 bits per I / O sensor (memory[4:0]). The second type is the higher minimum delay line position that generates a sensor fail during a complete measurement cycle ([N]x delay line cycles), requiring 5 bits per I / O sensor (memory[4:0]). The third type is a valid bit indicating that the readings for the lower minimum delay line position (first type) and the higher minimum delay line position (second type) correspond to actual fail indications. Specifically, this bit indicates that the I / O sensor output, i.e., the sensor fail indication signal (prtn_io_sensor_fail), was logically high at least once during the measurement cycle.

[0111] The fourth type is the sum of the minimum delay line positions that generate a sensor fail during each delay line cycle (one measurement cycle). This requires 14 bits (5+9) per I / O sensor if Count_length=512, and 13 bits (5+8) per I / O sensor if Count_length=256. The fifth type is the number of valid delay line cycles used in the sum of the minimum delay line values ​​(counts), which requires 9 bits (up to 512 counts) per I / O sensor. The fourth and fifth types are optional and depend on the readout mode (Readout_mode), which can be configured to read 11 bits per I / O sensor (44 x 11 = 484 in total, or about 61 bytes), 33 bits per I / O sensor (44 x 33 = 1452 in total, or about 181 bytes) with Count_length=512, or 31 bits per I / O sensor (44 x 31 = 1364 in total, or about 171 bytes) with Count_length=256.

[0112] During execution at WIN intervals, the block controller checks the sensor fail indicator signal (prtn_io_sensor_fail[43:0]) for each sensor. The signal is synchronized to the PLL-divided clock inside the block controller using a synchronizer. When the sensor fail indicator signal (prtn_io_sensor_fail) is logically high, the block controller stores the value of the delay line position executed during the WIN interval in Memory[x], but only if the delay line position is smaller than the value stored in Memory[x].

[0113] The first 5 bits ([4:0]) of Memory[x] store the delay line position, and the sixth bit ([5]) of Memory[x] is the valid bit. The valid bit is set to a logical high when the sensor([x]) sensor fail indicator signal (prtn_io_sensor_fail) is found to be logically high for the first time. At the end of the delay line cycle, the sensor's memory([x]) stores the minimum delay line value corresponding to the pin-by-pin margin.

[0114] The block controller (prtn_tca_block_controller) stores the minimum value of an adjustable delay line that fails across all delay line measurement cycles, and the maximum value among all minimum values ​​of adjustable delay lines that fail across all delay line measurement cycles. It also stores the total of up to 512 delay line cycles, the measured minimum delay line value, and the count of the total number of measurement cycles.

[0115] Communication between the block controller (prtn_tca_block_controller) and the I / O sensors within the block implements a high fan-out (FO) connection. The propagation delay of these signals is defined to the advantage of optimizing test efficiency, i.e., optimizing the active time for the entire test duration.

[0116] To ensure optimal operation of the I / O sensor, the signal driving the I / O sensor must reach the I / O sensor input with a clearly defined slope. Table 3 below defines the propagation time and signal slope (at the I / O sensor input) for each signal (between the block controller and the I / O sensor, optionally in both directions). [Table 3]

[0117] Further reference to the generalized meaning discussed above, the processing logic may be configured to repeatedly set an adjustable delay line for each of several durations and identify a minimum duration for each of several measurement cycles. The processing logic may then be further configured to determine one or more of the lowest minimum duration over several measurement cycles, the highest minimum duration over several measurement cycles, and the sum of the minimum durations over several measurement cycles.

[0118] Referring to Figure 9, a schematic diagram of a portion of the I / O block controller from Figure 8, configured for the Automatic Test Pattern Generation (ATPG) mode, is shown. Specifically, it comprises two series state elements (D flip-flops), both clocked by a PLL clock (1 GHz). The first state element has a constant logic high value (1'b1) as a data input and provides its output (Q) to the second state element as a data input. Both state elements have a central active-low reset signal (prtn_rst_n) from the FC controller as a reset input, which is also provided as the first input (logic low value) to the multiplexer. The output (Q) of the second state element is provided as the second input (logic high value) to the multiplexer.

[0119] Referring to Figure 10, a schematic circuit diagram of an implementation of the I / O sensor according to this disclosure for monitoring the degradation of a bidirectional or receive-only signal interconnect channel (lane) is shown. This implementation is used, in particular, in a High Bandwidth Memory 3 (HBM3) semiconductor 3D IC package. The interconnect signal channel has a near-end (NE) bump (connection such as a solder pin) and a far-end (FE) bump. The pads of the NE and FE have capacitance (Schematically indicated by capacitors labeled as C-pads). In this example, at the FE in the dynamic random-access memory (DRAM) portion of the 3D IC, a physical layer (Phy) transmit buffer receives an input (DQ[n]), which is received by an NE (pseudo) differential receive buffer (Diff Rx buffer) that compares the received signal to a threshold voltage (VREF). The output of the NE differential receive buffer is provided as a data input to an I / O sensor that also receives a clock (clk). In a bidirectional channel, a transmit buffer (Tx buffer) is also provided to the main chip (MC) physical layer (Phy) transmitter. The degradation of the transition slope of the transmitted signal (from slope-in ​​to slope-out) is indicated, which determines the margin. The receive buffer can also be implemented as a CMOS receiver (or another type of receive buffer), in which case it is not necessary to receive or perform a comparison with the threshold voltage (VREF). This also applies to other differential receive buffers disclosed below.

[0120] Referring to Figure 11, a schematic circuit diagram of the implementation of the I / O sensor according to this disclosure for monitoring the degradation of transmit-only signal interconnect channels (lanes) is shown, which is particularly suitable for HBM3 3D IC packages. For brevity, features common to Figure 10 will not be described again. Two signal interconnect channels are shown, each having an I / O sensor whose output of the channel's respective NE differential receive buffer is provided as a data input. In this operating mode, there is no reference signal, such as a clock signal, that can be used as a comparison for measuring setup or hold times. Therefore, the output of the other channel's NE differential receive buffer is provided as a clock input to its respective I / O sensor. This means that each I / O sensor measures the setup or hold time between signals from adjacent pins or lanes; that is, each pin is used as a reference signal for adjacent pins.

[0121] For example, the reference for the receiver output (Rx[0]) of the first lane is the delayed version of the receiver output (Rx[1]) of the second lane. The delay is given by ΔT. In this case, the data signal of the first lane I / O sensor is Rx[0] and the clock signal is Rx[1]+ΔT. The setup time is measured by the I / O sensor as the time difference (delta) from Rx[1]+ΔT to Rx[0]. Degradation of one of the signals (Rx[0] or Rx[1]) causes a change in the setup time detected by the sensor. Therefore, this is sensitive to changes in transmit buffer strength and NE bump resistance. ΔT is set such that at least one of the following conditions is held, taking into account the total skew from Rx[0] to Rx[1]: I / O sensor-specific delay (IO_Sensor int_Delay )≦Setup_time[0]≦Maximum setting window for the I / O sensor, and I / O sensor-specific delay≦Setup_time[1]≦Maximum setting window for the I / O sensor.

[0122] Referring to Figure 12, the waveform timings for three scenarios in degradation monitoring of a transmit-only signal interconnect channel are shown. In each case, ΔT is 1.5xIO_SensorI nt_Delay The initial timing relationship is determined by random variations in the receiver and data alignment (D[0] to D[1]). The timing scenario is used to determine ΔT for proper operation under a timing skew from the first lane to the second lane. In the first scenario (a), the timing of the first lane is the same as the timing of the second lane (i.e., Rx[0]=Rx[1]), in the second scenario (b), the timing of the first lane is before the second lane (e.g., Rx[0]-Rx[1]≧-20ps), and in the third scenario (c), the timing of the first lane is after the second lane (i.e., Rx[0]-Rx[1])≦20ps).

[0123] Referring to Figure 13, a schematic circuit diagram of an implementation of the I / O sensor according to this disclosure for monitoring degradation of differential interconnect receive channels (lanes), which is particularly suitable for HBM3 3D IC packages, is shown. For brevity, features common to Figures 10 and 11 will not be described again. In the case of a transmit-only lane, since there is no reference signal such as a clock, two single-ended signals Rx_c and Rx_t are delayed by ΔT and then used as a reference to each other (in the same way as in the transmit-only case). The first single-ended signal Rx_c is generated by comparing the signal received from one side of the differential channel with a threshold voltage (VREF), and the second single-ended signal Rx_t is generated by comparing the signal received from the opposite side of the differential channel with a threshold voltage (VREF). Degradation of one signal is detected by the I / O sensor (under the assumption that degradation of both signals does not occur simultaneously). This can be used for continuous measurement of clock or strobe symmetry (Rx_c-rise to Rx_t-rise).

[0124] Referring to Figure 14, a schematic circuit diagram of an implementation of the I / O sensor according to this disclosure for monitoring the degradation of differential interconnect transmit channels (lanes) is shown, which is particularly suitable for HBM3 3D IC packages. This shows a transmit strobe using a differential transmit buffer that receives a data input (D_in) and provides differential transmit outputs (cn, cp). Each differential transmit output is provided to a (pseudo) differential receive buffer (which can be implemented with alternative types of receive buffers, as mentioned above), each providing a data output (Rx_c, Rx_t). The figure also shows a method using a single I / O sensor and a multiplexed arrangement of Rx_c and Rx_t signals instead of two I / O sensors. This can also be used to monitor the degradation of a differential interconnect receive channel instead of the arrangement in Figure 13, or to monitor the degradation of multiple transmit-only signal interconnect channels (lanes) instead of the arrangement shown in Figure 11.

[0125] Returning to the generalized meaning considered above, an I / O block of a semiconductor IC can be considered (this can be combined with other embodiments disclosed herein). The I / O block comprises a receive buffer configured to receive voltage signals from an interconnected portion of the semiconductor IC and provide a receive buffer output, and an I / O sensor disclosed herein. The receive buffer output (which may indicate a logic level) can be provided as a data signal input to a delay circuit of the I / O sensor. The receive buffer may be a differential (or pseudo-differential) receive buffer and may be further configured to compare a received voltage signal with a voltage threshold input and, based on the comparison, provide a receive buffer output.

[0126] The I / O sensor is further configured, for the benefit of its ability, to receive a clock signal input (which may be used in various ways, as discussed elsewhere in this specification). In some embodiments, a clock signal associated with a received voltage signal may be provided as the clock signal input. This may be used for measurement and / or monitoring of bidirectional or receive-only pins or lanes.

[0127] In some implementations, a (differential) receive buffer is a first (differential) receive buffer configured to receive a first voltage signal from a first interconnected portion of a semiconductor IC and provide a first receive buffer output. The I / O block may then further include a second (differential) receive buffer configured to receive a second voltage signal from a second interconnected portion of the semiconductor IC, optionally compare the received second voltage signal with a voltage threshold input, and, if necessary, provide a second receive buffer output based on the comparison. In this case, the second receive buffer output, to which a (fixed or adjustable) delay is applied, may be provided as a clock signal input. This may be used for transmit-only or differential pin or lane measurement and / or monitoring. For example, the first and second interconnected portions of the semiconductor IC may form a differential channel (although in other embodiments they may simply be physically and / or logically adjacent).

[0128] In certain embodiments, the I / O sensor is a first I / O sensor, and the clock signal input is a first clock signal input. The I / O block may then further comprise a second I / O sensor disclosed herein, the second receive buffer output of which is provided to a delay circuit as a data signal input. The second I / O sensor may further be configured to receive a second clock signal input. The first receive buffer output, to which a (fixed or adjustable) delay is applied, may then be provided as a second clock signal input.

[0129] In other embodiments, a single I / O sensor may be used to measure the margin. The I / O block may then further include a multiplexed configuration configured to (a) apply a first receive buffer output to the I / O sensor as a data signal input and a second receive buffer output with a delay applied to it as a clock signal input to the I / O sensor, or a data signal is provided as a second state element input signal and a clock signal is provided as first and second clock inputs, or (b) apply a second receive buffer output to the I / O sensor as a data signal input and a first receive buffer output with a delay applied to it as a clock signal input to the I / O sensor.

[0130] Optionally, a mechanism for holding the output of a fifth state element (FF5) indicating a sensor fail indicator signal (ptrn_io_sensor_fail) may be masked. This option can be used to avoid locking the sensor fail indicator signal in situations where the data and / or clock are unstable (the unstable time interval may be defined by the protocol). This is done by adding a control signal that enables sampling by the fifth state element (FF5), and can control, for example, the reset or data input of the fifth state element (FF5).

[0131] In a general sense, what is offered here is either an I / O sensor or die connectivity monitoring system that is physically present (embedded) in a multi-IC module or a single IC, or multiple such sensors / systems that are physically present in multiple ICs of a multi-IC module, with one or more sensors per IC. Such sensors / systems may be beneficial to any interconnected part of any IC in a multi-IC module.

[0132] Through this disclosure, various embodiments may be presented in range form. It should be understood that the range form description is merely for convenience and brevity and should not be interpreted as an inflexible limitation on the scope of the invention. Therefore, the range description should be considered to specifically disclose all possible partial ranges, not just the individual numbers within that range. For example, a range description such as 1-6 should be considered to specifically disclose partial ranges such as 1-3, 1-4, 1-5, 2-4, 2-6, 3-6, and the individual numbers within that range, such as 1, 2, 3, 4, 5, and 6. This applies regardless of the width of the range.

[0133] Whenever a numerical range is indicated in this specification, it means that it includes any cited number (fraction or integer) within the indicated range. The expressions "in the range between the first and second indicated numbers" and "in the range from the first indicated number to the second indicated number" are used interchangeably in this specification and mean that the first and second indicated numbers and all fractions and integers between them are included.

[0134] In the description and claims of this application, the words “comprise,” “include,” and “have,” and their forms, are not necessarily limited to the elements in the list to which the words may be associated. Furthermore, in the event of any inconsistency between this application and any document incorporated by reference, this application shall prevail.

[0135] To clarify the references in this disclosure, the use of words as common nouns, proper nouns, named nouns, etc., is not intended to suggest that embodiments of the invention are limited to a single embodiment, and while many configurations of the disclosed components can be used to illustrate some embodiments of the invention, it should be noted that other configurations may be derived from these embodiments in different configurations.

[0136] For clarity, not all conventional features of the implementations described herein are shown or described. Naturally, it should be understood that developing any actual implementation will require numerous implementation-specific decisions to achieve the developer's specific objectives, such as compliance with application- and business-related constraints, and that these specific objectives will vary from implementation to implementation and from developer to developer. Furthermore, while such development efforts can be complex and time-consuming, it will nevertheless be understood as routine engineering work for those skilled in the art who are interested in this disclosure.

[0137] Based on the teachings of this disclosure, it is expected that those skilled in the art will be able to readily implement the present invention. The descriptions of the various embodiments provided herein are intended to provide sufficient insight and detail of the present invention to enable those skilled in the art to implement it. Furthermore, the various features and embodiments of the present invention described above are specifically intended to be used individually and in various combinations.

[0138] The present invention can be implemented using conventional and / or modern circuit design and layout tools. The specific embodiments described herein, in particular the various circuit arrangements, measurements, and data flows, are illustrative of exemplary embodiments and should not be considered as limiting the invention to the selection of such specific implementation forms. Accordingly, multiple instances may be provided as a single instance for the components described herein. Determination of margins and / or other parameters may be performed, for example, in different parts of the configuration. Eye parameters of types other than eye width may be determined using margin measurements. In fact, in some cases, it is not necessary to calculate eye parameters at all. Optionally, the IO sensor can be extended to simultaneously measure both sides of the data eye by implementing a second delay line in the clock signal.

[0139] While circuits and physical structures are conceptually assumed, it is well recognized in modern semiconductor design and manufacturing that physical structures and circuits can be embodied in a computer-readable description suitable for subsequent design, testing, or manufacturing stages, and for use in the resulting semiconductor integrated circuits. Therefore, claims relating to conventional circuits or structures can be read, in accordance with their specific wording, whether embodied in a medium or combined with a suitable reading function to enable improvement of the manufacturing, testing, or design of the corresponding circuit and / or structure. Structures and functions presented as separate components in exemplary configurations can be implemented as combined structures or components. The present invention is intended to include circuits, systems of circuits, related methods, and computer-readable (medium) encodings of such circuits, systems, and methods, all of which are described herein and defined in the appended claims. The computer-readable media used herein include non-transient media such as disks, tapes, or other magnetic, optical, or semiconductor media (e.g., flash memory cards, ROMs).

[0140] The detailed description above describes only a few of the many possible implementations of the present invention. Therefore, this detailed description is for illustrative purposes only, not limiting. Variations and modifications of the embodiments disclosed herein may be made based on the description herein without departing from the scope and spirit of the invention. Only the following claims, including all equivalents, are intended to define the scope of the invention. In particular, while the main embodiments are described in the context of 3D ICs, the teachings of the invention are considered advantageous for use with other types of semiconductor ICs that utilize I / O circuits. Furthermore, the techniques described herein may be applicable to other types of circuit applications. Thus, other variations, modifications, additions, and improvements may fall within the scope of the invention as defined in the following claims.

[0141] Embodiments of the present invention may be used to manufacture, produce, and / or assemble integrated circuits and / or products based on integrated circuits.

[0142] Aspects of the present invention are described herein with reference to flowcharts and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the present invention. It will be understood that each block in the flowcharts and / or block diagrams, and combinations of blocks in the flowcharts and / or block diagrams, can be implemented by computer-readable program instructions.

[0143] The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in a flowchart or block diagram may represent a module, segment, or part of an instruction, which contains one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions described in a block may occur in an order different from the order shown in the figure. For example, two blocks shown consecutively may actually be executed substantially simultaneously, or they may be executed in reverse order depending on the functions involved. It should also be noted that each block in a block diagram and / or flowchart, and combinations of blocks in a block diagram and / or flowchart, may be implemented by a dedicated hardware-based system that performs a specified function or action, or executes a combination of dedicated hardware and computer instructions.

[0144] The descriptions of various embodiments of the present invention are presented for illustrative purposes only and are not intended to be exhaustive or limit the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terms used herein have been selected to best describe the principles, practical applications, or technical improvements to the technologies available on the market of the embodiments, or to enable those skilled in the art to understand the embodiments disclosed herein.

Claims

1. A multi-IC (integrated circuit) module, A first IC equipped with a transmitter, A second IC interconnected to the first IC through multiple interconnection lanes, wherein the second IC is Receiver and An I / O (input / output) sensor configured to receive, as input, (a) a clock signal that also clocks data transmission through the plurality of interconnection lanes, and (b) a data signal transmitted by the transmitter of the first IC through a specific interconnection lane among the plurality of interconnection lanes and received by the receiver of the second IC, wherein the I / O sensor is An adjustable delay line configured to delay the aforementioned data signal and thereby generate a delayed data signal, A comparison circuit configured to generate a comparison signal by comparing the aforementioned data signal with the aforementioned delayed data signal, Processing logic, The adjustable delay line is set to a plurality of durations so as to gradually delay the data signal relative to the clock signal until a fail condition is detected from the comparison signal. Based on the detection of the failure state, the reliability of connectivity between the first IC and the second IC through the specific interconnection lane is determined. The processing logic is configured as follows: I / Ocom, A second IC equipped with, A multi-IC module equipped with the following features.

2. The multi-IC module according to claim 1, wherein the processing logic is further configured to adjust at least one of the data throughput and clock rate of the multi-IC module according to the determined reliability of connectivity.

3. The first IC and the second IC are at least, (a) Bump, (b) Microbumps, (c) Pin, (d) Redistribution Layer (RDL) and Integrated Fan-Out Via (TIV), (e) Through-silicon vias (TSVs), and (f) pad The multi-IC module according to claim 1, which is interconnected by the specific interconnection lanes using one or more of the following:

4. The multi-IC module according to claim 3, wherein the determination of the reliability of connectivity comprises determining at least one resistance parameter from (a) to (f).

5. The multi-IC module according to claim 3, wherein the reliability of the connectivity is affected by degradation of at least one of (a) to (f).

6. The multi-IC module according to claim 1, wherein the determination of the reliability of connectivity comprises determining a parameter indicating the symmetry of the differential signal.

7. The multi-IC module according to claim 1, wherein the determination of the reliability of connectivity includes determining the effect of the clock duty cycle on the eye width.

8. The reliability of the connectivity is affected by open circuits, according to claim 1, the multi-IC module.

9. The reliability of the connectivity is affected by short circuits, according to claim 1, the multi-IC module.

10. The reliability of the connectivity is affected by bridge short circuits, according to claim 1, the multi-IC module.

11. The multi-IC module according to claim 1, wherein the processing logic is further configured to measure a margin based on the minimum delay that caused the fail condition.

12. The multi-IC module according to claim 1, wherein the processing logic is further configured to determine the sum of the minimum durations that caused the fail state.

13. The multi-IC module according to claim 1, wherein the processing logic is further configured to measure the margin of the data signal based on the detection of the fail state.

14. The measured value of the margin is, Data signal setup time until the clock rising edge, Data signal setup time until the clock falling edge, The data signal hold time until the rising edge of the clock, and Data signal hold time until the clock falling edge The multi-IC module according to claim 13, comprising at least one of the following.

15. The adjustable delay line is part of a delay circuit, and the delay circuit is A first state element, configured to receive a first state element input signal and to provide a first state element output based on the first state element input signal and a first clock input, A second state element, configured to receive a second state element input signal and to provide a second state element output based on the second state element input signal and a second clock input, It is a redundant configuration, A data signal as an input signal to the adjustable delay line, wherein the output of the adjustable delay line is provided as the first state element input signal, the data signal is provided as the second state element input signal, and a clock signal is provided as the first clock input and the second clock input, and A clock signal as an input signal to the adjustable delay line, wherein the output of the adjustable delay line is provided as the first clock input, the data signal is provided as the first state element input signal and the second state element input signal, and the clock signal is provided as the second clock input. A multiplexed configuration configured to selectively apply one of the following, A multi-IC module according to claim 1, comprising:

16. The aforementioned multiplexing arrangement uses the following as the clock signal: Positive clock signal, or Negative clock signal is an inverted positive clock signal. The multi-IC module according to claim 15, further configured to selectively apply.

17. A computer program product comprising a non-temporary computer-readable storage medium that thereby embodies program code, wherein the program code is executable by at least one hardware processor to facilitate the manufacture of the multi-IC module described in any one of claims 1 to 16.

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